1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * core.c - DesignWare USB3 DRD Controller Core file
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/version.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/io.h>
22 #include <linux/list.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/of.h>
26 #include <linux/of_graph.h>
27 #include <linux/acpi.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/bitfield.h>
31
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
34 #include <linux/usb/of.h>
35 #include <linux/usb/otg.h>
36
37 #include "core.h"
38 #include "gadget.h"
39 #include "io.h"
40
41 #include "debug.h"
42
43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */
44
45 /**
46 * dwc3_get_dr_mode - Validates and sets dr_mode
47 * @dwc: pointer to our context structure
48 */
dwc3_get_dr_mode(struct dwc3 * dwc)49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
50 {
51 enum usb_dr_mode mode;
52 struct device *dev = dwc->dev;
53 unsigned int hw_mode;
54
55 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
56 dwc->dr_mode = USB_DR_MODE_OTG;
57
58 mode = dwc->dr_mode;
59 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
60
61 switch (hw_mode) {
62 case DWC3_GHWPARAMS0_MODE_GADGET:
63 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
64 dev_err(dev,
65 "Controller does not support host mode.\n");
66 return -EINVAL;
67 }
68 mode = USB_DR_MODE_PERIPHERAL;
69 break;
70 case DWC3_GHWPARAMS0_MODE_HOST:
71 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
72 dev_err(dev,
73 "Controller does not support device mode.\n");
74 return -EINVAL;
75 }
76 mode = USB_DR_MODE_HOST;
77 break;
78 default:
79 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
80 mode = USB_DR_MODE_HOST;
81 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
82 mode = USB_DR_MODE_PERIPHERAL;
83
84 /*
85 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
86 * mode. If the controller supports DRD but the dr_mode is not
87 * specified or set to OTG, then set the mode to peripheral.
88 */
89 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
90 (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
91 !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
92 !DWC3_VER_IS_PRIOR(DWC3, 330A))
93 mode = USB_DR_MODE_PERIPHERAL;
94 }
95
96 if (mode != dwc->dr_mode) {
97 dev_warn(dev,
98 "Configuration mismatch. dr_mode forced to %s\n",
99 mode == USB_DR_MODE_HOST ? "host" : "gadget");
100
101 dwc->dr_mode = mode;
102 }
103
104 return 0;
105 }
106
dwc3_enable_susphy(struct dwc3 * dwc,bool enable)107 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable)
108 {
109 u32 reg;
110
111 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
112 if (enable && !dwc->dis_u3_susphy_quirk)
113 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
114 else
115 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
116
117 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
118
119 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
120 if (enable && !dwc->dis_u2_susphy_quirk)
121 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
122 else
123 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
124
125 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
126 }
127
dwc3_set_prtcap(struct dwc3 * dwc,u32 mode)128 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
129 {
130 u32 reg;
131
132 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
133 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
134 reg |= DWC3_GCTL_PRTCAPDIR(mode);
135 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
136
137 dwc->current_dr_role = mode;
138 }
139
__dwc3_set_mode(struct work_struct * work)140 static void __dwc3_set_mode(struct work_struct *work)
141 {
142 struct dwc3 *dwc = work_to_dwc(work);
143 unsigned long flags;
144 int ret;
145 u32 reg;
146 u32 desired_dr_role;
147
148 mutex_lock(&dwc->mutex);
149 spin_lock_irqsave(&dwc->lock, flags);
150 desired_dr_role = dwc->desired_dr_role;
151 spin_unlock_irqrestore(&dwc->lock, flags);
152
153 pm_runtime_get_sync(dwc->dev);
154
155 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
156 dwc3_otg_update(dwc, 0);
157
158 if (!desired_dr_role)
159 goto out;
160
161 if (desired_dr_role == dwc->current_dr_role)
162 goto out;
163
164 if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
165 goto out;
166
167 switch (dwc->current_dr_role) {
168 case DWC3_GCTL_PRTCAP_HOST:
169 dwc3_host_exit(dwc);
170 break;
171 case DWC3_GCTL_PRTCAP_DEVICE:
172 dwc3_gadget_exit(dwc);
173 dwc3_event_buffers_cleanup(dwc);
174 break;
175 case DWC3_GCTL_PRTCAP_OTG:
176 dwc3_otg_exit(dwc);
177 spin_lock_irqsave(&dwc->lock, flags);
178 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
179 spin_unlock_irqrestore(&dwc->lock, flags);
180 dwc3_otg_update(dwc, 1);
181 break;
182 default:
183 break;
184 }
185
186 /*
187 * When current_dr_role is not set, there's no role switching.
188 * Only perform GCTL.CoreSoftReset when there's DRD role switching.
189 */
190 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
191 DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
192 desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
193 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
194 reg |= DWC3_GCTL_CORESOFTRESET;
195 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
196
197 /*
198 * Wait for internal clocks to synchronized. DWC_usb31 and
199 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
200 * keep it consistent across different IPs, let's wait up to
201 * 100ms before clearing GCTL.CORESOFTRESET.
202 */
203 msleep(100);
204
205 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
206 reg &= ~DWC3_GCTL_CORESOFTRESET;
207 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 }
209
210 spin_lock_irqsave(&dwc->lock, flags);
211
212 dwc3_set_prtcap(dwc, desired_dr_role);
213
214 spin_unlock_irqrestore(&dwc->lock, flags);
215
216 switch (desired_dr_role) {
217 case DWC3_GCTL_PRTCAP_HOST:
218 ret = dwc3_host_init(dwc);
219 if (ret) {
220 dev_err(dwc->dev, "failed to initialize host\n");
221 } else {
222 if (dwc->usb2_phy)
223 otg_set_vbus(dwc->usb2_phy->otg, true);
224 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
225 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
226 if (dwc->dis_split_quirk) {
227 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
228 reg |= DWC3_GUCTL3_SPLITDISABLE;
229 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
230 }
231 }
232 break;
233 case DWC3_GCTL_PRTCAP_DEVICE:
234 dwc3_core_soft_reset(dwc);
235
236 dwc3_event_buffers_setup(dwc);
237
238 if (dwc->usb2_phy)
239 otg_set_vbus(dwc->usb2_phy->otg, false);
240 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
241 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
242
243 ret = dwc3_gadget_init(dwc);
244 if (ret)
245 dev_err(dwc->dev, "failed to initialize peripheral\n");
246 break;
247 case DWC3_GCTL_PRTCAP_OTG:
248 dwc3_otg_init(dwc);
249 dwc3_otg_update(dwc, 0);
250 break;
251 default:
252 break;
253 }
254
255 out:
256 pm_runtime_mark_last_busy(dwc->dev);
257 pm_runtime_put_autosuspend(dwc->dev);
258 mutex_unlock(&dwc->mutex);
259 }
260
dwc3_set_mode(struct dwc3 * dwc,u32 mode)261 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
262 {
263 unsigned long flags;
264
265 if (dwc->dr_mode != USB_DR_MODE_OTG)
266 return;
267
268 spin_lock_irqsave(&dwc->lock, flags);
269 dwc->desired_dr_role = mode;
270 spin_unlock_irqrestore(&dwc->lock, flags);
271
272 queue_work(system_freezable_wq, &dwc->drd_work);
273 }
274
dwc3_core_fifo_space(struct dwc3_ep * dep,u8 type)275 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
276 {
277 struct dwc3 *dwc = dep->dwc;
278 u32 reg;
279
280 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
281 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
282 DWC3_GDBGFIFOSPACE_TYPE(type));
283
284 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
285
286 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
287 }
288
289 /**
290 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
291 * @dwc: pointer to our context structure
292 */
dwc3_core_soft_reset(struct dwc3 * dwc)293 int dwc3_core_soft_reset(struct dwc3 *dwc)
294 {
295 u32 reg;
296 int retries = 1000;
297
298 /*
299 * We're resetting only the device side because, if we're in host mode,
300 * XHCI driver will reset the host block. If dwc3 was configured for
301 * host-only mode, then we can return early.
302 */
303 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
304 return 0;
305
306 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
307 reg |= DWC3_DCTL_CSFTRST;
308 reg &= ~DWC3_DCTL_RUN_STOP;
309 dwc3_gadget_dctl_write_safe(dwc, reg);
310
311 /*
312 * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
313 * is cleared only after all the clocks are synchronized. This can
314 * take a little more than 50ms. Set the polling rate at 20ms
315 * for 10 times instead.
316 */
317 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
318 retries = 10;
319
320 do {
321 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
322 if (!(reg & DWC3_DCTL_CSFTRST))
323 goto done;
324
325 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
326 msleep(20);
327 else
328 udelay(1);
329 } while (--retries);
330
331 dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
332 return -ETIMEDOUT;
333
334 done:
335 /*
336 * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
337 * is cleared, we must wait at least 50ms before accessing the PHY
338 * domain (synchronization delay).
339 */
340 if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
341 msleep(50);
342
343 return 0;
344 }
345
346 /*
347 * dwc3_frame_length_adjustment - Adjusts frame length if required
348 * @dwc3: Pointer to our controller context structure
349 */
dwc3_frame_length_adjustment(struct dwc3 * dwc)350 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
351 {
352 u32 reg;
353 u32 dft;
354
355 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
356 return;
357
358 if (dwc->fladj == 0)
359 return;
360
361 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
362 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
363 if (dft != dwc->fladj) {
364 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
365 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
366 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
367 }
368 }
369
370 /**
371 * dwc3_ref_clk_period - Reference clock period configuration
372 * Default reference clock period depends on hardware
373 * configuration. For systems with reference clock that differs
374 * from the default, this will set clock period in DWC3_GUCTL
375 * register.
376 * @dwc: Pointer to our controller context structure
377 */
dwc3_ref_clk_period(struct dwc3 * dwc)378 static void dwc3_ref_clk_period(struct dwc3 *dwc)
379 {
380 unsigned long period;
381 unsigned long fladj;
382 unsigned long decr;
383 unsigned long rate;
384 u32 reg;
385
386 if (dwc->ref_clk) {
387 rate = clk_get_rate(dwc->ref_clk);
388 if (!rate)
389 return;
390 period = NSEC_PER_SEC / rate;
391 } else if (dwc->ref_clk_per) {
392 period = dwc->ref_clk_per;
393 rate = NSEC_PER_SEC / period;
394 } else {
395 return;
396 }
397
398 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
399 reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
400 reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
401 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
402
403 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
404 return;
405
406 /*
407 * The calculation below is
408 *
409 * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
410 *
411 * but rearranged for fixed-point arithmetic. The division must be
412 * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
413 * neither does rate * period).
414 *
415 * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
416 * nanoseconds of error caused by the truncation which happened during
417 * the division when calculating rate or period (whichever one was
418 * derived from the other). We first calculate the relative error, then
419 * scale it to units of 8 ppm.
420 */
421 fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
422 fladj -= 125000;
423
424 /*
425 * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
426 */
427 decr = 480000000 / rate;
428
429 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
430 reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
431 & ~DWC3_GFLADJ_240MHZDECR
432 & ~DWC3_GFLADJ_240MHZDECR_PLS1;
433 reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
434 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
435 | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
436
437 if (dwc->gfladj_refclk_lpm_sel)
438 reg |= DWC3_GFLADJ_REFCLK_LPM_SEL;
439
440 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
441 }
442
443 /**
444 * dwc3_free_one_event_buffer - Frees one event buffer
445 * @dwc: Pointer to our controller context structure
446 * @evt: Pointer to event buffer to be freed
447 */
dwc3_free_one_event_buffer(struct dwc3 * dwc,struct dwc3_event_buffer * evt)448 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
449 struct dwc3_event_buffer *evt)
450 {
451 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
452 }
453
454 /**
455 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
456 * @dwc: Pointer to our controller context structure
457 * @length: size of the event buffer
458 *
459 * Returns a pointer to the allocated event buffer structure on success
460 * otherwise ERR_PTR(errno).
461 */
dwc3_alloc_one_event_buffer(struct dwc3 * dwc,unsigned int length)462 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
463 unsigned int length)
464 {
465 struct dwc3_event_buffer *evt;
466
467 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
468 if (!evt)
469 return ERR_PTR(-ENOMEM);
470
471 evt->dwc = dwc;
472 evt->length = length;
473 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
474 if (!evt->cache)
475 return ERR_PTR(-ENOMEM);
476
477 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
478 &evt->dma, GFP_KERNEL);
479 if (!evt->buf)
480 return ERR_PTR(-ENOMEM);
481
482 return evt;
483 }
484
485 /**
486 * dwc3_free_event_buffers - frees all allocated event buffers
487 * @dwc: Pointer to our controller context structure
488 */
dwc3_free_event_buffers(struct dwc3 * dwc)489 static void dwc3_free_event_buffers(struct dwc3 *dwc)
490 {
491 struct dwc3_event_buffer *evt;
492
493 evt = dwc->ev_buf;
494 if (evt)
495 dwc3_free_one_event_buffer(dwc, evt);
496 }
497
498 /**
499 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
500 * @dwc: pointer to our controller context structure
501 * @length: size of event buffer
502 *
503 * Returns 0 on success otherwise negative errno. In the error case, dwc
504 * may contain some buffers allocated but not all which were requested.
505 */
dwc3_alloc_event_buffers(struct dwc3 * dwc,unsigned int length)506 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
507 {
508 struct dwc3_event_buffer *evt;
509
510 evt = dwc3_alloc_one_event_buffer(dwc, length);
511 if (IS_ERR(evt)) {
512 dev_err(dwc->dev, "can't allocate event buffer\n");
513 return PTR_ERR(evt);
514 }
515 dwc->ev_buf = evt;
516
517 return 0;
518 }
519
520 /**
521 * dwc3_event_buffers_setup - setup our allocated event buffers
522 * @dwc: pointer to our controller context structure
523 *
524 * Returns 0 on success otherwise negative errno.
525 */
dwc3_event_buffers_setup(struct dwc3 * dwc)526 int dwc3_event_buffers_setup(struct dwc3 *dwc)
527 {
528 struct dwc3_event_buffer *evt;
529
530 evt = dwc->ev_buf;
531 evt->lpos = 0;
532 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
533 lower_32_bits(evt->dma));
534 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
535 upper_32_bits(evt->dma));
536 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
537 DWC3_GEVNTSIZ_SIZE(evt->length));
538 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
539
540 return 0;
541 }
542
dwc3_event_buffers_cleanup(struct dwc3 * dwc)543 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
544 {
545 struct dwc3_event_buffer *evt;
546
547 evt = dwc->ev_buf;
548
549 evt->lpos = 0;
550
551 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
552 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
553 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
554 | DWC3_GEVNTSIZ_SIZE(0));
555 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
556 }
557
dwc3_core_num_eps(struct dwc3 * dwc)558 static void dwc3_core_num_eps(struct dwc3 *dwc)
559 {
560 struct dwc3_hwparams *parms = &dwc->hwparams;
561
562 dwc->num_eps = DWC3_NUM_EPS(parms);
563 }
564
dwc3_cache_hwparams(struct dwc3 * dwc)565 static void dwc3_cache_hwparams(struct dwc3 *dwc)
566 {
567 struct dwc3_hwparams *parms = &dwc->hwparams;
568
569 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
570 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
571 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
572 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
573 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
574 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
575 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
576 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
577 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
578
579 if (DWC3_IP_IS(DWC32))
580 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
581 }
582
dwc3_core_ulpi_init(struct dwc3 * dwc)583 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
584 {
585 int intf;
586 int ret = 0;
587
588 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
589
590 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
591 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
592 dwc->hsphy_interface &&
593 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
594 ret = dwc3_ulpi_init(dwc);
595
596 return ret;
597 }
598
599 /**
600 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
601 * @dwc: Pointer to our controller context structure
602 *
603 * Returns 0 on success. The USB PHY interfaces are configured but not
604 * initialized. The PHY interfaces and the PHYs get initialized together with
605 * the core in dwc3_core_init.
606 */
dwc3_phy_setup(struct dwc3 * dwc)607 static int dwc3_phy_setup(struct dwc3 *dwc)
608 {
609 u32 reg;
610
611 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
612
613 /*
614 * Make sure UX_EXIT_PX is cleared as that causes issues with some
615 * PHYs. Also, this bit is not supposed to be used in normal operation.
616 */
617 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
618
619 /*
620 * Above DWC_usb3.0 1.94a, it is recommended to set
621 * DWC3_GUSB3PIPECTL_SUSPHY to '0' during coreConsultant configuration.
622 * So default value will be '0' when the core is reset. Application
623 * needs to set it to '1' after the core initialization is completed.
624 *
625 * Similarly for DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be
626 * cleared after power-on reset, and it can be set after core
627 * initialization.
628 */
629 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
630
631 if (dwc->u2ss_inp3_quirk)
632 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
633
634 if (dwc->dis_rxdet_inp3_quirk)
635 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
636
637 if (dwc->req_p1p2p3_quirk)
638 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
639
640 if (dwc->del_p1p2p3_quirk)
641 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
642
643 if (dwc->del_phy_power_chg_quirk)
644 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
645
646 if (dwc->lfps_filter_quirk)
647 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
648
649 if (dwc->rx_detect_poll_quirk)
650 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
651
652 if (dwc->tx_de_emphasis_quirk)
653 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
654
655 if (dwc->dis_del_phy_power_chg_quirk)
656 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
657
658 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
659
660 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
661
662 /* Select the HS PHY interface */
663 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
664 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
665 if (dwc->hsphy_interface &&
666 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
667 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
668 break;
669 } else if (dwc->hsphy_interface &&
670 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
671 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
672 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
673 } else {
674 /* Relying on default value. */
675 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
676 break;
677 }
678 fallthrough;
679 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
680 default:
681 break;
682 }
683
684 switch (dwc->hsphy_mode) {
685 case USBPHY_INTERFACE_MODE_UTMI:
686 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
687 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
688 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
689 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
690 break;
691 case USBPHY_INTERFACE_MODE_UTMIW:
692 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
693 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
694 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
695 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
696 break;
697 default:
698 break;
699 }
700
701 /*
702 * Above DWC_usb3.0 1.94a, it is recommended to set
703 * DWC3_GUSB2PHYCFG_SUSPHY to '0' during coreConsultant configuration.
704 * So default value will be '0' when the core is reset. Application
705 * needs to set it to '1' after the core initialization is completed.
706 *
707 * Similarly for DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared
708 * after power-on reset, and it can be set after core initialization.
709 */
710 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
711
712 if (dwc->dis_enblslpm_quirk)
713 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
714 else
715 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
716
717 if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel)
718 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
719
720 /*
721 * Some ULPI USB PHY does not support internal VBUS supply, to drive
722 * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL
723 * bit of OTG_CTRL register. Controller configures the USB2 PHY
724 * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus
725 * with an external supply.
726 */
727 if (dwc->ulpi_ext_vbus_drv)
728 reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV;
729
730 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
731
732 return 0;
733 }
734
dwc3_phy_init(struct dwc3 * dwc)735 static int dwc3_phy_init(struct dwc3 *dwc)
736 {
737 int ret;
738
739 usb_phy_init(dwc->usb2_phy);
740 usb_phy_init(dwc->usb3_phy);
741
742 ret = phy_init(dwc->usb2_generic_phy);
743 if (ret < 0)
744 goto err_shutdown_usb3_phy;
745
746 ret = phy_init(dwc->usb3_generic_phy);
747 if (ret < 0)
748 goto err_exit_usb2_phy;
749
750 return 0;
751
752 err_exit_usb2_phy:
753 phy_exit(dwc->usb2_generic_phy);
754 err_shutdown_usb3_phy:
755 usb_phy_shutdown(dwc->usb3_phy);
756 usb_phy_shutdown(dwc->usb2_phy);
757
758 return ret;
759 }
760
dwc3_phy_exit(struct dwc3 * dwc)761 static void dwc3_phy_exit(struct dwc3 *dwc)
762 {
763 phy_exit(dwc->usb3_generic_phy);
764 phy_exit(dwc->usb2_generic_phy);
765
766 usb_phy_shutdown(dwc->usb3_phy);
767 usb_phy_shutdown(dwc->usb2_phy);
768 }
769
dwc3_phy_power_on(struct dwc3 * dwc)770 static int dwc3_phy_power_on(struct dwc3 *dwc)
771 {
772 int ret;
773
774 usb_phy_set_suspend(dwc->usb2_phy, 0);
775 usb_phy_set_suspend(dwc->usb3_phy, 0);
776
777 ret = phy_power_on(dwc->usb2_generic_phy);
778 if (ret < 0)
779 goto err_suspend_usb3_phy;
780
781 ret = phy_power_on(dwc->usb3_generic_phy);
782 if (ret < 0)
783 goto err_power_off_usb2_phy;
784
785 return 0;
786
787 err_power_off_usb2_phy:
788 phy_power_off(dwc->usb2_generic_phy);
789 err_suspend_usb3_phy:
790 usb_phy_set_suspend(dwc->usb3_phy, 1);
791 usb_phy_set_suspend(dwc->usb2_phy, 1);
792
793 return ret;
794 }
795
dwc3_phy_power_off(struct dwc3 * dwc)796 static void dwc3_phy_power_off(struct dwc3 *dwc)
797 {
798 phy_power_off(dwc->usb3_generic_phy);
799 phy_power_off(dwc->usb2_generic_phy);
800
801 usb_phy_set_suspend(dwc->usb3_phy, 1);
802 usb_phy_set_suspend(dwc->usb2_phy, 1);
803 }
804
dwc3_clk_enable(struct dwc3 * dwc)805 static int dwc3_clk_enable(struct dwc3 *dwc)
806 {
807 int ret;
808
809 ret = clk_prepare_enable(dwc->bus_clk);
810 if (ret)
811 return ret;
812
813 ret = clk_prepare_enable(dwc->ref_clk);
814 if (ret)
815 goto disable_bus_clk;
816
817 ret = clk_prepare_enable(dwc->susp_clk);
818 if (ret)
819 goto disable_ref_clk;
820
821 return 0;
822
823 disable_ref_clk:
824 clk_disable_unprepare(dwc->ref_clk);
825 disable_bus_clk:
826 clk_disable_unprepare(dwc->bus_clk);
827 return ret;
828 }
829
dwc3_clk_disable(struct dwc3 * dwc)830 static void dwc3_clk_disable(struct dwc3 *dwc)
831 {
832 clk_disable_unprepare(dwc->susp_clk);
833 clk_disable_unprepare(dwc->ref_clk);
834 clk_disable_unprepare(dwc->bus_clk);
835 }
836
dwc3_core_exit(struct dwc3 * dwc)837 static void dwc3_core_exit(struct dwc3 *dwc)
838 {
839 dwc3_event_buffers_cleanup(dwc);
840 dwc3_phy_power_off(dwc);
841 dwc3_phy_exit(dwc);
842 dwc3_clk_disable(dwc);
843 reset_control_assert(dwc->reset);
844 }
845
dwc3_core_is_valid(struct dwc3 * dwc)846 static bool dwc3_core_is_valid(struct dwc3 *dwc)
847 {
848 u32 reg;
849
850 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
851 dwc->ip = DWC3_GSNPS_ID(reg);
852
853 /* This should read as U3 followed by revision number */
854 if (DWC3_IP_IS(DWC3)) {
855 dwc->revision = reg;
856 } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
857 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
858 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
859 } else {
860 return false;
861 }
862
863 return true;
864 }
865
dwc3_core_setup_global_control(struct dwc3 * dwc)866 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
867 {
868 u32 reg;
869
870 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
871 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
872
873 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
874 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
875 /**
876 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
877 * issue which would cause xHCI compliance tests to fail.
878 *
879 * Because of that we cannot enable clock gating on such
880 * configurations.
881 *
882 * Refers to:
883 *
884 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
885 * SOF/ITP Mode Used
886 */
887 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
888 dwc->dr_mode == USB_DR_MODE_OTG) &&
889 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
890 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
891 else
892 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
893 break;
894 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
895 /*
896 * REVISIT Enabling this bit so that host-mode hibernation
897 * will work. Device-mode hibernation is not yet implemented.
898 */
899 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
900 break;
901 default:
902 /* nothing */
903 break;
904 }
905
906 /* check if current dwc3 is on simulation board */
907 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
908 dev_info(dwc->dev, "Running with FPGA optimizations\n");
909 dwc->is_fpga = true;
910 }
911
912 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
913 "disable_scramble cannot be used on non-FPGA builds\n");
914
915 if (dwc->disable_scramble_quirk && dwc->is_fpga)
916 reg |= DWC3_GCTL_DISSCRAMBLE;
917 else
918 reg &= ~DWC3_GCTL_DISSCRAMBLE;
919
920 if (dwc->u2exit_lfps_quirk)
921 reg |= DWC3_GCTL_U2EXIT_LFPS;
922
923 /*
924 * WORKAROUND: DWC3 revisions <1.90a have a bug
925 * where the device can fail to connect at SuperSpeed
926 * and falls back to high-speed mode which causes
927 * the device to enter a Connect/Disconnect loop
928 */
929 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
930 reg |= DWC3_GCTL_U2RSTECN;
931
932 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
933 }
934
935 static int dwc3_core_get_phy(struct dwc3 *dwc);
936 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
937
938 /* set global incr burst type configuration registers */
dwc3_set_incr_burst_type(struct dwc3 * dwc)939 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
940 {
941 struct device *dev = dwc->dev;
942 /* incrx_mode : for INCR burst type. */
943 bool incrx_mode;
944 /* incrx_size : for size of INCRX burst. */
945 u32 incrx_size;
946 u32 *vals;
947 u32 cfg;
948 int ntype;
949 int ret;
950 int i;
951
952 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
953
954 /*
955 * Handle property "snps,incr-burst-type-adjustment".
956 * Get the number of value from this property:
957 * result <= 0, means this property is not supported.
958 * result = 1, means INCRx burst mode supported.
959 * result > 1, means undefined length burst mode supported.
960 */
961 ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
962 if (ntype <= 0)
963 return;
964
965 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
966 if (!vals)
967 return;
968
969 /* Get INCR burst type, and parse it */
970 ret = device_property_read_u32_array(dev,
971 "snps,incr-burst-type-adjustment", vals, ntype);
972 if (ret) {
973 kfree(vals);
974 dev_err(dev, "Error to get property\n");
975 return;
976 }
977
978 incrx_size = *vals;
979
980 if (ntype > 1) {
981 /* INCRX (undefined length) burst mode */
982 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
983 for (i = 1; i < ntype; i++) {
984 if (vals[i] > incrx_size)
985 incrx_size = vals[i];
986 }
987 } else {
988 /* INCRX burst mode */
989 incrx_mode = INCRX_BURST_MODE;
990 }
991
992 kfree(vals);
993
994 /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
995 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
996 if (incrx_mode)
997 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
998 switch (incrx_size) {
999 case 256:
1000 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1001 break;
1002 case 128:
1003 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1004 break;
1005 case 64:
1006 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1007 break;
1008 case 32:
1009 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1010 break;
1011 case 16:
1012 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1013 break;
1014 case 8:
1015 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1016 break;
1017 case 4:
1018 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1019 break;
1020 case 1:
1021 break;
1022 default:
1023 dev_err(dev, "Invalid property\n");
1024 break;
1025 }
1026
1027 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1028 }
1029
dwc3_set_power_down_clk_scale(struct dwc3 * dwc)1030 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1031 {
1032 u32 scale;
1033 u32 reg;
1034
1035 if (!dwc->susp_clk)
1036 return;
1037
1038 /*
1039 * The power down scale field specifies how many suspend_clk
1040 * periods fit into a 16KHz clock period. When performing
1041 * the division, round up the remainder.
1042 *
1043 * The power down scale value is calculated using the fastest
1044 * frequency of the suspend_clk. If it isn't fixed (but within
1045 * the accuracy requirement), the driver may not know the max
1046 * rate of the suspend_clk, so only update the power down scale
1047 * if the default is less than the calculated value from
1048 * clk_get_rate() or if the default is questionably high
1049 * (3x or more) to be within the requirement.
1050 */
1051 scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1052 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1053 if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1054 (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1055 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1056 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1057 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1058 }
1059 }
1060
dwc3_config_threshold(struct dwc3 * dwc)1061 static void dwc3_config_threshold(struct dwc3 *dwc)
1062 {
1063 u32 reg;
1064 u8 rx_thr_num;
1065 u8 rx_maxburst;
1066 u8 tx_thr_num;
1067 u8 tx_maxburst;
1068
1069 /*
1070 * Must config both number of packets and max burst settings to enable
1071 * RX and/or TX threshold.
1072 */
1073 if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1074 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1075 rx_maxburst = dwc->rx_max_burst_prd;
1076 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1077 tx_maxburst = dwc->tx_max_burst_prd;
1078
1079 if (rx_thr_num && rx_maxburst) {
1080 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1081 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1082
1083 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1084 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1085
1086 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1087 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1088
1089 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1090 }
1091
1092 if (tx_thr_num && tx_maxburst) {
1093 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1094 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1095
1096 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1097 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1098
1099 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1100 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1101
1102 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1103 }
1104 }
1105
1106 rx_thr_num = dwc->rx_thr_num_pkt;
1107 rx_maxburst = dwc->rx_max_burst;
1108 tx_thr_num = dwc->tx_thr_num_pkt;
1109 tx_maxburst = dwc->tx_max_burst;
1110
1111 if (DWC3_IP_IS(DWC3)) {
1112 if (rx_thr_num && rx_maxburst) {
1113 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1114 reg |= DWC3_GRXTHRCFG_PKTCNTSEL;
1115
1116 reg &= ~DWC3_GRXTHRCFG_RXPKTCNT(~0);
1117 reg |= DWC3_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1118
1119 reg &= ~DWC3_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1120 reg |= DWC3_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1121
1122 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1123 }
1124
1125 if (tx_thr_num && tx_maxburst) {
1126 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1127 reg |= DWC3_GTXTHRCFG_PKTCNTSEL;
1128
1129 reg &= ~DWC3_GTXTHRCFG_TXPKTCNT(~0);
1130 reg |= DWC3_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1131
1132 reg &= ~DWC3_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1133 reg |= DWC3_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1134
1135 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1136 }
1137 } else {
1138 if (rx_thr_num && rx_maxburst) {
1139 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1140 reg |= DWC31_GRXTHRCFG_PKTCNTSEL;
1141
1142 reg &= ~DWC31_GRXTHRCFG_RXPKTCNT(~0);
1143 reg |= DWC31_GRXTHRCFG_RXPKTCNT(rx_thr_num);
1144
1145 reg &= ~DWC31_GRXTHRCFG_MAXRXBURSTSIZE(~0);
1146 reg |= DWC31_GRXTHRCFG_MAXRXBURSTSIZE(rx_maxburst);
1147
1148 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1149 }
1150
1151 if (tx_thr_num && tx_maxburst) {
1152 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1153 reg |= DWC31_GTXTHRCFG_PKTCNTSEL;
1154
1155 reg &= ~DWC31_GTXTHRCFG_TXPKTCNT(~0);
1156 reg |= DWC31_GTXTHRCFG_TXPKTCNT(tx_thr_num);
1157
1158 reg &= ~DWC31_GTXTHRCFG_MAXTXBURSTSIZE(~0);
1159 reg |= DWC31_GTXTHRCFG_MAXTXBURSTSIZE(tx_maxburst);
1160
1161 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1162 }
1163 }
1164 }
1165
1166 /**
1167 * dwc3_core_init - Low-level initialization of DWC3 Core
1168 * @dwc: Pointer to our controller context structure
1169 *
1170 * Returns 0 on success otherwise negative errno.
1171 */
dwc3_core_init(struct dwc3 * dwc)1172 static int dwc3_core_init(struct dwc3 *dwc)
1173 {
1174 unsigned int hw_mode;
1175 u32 reg;
1176 int ret;
1177
1178 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1179
1180 /*
1181 * Write Linux Version Code to our GUID register so it's easy to figure
1182 * out which kernel version a bug was found.
1183 */
1184 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1185
1186 ret = dwc3_phy_setup(dwc);
1187 if (ret)
1188 return ret;
1189
1190 if (!dwc->ulpi_ready) {
1191 ret = dwc3_core_ulpi_init(dwc);
1192 if (ret) {
1193 if (ret == -ETIMEDOUT) {
1194 dwc3_core_soft_reset(dwc);
1195 ret = -EPROBE_DEFER;
1196 }
1197 return ret;
1198 }
1199 dwc->ulpi_ready = true;
1200 }
1201
1202 if (!dwc->phys_ready) {
1203 ret = dwc3_core_get_phy(dwc);
1204 if (ret)
1205 goto err_exit_ulpi;
1206 dwc->phys_ready = true;
1207 }
1208
1209 ret = dwc3_phy_init(dwc);
1210 if (ret)
1211 goto err_exit_ulpi;
1212
1213 ret = dwc3_core_soft_reset(dwc);
1214 if (ret)
1215 goto err_exit_phy;
1216
1217 dwc3_core_setup_global_control(dwc);
1218 dwc3_core_num_eps(dwc);
1219
1220 /* Set power down scale of suspend_clk */
1221 dwc3_set_power_down_clk_scale(dwc);
1222
1223 /* Adjust Frame Length */
1224 dwc3_frame_length_adjustment(dwc);
1225
1226 /* Adjust Reference Clock Period */
1227 dwc3_ref_clk_period(dwc);
1228
1229 dwc3_set_incr_burst_type(dwc);
1230
1231 ret = dwc3_phy_power_on(dwc);
1232 if (ret)
1233 goto err_exit_phy;
1234
1235 ret = dwc3_event_buffers_setup(dwc);
1236 if (ret) {
1237 dev_err(dwc->dev, "failed to setup event buffers\n");
1238 goto err_power_off_phy;
1239 }
1240
1241 /*
1242 * ENDXFER polling is available on version 3.10a and later of
1243 * the DWC_usb3 controller. It is NOT available in the
1244 * DWC_usb31 controller.
1245 */
1246 if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1247 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1248 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1249 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1250 }
1251
1252 /*
1253 * When configured in HOST mode, after issuing U3/L2 exit controller
1254 * fails to send proper CRC checksum in CRC5 feild. Because of this
1255 * behaviour Transaction Error is generated, resulting in reset and
1256 * re-enumeration of usb device attached. All the termsel, xcvrsel,
1257 * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1
1258 * will correct this problem. This option is to support certain
1259 * legacy ULPI PHYs.
1260 */
1261 if (dwc->resume_hs_terminations) {
1262 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1263 reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST;
1264 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1265 }
1266
1267 if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1268 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1269
1270 /*
1271 * Enable hardware control of sending remote wakeup
1272 * in HS when the device is in the L1 state.
1273 */
1274 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1275 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1276
1277 /*
1278 * Decouple USB 2.0 L1 & L2 events which will allow for
1279 * gadget driver to only receive U3/L2 suspend & wakeup
1280 * events and prevent the more frequent L1 LPM transitions
1281 * from interrupting the driver.
1282 */
1283 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1284 reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1285
1286 if (dwc->dis_tx_ipgap_linecheck_quirk)
1287 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1288
1289 if (dwc->parkmode_disable_ss_quirk)
1290 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1291
1292 if (dwc->parkmode_disable_hs_quirk)
1293 reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
1294
1295 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1296 (dwc->maximum_speed == USB_SPEED_HIGH ||
1297 dwc->maximum_speed == USB_SPEED_FULL))
1298 reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1299
1300 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1301 }
1302
1303 dwc3_config_threshold(dwc);
1304
1305 return 0;
1306
1307 err_power_off_phy:
1308 dwc3_phy_power_off(dwc);
1309 err_exit_phy:
1310 dwc3_phy_exit(dwc);
1311 err_exit_ulpi:
1312 dwc3_ulpi_exit(dwc);
1313
1314 return ret;
1315 }
1316
dwc3_core_get_phy(struct dwc3 * dwc)1317 static int dwc3_core_get_phy(struct dwc3 *dwc)
1318 {
1319 struct device *dev = dwc->dev;
1320 struct device_node *node = dev->of_node;
1321 int ret;
1322
1323 if (node) {
1324 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1325 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1326 } else {
1327 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1328 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1329 }
1330
1331 if (IS_ERR(dwc->usb2_phy)) {
1332 ret = PTR_ERR(dwc->usb2_phy);
1333 if (ret == -ENXIO || ret == -ENODEV)
1334 dwc->usb2_phy = NULL;
1335 else
1336 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1337 }
1338
1339 if (IS_ERR(dwc->usb3_phy)) {
1340 ret = PTR_ERR(dwc->usb3_phy);
1341 if (ret == -ENXIO || ret == -ENODEV)
1342 dwc->usb3_phy = NULL;
1343 else
1344 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1345 }
1346
1347 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1348 if (IS_ERR(dwc->usb2_generic_phy)) {
1349 ret = PTR_ERR(dwc->usb2_generic_phy);
1350 if (ret == -ENOSYS || ret == -ENODEV)
1351 dwc->usb2_generic_phy = NULL;
1352 else
1353 return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1354 }
1355
1356 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1357 if (IS_ERR(dwc->usb3_generic_phy)) {
1358 ret = PTR_ERR(dwc->usb3_generic_phy);
1359 if (ret == -ENOSYS || ret == -ENODEV)
1360 dwc->usb3_generic_phy = NULL;
1361 else
1362 return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1363 }
1364
1365 return 0;
1366 }
1367
dwc3_core_init_mode(struct dwc3 * dwc)1368 static int dwc3_core_init_mode(struct dwc3 *dwc)
1369 {
1370 struct device *dev = dwc->dev;
1371 int ret;
1372
1373 switch (dwc->dr_mode) {
1374 case USB_DR_MODE_PERIPHERAL:
1375 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1376
1377 if (dwc->usb2_phy)
1378 otg_set_vbus(dwc->usb2_phy->otg, false);
1379 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1380 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1381
1382 ret = dwc3_gadget_init(dwc);
1383 if (ret)
1384 return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1385 break;
1386 case USB_DR_MODE_HOST:
1387 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1388
1389 if (dwc->usb2_phy)
1390 otg_set_vbus(dwc->usb2_phy->otg, true);
1391 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1392 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1393
1394 ret = dwc3_host_init(dwc);
1395 if (ret)
1396 return dev_err_probe(dev, ret, "failed to initialize host\n");
1397 break;
1398 case USB_DR_MODE_OTG:
1399 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1400 ret = dwc3_drd_init(dwc);
1401 if (ret)
1402 return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1403 break;
1404 default:
1405 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1406 return -EINVAL;
1407 }
1408
1409 return 0;
1410 }
1411
dwc3_core_exit_mode(struct dwc3 * dwc)1412 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1413 {
1414 switch (dwc->dr_mode) {
1415 case USB_DR_MODE_PERIPHERAL:
1416 dwc3_gadget_exit(dwc);
1417 break;
1418 case USB_DR_MODE_HOST:
1419 dwc3_host_exit(dwc);
1420 break;
1421 case USB_DR_MODE_OTG:
1422 dwc3_drd_exit(dwc);
1423 break;
1424 default:
1425 /* do nothing */
1426 break;
1427 }
1428
1429 /* de-assert DRVVBUS for HOST and OTG mode */
1430 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1431 }
1432
dwc3_get_properties(struct dwc3 * dwc)1433 static void dwc3_get_properties(struct dwc3 *dwc)
1434 {
1435 struct device *dev = dwc->dev;
1436 u8 lpm_nyet_threshold;
1437 u8 tx_de_emphasis;
1438 u8 hird_threshold;
1439 u8 rx_thr_num_pkt = 0;
1440 u8 rx_max_burst = 0;
1441 u8 tx_thr_num_pkt = 0;
1442 u8 tx_max_burst = 0;
1443 u8 rx_thr_num_pkt_prd = 0;
1444 u8 rx_max_burst_prd = 0;
1445 u8 tx_thr_num_pkt_prd = 0;
1446 u8 tx_max_burst_prd = 0;
1447 u8 tx_fifo_resize_max_num;
1448 const char *usb_psy_name;
1449 int ret;
1450
1451 /* default to highest possible threshold */
1452 lpm_nyet_threshold = 0xf;
1453
1454 /* default to -3.5dB de-emphasis */
1455 tx_de_emphasis = 1;
1456
1457 /*
1458 * default to assert utmi_sleep_n and use maximum allowed HIRD
1459 * threshold value of 0b1100
1460 */
1461 hird_threshold = 12;
1462
1463 /*
1464 * default to a TXFIFO size large enough to fit 6 max packets. This
1465 * allows for systems with larger bus latencies to have some headroom
1466 * for endpoints that have a large bMaxBurst value.
1467 */
1468 tx_fifo_resize_max_num = 6;
1469
1470 dwc->maximum_speed = usb_get_maximum_speed(dev);
1471 dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1472 dwc->dr_mode = usb_get_dr_mode(dev);
1473 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1474
1475 dwc->sysdev_is_parent = device_property_read_bool(dev,
1476 "linux,sysdev_is_parent");
1477 if (dwc->sysdev_is_parent)
1478 dwc->sysdev = dwc->dev->parent;
1479 else
1480 dwc->sysdev = dwc->dev;
1481
1482 dwc->sys_wakeup = device_may_wakeup(dwc->sysdev);
1483
1484 ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1485 if (ret >= 0) {
1486 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1487 if (!dwc->usb_psy)
1488 dev_err(dev, "couldn't get usb power supply\n");
1489 }
1490
1491 dwc->has_lpm_erratum = device_property_read_bool(dev,
1492 "snps,has-lpm-erratum");
1493 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1494 &lpm_nyet_threshold);
1495 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1496 "snps,is-utmi-l1-suspend");
1497 device_property_read_u8(dev, "snps,hird-threshold",
1498 &hird_threshold);
1499 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1500 "snps,dis-start-transfer-quirk");
1501 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1502 "snps,usb3_lpm_capable");
1503 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1504 "snps,usb2-lpm-disable");
1505 dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1506 "snps,usb2-gadget-lpm-disable");
1507 device_property_read_u8(dev, "snps,rx-thr-num-pkt",
1508 &rx_thr_num_pkt);
1509 device_property_read_u8(dev, "snps,rx-max-burst",
1510 &rx_max_burst);
1511 device_property_read_u8(dev, "snps,tx-thr-num-pkt",
1512 &tx_thr_num_pkt);
1513 device_property_read_u8(dev, "snps,tx-max-burst",
1514 &tx_max_burst);
1515 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1516 &rx_thr_num_pkt_prd);
1517 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1518 &rx_max_burst_prd);
1519 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1520 &tx_thr_num_pkt_prd);
1521 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1522 &tx_max_burst_prd);
1523 dwc->do_fifo_resize = device_property_read_bool(dev,
1524 "tx-fifo-resize");
1525 if (dwc->do_fifo_resize)
1526 device_property_read_u8(dev, "tx-fifo-max-num",
1527 &tx_fifo_resize_max_num);
1528
1529 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1530 "snps,disable_scramble_quirk");
1531 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1532 "snps,u2exit_lfps_quirk");
1533 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1534 "snps,u2ss_inp3_quirk");
1535 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1536 "snps,req_p1p2p3_quirk");
1537 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1538 "snps,del_p1p2p3_quirk");
1539 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1540 "snps,del_phy_power_chg_quirk");
1541 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1542 "snps,lfps_filter_quirk");
1543 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1544 "snps,rx_detect_poll_quirk");
1545 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1546 "snps,dis_u3_susphy_quirk");
1547 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1548 "snps,dis_u2_susphy_quirk");
1549 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1550 "snps,dis_enblslpm_quirk");
1551 dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1552 "snps,dis-u1-entry-quirk");
1553 dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1554 "snps,dis-u2-entry-quirk");
1555 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1556 "snps,dis_rxdet_inp3_quirk");
1557 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1558 "snps,dis-u2-freeclk-exists-quirk");
1559 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1560 "snps,dis-del-phy-power-chg-quirk");
1561 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1562 "snps,dis-tx-ipgap-linecheck-quirk");
1563 dwc->resume_hs_terminations = device_property_read_bool(dev,
1564 "snps,resume-hs-terminations");
1565 dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev,
1566 "snps,ulpi-ext-vbus-drv");
1567 dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1568 "snps,parkmode-disable-ss-quirk");
1569 dwc->parkmode_disable_hs_quirk = device_property_read_bool(dev,
1570 "snps,parkmode-disable-hs-quirk");
1571 dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev,
1572 "snps,gfladj-refclk-lpm-sel-quirk");
1573
1574 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1575 "snps,tx_de_emphasis_quirk");
1576 device_property_read_u8(dev, "snps,tx_de_emphasis",
1577 &tx_de_emphasis);
1578 device_property_read_string(dev, "snps,hsphy_interface",
1579 &dwc->hsphy_interface);
1580 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1581 &dwc->fladj);
1582 device_property_read_u32(dev, "snps,ref-clock-period-ns",
1583 &dwc->ref_clk_per);
1584
1585 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1586 "snps,dis_metastability_quirk");
1587
1588 dwc->dis_split_quirk = device_property_read_bool(dev,
1589 "snps,dis-split-quirk");
1590
1591 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1592 dwc->tx_de_emphasis = tx_de_emphasis;
1593
1594 dwc->hird_threshold = hird_threshold;
1595
1596 dwc->rx_thr_num_pkt = rx_thr_num_pkt;
1597 dwc->rx_max_burst = rx_max_burst;
1598
1599 dwc->tx_thr_num_pkt = tx_thr_num_pkt;
1600 dwc->tx_max_burst = tx_max_burst;
1601
1602 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1603 dwc->rx_max_burst_prd = rx_max_burst_prd;
1604
1605 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1606 dwc->tx_max_burst_prd = tx_max_burst_prd;
1607
1608 dwc->imod_interval = 0;
1609
1610 dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1611 }
1612
1613 /* check whether the core supports IMOD */
dwc3_has_imod(struct dwc3 * dwc)1614 bool dwc3_has_imod(struct dwc3 *dwc)
1615 {
1616 return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1617 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1618 DWC3_IP_IS(DWC32);
1619 }
1620
dwc3_check_params(struct dwc3 * dwc)1621 static void dwc3_check_params(struct dwc3 *dwc)
1622 {
1623 struct device *dev = dwc->dev;
1624 unsigned int hwparam_gen =
1625 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1626
1627 /* Check for proper value of imod_interval */
1628 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1629 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1630 dwc->imod_interval = 0;
1631 }
1632
1633 /*
1634 * Workaround for STAR 9000961433 which affects only version
1635 * 3.00a of the DWC_usb3 core. This prevents the controller
1636 * interrupt from being masked while handling events. IMOD
1637 * allows us to work around this issue. Enable it for the
1638 * affected version.
1639 */
1640 if (!dwc->imod_interval &&
1641 DWC3_VER_IS(DWC3, 300A))
1642 dwc->imod_interval = 1;
1643
1644 /* Check the maximum_speed parameter */
1645 switch (dwc->maximum_speed) {
1646 case USB_SPEED_FULL:
1647 case USB_SPEED_HIGH:
1648 break;
1649 case USB_SPEED_SUPER:
1650 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1651 dev_warn(dev, "UDC doesn't support Gen 1\n");
1652 break;
1653 case USB_SPEED_SUPER_PLUS:
1654 if ((DWC3_IP_IS(DWC32) &&
1655 hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1656 (!DWC3_IP_IS(DWC32) &&
1657 hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1658 dev_warn(dev, "UDC doesn't support SSP\n");
1659 break;
1660 default:
1661 dev_err(dev, "invalid maximum_speed parameter %d\n",
1662 dwc->maximum_speed);
1663 fallthrough;
1664 case USB_SPEED_UNKNOWN:
1665 switch (hwparam_gen) {
1666 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1667 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1668 break;
1669 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1670 if (DWC3_IP_IS(DWC32))
1671 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1672 else
1673 dwc->maximum_speed = USB_SPEED_SUPER;
1674 break;
1675 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1676 dwc->maximum_speed = USB_SPEED_HIGH;
1677 break;
1678 default:
1679 dwc->maximum_speed = USB_SPEED_SUPER;
1680 break;
1681 }
1682 break;
1683 }
1684
1685 /*
1686 * Currently the controller does not have visibility into the HW
1687 * parameter to determine the maximum number of lanes the HW supports.
1688 * If the number of lanes is not specified in the device property, then
1689 * set the default to support dual-lane for DWC_usb32 and single-lane
1690 * for DWC_usb31 for super-speed-plus.
1691 */
1692 if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1693 switch (dwc->max_ssp_rate) {
1694 case USB_SSP_GEN_2x1:
1695 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1696 dev_warn(dev, "UDC only supports Gen 1\n");
1697 break;
1698 case USB_SSP_GEN_1x2:
1699 case USB_SSP_GEN_2x2:
1700 if (DWC3_IP_IS(DWC31))
1701 dev_warn(dev, "UDC only supports single lane\n");
1702 break;
1703 case USB_SSP_GEN_UNKNOWN:
1704 default:
1705 switch (hwparam_gen) {
1706 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1707 if (DWC3_IP_IS(DWC32))
1708 dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1709 else
1710 dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1711 break;
1712 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1713 if (DWC3_IP_IS(DWC32))
1714 dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1715 break;
1716 }
1717 break;
1718 }
1719 }
1720 }
1721
dwc3_get_extcon(struct dwc3 * dwc)1722 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1723 {
1724 struct device *dev = dwc->dev;
1725 struct device_node *np_phy;
1726 struct extcon_dev *edev = NULL;
1727 const char *name;
1728
1729 if (device_property_read_bool(dev, "extcon"))
1730 return extcon_get_edev_by_phandle(dev, 0);
1731
1732 /*
1733 * Device tree platforms should get extcon via phandle.
1734 * On ACPI platforms, we get the name from a device property.
1735 * This device property is for kernel internal use only and
1736 * is expected to be set by the glue code.
1737 */
1738 if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1739 return extcon_get_extcon_dev(name);
1740
1741 /*
1742 * Check explicitly if "usb-role-switch" is used since
1743 * extcon_find_edev_by_node() can not be used to check the absence of
1744 * an extcon device. In the absence of an device it will always return
1745 * EPROBE_DEFER.
1746 */
1747 if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) &&
1748 device_property_read_bool(dev, "usb-role-switch"))
1749 return NULL;
1750
1751 /*
1752 * Try to get an extcon device from the USB PHY controller's "port"
1753 * node. Check if it has the "port" node first, to avoid printing the
1754 * error message from underlying code, as it's a valid case: extcon
1755 * device (and "port" node) may be missing in case of "usb-role-switch"
1756 * or OTG mode.
1757 */
1758 np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1759 if (of_graph_is_present(np_phy)) {
1760 struct device_node *np_conn;
1761
1762 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1763 if (np_conn)
1764 edev = extcon_find_edev_by_node(np_conn);
1765 of_node_put(np_conn);
1766 }
1767 of_node_put(np_phy);
1768
1769 return edev;
1770 }
1771
dwc3_get_clocks(struct dwc3 * dwc)1772 static int dwc3_get_clocks(struct dwc3 *dwc)
1773 {
1774 struct device *dev = dwc->dev;
1775
1776 if (!dev->of_node)
1777 return 0;
1778
1779 /*
1780 * Clocks are optional, but new DT platforms should support all clocks
1781 * as required by the DT-binding.
1782 * Some devices have different clock names in legacy device trees,
1783 * check for them to retain backwards compatibility.
1784 */
1785 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1786 if (IS_ERR(dwc->bus_clk)) {
1787 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1788 "could not get bus clock\n");
1789 }
1790
1791 if (dwc->bus_clk == NULL) {
1792 dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1793 if (IS_ERR(dwc->bus_clk)) {
1794 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1795 "could not get bus clock\n");
1796 }
1797 }
1798
1799 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1800 if (IS_ERR(dwc->ref_clk)) {
1801 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1802 "could not get ref clock\n");
1803 }
1804
1805 if (dwc->ref_clk == NULL) {
1806 dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1807 if (IS_ERR(dwc->ref_clk)) {
1808 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1809 "could not get ref clock\n");
1810 }
1811 }
1812
1813 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1814 if (IS_ERR(dwc->susp_clk)) {
1815 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1816 "could not get suspend clock\n");
1817 }
1818
1819 if (dwc->susp_clk == NULL) {
1820 dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1821 if (IS_ERR(dwc->susp_clk)) {
1822 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1823 "could not get suspend clock\n");
1824 }
1825 }
1826
1827 return 0;
1828 }
1829
dwc3_probe(struct platform_device * pdev)1830 static int dwc3_probe(struct platform_device *pdev)
1831 {
1832 struct device *dev = &pdev->dev;
1833 struct resource *res, dwc_res;
1834 void __iomem *regs;
1835 struct dwc3 *dwc;
1836 int ret;
1837
1838 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1839 if (!dwc)
1840 return -ENOMEM;
1841
1842 dwc->dev = dev;
1843
1844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1845 if (!res) {
1846 dev_err(dev, "missing memory resource\n");
1847 return -ENODEV;
1848 }
1849
1850 dwc->xhci_resources[0].start = res->start;
1851 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1852 DWC3_XHCI_REGS_END;
1853 dwc->xhci_resources[0].flags = res->flags;
1854 dwc->xhci_resources[0].name = res->name;
1855
1856 /*
1857 * Request memory region but exclude xHCI regs,
1858 * since it will be requested by the xhci-plat driver.
1859 */
1860 dwc_res = *res;
1861 dwc_res.start += DWC3_GLOBALS_REGS_START;
1862
1863 if (dev->of_node) {
1864 struct device_node *parent = of_get_parent(dev->of_node);
1865
1866 if (of_device_is_compatible(parent, "realtek,rtd-dwc3")) {
1867 dwc_res.start -= DWC3_GLOBALS_REGS_START;
1868 dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
1869 }
1870
1871 of_node_put(parent);
1872 }
1873
1874 regs = devm_ioremap_resource(dev, &dwc_res);
1875 if (IS_ERR(regs))
1876 return PTR_ERR(regs);
1877
1878 dwc->regs = regs;
1879 dwc->regs_size = resource_size(&dwc_res);
1880
1881 dwc3_get_properties(dwc);
1882
1883 dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1884 if (IS_ERR(dwc->reset)) {
1885 ret = PTR_ERR(dwc->reset);
1886 goto err_put_psy;
1887 }
1888
1889 ret = dwc3_get_clocks(dwc);
1890 if (ret)
1891 goto err_put_psy;
1892
1893 ret = reset_control_deassert(dwc->reset);
1894 if (ret)
1895 goto err_put_psy;
1896
1897 ret = dwc3_clk_enable(dwc);
1898 if (ret)
1899 goto err_assert_reset;
1900
1901 if (!dwc3_core_is_valid(dwc)) {
1902 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1903 ret = -ENODEV;
1904 goto err_disable_clks;
1905 }
1906
1907 platform_set_drvdata(pdev, dwc);
1908 dwc3_cache_hwparams(dwc);
1909
1910 if (!dwc->sysdev_is_parent &&
1911 DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
1912 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1913 if (ret)
1914 goto err_disable_clks;
1915 }
1916
1917 spin_lock_init(&dwc->lock);
1918 mutex_init(&dwc->mutex);
1919
1920 pm_runtime_get_noresume(dev);
1921 pm_runtime_set_active(dev);
1922 pm_runtime_use_autosuspend(dev);
1923 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1924 pm_runtime_enable(dev);
1925
1926 pm_runtime_forbid(dev);
1927
1928 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1929 if (ret) {
1930 dev_err(dwc->dev, "failed to allocate event buffers\n");
1931 ret = -ENOMEM;
1932 goto err_allow_rpm;
1933 }
1934
1935 dwc->edev = dwc3_get_extcon(dwc);
1936 if (IS_ERR(dwc->edev)) {
1937 ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n");
1938 goto err_free_event_buffers;
1939 }
1940
1941 ret = dwc3_get_dr_mode(dwc);
1942 if (ret)
1943 goto err_free_event_buffers;
1944
1945 ret = dwc3_core_init(dwc);
1946 if (ret) {
1947 dev_err_probe(dev, ret, "failed to initialize core\n");
1948 goto err_free_event_buffers;
1949 }
1950
1951 dwc3_check_params(dwc);
1952 dwc3_debugfs_init(dwc);
1953
1954 ret = dwc3_core_init_mode(dwc);
1955 if (ret)
1956 goto err_exit_debugfs;
1957
1958 pm_runtime_put(dev);
1959
1960 dma_set_max_seg_size(dev, UINT_MAX);
1961
1962 return 0;
1963
1964 err_exit_debugfs:
1965 dwc3_debugfs_exit(dwc);
1966 dwc3_event_buffers_cleanup(dwc);
1967 dwc3_phy_power_off(dwc);
1968 dwc3_phy_exit(dwc);
1969 dwc3_ulpi_exit(dwc);
1970 err_free_event_buffers:
1971 dwc3_free_event_buffers(dwc);
1972 err_allow_rpm:
1973 pm_runtime_allow(dev);
1974 pm_runtime_disable(dev);
1975 pm_runtime_dont_use_autosuspend(dev);
1976 pm_runtime_set_suspended(dev);
1977 pm_runtime_put_noidle(dev);
1978 err_disable_clks:
1979 dwc3_clk_disable(dwc);
1980 err_assert_reset:
1981 reset_control_assert(dwc->reset);
1982 err_put_psy:
1983 if (dwc->usb_psy)
1984 power_supply_put(dwc->usb_psy);
1985
1986 return ret;
1987 }
1988
dwc3_remove(struct platform_device * pdev)1989 static void dwc3_remove(struct platform_device *pdev)
1990 {
1991 struct dwc3 *dwc = platform_get_drvdata(pdev);
1992
1993 pm_runtime_get_sync(&pdev->dev);
1994
1995 dwc3_core_exit_mode(dwc);
1996 dwc3_debugfs_exit(dwc);
1997
1998 dwc3_core_exit(dwc);
1999 dwc3_ulpi_exit(dwc);
2000
2001 pm_runtime_allow(&pdev->dev);
2002 pm_runtime_disable(&pdev->dev);
2003 pm_runtime_dont_use_autosuspend(&pdev->dev);
2004 pm_runtime_put_noidle(&pdev->dev);
2005 /*
2006 * HACK: Clear the driver data, which is currently accessed by parent
2007 * glue drivers, before allowing the parent to suspend.
2008 */
2009 platform_set_drvdata(pdev, NULL);
2010 pm_runtime_set_suspended(&pdev->dev);
2011
2012 dwc3_free_event_buffers(dwc);
2013
2014 if (dwc->usb_psy)
2015 power_supply_put(dwc->usb_psy);
2016 }
2017
2018 #ifdef CONFIG_PM
dwc3_core_init_for_resume(struct dwc3 * dwc)2019 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
2020 {
2021 int ret;
2022
2023 ret = reset_control_deassert(dwc->reset);
2024 if (ret)
2025 return ret;
2026
2027 ret = dwc3_clk_enable(dwc);
2028 if (ret)
2029 goto assert_reset;
2030
2031 ret = dwc3_core_init(dwc);
2032 if (ret)
2033 goto disable_clks;
2034
2035 return 0;
2036
2037 disable_clks:
2038 dwc3_clk_disable(dwc);
2039 assert_reset:
2040 reset_control_assert(dwc->reset);
2041
2042 return ret;
2043 }
2044
dwc3_suspend_common(struct dwc3 * dwc,pm_message_t msg)2045 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
2046 {
2047 unsigned long flags;
2048 u32 reg;
2049
2050 switch (dwc->current_dr_role) {
2051 case DWC3_GCTL_PRTCAP_DEVICE:
2052 if (pm_runtime_suspended(dwc->dev))
2053 break;
2054 dwc3_gadget_suspend(dwc);
2055 synchronize_irq(dwc->irq_gadget);
2056 dwc3_core_exit(dwc);
2057 break;
2058 case DWC3_GCTL_PRTCAP_HOST:
2059 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2060 dwc3_core_exit(dwc);
2061 break;
2062 }
2063
2064 /* Let controller to suspend HSPHY before PHY driver suspends */
2065 if (dwc->dis_u2_susphy_quirk ||
2066 dwc->dis_enblslpm_quirk) {
2067 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2068 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
2069 DWC3_GUSB2PHYCFG_SUSPHY;
2070 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2071
2072 /* Give some time for USB2 PHY to suspend */
2073 usleep_range(5000, 6000);
2074 }
2075
2076 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2077 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2078 break;
2079 case DWC3_GCTL_PRTCAP_OTG:
2080 /* do nothing during runtime_suspend */
2081 if (PMSG_IS_AUTO(msg))
2082 break;
2083
2084 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2085 spin_lock_irqsave(&dwc->lock, flags);
2086 dwc3_gadget_suspend(dwc);
2087 spin_unlock_irqrestore(&dwc->lock, flags);
2088 synchronize_irq(dwc->irq_gadget);
2089 }
2090
2091 dwc3_otg_exit(dwc);
2092 dwc3_core_exit(dwc);
2093 break;
2094 default:
2095 /* do nothing */
2096 break;
2097 }
2098
2099 return 0;
2100 }
2101
dwc3_resume_common(struct dwc3 * dwc,pm_message_t msg)2102 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2103 {
2104 unsigned long flags;
2105 int ret;
2106 u32 reg;
2107
2108 switch (dwc->current_dr_role) {
2109 case DWC3_GCTL_PRTCAP_DEVICE:
2110 ret = dwc3_core_init_for_resume(dwc);
2111 if (ret)
2112 return ret;
2113
2114 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2115 dwc3_gadget_resume(dwc);
2116 break;
2117 case DWC3_GCTL_PRTCAP_HOST:
2118 if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) {
2119 ret = dwc3_core_init_for_resume(dwc);
2120 if (ret)
2121 return ret;
2122 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2123 break;
2124 }
2125 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2126 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2127 if (dwc->dis_u2_susphy_quirk)
2128 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2129
2130 if (dwc->dis_enblslpm_quirk)
2131 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2132
2133 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2134
2135 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2136 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2137 break;
2138 case DWC3_GCTL_PRTCAP_OTG:
2139 /* nothing to do on runtime_resume */
2140 if (PMSG_IS_AUTO(msg))
2141 break;
2142
2143 ret = dwc3_core_init_for_resume(dwc);
2144 if (ret)
2145 return ret;
2146
2147 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2148
2149 dwc3_otg_init(dwc);
2150 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2151 dwc3_otg_host_init(dwc);
2152 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2153 spin_lock_irqsave(&dwc->lock, flags);
2154 dwc3_gadget_resume(dwc);
2155 spin_unlock_irqrestore(&dwc->lock, flags);
2156 }
2157
2158 break;
2159 default:
2160 /* do nothing */
2161 break;
2162 }
2163
2164 return 0;
2165 }
2166
dwc3_runtime_checks(struct dwc3 * dwc)2167 static int dwc3_runtime_checks(struct dwc3 *dwc)
2168 {
2169 switch (dwc->current_dr_role) {
2170 case DWC3_GCTL_PRTCAP_DEVICE:
2171 if (dwc->connected)
2172 return -EBUSY;
2173 break;
2174 case DWC3_GCTL_PRTCAP_HOST:
2175 default:
2176 /* do nothing */
2177 break;
2178 }
2179
2180 return 0;
2181 }
2182
dwc3_runtime_suspend(struct device * dev)2183 static int dwc3_runtime_suspend(struct device *dev)
2184 {
2185 struct dwc3 *dwc = dev_get_drvdata(dev);
2186 int ret;
2187
2188 if (dwc3_runtime_checks(dwc))
2189 return -EBUSY;
2190
2191 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2192 if (ret)
2193 return ret;
2194
2195 return 0;
2196 }
2197
dwc3_runtime_resume(struct device * dev)2198 static int dwc3_runtime_resume(struct device *dev)
2199 {
2200 struct dwc3 *dwc = dev_get_drvdata(dev);
2201 int ret;
2202
2203 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2204 if (ret)
2205 return ret;
2206
2207 switch (dwc->current_dr_role) {
2208 case DWC3_GCTL_PRTCAP_DEVICE:
2209 dwc3_gadget_process_pending_events(dwc);
2210 break;
2211 case DWC3_GCTL_PRTCAP_HOST:
2212 default:
2213 /* do nothing */
2214 break;
2215 }
2216
2217 pm_runtime_mark_last_busy(dev);
2218
2219 return 0;
2220 }
2221
dwc3_runtime_idle(struct device * dev)2222 static int dwc3_runtime_idle(struct device *dev)
2223 {
2224 struct dwc3 *dwc = dev_get_drvdata(dev);
2225
2226 switch (dwc->current_dr_role) {
2227 case DWC3_GCTL_PRTCAP_DEVICE:
2228 if (dwc3_runtime_checks(dwc))
2229 return -EBUSY;
2230 break;
2231 case DWC3_GCTL_PRTCAP_HOST:
2232 default:
2233 /* do nothing */
2234 break;
2235 }
2236
2237 pm_runtime_mark_last_busy(dev);
2238 pm_runtime_autosuspend(dev);
2239
2240 return 0;
2241 }
2242 #endif /* CONFIG_PM */
2243
2244 #ifdef CONFIG_PM_SLEEP
dwc3_suspend(struct device * dev)2245 static int dwc3_suspend(struct device *dev)
2246 {
2247 struct dwc3 *dwc = dev_get_drvdata(dev);
2248 int ret;
2249
2250 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2251 if (ret)
2252 return ret;
2253
2254 pinctrl_pm_select_sleep_state(dev);
2255
2256 return 0;
2257 }
2258
dwc3_resume(struct device * dev)2259 static int dwc3_resume(struct device *dev)
2260 {
2261 struct dwc3 *dwc = dev_get_drvdata(dev);
2262 int ret;
2263
2264 pinctrl_pm_select_default_state(dev);
2265
2266 ret = dwc3_resume_common(dwc, PMSG_RESUME);
2267 if (ret)
2268 return ret;
2269
2270 pm_runtime_disable(dev);
2271 pm_runtime_set_active(dev);
2272 pm_runtime_enable(dev);
2273
2274 return 0;
2275 }
2276
dwc3_complete(struct device * dev)2277 static void dwc3_complete(struct device *dev)
2278 {
2279 struct dwc3 *dwc = dev_get_drvdata(dev);
2280 u32 reg;
2281
2282 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2283 dwc->dis_split_quirk) {
2284 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2285 reg |= DWC3_GUCTL3_SPLITDISABLE;
2286 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2287 }
2288 }
2289 #else
2290 #define dwc3_complete NULL
2291 #endif /* CONFIG_PM_SLEEP */
2292
2293 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2294 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2295 .complete = dwc3_complete,
2296 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2297 dwc3_runtime_idle)
2298 };
2299
2300 #ifdef CONFIG_OF
2301 static const struct of_device_id of_dwc3_match[] = {
2302 {
2303 .compatible = "snps,dwc3"
2304 },
2305 {
2306 .compatible = "synopsys,dwc3"
2307 },
2308 { },
2309 };
2310 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2311 #endif
2312
2313 #ifdef CONFIG_ACPI
2314
2315 #define ACPI_ID_INTEL_BSW "808622B7"
2316
2317 static const struct acpi_device_id dwc3_acpi_match[] = {
2318 { ACPI_ID_INTEL_BSW, 0 },
2319 { },
2320 };
2321 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2322 #endif
2323
2324 static struct platform_driver dwc3_driver = {
2325 .probe = dwc3_probe,
2326 .remove_new = dwc3_remove,
2327 .driver = {
2328 .name = "dwc3",
2329 .of_match_table = of_match_ptr(of_dwc3_match),
2330 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2331 .pm = &dwc3_dev_pm_ops,
2332 },
2333 };
2334
2335 module_platform_driver(dwc3_driver);
2336
2337 MODULE_ALIAS("platform:dwc3");
2338 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2339 MODULE_LICENSE("GPL v2");
2340 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2341