15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 260f010171SAndrey Smirnov #include <linux/of_graph.h> 27404905a6SHeikki Krogerus #include <linux/acpi.h> 286344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 29fe8abf33SMasahiro Yamada #include <linux/reset.h> 307bee3188SBalaji Prakash J #include <linux/bitfield.h> 3172246da4SFelipe Balbi 3272246da4SFelipe Balbi #include <linux/usb/ch9.h> 3372246da4SFelipe Balbi #include <linux/usb/gadget.h> 34f7e846f0SFelipe Balbi #include <linux/usb/of.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3672246da4SFelipe Balbi 3772246da4SFelipe Balbi #include "core.h" 3872246da4SFelipe Balbi #include "gadget.h" 3972246da4SFelipe Balbi #include "io.h" 4072246da4SFelipe Balbi 4172246da4SFelipe Balbi #include "debug.h" 4272246da4SFelipe Balbi 43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 448300dd23SFelipe Balbi 459d6173e1SThinh Nguyen /** 469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 479d6173e1SThinh Nguyen * @dwc: pointer to our context structure 489d6173e1SThinh Nguyen */ 499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 509d6173e1SThinh Nguyen { 519d6173e1SThinh Nguyen enum usb_dr_mode mode; 529d6173e1SThinh Nguyen struct device *dev = dwc->dev; 539d6173e1SThinh Nguyen unsigned int hw_mode; 549d6173e1SThinh Nguyen 559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 579d6173e1SThinh Nguyen 589d6173e1SThinh Nguyen mode = dwc->dr_mode; 599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 609d6173e1SThinh Nguyen 619d6173e1SThinh Nguyen switch (hw_mode) { 629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 649d6173e1SThinh Nguyen dev_err(dev, 659d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 669d6173e1SThinh Nguyen return -EINVAL; 679d6173e1SThinh Nguyen } 689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 699d6173e1SThinh Nguyen break; 709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 729d6173e1SThinh Nguyen dev_err(dev, 739d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 749d6173e1SThinh Nguyen return -EINVAL; 759d6173e1SThinh Nguyen } 769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 779d6173e1SThinh Nguyen break; 789d6173e1SThinh Nguyen default: 799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 83a7700468SThinh Nguyen 84a7700468SThinh Nguyen /* 8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 88a7700468SThinh Nguyen */ 890f010171SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev && 908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 949d6173e1SThinh Nguyen } 959d6173e1SThinh Nguyen 969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 979d6173e1SThinh Nguyen dev_warn(dev, 989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 1009d6173e1SThinh Nguyen 1019d6173e1SThinh Nguyen dwc->dr_mode = mode; 1029d6173e1SThinh Nguyen } 1039d6173e1SThinh Nguyen 1049d6173e1SThinh Nguyen return 0; 1059d6173e1SThinh Nguyen } 1069d6173e1SThinh Nguyen 107f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1083140e8cbSSebastian Andrzej Siewior { 1093140e8cbSSebastian Andrzej Siewior u32 reg; 1103140e8cbSSebastian Andrzej Siewior 1113140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1123140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1133140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1143140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115c4a5153eSManu Gautam 116c4a5153eSManu Gautam dwc->current_dr_role = mode; 11741ce1456SRoger Quadros } 1186b3261a2SRoger Quadros 11941ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12041ce1456SRoger Quadros { 12141ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12241ce1456SRoger Quadros unsigned long flags; 12341ce1456SRoger Quadros int ret; 124f580170fSYu Chen u32 reg; 12541ce1456SRoger Quadros 126f88359e1SYu Chen mutex_lock(&dwc->mutex); 127f88359e1SYu Chen 128c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 129c2cd3452SMartin Kepplinger 130f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 131f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 132f09cc79bSRoger Quadros 13341ce1456SRoger Quadros if (!dwc->desired_dr_role) 134c2cd3452SMartin Kepplinger goto out; 13541ce1456SRoger Quadros 13641ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 137c2cd3452SMartin Kepplinger goto out; 13841ce1456SRoger Quadros 139f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 140c2cd3452SMartin Kepplinger goto out; 14141ce1456SRoger Quadros 14241ce1456SRoger Quadros switch (dwc->current_dr_role) { 14341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14441ce1456SRoger Quadros dwc3_host_exit(dwc); 14541ce1456SRoger Quadros break; 14641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14741ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14841ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14941ce1456SRoger Quadros break; 150f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 151f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 152f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 153f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 154f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 155f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 156f09cc79bSRoger Quadros break; 15741ce1456SRoger Quadros default: 15841ce1456SRoger Quadros break; 15941ce1456SRoger Quadros } 16041ce1456SRoger Quadros 161f88359e1SYu Chen /* For DRD host or device mode only */ 162f88359e1SYu Chen if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { 163f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 164f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 165f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 166f88359e1SYu Chen 167f88359e1SYu Chen /* 168f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 169f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 170f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 171f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 172f88359e1SYu Chen */ 173f88359e1SYu Chen msleep(100); 174f88359e1SYu Chen 175f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 176f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 177f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 178f88359e1SYu Chen } 179f88359e1SYu Chen 18041ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18141ce1456SRoger Quadros 18241ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18341ce1456SRoger Quadros 18441ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 18541ce1456SRoger Quadros 18641ce1456SRoger Quadros switch (dwc->desired_dr_role) { 18741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 18841ce1456SRoger Quadros ret = dwc3_host_init(dwc); 189958d1a4cSFelipe Balbi if (ret) { 19041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 191958d1a4cSFelipe Balbi } else { 192958d1a4cSFelipe Balbi if (dwc->usb2_phy) 193958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 194958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 195644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 196f580170fSYu Chen if (dwc->dis_split_quirk) { 197f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 198f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 199f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 200f580170fSYu Chen } 201958d1a4cSFelipe Balbi } 20241ce1456SRoger Quadros break; 20341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 204f88359e1SYu Chen dwc3_core_soft_reset(dwc); 205f88359e1SYu Chen 20641ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 207958d1a4cSFelipe Balbi 208958d1a4cSFelipe Balbi if (dwc->usb2_phy) 209958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 210958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 211644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 212958d1a4cSFelipe Balbi 21341ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21441ce1456SRoger Quadros if (ret) 21541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 21641ce1456SRoger Quadros break; 217f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 218f09cc79bSRoger Quadros dwc3_otg_init(dwc); 219f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 220f09cc79bSRoger Quadros break; 22141ce1456SRoger Quadros default: 22241ce1456SRoger Quadros break; 22341ce1456SRoger Quadros } 224f09cc79bSRoger Quadros 225c2cd3452SMartin Kepplinger out: 226c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 227c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 228f88359e1SYu Chen mutex_unlock(&dwc->mutex); 22941ce1456SRoger Quadros } 23041ce1456SRoger Quadros 23141ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23241ce1456SRoger Quadros { 23341ce1456SRoger Quadros unsigned long flags; 23441ce1456SRoger Quadros 235dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 236dc336b19SLi Jun return; 237dc336b19SLi Jun 23841ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 23941ce1456SRoger Quadros dwc->desired_dr_role = mode; 24041ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24141ce1456SRoger Quadros 242084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2433140e8cbSSebastian Andrzej Siewior } 2448300dd23SFelipe Balbi 245cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 246cf6d867dSFelipe Balbi { 247cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 248cf6d867dSFelipe Balbi u32 reg; 249cf6d867dSFelipe Balbi 250cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 251cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 252cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 253cf6d867dSFelipe Balbi 254cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 255cf6d867dSFelipe Balbi 256cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 257cf6d867dSFelipe Balbi } 258cf6d867dSFelipe Balbi 25972246da4SFelipe Balbi /** 26072246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26172246da4SFelipe Balbi * @dwc: pointer to our context structure 26272246da4SFelipe Balbi */ 2630066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 26472246da4SFelipe Balbi { 26572246da4SFelipe Balbi u32 reg; 266f59dcab1SFelipe Balbi int retries = 1000; 26772246da4SFelipe Balbi 268f59dcab1SFelipe Balbi /* 269f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 270f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 271f59dcab1SFelipe Balbi * host-only mode, then we can return early. 272f59dcab1SFelipe Balbi */ 273c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27457303488SKishon Vijay Abraham I return 0; 275f59dcab1SFelipe Balbi 276f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 277f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 278f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP; 279f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg); 280f59dcab1SFelipe Balbi 2814749e0e6SThinh Nguyen /* 2824749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2834749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2844749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2854749e0e6SThinh Nguyen * for 10 times instead. 2864749e0e6SThinh Nguyen */ 2879af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2884749e0e6SThinh Nguyen retries = 10; 2894749e0e6SThinh Nguyen 290f59dcab1SFelipe Balbi do { 291f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 292f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 293fab38333SThinh Nguyen goto done; 294f59dcab1SFelipe Balbi 2959af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2964749e0e6SThinh Nguyen msleep(20); 2974749e0e6SThinh Nguyen else 298f59dcab1SFelipe Balbi udelay(1); 299f59dcab1SFelipe Balbi } while (--retries); 300f59dcab1SFelipe Balbi 301859bdc35SMayank Rana dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 302f59dcab1SFelipe Balbi return -ETIMEDOUT; 303fab38333SThinh Nguyen 304fab38333SThinh Nguyen done: 305fab38333SThinh Nguyen /* 3064749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3074749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3084749e0e6SThinh Nguyen * domain (synchronization delay). 309fab38333SThinh Nguyen */ 3109af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 311fab38333SThinh Nguyen msleep(50); 312fab38333SThinh Nguyen 313fab38333SThinh Nguyen return 0; 31472246da4SFelipe Balbi } 31572246da4SFelipe Balbi 316db2be4e9SNikhil Badola /* 317db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 318db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 319db2be4e9SNikhil Badola */ 320bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 321db2be4e9SNikhil Badola { 322db2be4e9SNikhil Badola u32 reg; 323db2be4e9SNikhil Badola u32 dft; 324db2be4e9SNikhil Badola 3259af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 326db2be4e9SNikhil Badola return; 327db2be4e9SNikhil Badola 328bcdb3272SFelipe Balbi if (dwc->fladj == 0) 329db2be4e9SNikhil Badola return; 330db2be4e9SNikhil Badola 331db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 332db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 333a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 334db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 335bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 336db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 337db2be4e9SNikhil Badola } 338db2be4e9SNikhil Badola } 339db2be4e9SNikhil Badola 340c5cc74e8SHeikki Krogerus /** 3417bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3427bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3437bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3447bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3457bee3188SBalaji Prakash J * register. 3467bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3477bee3188SBalaji Prakash J */ 3487bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3497bee3188SBalaji Prakash J { 3505114c3eeSSean Anderson unsigned long period; 351596c8785SSean Anderson unsigned long fladj; 352596c8785SSean Anderson unsigned long decr; 3535114c3eeSSean Anderson unsigned long rate; 3547bee3188SBalaji Prakash J u32 reg; 3557bee3188SBalaji Prakash J 3565114c3eeSSean Anderson if (dwc->ref_clk) { 3575114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3585114c3eeSSean Anderson if (!rate) 3597bee3188SBalaji Prakash J return; 3605114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3615114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3625114c3eeSSean Anderson period = dwc->ref_clk_per; 363596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3645114c3eeSSean Anderson } else { 3655114c3eeSSean Anderson return; 3665114c3eeSSean Anderson } 3677bee3188SBalaji Prakash J 3687bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3697bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3705114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3717bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3727bee3188SBalaji Prakash J 373596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 374596c8785SSean Anderson return; 375596c8785SSean Anderson 376596c8785SSean Anderson /* 377596c8785SSean Anderson * The calculation below is 378596c8785SSean Anderson * 379596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 380596c8785SSean Anderson * 381596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 382596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 383596c8785SSean Anderson * neither does rate * period). 384596c8785SSean Anderson * 385596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 386596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 387596c8785SSean Anderson * the division when calculating rate or period (whichever one was 388596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 389596c8785SSean Anderson * scale it to units of 8 ppm. 390596c8785SSean Anderson */ 391596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 392596c8785SSean Anderson fladj -= 125000; 393596c8785SSean Anderson 394596c8785SSean Anderson /* 395596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 396596c8785SSean Anderson */ 397596c8785SSean Anderson decr = 480000000 / rate; 398596c8785SSean Anderson 399596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 400596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 401596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 402596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 403596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 404596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 405596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 406596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 407596c8785SSean Anderson } 4087bee3188SBalaji Prakash J 4097bee3188SBalaji Prakash J /** 41072246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 41172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 41272246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 41372246da4SFelipe Balbi */ 41472246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 41572246da4SFelipe Balbi struct dwc3_event_buffer *evt) 41672246da4SFelipe Balbi { 417d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 41872246da4SFelipe Balbi } 41972246da4SFelipe Balbi 42072246da4SFelipe Balbi /** 4211d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 42272246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42372246da4SFelipe Balbi * @length: size of the event buffer 42472246da4SFelipe Balbi * 4251d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 42672246da4SFelipe Balbi * otherwise ERR_PTR(errno). 42772246da4SFelipe Balbi */ 42867d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 429ca80ca61SKushagra Verma unsigned int length) 43072246da4SFelipe Balbi { 43172246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43272246da4SFelipe Balbi 433380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 43472246da4SFelipe Balbi if (!evt) 43572246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 43672246da4SFelipe Balbi 43772246da4SFelipe Balbi evt->dwc = dwc; 43872246da4SFelipe Balbi evt->length = length; 439d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 440d9fa4c63SJohn Youn if (!evt->cache) 441d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 442d9fa4c63SJohn Youn 443d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 44472246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 445e32672f0SFelipe Balbi if (!evt->buf) 44672246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44772246da4SFelipe Balbi 44872246da4SFelipe Balbi return evt; 44972246da4SFelipe Balbi } 45072246da4SFelipe Balbi 45172246da4SFelipe Balbi /** 45272246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 45372246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 45472246da4SFelipe Balbi */ 45572246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 45672246da4SFelipe Balbi { 45772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 45872246da4SFelipe Balbi 459696c8b12SFelipe Balbi evt = dwc->ev_buf; 46064b6c8a7SAnton Tikhomirov if (evt) 46172246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 46272246da4SFelipe Balbi } 46372246da4SFelipe Balbi 46472246da4SFelipe Balbi /** 46572246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4661d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 46772246da4SFelipe Balbi * @length: size of event buffer 46872246da4SFelipe Balbi * 4691d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 47072246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 47172246da4SFelipe Balbi */ 472ca80ca61SKushagra Verma static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 47372246da4SFelipe Balbi { 47472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 47572246da4SFelipe Balbi 47672246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 47772246da4SFelipe Balbi if (IS_ERR(evt)) { 47872246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 47972246da4SFelipe Balbi return PTR_ERR(evt); 48072246da4SFelipe Balbi } 481696c8b12SFelipe Balbi dwc->ev_buf = evt; 48272246da4SFelipe Balbi 48372246da4SFelipe Balbi return 0; 48472246da4SFelipe Balbi } 48572246da4SFelipe Balbi 48672246da4SFelipe Balbi /** 48772246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4881d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 48972246da4SFelipe Balbi * 49072246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 49172246da4SFelipe Balbi */ 492f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 49372246da4SFelipe Balbi { 49472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 49572246da4SFelipe Balbi 496696c8b12SFelipe Balbi evt = dwc->ev_buf; 4977acd85e0SPaul Zimmerman evt->lpos = 0; 498660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 49972246da4SFelipe Balbi lower_32_bits(evt->dma)); 500660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 50172246da4SFelipe Balbi upper_32_bits(evt->dma)); 502660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 50368d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 504660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 50572246da4SFelipe Balbi 50672246da4SFelipe Balbi return 0; 50772246da4SFelipe Balbi } 50872246da4SFelipe Balbi 509f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 51072246da4SFelipe Balbi { 51172246da4SFelipe Balbi struct dwc3_event_buffer *evt; 51272246da4SFelipe Balbi 513696c8b12SFelipe Balbi evt = dwc->ev_buf; 5147acd85e0SPaul Zimmerman 5157acd85e0SPaul Zimmerman evt->lpos = 0; 5167acd85e0SPaul Zimmerman 517660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 518660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 519660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 52068d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 521660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 52272246da4SFelipe Balbi } 52372246da4SFelipe Balbi 5240ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5250ffcaf37SFelipe Balbi { 5260ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5270ffcaf37SFelipe Balbi return 0; 5280ffcaf37SFelipe Balbi 5290ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5300ffcaf37SFelipe Balbi return 0; 5310ffcaf37SFelipe Balbi 5320ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5330ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5340ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5350ffcaf37SFelipe Balbi return -ENOMEM; 5360ffcaf37SFelipe Balbi 5370ffcaf37SFelipe Balbi return 0; 5380ffcaf37SFelipe Balbi } 5390ffcaf37SFelipe Balbi 5400ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5410ffcaf37SFelipe Balbi { 5420ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5430ffcaf37SFelipe Balbi u32 param; 5440ffcaf37SFelipe Balbi int ret; 5450ffcaf37SFelipe Balbi 5460ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5470ffcaf37SFelipe Balbi return 0; 5480ffcaf37SFelipe Balbi 5490ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5500ffcaf37SFelipe Balbi return 0; 5510ffcaf37SFelipe Balbi 5520ffcaf37SFelipe Balbi /* should never fall here */ 5530ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5540ffcaf37SFelipe Balbi return 0; 5550ffcaf37SFelipe Balbi 556d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5570ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5580ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 559d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 560d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5610ffcaf37SFelipe Balbi ret = -EFAULT; 5620ffcaf37SFelipe Balbi goto err0; 5630ffcaf37SFelipe Balbi } 5640ffcaf37SFelipe Balbi 5650ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5660ffcaf37SFelipe Balbi 5670ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5680ffcaf37SFelipe Balbi 5690ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5700ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5710ffcaf37SFelipe Balbi if (ret < 0) 5720ffcaf37SFelipe Balbi goto err1; 5730ffcaf37SFelipe Balbi 5740ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5750ffcaf37SFelipe Balbi 5760ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5770ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5780ffcaf37SFelipe Balbi if (ret < 0) 5790ffcaf37SFelipe Balbi goto err1; 5800ffcaf37SFelipe Balbi 5810ffcaf37SFelipe Balbi return 0; 5820ffcaf37SFelipe Balbi 5830ffcaf37SFelipe Balbi err1: 584d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5850ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5860ffcaf37SFelipe Balbi 5870ffcaf37SFelipe Balbi err0: 5880ffcaf37SFelipe Balbi return ret; 5890ffcaf37SFelipe Balbi } 5900ffcaf37SFelipe Balbi 5910ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5920ffcaf37SFelipe Balbi { 5930ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5940ffcaf37SFelipe Balbi return; 5950ffcaf37SFelipe Balbi 5960ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5970ffcaf37SFelipe Balbi return; 5980ffcaf37SFelipe Balbi 5990ffcaf37SFelipe Balbi /* should never fall here */ 6000ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6010ffcaf37SFelipe Balbi return; 6020ffcaf37SFelipe Balbi 603d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6040ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6050ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6060ffcaf37SFelipe Balbi } 6070ffcaf37SFelipe Balbi 608789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 609789451f6SFelipe Balbi { 610789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 611789451f6SFelipe Balbi 61247d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 613789451f6SFelipe Balbi } 614789451f6SFelipe Balbi 61541ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 61626ceca97SFelipe Balbi { 61726ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 61826ceca97SFelipe Balbi 61926ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 62026ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 62126ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 62226ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 62326ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 62426ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 62526ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 62626ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 62726ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 62816710380SThinh Nguyen 62916710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 63016710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 63126ceca97SFelipe Balbi } 63226ceca97SFelipe Balbi 63398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 63498112041SRoger Quadros { 63598112041SRoger Quadros int intf; 63698112041SRoger Quadros int ret = 0; 63798112041SRoger Quadros 63898112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 63998112041SRoger Quadros 64098112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 64198112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 64298112041SRoger Quadros dwc->hsphy_interface && 64398112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 64498112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 64598112041SRoger Quadros 64698112041SRoger Quadros return ret; 64798112041SRoger Quadros } 64898112041SRoger Quadros 64972246da4SFelipe Balbi /** 650b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 651b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 65288bc9d19SHeikki Krogerus * 65388bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 65488bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 65588bc9d19SHeikki Krogerus * the core in dwc3_core_init. 656b5a65c40SHuang Rui */ 65788bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 658b5a65c40SHuang Rui { 6599ba3aca8SThinh Nguyen unsigned int hw_mode; 660b5a65c40SHuang Rui u32 reg; 661b5a65c40SHuang Rui 6629ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6639ba3aca8SThinh Nguyen 664b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 665b5a65c40SHuang Rui 6662164a476SHuang Rui /* 6671966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6681966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6691966b865SFelipe Balbi */ 6701966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6711966b865SFelipe Balbi 6721966b865SFelipe Balbi /* 6732164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6742164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6752164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6762164a476SHuang Rui * to '1' after the core initialization is completed. 6772164a476SHuang Rui */ 6789af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6792164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6802164a476SHuang Rui 6819ba3aca8SThinh Nguyen /* 6829ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6839ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6849ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6859ba3aca8SThinh Nguyen */ 6869ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6879ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6889ba3aca8SThinh Nguyen 689b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 690b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 691b5a65c40SHuang Rui 692e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 693e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 694e58dd357SRajesh Bhagat 695df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 696df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 697df31f5b3SHuang Rui 698a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 699a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 700a2a1d0f5SHuang Rui 70141c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 70241c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 70341c06ffdSHuang Rui 704fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 705fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 706fb67afcaSHuang Rui 70714f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 70814f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 70914f4ac53SHuang Rui 7106b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7116b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7126b6a0c9aSHuang Rui 713cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 71459acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 71559acfa20SHuang Rui 71600fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 71700fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 71800fe081dSWilliam Wu 719b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 720b5a65c40SHuang Rui 7212164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7222164a476SHuang Rui 7233e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7243e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7253e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 72643cacb03SFelipe Balbi if (dwc->hsphy_interface && 72743cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7283e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 72988bc9d19SHeikki Krogerus break; 73043cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 73143cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7323e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 73388bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7343e10a2ceSHeikki Krogerus } else { 73588bc9d19SHeikki Krogerus /* Relying on default value. */ 73688bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7373e10a2ceSHeikki Krogerus break; 7383e10a2ceSHeikki Krogerus } 739df561f66SGustavo A. R. Silva fallthrough; 74088bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7413e10a2ceSHeikki Krogerus default: 7423e10a2ceSHeikki Krogerus break; 7433e10a2ceSHeikki Krogerus } 7443e10a2ceSHeikki Krogerus 74532f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 74632f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 74732f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 74832f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 74932f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 75032f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 75132f2ed86SWilliam Wu break; 75232f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 75332f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75432f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75532f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 75632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 75732f2ed86SWilliam Wu break; 75832f2ed86SWilliam Wu default: 75932f2ed86SWilliam Wu break; 76032f2ed86SWilliam Wu } 76132f2ed86SWilliam Wu 7622164a476SHuang Rui /* 7632164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7642164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7652164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7662164a476SHuang Rui * '1' after the core initialization is completed. 7672164a476SHuang Rui */ 7689af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7692164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7702164a476SHuang Rui 7719ba3aca8SThinh Nguyen /* 7729ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7739ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7749ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7759ba3aca8SThinh Nguyen */ 7769ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7779ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7789ba3aca8SThinh Nguyen 779cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7800effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7810effe0a3SHuang Rui 782ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 783ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 784eafeacf1SThinh Nguyen else 785eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 786ec791d14SJohn Youn 78716199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 78816199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 78916199f33SWilliam Wu 7902164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79188bc9d19SHeikki Krogerus 79288bc9d19SHeikki Krogerus return 0; 793b5a65c40SHuang Rui } 794b5a65c40SHuang Rui 79533fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 79633fb697eSSean Anderson { 79733fb697eSSean Anderson int ret; 79833fb697eSSean Anderson 79933fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 80033fb697eSSean Anderson if (ret) 80133fb697eSSean Anderson return ret; 80233fb697eSSean Anderson 80333fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 80433fb697eSSean Anderson if (ret) 80533fb697eSSean Anderson goto disable_bus_clk; 80633fb697eSSean Anderson 80733fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 80833fb697eSSean Anderson if (ret) 80933fb697eSSean Anderson goto disable_ref_clk; 81033fb697eSSean Anderson 81133fb697eSSean Anderson return 0; 81233fb697eSSean Anderson 81333fb697eSSean Anderson disable_ref_clk: 81433fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 81533fb697eSSean Anderson disable_bus_clk: 81633fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 81733fb697eSSean Anderson return ret; 81833fb697eSSean Anderson } 81933fb697eSSean Anderson 82033fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 82133fb697eSSean Anderson { 82233fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 82333fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82433fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82533fb697eSSean Anderson } 82633fb697eSSean Anderson 827c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 828c499ff71SFelipe Balbi { 829c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 830c499ff71SFelipe Balbi 831c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 832c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 833c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 834c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 835c499ff71SFelipe Balbi 836c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 837c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 838c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 839c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 84033fb697eSSean Anderson dwc3_clk_disable(dwc); 841fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 842c499ff71SFelipe Balbi } 843c499ff71SFelipe Balbi 8440759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 84572246da4SFelipe Balbi { 84672246da4SFelipe Balbi u32 reg; 84772246da4SFelipe Balbi 8487650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8499af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8500759956fSFelipe Balbi 8517650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8529af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 853690fb371SJohn Youn dwc->revision = reg; 8549af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 855690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 856475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 857690fb371SJohn Youn } else { 8580759956fSFelipe Balbi return false; 8597650bd74SSebastian Andrzej Siewior } 8607650bd74SSebastian Andrzej Siewior 8610759956fSFelipe Balbi return true; 8620e1e5c47SPaul Zimmerman } 8630e1e5c47SPaul Zimmerman 864941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 86572246da4SFelipe Balbi { 86672246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 86772246da4SFelipe Balbi u32 reg; 868c499ff71SFelipe Balbi 8694878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8703e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8714878a028SSebastian Andrzej Siewior 872164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8734878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87432a4a135SFelipe Balbi /** 87532a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 87632a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 87732a4a135SFelipe Balbi * 87832a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 87932a4a135SFelipe Balbi * configurations. 88032a4a135SFelipe Balbi * 88132a4a135SFelipe Balbi * Refers to: 88232a4a135SFelipe Balbi * 88332a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 88432a4a135SFelipe Balbi * SOF/ITP Mode Used 88532a4a135SFelipe Balbi */ 88632a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 88732a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8889af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 88932a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 89032a4a135SFelipe Balbi else 8914878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 8924878a028SSebastian Andrzej Siewior break; 8930ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 8940ffcaf37SFelipe Balbi /* enable hibernation here */ 8950ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 8962eac3992SHuang Rui 8972eac3992SHuang Rui /* 8982eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 8992eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 9002eac3992SHuang Rui */ 9012eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9020ffcaf37SFelipe Balbi break; 9034878a028SSebastian Andrzej Siewior default: 9045eb30cedSFelipe Balbi /* nothing */ 9055eb30cedSFelipe Balbi break; 9064878a028SSebastian Andrzej Siewior } 9074878a028SSebastian Andrzej Siewior 908946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 909946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9106af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 911946bd579SHuang Rui dwc->is_fpga = true; 912946bd579SHuang Rui } 913946bd579SHuang Rui 9143b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9153b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9163b81221aSHuang Rui 9173b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9183b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9193b81221aSHuang Rui else 9203b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9213b81221aSHuang Rui 9229a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9239a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9249a5b2f31SHuang Rui 9254878a028SSebastian Andrzej Siewior /* 9264878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9271d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9284878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9291d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9304878a028SSebastian Andrzej Siewior */ 9319af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9324878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9334878a028SSebastian Andrzej Siewior 9344878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 935941f918eSFelipe Balbi } 9364878a028SSebastian Andrzej Siewior 937f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 93898112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 939f54edb53SFelipe Balbi 940d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 941d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 942d9612c2fSPengbo Mu { 943d9612c2fSPengbo Mu struct device *dev = dwc->dev; 944d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 945d9612c2fSPengbo Mu bool incrx_mode; 946d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 947d9612c2fSPengbo Mu u32 incrx_size; 948d9612c2fSPengbo Mu u32 *vals; 949d9612c2fSPengbo Mu u32 cfg; 950d9612c2fSPengbo Mu int ntype; 951d9612c2fSPengbo Mu int ret; 952d9612c2fSPengbo Mu int i; 953d9612c2fSPengbo Mu 954d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 955d9612c2fSPengbo Mu 956d9612c2fSPengbo Mu /* 957d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 958d9612c2fSPengbo Mu * Get the number of value from this property: 959d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 960d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 961d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 962d9612c2fSPengbo Mu */ 963a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 964d9612c2fSPengbo Mu if (ntype <= 0) 965d9612c2fSPengbo Mu return; 966d9612c2fSPengbo Mu 967d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 9684ea15088SKushagra Verma if (!vals) 969d9612c2fSPengbo Mu return; 970d9612c2fSPengbo Mu 971d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 972d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 973d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 974d9612c2fSPengbo Mu if (ret) { 97575ecb9ddSAndy Shevchenko kfree(vals); 976d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 977d9612c2fSPengbo Mu return; 978d9612c2fSPengbo Mu } 979d9612c2fSPengbo Mu 980d9612c2fSPengbo Mu incrx_size = *vals; 981d9612c2fSPengbo Mu 982d9612c2fSPengbo Mu if (ntype > 1) { 983d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 984d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 985d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 986d9612c2fSPengbo Mu if (vals[i] > incrx_size) 987d9612c2fSPengbo Mu incrx_size = vals[i]; 988d9612c2fSPengbo Mu } 989d9612c2fSPengbo Mu } else { 990d9612c2fSPengbo Mu /* INCRX burst mode */ 991d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 992d9612c2fSPengbo Mu } 993d9612c2fSPengbo Mu 99475ecb9ddSAndy Shevchenko kfree(vals); 99575ecb9ddSAndy Shevchenko 996d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 997d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 998d9612c2fSPengbo Mu if (incrx_mode) 999d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1000d9612c2fSPengbo Mu switch (incrx_size) { 1001d9612c2fSPengbo Mu case 256: 1002d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1003d9612c2fSPengbo Mu break; 1004d9612c2fSPengbo Mu case 128: 1005d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1006d9612c2fSPengbo Mu break; 1007d9612c2fSPengbo Mu case 64: 1008d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1009d9612c2fSPengbo Mu break; 1010d9612c2fSPengbo Mu case 32: 1011d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1012d9612c2fSPengbo Mu break; 1013d9612c2fSPengbo Mu case 16: 1014d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1015d9612c2fSPengbo Mu break; 1016d9612c2fSPengbo Mu case 8: 1017d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1018d9612c2fSPengbo Mu break; 1019d9612c2fSPengbo Mu case 4: 1020d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1021d9612c2fSPengbo Mu break; 1022d9612c2fSPengbo Mu case 1: 1023d9612c2fSPengbo Mu break; 1024d9612c2fSPengbo Mu default: 1025d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1026d9612c2fSPengbo Mu break; 1027d9612c2fSPengbo Mu } 1028d9612c2fSPengbo Mu 1029d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1030d9612c2fSPengbo Mu } 1031d9612c2fSPengbo Mu 10323497b9a5SLi Jun static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 10333497b9a5SLi Jun { 10343497b9a5SLi Jun u32 scale; 10353497b9a5SLi Jun u32 reg; 10363497b9a5SLi Jun 10373497b9a5SLi Jun if (!dwc->susp_clk) 10383497b9a5SLi Jun return; 10393497b9a5SLi Jun 10403497b9a5SLi Jun /* 10413497b9a5SLi Jun * The power down scale field specifies how many suspend_clk 10423497b9a5SLi Jun * periods fit into a 16KHz clock period. When performing 10433497b9a5SLi Jun * the division, round up the remainder. 10443497b9a5SLi Jun * 10453497b9a5SLi Jun * The power down scale value is calculated using the fastest 10463497b9a5SLi Jun * frequency of the suspend_clk. If it isn't fixed (but within 10473497b9a5SLi Jun * the accuracy requirement), the driver may not know the max 10483497b9a5SLi Jun * rate of the suspend_clk, so only update the power down scale 10493497b9a5SLi Jun * if the default is less than the calculated value from 10503497b9a5SLi Jun * clk_get_rate() or if the default is questionably high 10513497b9a5SLi Jun * (3x or more) to be within the requirement. 10523497b9a5SLi Jun */ 10533497b9a5SLi Jun scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 10543497b9a5SLi Jun reg = dwc3_readl(dwc->regs, DWC3_GCTL); 10553497b9a5SLi Jun if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 10563497b9a5SLi Jun (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 10573497b9a5SLi Jun reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 10583497b9a5SLi Jun reg |= DWC3_GCTL_PWRDNSCALE(scale); 10593497b9a5SLi Jun dwc3_writel(dwc->regs, DWC3_GCTL, reg); 10603497b9a5SLi Jun } 10613497b9a5SLi Jun } 10623497b9a5SLi Jun 1063941f918eSFelipe Balbi /** 1064941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1065941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1066941f918eSFelipe Balbi * 1067941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1068941f918eSFelipe Balbi */ 1069941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1070941f918eSFelipe Balbi { 10719ba3aca8SThinh Nguyen unsigned int hw_mode; 1072941f918eSFelipe Balbi u32 reg; 1073941f918eSFelipe Balbi int ret; 1074941f918eSFelipe Balbi 10759ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10769ba3aca8SThinh Nguyen 1077941f918eSFelipe Balbi /* 1078941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1079941f918eSFelipe Balbi * out which kernel version a bug was found. 1080941f918eSFelipe Balbi */ 1081941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1082941f918eSFelipe Balbi 1083941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1084941f918eSFelipe Balbi if (ret) 1085941f918eSFelipe Balbi goto err0; 1086941f918eSFelipe Balbi 108798112041SRoger Quadros if (!dwc->ulpi_ready) { 108898112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 108998112041SRoger Quadros if (ret) 109098112041SRoger Quadros goto err0; 109198112041SRoger Quadros dwc->ulpi_ready = true; 109298112041SRoger Quadros } 109398112041SRoger Quadros 109498112041SRoger Quadros if (!dwc->phys_ready) { 109598112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 109698112041SRoger Quadros if (ret) 109798112041SRoger Quadros goto err0a; 109898112041SRoger Quadros dwc->phys_ready = true; 109998112041SRoger Quadros } 110098112041SRoger Quadros 11018cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 11028cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 11038cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 11048cfac9a6SLi Jun if (ret < 0) 11058cfac9a6SLi Jun goto err0a; 11068cfac9a6SLi Jun 11078cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 11088cfac9a6SLi Jun if (ret < 0) { 11098cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 11108cfac9a6SLi Jun goto err0a; 11118cfac9a6SLi Jun } 11128cfac9a6SLi Jun 111398112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 111498112041SRoger Quadros if (ret) 11158cfac9a6SLi Jun goto err1; 111698112041SRoger Quadros 11179ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 11189af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 11199ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 11209ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 11219ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 11229ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 11239ba3aca8SThinh Nguyen } 11249ba3aca8SThinh Nguyen 11259ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 11269ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 11279ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 11289ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 11299ba3aca8SThinh Nguyen } 11309ba3aca8SThinh Nguyen } 11319ba3aca8SThinh Nguyen 1132941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1133c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11340ffcaf37SFelipe Balbi 11350ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11360ffcaf37SFelipe Balbi if (ret) 1137c499ff71SFelipe Balbi goto err1; 1138c499ff71SFelipe Balbi 11393497b9a5SLi Jun /* Set power down scale of suspend_clk */ 11403497b9a5SLi Jun dwc3_set_power_down_clk_scale(dwc); 11413497b9a5SLi Jun 1142c499ff71SFelipe Balbi /* Adjust Frame Length */ 1143c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1144c499ff71SFelipe Balbi 11457bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11467bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11477bee3188SBalaji Prakash J 1148d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1149d9612c2fSPengbo Mu 1150c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1151c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1152c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1153c499ff71SFelipe Balbi if (ret < 0) 11540ffcaf37SFelipe Balbi goto err2; 11550ffcaf37SFelipe Balbi 1156c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1157c499ff71SFelipe Balbi if (ret < 0) 1158c499ff71SFelipe Balbi goto err3; 1159c499ff71SFelipe Balbi 1160c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1161c499ff71SFelipe Balbi if (ret) { 1162c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1163c499ff71SFelipe Balbi goto err4; 1164c499ff71SFelipe Balbi } 1165c499ff71SFelipe Balbi 116606281d46SJohn Youn /* 116706281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 116806281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 116906281d46SJohn Youn * DWC_usb31 controller. 117006281d46SJohn Youn */ 11719af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 117206281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 117306281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 117406281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 117506281d46SJohn Youn } 117606281d46SJohn Youn 11779af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 11780bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 117965db7a0cSWilliam Wu 118065db7a0cSWilliam Wu /* 118165db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 118265db7a0cSWilliam Wu * in HS when the device is in the L1 state. 118365db7a0cSWilliam Wu */ 11849af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 11850bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 118665db7a0cSWilliam Wu 1187843714bbSJack Pham /* 1188843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1189843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1190843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1191843714bbSJack Pham * from interrupting the driver. 1192843714bbSJack Pham */ 1193843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1194843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1195843714bbSJack Pham 119665db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 119765db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 119865db7a0cSWilliam Wu 11997ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 12007ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 12017ba6b09fSNeil Armstrong 120262b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 120362b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 120462b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 120562b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 120662b20e6eSBin Yang 12070bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 12080bb39ca1SJohn Youn } 12090bb39ca1SJohn Youn 1210b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1211b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1212b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1213b138e23dSAnurag Kumar Vulisha 1214b138e23dSAnurag Kumar Vulisha /* 1215b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1216b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1217b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1218b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1219b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1220b138e23dSAnurag Kumar Vulisha */ 1221b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1222b138e23dSAnurag Kumar Vulisha 1223b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1224b138e23dSAnurag Kumar Vulisha } 1225b138e23dSAnurag Kumar Vulisha 1226938a5ad1SThinh Nguyen /* 1227938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1228938a5ad1SThinh Nguyen * RX and/or TX threshold. 1229938a5ad1SThinh Nguyen */ 12309af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1231938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1232938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1233938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1234938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1235938a5ad1SThinh Nguyen 1236938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1237938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1238938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1239938a5ad1SThinh Nguyen 1240938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1241938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1242938a5ad1SThinh Nguyen 1243938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1244938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1245938a5ad1SThinh Nguyen 1246938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1247938a5ad1SThinh Nguyen } 1248938a5ad1SThinh Nguyen 1249938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1250938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1251938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1252938a5ad1SThinh Nguyen 1253938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1254938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1255938a5ad1SThinh Nguyen 1256938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1257938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1258938a5ad1SThinh Nguyen 1259938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1260938a5ad1SThinh Nguyen } 1261938a5ad1SThinh Nguyen } 1262938a5ad1SThinh Nguyen 126372246da4SFelipe Balbi return 0; 126472246da4SFelipe Balbi 1265c499ff71SFelipe Balbi err4: 12669b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1267c499ff71SFelipe Balbi 1268c499ff71SFelipe Balbi err3: 12699b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1270c499ff71SFelipe Balbi 12710ffcaf37SFelipe Balbi err2: 1272c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1273c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12740ffcaf37SFelipe Balbi 12750ffcaf37SFelipe Balbi err1: 12760ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 12770ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 127857303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 127957303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 12800ffcaf37SFelipe Balbi 128198112041SRoger Quadros err0a: 128298112041SRoger Quadros dwc3_ulpi_exit(dwc); 128398112041SRoger Quadros 128472246da4SFelipe Balbi err0: 128572246da4SFelipe Balbi return ret; 128672246da4SFelipe Balbi } 128772246da4SFelipe Balbi 12883c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 128972246da4SFelipe Balbi { 12903c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1291941ea361SFelipe Balbi struct device_node *node = dev->of_node; 12923c9f94acSFelipe Balbi int ret; 129372246da4SFelipe Balbi 12945088b6f5SKishon Vijay Abraham I if (node) { 12955088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 12965088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1297bb674907SFelipe Balbi } else { 1298bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1299bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 13005088b6f5SKishon Vijay Abraham I } 13015088b6f5SKishon Vijay Abraham I 1302d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1303d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1304d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1305122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1306d090c7a2SKushagra Verma else 13070c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1308122f06e6SKishon Vijay Abraham I } 130951e1e7bcSFelipe Balbi 1310d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1311315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1312d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1313122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1314d090c7a2SKushagra Verma else 13150c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1316122f06e6SKishon Vijay Abraham I } 131751e1e7bcSFelipe Balbi 131857303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 131957303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 132057303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 1321*fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 132257303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 1323d090c7a2SKushagra Verma else 13240c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 132557303488SKishon Vijay Abraham I } 132657303488SKishon Vijay Abraham I 132757303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 132857303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 132957303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 1330*fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 133157303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 1332d090c7a2SKushagra Verma else 13330c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 133457303488SKishon Vijay Abraham I } 133557303488SKishon Vijay Abraham I 13363c9f94acSFelipe Balbi return 0; 13373c9f94acSFelipe Balbi } 13383c9f94acSFelipe Balbi 13395f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13405f94adfeSFelipe Balbi { 13415f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13425f94adfeSFelipe Balbi int ret; 13435f94adfeSFelipe Balbi 13445f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13455f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 134641ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1347958d1a4cSFelipe Balbi 1348958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1349958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1350958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1351644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1352958d1a4cSFelipe Balbi 13535f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13540c0a20f6SAndy Shevchenko if (ret) 13550c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13565f94adfeSFelipe Balbi break; 13575f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 135841ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1359958d1a4cSFelipe Balbi 1360958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1361958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1362958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1363644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1364958d1a4cSFelipe Balbi 13655f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13660c0a20f6SAndy Shevchenko if (ret) 13670c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13685f94adfeSFelipe Balbi break; 13695f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 137041ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13719840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13720c0a20f6SAndy Shevchenko if (ret) 13730c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13745f94adfeSFelipe Balbi break; 13755f94adfeSFelipe Balbi default: 13765f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 13775f94adfeSFelipe Balbi return -EINVAL; 13785f94adfeSFelipe Balbi } 13795f94adfeSFelipe Balbi 13805f94adfeSFelipe Balbi return 0; 13815f94adfeSFelipe Balbi } 13825f94adfeSFelipe Balbi 13835f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 13845f94adfeSFelipe Balbi { 13855f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13865f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 13875f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 13885f94adfeSFelipe Balbi break; 13895f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 13905f94adfeSFelipe Balbi dwc3_host_exit(dwc); 13915f94adfeSFelipe Balbi break; 13925f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 13939840354fSRoger Quadros dwc3_drd_exit(dwc); 13945f94adfeSFelipe Balbi break; 13955f94adfeSFelipe Balbi default: 13965f94adfeSFelipe Balbi /* do nothing */ 13975f94adfeSFelipe Balbi break; 13985f94adfeSFelipe Balbi } 139909ed259fSBin Liu 140009ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 140109ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 14025f94adfeSFelipe Balbi } 14035f94adfeSFelipe Balbi 1404c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 14053c9f94acSFelipe Balbi { 1406c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 140780caf7d2SHuang Rui u8 lpm_nyet_threshold; 14086b6a0c9aSHuang Rui u8 tx_de_emphasis; 1409460d098cSHuang Rui u8 hird_threshold; 1410f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0; 1411f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0; 1412f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0; 1413f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0; 14149f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 14156f0764b5SRay Chi const char *usb_psy_name; 14166f0764b5SRay Chi int ret; 14173c9f94acSFelipe Balbi 141880caf7d2SHuang Rui /* default to highest possible threshold */ 14198d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 142080caf7d2SHuang Rui 14216b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 14226b6a0c9aSHuang Rui tx_de_emphasis = 1; 14236b6a0c9aSHuang Rui 1424460d098cSHuang Rui /* 1425460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1426460d098cSHuang Rui * threshold value of 0b1100 1427460d098cSHuang Rui */ 1428460d098cSHuang Rui hird_threshold = 12; 1429460d098cSHuang Rui 14309f607a30SWesley Cheng /* 14319f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 14329f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14339f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14349f607a30SWesley Cheng */ 14359f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14369f607a30SWesley Cheng 143763863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 143867848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 143906e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 144032f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 144163863b98SHeikki Krogerus 1442d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1443d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1444d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1445d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1446d64ff406SArnd Bergmann else 1447d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1448d64ff406SArnd Bergmann 14496f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14506f0764b5SRay Chi if (ret >= 0) { 14516f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14526f0764b5SRay Chi if (!dwc->usb_psy) 14536f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14546f0764b5SRay Chi } 14556f0764b5SRay Chi 14563d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 145780caf7d2SHuang Rui "snps,has-lpm-erratum"); 14583d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 145980caf7d2SHuang Rui &lpm_nyet_threshold); 14603d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1461460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14623d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1463460d098cSHuang Rui &hird_threshold); 1464d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1465d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14663d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1467eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1468022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1469022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1470475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1471475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1472938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1473938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1474938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1475938a5ad1SThinh Nguyen &rx_max_burst_prd); 1476938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1477938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1478938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1479938a5ad1SThinh Nguyen &tx_max_burst_prd); 14809f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 14819f607a30SWesley Cheng "tx-fifo-resize"); 14829f607a30SWesley Cheng if (dwc->do_fifo_resize) 14839f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 14849f607a30SWesley Cheng &tx_fifo_resize_max_num); 14853c9f94acSFelipe Balbi 14863d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 14873b81221aSHuang Rui "snps,disable_scramble_quirk"); 14883d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 14899a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 14903d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1491b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 14923d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1493df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 14943d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1495a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 14963d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 149741c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 14983d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1499fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 15003d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 150114f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 15023d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 150359acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 15043d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 15050effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1506ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1507ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1508729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1509729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1510729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1511729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1512e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1513e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 151416199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 151516199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 151600fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 151700fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 151865db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 151965db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 15207ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 15217ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 15226b6a0c9aSHuang Rui 15233d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 15246b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 15253d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 15266b6a0c9aSHuang Rui &tx_de_emphasis); 15273d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 15283e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 15293d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1530bcdb3272SFelipe Balbi &dwc->fladj); 15317bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 15327bee3188SBalaji Prakash J &dwc->ref_clk_per); 15333d128919SHeikki Krogerus 153442bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 153542bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 153642bf02ecSRoger Quadros 1537f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1538f580170fSYu Chen "snps,dis-split-quirk"); 1539f580170fSYu Chen 154080caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15416b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 154280caf7d2SHuang Rui 154316fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1544460d098cSHuang Rui 1545938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1546938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1547938a5ad1SThinh Nguyen 1548938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1549938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1550938a5ad1SThinh Nguyen 1551cf40b86bSJohn Youn dwc->imod_interval = 0; 15529f607a30SWesley Cheng 15539f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1554cf40b86bSJohn Youn } 1555cf40b86bSJohn Youn 1556cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1557cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1558cf40b86bSJohn Youn { 15599af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15609af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15619af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1562c5ac6116SFelipe Balbi } 1563c5ac6116SFelipe Balbi 15647ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15657ac51a12SJohn Youn { 15667ac51a12SJohn Youn struct device *dev = dwc->dev; 1567b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1568b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15697ac51a12SJohn Youn 1570cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1571cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1572cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1573cf40b86bSJohn Youn dwc->imod_interval = 0; 1574cf40b86bSJohn Youn } 1575cf40b86bSJohn Youn 157628632b44SJohn Youn /* 157728632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 157828632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 157928632b44SJohn Youn * interrupt from being masked while handling events. IMOD 158028632b44SJohn Youn * allows us to work around this issue. Enable it for the 158128632b44SJohn Youn * affected version. 158228632b44SJohn Youn */ 158328632b44SJohn Youn if (!dwc->imod_interval && 15849af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 158528632b44SJohn Youn dwc->imod_interval = 1; 158628632b44SJohn Youn 15877ac51a12SJohn Youn /* Check the maximum_speed parameter */ 15887ac51a12SJohn Youn switch (dwc->maximum_speed) { 15897ac51a12SJohn Youn case USB_SPEED_FULL: 15907ac51a12SJohn Youn case USB_SPEED_HIGH: 1591e518bdd9SThinh Nguyen break; 15927ac51a12SJohn Youn case USB_SPEED_SUPER: 1593e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1594e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1595e518bdd9SThinh Nguyen break; 15967ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1597e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1598e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1599e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1600e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1601e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 16027ac51a12SJohn Youn break; 16037ac51a12SJohn Youn default: 16047ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 16057ac51a12SJohn Youn dwc->maximum_speed); 1606df561f66SGustavo A. R. Silva fallthrough; 16077ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1608b574ce3eSThinh Nguyen switch (hwparam_gen) { 1609b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 16107ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1611b574ce3eSThinh Nguyen break; 1612b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1613b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1614b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1615b574ce3eSThinh Nguyen else 1616b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1617b574ce3eSThinh Nguyen break; 1618b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1619b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1620b574ce3eSThinh Nguyen break; 1621b574ce3eSThinh Nguyen default: 1622b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1623b574ce3eSThinh Nguyen break; 1624b574ce3eSThinh Nguyen } 16257ac51a12SJohn Youn break; 16267ac51a12SJohn Youn } 162767848146SThinh Nguyen 162867848146SThinh Nguyen /* 162967848146SThinh Nguyen * Currently the controller does not have visibility into the HW 163067848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 163167848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 163267848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 163367848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 163467848146SThinh Nguyen */ 163567848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 163667848146SThinh Nguyen switch (dwc->max_ssp_rate) { 163767848146SThinh Nguyen case USB_SSP_GEN_2x1: 163867848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 163967848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 164067848146SThinh Nguyen break; 164167848146SThinh Nguyen case USB_SSP_GEN_1x2: 164267848146SThinh Nguyen case USB_SSP_GEN_2x2: 164367848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 164467848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 164567848146SThinh Nguyen break; 164667848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 164767848146SThinh Nguyen default: 164867848146SThinh Nguyen switch (hwparam_gen) { 164967848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 165067848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 165167848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 165267848146SThinh Nguyen else 165367848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 165467848146SThinh Nguyen break; 165567848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 165667848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 165767848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 165867848146SThinh Nguyen break; 165967848146SThinh Nguyen } 166067848146SThinh Nguyen break; 166167848146SThinh Nguyen } 166267848146SThinh Nguyen } 16637ac51a12SJohn Youn } 16647ac51a12SJohn Youn 16650f010171SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 16660f010171SAndrey Smirnov { 16670f010171SAndrey Smirnov struct device *dev = dwc->dev; 16680f010171SAndrey Smirnov struct device_node *np_phy; 16690f010171SAndrey Smirnov struct extcon_dev *edev = NULL; 16700f010171SAndrey Smirnov const char *name; 16710f010171SAndrey Smirnov 16720f010171SAndrey Smirnov if (device_property_read_bool(dev, "extcon")) 16730f010171SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0); 16740f010171SAndrey Smirnov 16750f010171SAndrey Smirnov /* 16760f010171SAndrey Smirnov * Device tree platforms should get extcon via phandle. 16770f010171SAndrey Smirnov * On ACPI platforms, we get the name from a device property. 16780f010171SAndrey Smirnov * This device property is for kernel internal use only and 16790f010171SAndrey Smirnov * is expected to be set by the glue code. 16800f010171SAndrey Smirnov */ 16818bd6b8c4SStephen Rothwell if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 16828bd6b8c4SStephen Rothwell return extcon_get_extcon_dev(name); 16830f010171SAndrey Smirnov 16840f010171SAndrey Smirnov /* 16850f010171SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port" 16860f010171SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the 16870f010171SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon 16880f010171SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch" 16890f010171SAndrey Smirnov * or OTG mode. 16900f010171SAndrey Smirnov */ 16910f010171SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0); 16920f010171SAndrey Smirnov if (of_graph_is_present(np_phy)) { 16930f010171SAndrey Smirnov struct device_node *np_conn; 16940f010171SAndrey Smirnov 16950f010171SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1); 16960f010171SAndrey Smirnov if (np_conn) 16970f010171SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn); 16980f010171SAndrey Smirnov of_node_put(np_conn); 16990f010171SAndrey Smirnov } 17000f010171SAndrey Smirnov of_node_put(np_phy); 17010f010171SAndrey Smirnov 17020f010171SAndrey Smirnov return edev; 17030f010171SAndrey Smirnov } 17040f010171SAndrey Smirnov 1705c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1706c5ac6116SFelipe Balbi { 1707c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 170844feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1709c5ac6116SFelipe Balbi struct dwc3 *dwc; 1710c5ac6116SFelipe Balbi 1711c5ac6116SFelipe Balbi int ret; 1712c5ac6116SFelipe Balbi 1713c5ac6116SFelipe Balbi void __iomem *regs; 1714c5ac6116SFelipe Balbi 1715c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1716c5ac6116SFelipe Balbi if (!dwc) 1717c5ac6116SFelipe Balbi return -ENOMEM; 1718c5ac6116SFelipe Balbi 1719c5ac6116SFelipe Balbi dwc->dev = dev; 1720c5ac6116SFelipe Balbi 1721c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1722c5ac6116SFelipe Balbi if (!res) { 1723c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1724c5ac6116SFelipe Balbi return -ENODEV; 1725c5ac6116SFelipe Balbi } 1726c5ac6116SFelipe Balbi 1727c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1728c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1729c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1730c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1731c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1732c5ac6116SFelipe Balbi 1733c5ac6116SFelipe Balbi /* 1734c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1735c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1736c5ac6116SFelipe Balbi */ 173744feb8e6SMasahiro Yamada dwc_res = *res; 173844feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 173944feb8e6SMasahiro Yamada 174044feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 174144feb8e6SMasahiro Yamada if (IS_ERR(regs)) 174244feb8e6SMasahiro Yamada return PTR_ERR(regs); 1743c5ac6116SFelipe Balbi 1744c5ac6116SFelipe Balbi dwc->regs = regs; 174544feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1746c5ac6116SFelipe Balbi 1747c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1748c5ac6116SFelipe Balbi 174947ce4590SFabio Aiuto if (!dwc->sysdev_is_parent) { 175045d39448SSven Peter ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 175145d39448SSven Peter if (ret) 175245d39448SSven Peter return ret; 175347ce4590SFabio Aiuto } 175445d39448SSven Peter 1755babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1756fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1757fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1758fe8abf33SMasahiro Yamada 175961527777SHans de Goede if (dev->of_node) { 1760fe8abf33SMasahiro Yamada /* 176161527777SHans de Goede * Clocks are optional, but new DT platforms should support all 176261527777SHans de Goede * clocks as required by the DT-binding. 17634e64cd77SPeter Geis * Some devices have different clock names in legacy device trees, 17644e64cd77SPeter Geis * check for them to retain backwards compatibility. 1765fe8abf33SMasahiro Yamada */ 176633fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 176733fb697eSSean Anderson if (IS_ERR(dwc->bus_clk)) 176833fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 176933fb697eSSean Anderson "could not get bus clock\n"); 17700d3a9708SJohn Stultz 17714e64cd77SPeter Geis if (dwc->bus_clk == NULL) { 17724e64cd77SPeter Geis dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 17734e64cd77SPeter Geis if (IS_ERR(dwc->bus_clk)) 17744e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 17754e64cd77SPeter Geis "could not get bus clock\n"); 17764e64cd77SPeter Geis } 17774e64cd77SPeter Geis 177833fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 177933fb697eSSean Anderson if (IS_ERR(dwc->ref_clk)) 178033fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 178133fb697eSSean Anderson "could not get ref clock\n"); 178233fb697eSSean Anderson 17834e64cd77SPeter Geis if (dwc->ref_clk == NULL) { 17844e64cd77SPeter Geis dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 17854e64cd77SPeter Geis if (IS_ERR(dwc->ref_clk)) 17864e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 17874e64cd77SPeter Geis "could not get ref clock\n"); 17884e64cd77SPeter Geis } 17894e64cd77SPeter Geis 179033fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 179133fb697eSSean Anderson if (IS_ERR(dwc->susp_clk)) 179233fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 179333fb697eSSean Anderson "could not get suspend clock\n"); 17944e64cd77SPeter Geis 17954e64cd77SPeter Geis if (dwc->susp_clk == NULL) { 17964e64cd77SPeter Geis dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 17974e64cd77SPeter Geis if (IS_ERR(dwc->susp_clk)) 17984e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 17994e64cd77SPeter Geis "could not get suspend clock\n"); 18004e64cd77SPeter Geis } 180161527777SHans de Goede } 1802fe8abf33SMasahiro Yamada 1803fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1804fe8abf33SMasahiro Yamada if (ret) 180503bf32bbSAndrey Smirnov return ret; 1806fe8abf33SMasahiro Yamada 180733fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1808fe8abf33SMasahiro Yamada if (ret) 1809fe8abf33SMasahiro Yamada goto assert_reset; 1810fe8abf33SMasahiro Yamada 1811dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1812dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1813dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1814dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1815dc1b5d9aSEnric Balletbo i Serra } 1816dc1b5d9aSEnric Balletbo i Serra 18176c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 18182917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 18196c89cce0SHeikki Krogerus 182072246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1821f88359e1SYu Chen mutex_init(&dwc->mutex); 182272246da4SFelipe Balbi 1823fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1824fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1825fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1826802ca850SChanho Park pm_runtime_enable(dev); 182732808237SRoger Quadros ret = pm_runtime_get_sync(dev); 182832808237SRoger Quadros if (ret < 0) 182932808237SRoger Quadros goto err1; 183032808237SRoger Quadros 1831802ca850SChanho Park pm_runtime_forbid(dev); 183272246da4SFelipe Balbi 18333921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 18343921426bSFelipe Balbi if (ret) { 18353921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 18363921426bSFelipe Balbi ret = -ENOMEM; 183732808237SRoger Quadros goto err2; 18383921426bSFelipe Balbi } 18393921426bSFelipe Balbi 18400f010171SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc); 18410f010171SAndrey Smirnov if (IS_ERR(dwc->edev)) { 18420f010171SAndrey Smirnov ret = PTR_ERR(dwc->edev); 18430f010171SAndrey Smirnov dev_err_probe(dwc->dev, ret, "failed to get extcon\n"); 18440f010171SAndrey Smirnov goto err3; 18450f010171SAndrey Smirnov } 18460f010171SAndrey Smirnov 18479d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 18489d6173e1SThinh Nguyen if (ret) 18499d6173e1SThinh Nguyen goto err3; 185032a4a135SFelipe Balbi 1851c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1852c499ff71SFelipe Balbi if (ret) 185332808237SRoger Quadros goto err3; 1854c499ff71SFelipe Balbi 185572246da4SFelipe Balbi ret = dwc3_core_init(dwc); 185672246da4SFelipe Balbi if (ret) { 18570c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 185832808237SRoger Quadros goto err4; 185972246da4SFelipe Balbi } 186072246da4SFelipe Balbi 18617ac51a12SJohn Youn dwc3_check_params(dwc); 186284524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 18632c7f1bd9SJohn Youn 18645f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 18655f94adfeSFelipe Balbi if (ret) 186632808237SRoger Quadros goto err5; 186772246da4SFelipe Balbi 1868fc8bb91bSFelipe Balbi pm_runtime_put(dev); 186972246da4SFelipe Balbi 187072246da4SFelipe Balbi return 0; 187172246da4SFelipe Balbi 187232808237SRoger Quadros err5: 187384524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1874f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 187503c1fd62SLi Jun 187603c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 187703c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 187803c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 187903c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 188003c1fd62SLi Jun 188103c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 188203c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 188303c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 188403c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 188503c1fd62SLi Jun 188608fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1887f122d33eSFelipe Balbi 188832808237SRoger Quadros err4: 1889c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 189072246da4SFelipe Balbi 189132808237SRoger Quadros err3: 18923921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 18933921426bSFelipe Balbi 189432808237SRoger Quadros err2: 189532808237SRoger Quadros pm_runtime_allow(&pdev->dev); 189632808237SRoger Quadros 189732808237SRoger Quadros err1: 189832808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 189932808237SRoger Quadros pm_runtime_disable(&pdev->dev); 190032808237SRoger Quadros 1901dc1b5d9aSEnric Balletbo i Serra disable_clks: 190233fb697eSSean Anderson dwc3_clk_disable(dwc); 1903fe8abf33SMasahiro Yamada assert_reset: 1904fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1905fe8abf33SMasahiro Yamada 1906b0bf77cdSColin Ian King if (dwc->usb_psy) 19076f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19086f0764b5SRay Chi 190972246da4SFelipe Balbi return ret; 191072246da4SFelipe Balbi } 191172246da4SFelipe Balbi 1912fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 191372246da4SFelipe Balbi { 191472246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 19153da1f6eeSFelipe Balbi 1916fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 191772246da4SFelipe Balbi 1918dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 19192a042767SPeter Chen dwc3_debugfs_exit(dwc); 19208ba007a9SKishon Vijay Abraham I 192172246da4SFelipe Balbi dwc3_core_exit(dwc); 192288bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 192372246da4SFelipe Balbi 1924fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1925266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1926266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1927fc8bb91bSFelipe Balbi 1928c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1929c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1930c499ff71SFelipe Balbi 1931b0bf77cdSColin Ian King if (dwc->usb_psy) 19326f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19336f0764b5SRay Chi 193472246da4SFelipe Balbi return 0; 193572246da4SFelipe Balbi } 193672246da4SFelipe Balbi 1937fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1938fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1939fe8abf33SMasahiro Yamada { 1940fe8abf33SMasahiro Yamada int ret; 1941fe8abf33SMasahiro Yamada 1942fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1943fe8abf33SMasahiro Yamada if (ret) 1944fe8abf33SMasahiro Yamada return ret; 1945fe8abf33SMasahiro Yamada 194633fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1947fe8abf33SMasahiro Yamada if (ret) 1948fe8abf33SMasahiro Yamada goto assert_reset; 1949fe8abf33SMasahiro Yamada 1950fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1951fe8abf33SMasahiro Yamada if (ret) 1952fe8abf33SMasahiro Yamada goto disable_clks; 1953fe8abf33SMasahiro Yamada 1954fe8abf33SMasahiro Yamada return 0; 1955fe8abf33SMasahiro Yamada 1956fe8abf33SMasahiro Yamada disable_clks: 195733fb697eSSean Anderson dwc3_clk_disable(dwc); 1958fe8abf33SMasahiro Yamada assert_reset: 1959fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1960fe8abf33SMasahiro Yamada 1961fe8abf33SMasahiro Yamada return ret; 1962fe8abf33SMasahiro Yamada } 1963fe8abf33SMasahiro Yamada 1964c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 19657415f17cSFelipe Balbi { 1966fc8bb91bSFelipe Balbi unsigned long flags; 1967bcb12877SManu Gautam u32 reg; 19687415f17cSFelipe Balbi 1969689bf72cSManu Gautam switch (dwc->current_dr_role) { 1970689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 19710227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 19720227cc84SLi Jun break; 1973fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 19747415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1975fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 197641a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1977689bf72cSManu Gautam dwc3_core_exit(dwc); 197851f5d49aSFelipe Balbi break; 1979689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1980bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1981c4a5153eSManu Gautam dwc3_core_exit(dwc); 1982c4a5153eSManu Gautam break; 1983bcb12877SManu Gautam } 1984bcb12877SManu Gautam 1985bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1986bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1987bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1988bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1989bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1990bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1991bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1992bcb12877SManu Gautam 1993bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1994bcb12877SManu Gautam usleep_range(5000, 6000); 1995bcb12877SManu Gautam } 1996bcb12877SManu Gautam 1997bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1998bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1999bcb12877SManu Gautam break; 2000f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2001f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 2002f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2003f09cc79bSRoger Quadros break; 2004f09cc79bSRoger Quadros 2005f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2006f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2007f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 2008f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 200941a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2010f09cc79bSRoger Quadros } 2011f09cc79bSRoger Quadros 2012f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 2013f09cc79bSRoger Quadros dwc3_core_exit(dwc); 2014f09cc79bSRoger Quadros break; 20157415f17cSFelipe Balbi default: 201651f5d49aSFelipe Balbi /* do nothing */ 20177415f17cSFelipe Balbi break; 20187415f17cSFelipe Balbi } 20197415f17cSFelipe Balbi 2020fc8bb91bSFelipe Balbi return 0; 2021fc8bb91bSFelipe Balbi } 2022fc8bb91bSFelipe Balbi 2023c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2024fc8bb91bSFelipe Balbi { 2025fc8bb91bSFelipe Balbi unsigned long flags; 2026fc8bb91bSFelipe Balbi int ret; 2027bcb12877SManu Gautam u32 reg; 2028fc8bb91bSFelipe Balbi 2029689bf72cSManu Gautam switch (dwc->current_dr_role) { 2030689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2031fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2032fc8bb91bSFelipe Balbi if (ret) 2033fc8bb91bSFelipe Balbi return ret; 2034fc8bb91bSFelipe Balbi 20357d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2036fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 2037fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 2038fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 2039689bf72cSManu Gautam break; 2040689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2041c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 2042fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2043c4a5153eSManu Gautam if (ret) 2044c4a5153eSManu Gautam return ret; 20457d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2046bcb12877SManu Gautam break; 2047c4a5153eSManu Gautam } 2048bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2049bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2050bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 2051bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2052bcb12877SManu Gautam 2053bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 2054bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2055bcb12877SManu Gautam 2056bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2057bcb12877SManu Gautam 2058bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2059bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2060c4a5153eSManu Gautam break; 2061f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2062f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 2063f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2064f09cc79bSRoger Quadros break; 2065f09cc79bSRoger Quadros 20660e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 2067f09cc79bSRoger Quadros if (ret) 2068f09cc79bSRoger Quadros return ret; 2069f09cc79bSRoger Quadros 2070f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 2071f09cc79bSRoger Quadros 2072f09cc79bSRoger Quadros dwc3_otg_init(dwc); 2073f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2074f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 2075f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2076f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2077f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 2078f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 2079f09cc79bSRoger Quadros } 2080f09cc79bSRoger Quadros 2081f09cc79bSRoger Quadros break; 2082fc8bb91bSFelipe Balbi default: 2083fc8bb91bSFelipe Balbi /* do nothing */ 2084fc8bb91bSFelipe Balbi break; 2085fc8bb91bSFelipe Balbi } 2086fc8bb91bSFelipe Balbi 2087fc8bb91bSFelipe Balbi return 0; 2088fc8bb91bSFelipe Balbi } 2089fc8bb91bSFelipe Balbi 2090fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 2091fc8bb91bSFelipe Balbi { 2092689bf72cSManu Gautam switch (dwc->current_dr_role) { 2093c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2094fc8bb91bSFelipe Balbi if (dwc->connected) 2095fc8bb91bSFelipe Balbi return -EBUSY; 2096fc8bb91bSFelipe Balbi break; 2097c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2098fc8bb91bSFelipe Balbi default: 2099fc8bb91bSFelipe Balbi /* do nothing */ 2100fc8bb91bSFelipe Balbi break; 2101fc8bb91bSFelipe Balbi } 2102fc8bb91bSFelipe Balbi 2103fc8bb91bSFelipe Balbi return 0; 2104fc8bb91bSFelipe Balbi } 2105fc8bb91bSFelipe Balbi 2106fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2107fc8bb91bSFelipe Balbi { 2108fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2109fc8bb91bSFelipe Balbi int ret; 2110fc8bb91bSFelipe Balbi 2111fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2112fc8bb91bSFelipe Balbi return -EBUSY; 2113fc8bb91bSFelipe Balbi 2114c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2115fc8bb91bSFelipe Balbi if (ret) 2116fc8bb91bSFelipe Balbi return ret; 2117fc8bb91bSFelipe Balbi 2118fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 2119fc8bb91bSFelipe Balbi 2120fc8bb91bSFelipe Balbi return 0; 2121fc8bb91bSFelipe Balbi } 2122fc8bb91bSFelipe Balbi 2123fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2124fc8bb91bSFelipe Balbi { 2125fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2126fc8bb91bSFelipe Balbi int ret; 2127fc8bb91bSFelipe Balbi 2128fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 2129fc8bb91bSFelipe Balbi 2130c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2131fc8bb91bSFelipe Balbi if (ret) 2132fc8bb91bSFelipe Balbi return ret; 2133fc8bb91bSFelipe Balbi 2134689bf72cSManu Gautam switch (dwc->current_dr_role) { 2135689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2136fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2137fc8bb91bSFelipe Balbi break; 2138689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2139fc8bb91bSFelipe Balbi default: 2140fc8bb91bSFelipe Balbi /* do nothing */ 2141fc8bb91bSFelipe Balbi break; 2142fc8bb91bSFelipe Balbi } 2143fc8bb91bSFelipe Balbi 2144fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2145fc8bb91bSFelipe Balbi 2146fc8bb91bSFelipe Balbi return 0; 2147fc8bb91bSFelipe Balbi } 2148fc8bb91bSFelipe Balbi 2149fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2150fc8bb91bSFelipe Balbi { 2151fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2152fc8bb91bSFelipe Balbi 2153689bf72cSManu Gautam switch (dwc->current_dr_role) { 2154689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2155fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2156fc8bb91bSFelipe Balbi return -EBUSY; 2157fc8bb91bSFelipe Balbi break; 2158689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2159fc8bb91bSFelipe Balbi default: 2160fc8bb91bSFelipe Balbi /* do nothing */ 2161fc8bb91bSFelipe Balbi break; 2162fc8bb91bSFelipe Balbi } 2163fc8bb91bSFelipe Balbi 2164fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2165fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2166fc8bb91bSFelipe Balbi 2167fc8bb91bSFelipe Balbi return 0; 2168fc8bb91bSFelipe Balbi } 2169fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2170fc8bb91bSFelipe Balbi 2171fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2172fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2173fc8bb91bSFelipe Balbi { 2174fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2175fc8bb91bSFelipe Balbi int ret; 2176fc8bb91bSFelipe Balbi 2177c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2178fc8bb91bSFelipe Balbi if (ret) 2179fc8bb91bSFelipe Balbi return ret; 2180fc8bb91bSFelipe Balbi 21816344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 21826344475fSSekhar Nori 21837415f17cSFelipe Balbi return 0; 21847415f17cSFelipe Balbi } 21857415f17cSFelipe Balbi 21867415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 21877415f17cSFelipe Balbi { 21887415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 218957303488SKishon Vijay Abraham I int ret; 21907415f17cSFelipe Balbi 21916344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 21926344475fSSekhar Nori 2193c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 219451f5d49aSFelipe Balbi if (ret) 21955c4ad318SFelipe Balbi return ret; 21965c4ad318SFelipe Balbi 21977415f17cSFelipe Balbi pm_runtime_disable(dev); 21987415f17cSFelipe Balbi pm_runtime_set_active(dev); 21997415f17cSFelipe Balbi pm_runtime_enable(dev); 22007415f17cSFelipe Balbi 22017415f17cSFelipe Balbi return 0; 22027415f17cSFelipe Balbi } 2203f580170fSYu Chen 2204f580170fSYu Chen static void dwc3_complete(struct device *dev) 2205f580170fSYu Chen { 2206f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2207f580170fSYu Chen u32 reg; 2208f580170fSYu Chen 2209f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2210f580170fSYu Chen dwc->dis_split_quirk) { 2211f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2212f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2213f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2214f580170fSYu Chen } 2215f580170fSYu Chen } 2216f580170fSYu Chen #else 2217f580170fSYu Chen #define dwc3_complete NULL 22187f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 22197415f17cSFelipe Balbi 22207415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 22217415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2222f580170fSYu Chen .complete = dwc3_complete, 2223fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2224fc8bb91bSFelipe Balbi dwc3_runtime_idle) 22257415f17cSFelipe Balbi }; 22267415f17cSFelipe Balbi 22275088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 22285088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 22295088b6f5SKishon Vijay Abraham I { 223022a5aa17SFelipe Balbi .compatible = "snps,dwc3" 223122a5aa17SFelipe Balbi }, 223222a5aa17SFelipe Balbi { 22335088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 22345088b6f5SKishon Vijay Abraham I }, 22355088b6f5SKishon Vijay Abraham I { }, 22365088b6f5SKishon Vijay Abraham I }; 22375088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 22385088b6f5SKishon Vijay Abraham I #endif 22395088b6f5SKishon Vijay Abraham I 2240404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2241404905a6SHeikki Krogerus 2242404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2243404905a6SHeikki Krogerus 2244404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2245404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2246404905a6SHeikki Krogerus { }, 2247404905a6SHeikki Krogerus }; 2248404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2249404905a6SHeikki Krogerus #endif 2250404905a6SHeikki Krogerus 225172246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 225272246da4SFelipe Balbi .probe = dwc3_probe, 22537690417dSBill Pemberton .remove = dwc3_remove, 225472246da4SFelipe Balbi .driver = { 225572246da4SFelipe Balbi .name = "dwc3", 22565088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2257404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 22587f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 225972246da4SFelipe Balbi }, 226072246da4SFelipe Balbi }; 226172246da4SFelipe Balbi 2262b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2263b1116dccSTobias Klauser 22647ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 226572246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 22665945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 226772246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 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