15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26d182c2e1SAndrey Smirnov #include <linux/of_graph.h> 27404905a6SHeikki Krogerus #include <linux/acpi.h> 286344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 29fe8abf33SMasahiro Yamada #include <linux/reset.h> 307bee3188SBalaji Prakash J #include <linux/bitfield.h> 3172246da4SFelipe Balbi 3272246da4SFelipe Balbi #include <linux/usb/ch9.h> 3372246da4SFelipe Balbi #include <linux/usb/gadget.h> 34f7e846f0SFelipe Balbi #include <linux/usb/of.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3672246da4SFelipe Balbi 3772246da4SFelipe Balbi #include "core.h" 3872246da4SFelipe Balbi #include "gadget.h" 3972246da4SFelipe Balbi #include "io.h" 4072246da4SFelipe Balbi 4172246da4SFelipe Balbi #include "debug.h" 4272246da4SFelipe Balbi 43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 448300dd23SFelipe Balbi 459d6173e1SThinh Nguyen /** 469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 479d6173e1SThinh Nguyen * @dwc: pointer to our context structure 489d6173e1SThinh Nguyen */ 499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 509d6173e1SThinh Nguyen { 519d6173e1SThinh Nguyen enum usb_dr_mode mode; 529d6173e1SThinh Nguyen struct device *dev = dwc->dev; 539d6173e1SThinh Nguyen unsigned int hw_mode; 549d6173e1SThinh Nguyen 559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 579d6173e1SThinh Nguyen 589d6173e1SThinh Nguyen mode = dwc->dr_mode; 599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 609d6173e1SThinh Nguyen 619d6173e1SThinh Nguyen switch (hw_mode) { 629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 649d6173e1SThinh Nguyen dev_err(dev, 659d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 669d6173e1SThinh Nguyen return -EINVAL; 679d6173e1SThinh Nguyen } 689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 699d6173e1SThinh Nguyen break; 709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 729d6173e1SThinh Nguyen dev_err(dev, 739d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 749d6173e1SThinh Nguyen return -EINVAL; 759d6173e1SThinh Nguyen } 769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 779d6173e1SThinh Nguyen break; 789d6173e1SThinh Nguyen default: 799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 83a7700468SThinh Nguyen 84a7700468SThinh Nguyen /* 8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 88a7700468SThinh Nguyen */ 89d182c2e1SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev && 908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 949d6173e1SThinh Nguyen } 959d6173e1SThinh Nguyen 969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 979d6173e1SThinh Nguyen dev_warn(dev, 989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 1009d6173e1SThinh Nguyen 1019d6173e1SThinh Nguyen dwc->dr_mode = mode; 1029d6173e1SThinh Nguyen } 1039d6173e1SThinh Nguyen 1049d6173e1SThinh Nguyen return 0; 1059d6173e1SThinh Nguyen } 1069d6173e1SThinh Nguyen 107f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1083140e8cbSSebastian Andrzej Siewior { 1093140e8cbSSebastian Andrzej Siewior u32 reg; 1103140e8cbSSebastian Andrzej Siewior 1113140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1123140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1133140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1143140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115c4a5153eSManu Gautam 116c4a5153eSManu Gautam dwc->current_dr_role = mode; 11741ce1456SRoger Quadros } 1186b3261a2SRoger Quadros 11941ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12041ce1456SRoger Quadros { 12141ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12241ce1456SRoger Quadros unsigned long flags; 12341ce1456SRoger Quadros int ret; 124f580170fSYu Chen u32 reg; 12541ce1456SRoger Quadros 126f88359e1SYu Chen mutex_lock(&dwc->mutex); 127f88359e1SYu Chen 128c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 129c2cd3452SMartin Kepplinger 130f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 131f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 132f09cc79bSRoger Quadros 13341ce1456SRoger Quadros if (!dwc->desired_dr_role) 134c2cd3452SMartin Kepplinger goto out; 13541ce1456SRoger Quadros 13641ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 137c2cd3452SMartin Kepplinger goto out; 13841ce1456SRoger Quadros 139f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 140c2cd3452SMartin Kepplinger goto out; 14141ce1456SRoger Quadros 14241ce1456SRoger Quadros switch (dwc->current_dr_role) { 14341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14441ce1456SRoger Quadros dwc3_host_exit(dwc); 14541ce1456SRoger Quadros break; 14641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14741ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14841ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14941ce1456SRoger Quadros break; 150f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 151f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 152f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 153f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 154f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 155f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 156f09cc79bSRoger Quadros break; 15741ce1456SRoger Quadros default: 15841ce1456SRoger Quadros break; 15941ce1456SRoger Quadros } 16041ce1456SRoger Quadros 16107903626SRohith Kollalsi /* 16207903626SRohith Kollalsi * When current_dr_role is not set, there's no role switching. 16307903626SRohith Kollalsi * Only perform GCTL.CoreSoftReset when there's DRD role switching. 16407903626SRohith Kollalsi */ 16507903626SRohith Kollalsi if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 16607903626SRohith Kollalsi DWC3_VER_IS_PRIOR(DWC31, 190A)) && 16707903626SRohith Kollalsi dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 168f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 169f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 170f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 171f88359e1SYu Chen 172f88359e1SYu Chen /* 173f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 174f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 175f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 176f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 177f88359e1SYu Chen */ 178f88359e1SYu Chen msleep(100); 179f88359e1SYu Chen 180f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 181f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 182f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 183f88359e1SYu Chen } 184f88359e1SYu Chen 18541ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18641ce1456SRoger Quadros 18741ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18841ce1456SRoger Quadros 18941ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 19041ce1456SRoger Quadros 19141ce1456SRoger Quadros switch (dwc->desired_dr_role) { 19241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 19341ce1456SRoger Quadros ret = dwc3_host_init(dwc); 194958d1a4cSFelipe Balbi if (ret) { 19541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 196958d1a4cSFelipe Balbi } else { 197958d1a4cSFelipe Balbi if (dwc->usb2_phy) 198958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 199958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 200644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 201f580170fSYu Chen if (dwc->dis_split_quirk) { 202f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 203f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 204f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 205f580170fSYu Chen } 206958d1a4cSFelipe Balbi } 20741ce1456SRoger Quadros break; 20841ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 209f88359e1SYu Chen dwc3_core_soft_reset(dwc); 210f88359e1SYu Chen 21141ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 212958d1a4cSFelipe Balbi 213958d1a4cSFelipe Balbi if (dwc->usb2_phy) 214958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 215958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 216644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 217958d1a4cSFelipe Balbi 21841ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21941ce1456SRoger Quadros if (ret) 22041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 22141ce1456SRoger Quadros break; 222f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 223f09cc79bSRoger Quadros dwc3_otg_init(dwc); 224f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 225f09cc79bSRoger Quadros break; 22641ce1456SRoger Quadros default: 22741ce1456SRoger Quadros break; 22841ce1456SRoger Quadros } 229f09cc79bSRoger Quadros 230c2cd3452SMartin Kepplinger out: 231c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 232c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 233f88359e1SYu Chen mutex_unlock(&dwc->mutex); 23441ce1456SRoger Quadros } 23541ce1456SRoger Quadros 23641ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23741ce1456SRoger Quadros { 23841ce1456SRoger Quadros unsigned long flags; 23941ce1456SRoger Quadros 240dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 241dc336b19SLi Jun return; 242dc336b19SLi Jun 24341ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 24441ce1456SRoger Quadros dwc->desired_dr_role = mode; 24541ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24641ce1456SRoger Quadros 247084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2483140e8cbSSebastian Andrzej Siewior } 2498300dd23SFelipe Balbi 250cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 251cf6d867dSFelipe Balbi { 252cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 253cf6d867dSFelipe Balbi u32 reg; 254cf6d867dSFelipe Balbi 255cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 256cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 257cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 258cf6d867dSFelipe Balbi 259cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 260cf6d867dSFelipe Balbi 261cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 262cf6d867dSFelipe Balbi } 263cf6d867dSFelipe Balbi 26472246da4SFelipe Balbi /** 26572246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26672246da4SFelipe Balbi * @dwc: pointer to our context structure 26772246da4SFelipe Balbi */ 2680066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 26972246da4SFelipe Balbi { 27072246da4SFelipe Balbi u32 reg; 271f59dcab1SFelipe Balbi int retries = 1000; 27272246da4SFelipe Balbi 273f59dcab1SFelipe Balbi /* 274f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 275f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 276f59dcab1SFelipe Balbi * host-only mode, then we can return early. 277f59dcab1SFelipe Balbi */ 278c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27957303488SKishon Vijay Abraham I return 0; 280f59dcab1SFelipe Balbi 281f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 282f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 283f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP; 284f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg); 285f59dcab1SFelipe Balbi 2864749e0e6SThinh Nguyen /* 2874749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2884749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2894749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2904749e0e6SThinh Nguyen * for 10 times instead. 2914749e0e6SThinh Nguyen */ 2929af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2934749e0e6SThinh Nguyen retries = 10; 2944749e0e6SThinh Nguyen 295f59dcab1SFelipe Balbi do { 296f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 297f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 298fab38333SThinh Nguyen goto done; 299f59dcab1SFelipe Balbi 3009af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 3014749e0e6SThinh Nguyen msleep(20); 3024749e0e6SThinh Nguyen else 303f59dcab1SFelipe Balbi udelay(1); 304f59dcab1SFelipe Balbi } while (--retries); 305f59dcab1SFelipe Balbi 306859bdc35SMayank Rana dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 307f59dcab1SFelipe Balbi return -ETIMEDOUT; 308fab38333SThinh Nguyen 309fab38333SThinh Nguyen done: 310fab38333SThinh Nguyen /* 3114749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3124749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3134749e0e6SThinh Nguyen * domain (synchronization delay). 314fab38333SThinh Nguyen */ 3159af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 316fab38333SThinh Nguyen msleep(50); 317fab38333SThinh Nguyen 318fab38333SThinh Nguyen return 0; 31972246da4SFelipe Balbi } 32072246da4SFelipe Balbi 321db2be4e9SNikhil Badola /* 322db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 323db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 324db2be4e9SNikhil Badola */ 325bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 326db2be4e9SNikhil Badola { 327db2be4e9SNikhil Badola u32 reg; 328db2be4e9SNikhil Badola u32 dft; 329db2be4e9SNikhil Badola 3309af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 331db2be4e9SNikhil Badola return; 332db2be4e9SNikhil Badola 333bcdb3272SFelipe Balbi if (dwc->fladj == 0) 334db2be4e9SNikhil Badola return; 335db2be4e9SNikhil Badola 336db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 337db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 338a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 339db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 340bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 341db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 342db2be4e9SNikhil Badola } 343db2be4e9SNikhil Badola } 344db2be4e9SNikhil Badola 345c5cc74e8SHeikki Krogerus /** 3467bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3477bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3487bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3497bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3507bee3188SBalaji Prakash J * register. 3517bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3527bee3188SBalaji Prakash J */ 3537bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3547bee3188SBalaji Prakash J { 3555114c3eeSSean Anderson unsigned long period; 356596c8785SSean Anderson unsigned long fladj; 357596c8785SSean Anderson unsigned long decr; 3585114c3eeSSean Anderson unsigned long rate; 3597bee3188SBalaji Prakash J u32 reg; 3607bee3188SBalaji Prakash J 3615114c3eeSSean Anderson if (dwc->ref_clk) { 3625114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3635114c3eeSSean Anderson if (!rate) 3647bee3188SBalaji Prakash J return; 3655114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3665114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3675114c3eeSSean Anderson period = dwc->ref_clk_per; 368596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3695114c3eeSSean Anderson } else { 3705114c3eeSSean Anderson return; 3715114c3eeSSean Anderson } 3727bee3188SBalaji Prakash J 3737bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3747bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3755114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3767bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3777bee3188SBalaji Prakash J 378596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 379596c8785SSean Anderson return; 380596c8785SSean Anderson 381596c8785SSean Anderson /* 382596c8785SSean Anderson * The calculation below is 383596c8785SSean Anderson * 384596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 385596c8785SSean Anderson * 386596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 387596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 388596c8785SSean Anderson * neither does rate * period). 389596c8785SSean Anderson * 390596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 391596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 392596c8785SSean Anderson * the division when calculating rate or period (whichever one was 393596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 394596c8785SSean Anderson * scale it to units of 8 ppm. 395596c8785SSean Anderson */ 396596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 397596c8785SSean Anderson fladj -= 125000; 398596c8785SSean Anderson 399596c8785SSean Anderson /* 400596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 401596c8785SSean Anderson */ 402596c8785SSean Anderson decr = 480000000 / rate; 403596c8785SSean Anderson 404596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 405596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 406596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 407596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 408596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 409596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 410596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 411a6fc2f1bSAlexander Stein 412a6fc2f1bSAlexander Stein if (dwc->gfladj_refclk_lpm_sel) 413a6fc2f1bSAlexander Stein reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 414a6fc2f1bSAlexander Stein 415596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 416596c8785SSean Anderson } 4177bee3188SBalaji Prakash J 4187bee3188SBalaji Prakash J /** 41972246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 42072246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42172246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 42272246da4SFelipe Balbi */ 42372246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 42472246da4SFelipe Balbi struct dwc3_event_buffer *evt) 42572246da4SFelipe Balbi { 426d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 42772246da4SFelipe Balbi } 42872246da4SFelipe Balbi 42972246da4SFelipe Balbi /** 4301d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 43172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 43272246da4SFelipe Balbi * @length: size of the event buffer 43372246da4SFelipe Balbi * 4341d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 43572246da4SFelipe Balbi * otherwise ERR_PTR(errno). 43672246da4SFelipe Balbi */ 43767d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 438ca80ca61SKushagra Verma unsigned int length) 43972246da4SFelipe Balbi { 44072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 44172246da4SFelipe Balbi 442380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 44372246da4SFelipe Balbi if (!evt) 44472246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44572246da4SFelipe Balbi 44672246da4SFelipe Balbi evt->dwc = dwc; 44772246da4SFelipe Balbi evt->length = length; 448d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 449d9fa4c63SJohn Youn if (!evt->cache) 450d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 451d9fa4c63SJohn Youn 452d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 45372246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 454e32672f0SFelipe Balbi if (!evt->buf) 45572246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 45672246da4SFelipe Balbi 45772246da4SFelipe Balbi return evt; 45872246da4SFelipe Balbi } 45972246da4SFelipe Balbi 46072246da4SFelipe Balbi /** 46172246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 46272246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 46372246da4SFelipe Balbi */ 46472246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 46572246da4SFelipe Balbi { 46672246da4SFelipe Balbi struct dwc3_event_buffer *evt; 46772246da4SFelipe Balbi 468696c8b12SFelipe Balbi evt = dwc->ev_buf; 46964b6c8a7SAnton Tikhomirov if (evt) 47072246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 47172246da4SFelipe Balbi } 47272246da4SFelipe Balbi 47372246da4SFelipe Balbi /** 47472246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4751d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 47672246da4SFelipe Balbi * @length: size of event buffer 47772246da4SFelipe Balbi * 4781d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 47972246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 48072246da4SFelipe Balbi */ 481ca80ca61SKushagra Verma static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 48272246da4SFelipe Balbi { 48372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 48472246da4SFelipe Balbi 48572246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 48672246da4SFelipe Balbi if (IS_ERR(evt)) { 48772246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 48872246da4SFelipe Balbi return PTR_ERR(evt); 48972246da4SFelipe Balbi } 490696c8b12SFelipe Balbi dwc->ev_buf = evt; 49172246da4SFelipe Balbi 49272246da4SFelipe Balbi return 0; 49372246da4SFelipe Balbi } 49472246da4SFelipe Balbi 49572246da4SFelipe Balbi /** 49672246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4971d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 49872246da4SFelipe Balbi * 49972246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 50072246da4SFelipe Balbi */ 501f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 50272246da4SFelipe Balbi { 50372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 50472246da4SFelipe Balbi 505696c8b12SFelipe Balbi evt = dwc->ev_buf; 5067acd85e0SPaul Zimmerman evt->lpos = 0; 507660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 50872246da4SFelipe Balbi lower_32_bits(evt->dma)); 509660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 51072246da4SFelipe Balbi upper_32_bits(evt->dma)); 511660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 51268d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 513660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 51472246da4SFelipe Balbi 51572246da4SFelipe Balbi return 0; 51672246da4SFelipe Balbi } 51772246da4SFelipe Balbi 518f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 51972246da4SFelipe Balbi { 52072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 52172246da4SFelipe Balbi 522696c8b12SFelipe Balbi evt = dwc->ev_buf; 5237acd85e0SPaul Zimmerman 5247acd85e0SPaul Zimmerman evt->lpos = 0; 5257acd85e0SPaul Zimmerman 526660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 527660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 528660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 52968d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 530660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 53172246da4SFelipe Balbi } 53272246da4SFelipe Balbi 5330ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5340ffcaf37SFelipe Balbi { 5350ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5360ffcaf37SFelipe Balbi return 0; 5370ffcaf37SFelipe Balbi 5380ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5390ffcaf37SFelipe Balbi return 0; 5400ffcaf37SFelipe Balbi 5410ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5420ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5430ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5440ffcaf37SFelipe Balbi return -ENOMEM; 5450ffcaf37SFelipe Balbi 5460ffcaf37SFelipe Balbi return 0; 5470ffcaf37SFelipe Balbi } 5480ffcaf37SFelipe Balbi 5490ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5500ffcaf37SFelipe Balbi { 5510ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5520ffcaf37SFelipe Balbi u32 param; 5530ffcaf37SFelipe Balbi int ret; 5540ffcaf37SFelipe Balbi 5550ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5560ffcaf37SFelipe Balbi return 0; 5570ffcaf37SFelipe Balbi 5580ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5590ffcaf37SFelipe Balbi return 0; 5600ffcaf37SFelipe Balbi 5610ffcaf37SFelipe Balbi /* should never fall here */ 5620ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5630ffcaf37SFelipe Balbi return 0; 5640ffcaf37SFelipe Balbi 565d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5660ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5670ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 568d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 569d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5700ffcaf37SFelipe Balbi ret = -EFAULT; 5710ffcaf37SFelipe Balbi goto err0; 5720ffcaf37SFelipe Balbi } 5730ffcaf37SFelipe Balbi 5740ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5750ffcaf37SFelipe Balbi 5760ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5770ffcaf37SFelipe Balbi 5780ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5790ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5800ffcaf37SFelipe Balbi if (ret < 0) 5810ffcaf37SFelipe Balbi goto err1; 5820ffcaf37SFelipe Balbi 5830ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5840ffcaf37SFelipe Balbi 5850ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5860ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5870ffcaf37SFelipe Balbi if (ret < 0) 5880ffcaf37SFelipe Balbi goto err1; 5890ffcaf37SFelipe Balbi 5900ffcaf37SFelipe Balbi return 0; 5910ffcaf37SFelipe Balbi 5920ffcaf37SFelipe Balbi err1: 593d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5940ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5950ffcaf37SFelipe Balbi 5960ffcaf37SFelipe Balbi err0: 5970ffcaf37SFelipe Balbi return ret; 5980ffcaf37SFelipe Balbi } 5990ffcaf37SFelipe Balbi 6000ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 6010ffcaf37SFelipe Balbi { 6020ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 6030ffcaf37SFelipe Balbi return; 6040ffcaf37SFelipe Balbi 6050ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 6060ffcaf37SFelipe Balbi return; 6070ffcaf37SFelipe Balbi 6080ffcaf37SFelipe Balbi /* should never fall here */ 6090ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6100ffcaf37SFelipe Balbi return; 6110ffcaf37SFelipe Balbi 612d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6130ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6140ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6150ffcaf37SFelipe Balbi } 6160ffcaf37SFelipe Balbi 617789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 618789451f6SFelipe Balbi { 619789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 620789451f6SFelipe Balbi 62147d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 622789451f6SFelipe Balbi } 623789451f6SFelipe Balbi 62441ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 62526ceca97SFelipe Balbi { 62626ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 62726ceca97SFelipe Balbi 62826ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 62926ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 63026ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 63126ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 63226ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 63326ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 63426ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 63526ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 63626ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 63716710380SThinh Nguyen 63816710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 63916710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 64026ceca97SFelipe Balbi } 64126ceca97SFelipe Balbi 64298112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 64398112041SRoger Quadros { 64498112041SRoger Quadros int intf; 64598112041SRoger Quadros int ret = 0; 64698112041SRoger Quadros 64798112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 64898112041SRoger Quadros 64998112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 65098112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 65198112041SRoger Quadros dwc->hsphy_interface && 65298112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 65398112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 65498112041SRoger Quadros 65598112041SRoger Quadros return ret; 65698112041SRoger Quadros } 65798112041SRoger Quadros 65872246da4SFelipe Balbi /** 659b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 660b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 66188bc9d19SHeikki Krogerus * 66288bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 66388bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 66488bc9d19SHeikki Krogerus * the core in dwc3_core_init. 665b5a65c40SHuang Rui */ 66688bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 667b5a65c40SHuang Rui { 6689ba3aca8SThinh Nguyen unsigned int hw_mode; 669b5a65c40SHuang Rui u32 reg; 670b5a65c40SHuang Rui 6719ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6729ba3aca8SThinh Nguyen 673b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 674b5a65c40SHuang Rui 6752164a476SHuang Rui /* 6761966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6771966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6781966b865SFelipe Balbi */ 6791966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6801966b865SFelipe Balbi 6811966b865SFelipe Balbi /* 6822164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6832164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6842164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6852164a476SHuang Rui * to '1' after the core initialization is completed. 6862164a476SHuang Rui */ 6879af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6882164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6892164a476SHuang Rui 6909ba3aca8SThinh Nguyen /* 6919ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6929ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6939ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6949ba3aca8SThinh Nguyen */ 6959ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6969ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6979ba3aca8SThinh Nguyen 698b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 699b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 700b5a65c40SHuang Rui 701e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 702e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 703e58dd357SRajesh Bhagat 704df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 705df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 706df31f5b3SHuang Rui 707a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 708a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 709a2a1d0f5SHuang Rui 71041c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 71141c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 71241c06ffdSHuang Rui 713fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 714fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 715fb67afcaSHuang Rui 71614f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 71714f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 71814f4ac53SHuang Rui 7196b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7206b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7216b6a0c9aSHuang Rui 722cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 72359acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 72459acfa20SHuang Rui 72500fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 72600fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 72700fe081dSWilliam Wu 728b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 729b5a65c40SHuang Rui 7302164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7312164a476SHuang Rui 7323e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7333e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7343e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 73543cacb03SFelipe Balbi if (dwc->hsphy_interface && 73643cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7373e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 73888bc9d19SHeikki Krogerus break; 73943cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 74043cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7413e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 74288bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7433e10a2ceSHeikki Krogerus } else { 74488bc9d19SHeikki Krogerus /* Relying on default value. */ 74588bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7463e10a2ceSHeikki Krogerus break; 7473e10a2ceSHeikki Krogerus } 748df561f66SGustavo A. R. Silva fallthrough; 74988bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7503e10a2ceSHeikki Krogerus default: 7513e10a2ceSHeikki Krogerus break; 7523e10a2ceSHeikki Krogerus } 7533e10a2ceSHeikki Krogerus 75432f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 75532f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 75632f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75732f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75832f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 75932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 76032f2ed86SWilliam Wu break; 76132f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 76232f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 76332f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 76432f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 76532f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 76632f2ed86SWilliam Wu break; 76732f2ed86SWilliam Wu default: 76832f2ed86SWilliam Wu break; 76932f2ed86SWilliam Wu } 77032f2ed86SWilliam Wu 7712164a476SHuang Rui /* 7722164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7732164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7742164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7752164a476SHuang Rui * '1' after the core initialization is completed. 7762164a476SHuang Rui */ 7779af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7782164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7792164a476SHuang Rui 7809ba3aca8SThinh Nguyen /* 7819ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7829ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7839ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7849ba3aca8SThinh Nguyen */ 7859ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7869ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7879ba3aca8SThinh Nguyen 788cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7890effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7900effe0a3SHuang Rui 791ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 792ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 793eafeacf1SThinh Nguyen else 794eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 795ec791d14SJohn Youn 796a6fc2f1bSAlexander Stein if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 79716199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 79816199f33SWilliam Wu 7992164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 80088bc9d19SHeikki Krogerus 80188bc9d19SHeikki Krogerus return 0; 802b5a65c40SHuang Rui } 803b5a65c40SHuang Rui 80433fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 80533fb697eSSean Anderson { 80633fb697eSSean Anderson int ret; 80733fb697eSSean Anderson 80833fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 80933fb697eSSean Anderson if (ret) 81033fb697eSSean Anderson return ret; 81133fb697eSSean Anderson 81233fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 81333fb697eSSean Anderson if (ret) 81433fb697eSSean Anderson goto disable_bus_clk; 81533fb697eSSean Anderson 81633fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 81733fb697eSSean Anderson if (ret) 81833fb697eSSean Anderson goto disable_ref_clk; 81933fb697eSSean Anderson 82033fb697eSSean Anderson return 0; 82133fb697eSSean Anderson 82233fb697eSSean Anderson disable_ref_clk: 82333fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82433fb697eSSean Anderson disable_bus_clk: 82533fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82633fb697eSSean Anderson return ret; 82733fb697eSSean Anderson } 82833fb697eSSean Anderson 82933fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 83033fb697eSSean Anderson { 83133fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 83233fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 83333fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 83433fb697eSSean Anderson } 83533fb697eSSean Anderson 836c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 837c499ff71SFelipe Balbi { 838c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 839c499ff71SFelipe Balbi 840d2ac7befSJohan Hovold usb_phy_set_suspend(dwc->usb2_phy, 1); 841d2ac7befSJohan Hovold usb_phy_set_suspend(dwc->usb3_phy, 1); 842d2ac7befSJohan Hovold phy_power_off(dwc->usb2_generic_phy); 843d2ac7befSJohan Hovold phy_power_off(dwc->usb3_generic_phy); 844d2ac7befSJohan Hovold 845c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 846c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 847c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 848c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 849c499ff71SFelipe Balbi 85033fb697eSSean Anderson dwc3_clk_disable(dwc); 851fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 852c499ff71SFelipe Balbi } 853c499ff71SFelipe Balbi 8540759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 85572246da4SFelipe Balbi { 85672246da4SFelipe Balbi u32 reg; 85772246da4SFelipe Balbi 8587650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8599af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8600759956fSFelipe Balbi 8617650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8629af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 863690fb371SJohn Youn dwc->revision = reg; 8649af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 865690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 866475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 867690fb371SJohn Youn } else { 8680759956fSFelipe Balbi return false; 8697650bd74SSebastian Andrzej Siewior } 8707650bd74SSebastian Andrzej Siewior 8710759956fSFelipe Balbi return true; 8720e1e5c47SPaul Zimmerman } 8730e1e5c47SPaul Zimmerman 874941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 87572246da4SFelipe Balbi { 87672246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 87772246da4SFelipe Balbi u32 reg; 878c499ff71SFelipe Balbi 8794878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8803e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8814878a028SSebastian Andrzej Siewior 882164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8834878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 88432a4a135SFelipe Balbi /** 88532a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 88632a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 88732a4a135SFelipe Balbi * 88832a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 88932a4a135SFelipe Balbi * configurations. 89032a4a135SFelipe Balbi * 89132a4a135SFelipe Balbi * Refers to: 89232a4a135SFelipe Balbi * 89332a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 89432a4a135SFelipe Balbi * SOF/ITP Mode Used 89532a4a135SFelipe Balbi */ 89632a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 89732a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8989af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 89932a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 90032a4a135SFelipe Balbi else 9014878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 9024878a028SSebastian Andrzej Siewior break; 9030ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 9040ffcaf37SFelipe Balbi /* enable hibernation here */ 9050ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 9062eac3992SHuang Rui 9072eac3992SHuang Rui /* 9082eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 9092eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 9102eac3992SHuang Rui */ 9112eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9120ffcaf37SFelipe Balbi break; 9134878a028SSebastian Andrzej Siewior default: 9145eb30cedSFelipe Balbi /* nothing */ 9155eb30cedSFelipe Balbi break; 9164878a028SSebastian Andrzej Siewior } 9174878a028SSebastian Andrzej Siewior 918946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 919946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9206af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 921946bd579SHuang Rui dwc->is_fpga = true; 922946bd579SHuang Rui } 923946bd579SHuang Rui 9243b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9253b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9263b81221aSHuang Rui 9273b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9283b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9293b81221aSHuang Rui else 9303b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9313b81221aSHuang Rui 9329a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9339a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9349a5b2f31SHuang Rui 9354878a028SSebastian Andrzej Siewior /* 9364878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9371d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9384878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9391d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9404878a028SSebastian Andrzej Siewior */ 9419af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9424878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9434878a028SSebastian Andrzej Siewior 9444878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 945941f918eSFelipe Balbi } 9464878a028SSebastian Andrzej Siewior 947f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 94898112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 949f54edb53SFelipe Balbi 950d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 951d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 952d9612c2fSPengbo Mu { 953d9612c2fSPengbo Mu struct device *dev = dwc->dev; 954d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 955d9612c2fSPengbo Mu bool incrx_mode; 956d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 957d9612c2fSPengbo Mu u32 incrx_size; 958d9612c2fSPengbo Mu u32 *vals; 959d9612c2fSPengbo Mu u32 cfg; 960d9612c2fSPengbo Mu int ntype; 961d9612c2fSPengbo Mu int ret; 962d9612c2fSPengbo Mu int i; 963d9612c2fSPengbo Mu 964d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 965d9612c2fSPengbo Mu 966d9612c2fSPengbo Mu /* 967d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 968d9612c2fSPengbo Mu * Get the number of value from this property: 969d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 970d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 971d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 972d9612c2fSPengbo Mu */ 973a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 974d9612c2fSPengbo Mu if (ntype <= 0) 975d9612c2fSPengbo Mu return; 976d9612c2fSPengbo Mu 977d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 9784ea15088SKushagra Verma if (!vals) 979d9612c2fSPengbo Mu return; 980d9612c2fSPengbo Mu 981d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 982d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 983d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 984d9612c2fSPengbo Mu if (ret) { 98575ecb9ddSAndy Shevchenko kfree(vals); 986d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 987d9612c2fSPengbo Mu return; 988d9612c2fSPengbo Mu } 989d9612c2fSPengbo Mu 990d9612c2fSPengbo Mu incrx_size = *vals; 991d9612c2fSPengbo Mu 992d9612c2fSPengbo Mu if (ntype > 1) { 993d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 994d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 995d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 996d9612c2fSPengbo Mu if (vals[i] > incrx_size) 997d9612c2fSPengbo Mu incrx_size = vals[i]; 998d9612c2fSPengbo Mu } 999d9612c2fSPengbo Mu } else { 1000d9612c2fSPengbo Mu /* INCRX burst mode */ 1001d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 1002d9612c2fSPengbo Mu } 1003d9612c2fSPengbo Mu 100475ecb9ddSAndy Shevchenko kfree(vals); 100575ecb9ddSAndy Shevchenko 1006d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1007d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1008d9612c2fSPengbo Mu if (incrx_mode) 1009d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1010d9612c2fSPengbo Mu switch (incrx_size) { 1011d9612c2fSPengbo Mu case 256: 1012d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1013d9612c2fSPengbo Mu break; 1014d9612c2fSPengbo Mu case 128: 1015d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1016d9612c2fSPengbo Mu break; 1017d9612c2fSPengbo Mu case 64: 1018d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1019d9612c2fSPengbo Mu break; 1020d9612c2fSPengbo Mu case 32: 1021d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1022d9612c2fSPengbo Mu break; 1023d9612c2fSPengbo Mu case 16: 1024d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1025d9612c2fSPengbo Mu break; 1026d9612c2fSPengbo Mu case 8: 1027d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1028d9612c2fSPengbo Mu break; 1029d9612c2fSPengbo Mu case 4: 1030d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1031d9612c2fSPengbo Mu break; 1032d9612c2fSPengbo Mu case 1: 1033d9612c2fSPengbo Mu break; 1034d9612c2fSPengbo Mu default: 1035d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1036d9612c2fSPengbo Mu break; 1037d9612c2fSPengbo Mu } 1038d9612c2fSPengbo Mu 1039d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1040d9612c2fSPengbo Mu } 1041d9612c2fSPengbo Mu 10423497b9a5SLi Jun static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 10433497b9a5SLi Jun { 10443497b9a5SLi Jun u32 scale; 10453497b9a5SLi Jun u32 reg; 10463497b9a5SLi Jun 10473497b9a5SLi Jun if (!dwc->susp_clk) 10483497b9a5SLi Jun return; 10493497b9a5SLi Jun 10503497b9a5SLi Jun /* 10513497b9a5SLi Jun * The power down scale field specifies how many suspend_clk 10523497b9a5SLi Jun * periods fit into a 16KHz clock period. When performing 10533497b9a5SLi Jun * the division, round up the remainder. 10543497b9a5SLi Jun * 10553497b9a5SLi Jun * The power down scale value is calculated using the fastest 10563497b9a5SLi Jun * frequency of the suspend_clk. If it isn't fixed (but within 10573497b9a5SLi Jun * the accuracy requirement), the driver may not know the max 10583497b9a5SLi Jun * rate of the suspend_clk, so only update the power down scale 10593497b9a5SLi Jun * if the default is less than the calculated value from 10603497b9a5SLi Jun * clk_get_rate() or if the default is questionably high 10613497b9a5SLi Jun * (3x or more) to be within the requirement. 10623497b9a5SLi Jun */ 10633497b9a5SLi Jun scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 10643497b9a5SLi Jun reg = dwc3_readl(dwc->regs, DWC3_GCTL); 10653497b9a5SLi Jun if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 10663497b9a5SLi Jun (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 10673497b9a5SLi Jun reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 10683497b9a5SLi Jun reg |= DWC3_GCTL_PWRDNSCALE(scale); 10693497b9a5SLi Jun dwc3_writel(dwc->regs, DWC3_GCTL, reg); 10703497b9a5SLi Jun } 10713497b9a5SLi Jun } 10723497b9a5SLi Jun 1073941f918eSFelipe Balbi /** 1074941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1075941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1076941f918eSFelipe Balbi * 1077941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1078941f918eSFelipe Balbi */ 1079941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1080941f918eSFelipe Balbi { 10819ba3aca8SThinh Nguyen unsigned int hw_mode; 1082941f918eSFelipe Balbi u32 reg; 1083941f918eSFelipe Balbi int ret; 1084941f918eSFelipe Balbi 10859ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10869ba3aca8SThinh Nguyen 1087941f918eSFelipe Balbi /* 1088941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1089941f918eSFelipe Balbi * out which kernel version a bug was found. 1090941f918eSFelipe Balbi */ 1091941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1092941f918eSFelipe Balbi 1093941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1094941f918eSFelipe Balbi if (ret) 1095941f918eSFelipe Balbi goto err0; 1096941f918eSFelipe Balbi 109798112041SRoger Quadros if (!dwc->ulpi_ready) { 109898112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 109998112041SRoger Quadros if (ret) 110098112041SRoger Quadros goto err0; 110198112041SRoger Quadros dwc->ulpi_ready = true; 110298112041SRoger Quadros } 110398112041SRoger Quadros 110498112041SRoger Quadros if (!dwc->phys_ready) { 110598112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 110698112041SRoger Quadros if (ret) 110798112041SRoger Quadros goto err0a; 110898112041SRoger Quadros dwc->phys_ready = true; 110998112041SRoger Quadros } 111098112041SRoger Quadros 11118cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 11128cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 11138cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 11148cfac9a6SLi Jun if (ret < 0) 11158cfac9a6SLi Jun goto err0a; 11168cfac9a6SLi Jun 11178cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 11188cfac9a6SLi Jun if (ret < 0) { 11198cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 11208cfac9a6SLi Jun goto err0a; 11218cfac9a6SLi Jun } 11228cfac9a6SLi Jun 112398112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 112498112041SRoger Quadros if (ret) 11258cfac9a6SLi Jun goto err1; 112698112041SRoger Quadros 11279ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 11289af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 11299ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 11309ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 11319ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 11329ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 11339ba3aca8SThinh Nguyen } 11349ba3aca8SThinh Nguyen 11359ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 11369ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 11379ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 11389ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 11399ba3aca8SThinh Nguyen } 11409ba3aca8SThinh Nguyen } 11419ba3aca8SThinh Nguyen 1142941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1143c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11440ffcaf37SFelipe Balbi 11450ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11460ffcaf37SFelipe Balbi if (ret) 1147c499ff71SFelipe Balbi goto err1; 1148c499ff71SFelipe Balbi 11493497b9a5SLi Jun /* Set power down scale of suspend_clk */ 11503497b9a5SLi Jun dwc3_set_power_down_clk_scale(dwc); 11513497b9a5SLi Jun 1152c499ff71SFelipe Balbi /* Adjust Frame Length */ 1153c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1154c499ff71SFelipe Balbi 11557bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11567bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11577bee3188SBalaji Prakash J 1158d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1159d9612c2fSPengbo Mu 1160c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1161c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1162c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1163c499ff71SFelipe Balbi if (ret < 0) 11640ffcaf37SFelipe Balbi goto err2; 11650ffcaf37SFelipe Balbi 1166c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1167c499ff71SFelipe Balbi if (ret < 0) 1168c499ff71SFelipe Balbi goto err3; 1169c499ff71SFelipe Balbi 1170c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1171c499ff71SFelipe Balbi if (ret) { 1172c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1173c499ff71SFelipe Balbi goto err4; 1174c499ff71SFelipe Balbi } 1175c499ff71SFelipe Balbi 117606281d46SJohn Youn /* 117706281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 117806281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 117906281d46SJohn Youn * DWC_usb31 controller. 118006281d46SJohn Youn */ 11819af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 118206281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 118306281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 118406281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 118506281d46SJohn Youn } 118606281d46SJohn Youn 118763d7f981SPiyush Mehta /* 118863d7f981SPiyush Mehta * When configured in HOST mode, after issuing U3/L2 exit controller 118963d7f981SPiyush Mehta * fails to send proper CRC checksum in CRC5 feild. Because of this 119063d7f981SPiyush Mehta * behaviour Transaction Error is generated, resulting in reset and 119163d7f981SPiyush Mehta * re-enumeration of usb device attached. All the termsel, xcvrsel, 119263d7f981SPiyush Mehta * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 119363d7f981SPiyush Mehta * will correct this problem. This option is to support certain 119463d7f981SPiyush Mehta * legacy ULPI PHYs. 119563d7f981SPiyush Mehta */ 119663d7f981SPiyush Mehta if (dwc->resume_hs_terminations) { 119763d7f981SPiyush Mehta reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 119863d7f981SPiyush Mehta reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 119963d7f981SPiyush Mehta dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 120063d7f981SPiyush Mehta } 120163d7f981SPiyush Mehta 12029af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 12030bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 120465db7a0cSWilliam Wu 120565db7a0cSWilliam Wu /* 120665db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 120765db7a0cSWilliam Wu * in HS when the device is in the L1 state. 120865db7a0cSWilliam Wu */ 12099af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 12100bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 121165db7a0cSWilliam Wu 1212843714bbSJack Pham /* 1213843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1214843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1215843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1216843714bbSJack Pham * from interrupting the driver. 1217843714bbSJack Pham */ 1218843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1219843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1220843714bbSJack Pham 122165db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 122265db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 122365db7a0cSWilliam Wu 12247ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 12257ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 12267ba6b09fSNeil Armstrong 122762b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 122862b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 122962b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 123062b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 123162b20e6eSBin Yang 12320bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 12330bb39ca1SJohn Youn } 12340bb39ca1SJohn Youn 1235b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1236b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1237b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1238b138e23dSAnurag Kumar Vulisha 1239b138e23dSAnurag Kumar Vulisha /* 1240b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1241b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1242b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1243b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1244b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1245b138e23dSAnurag Kumar Vulisha */ 1246b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1247b138e23dSAnurag Kumar Vulisha 1248b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1249b138e23dSAnurag Kumar Vulisha } 1250b138e23dSAnurag Kumar Vulisha 1251938a5ad1SThinh Nguyen /* 1252938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1253938a5ad1SThinh Nguyen * RX and/or TX threshold. 1254938a5ad1SThinh Nguyen */ 12559af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1256938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1257938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1258938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1259938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1260938a5ad1SThinh Nguyen 1261938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1262938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1263938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1264938a5ad1SThinh Nguyen 1265938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1266938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1267938a5ad1SThinh Nguyen 1268938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1269938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1270938a5ad1SThinh Nguyen 1271938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1272938a5ad1SThinh Nguyen } 1273938a5ad1SThinh Nguyen 1274938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1275938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1276938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1277938a5ad1SThinh Nguyen 1278938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1279938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1280938a5ad1SThinh Nguyen 1281938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1282938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1283938a5ad1SThinh Nguyen 1284938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1285938a5ad1SThinh Nguyen } 1286938a5ad1SThinh Nguyen } 1287938a5ad1SThinh Nguyen 128872246da4SFelipe Balbi return 0; 128972246da4SFelipe Balbi 1290c499ff71SFelipe Balbi err4: 12919b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1292c499ff71SFelipe Balbi 1293c499ff71SFelipe Balbi err3: 12949b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1295c499ff71SFelipe Balbi 12960ffcaf37SFelipe Balbi err2: 1297c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1298c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12990ffcaf37SFelipe Balbi 13000ffcaf37SFelipe Balbi err1: 13010ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 13020ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 130357303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 130457303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 13050ffcaf37SFelipe Balbi 130698112041SRoger Quadros err0a: 130798112041SRoger Quadros dwc3_ulpi_exit(dwc); 130898112041SRoger Quadros 130972246da4SFelipe Balbi err0: 131072246da4SFelipe Balbi return ret; 131172246da4SFelipe Balbi } 131272246da4SFelipe Balbi 13133c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 131472246da4SFelipe Balbi { 13153c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1316941ea361SFelipe Balbi struct device_node *node = dev->of_node; 13173c9f94acSFelipe Balbi int ret; 131872246da4SFelipe Balbi 13195088b6f5SKishon Vijay Abraham I if (node) { 13205088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 13215088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1322bb674907SFelipe Balbi } else { 1323bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1324bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 13255088b6f5SKishon Vijay Abraham I } 13265088b6f5SKishon Vijay Abraham I 1327d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1328d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1329d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1330122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1331d090c7a2SKushagra Verma else 13320c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1333122f06e6SKishon Vijay Abraham I } 133451e1e7bcSFelipe Balbi 1335d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1336315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1337d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1338122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1339d090c7a2SKushagra Verma else 13400c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1341122f06e6SKishon Vijay Abraham I } 134251e1e7bcSFelipe Balbi 134357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 134457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 134557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 1346fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 134757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 1348d090c7a2SKushagra Verma else 13490c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 135057303488SKishon Vijay Abraham I } 135157303488SKishon Vijay Abraham I 135257303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 135357303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 135457303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 1355fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 135657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 1357d090c7a2SKushagra Verma else 13580c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 135957303488SKishon Vijay Abraham I } 136057303488SKishon Vijay Abraham I 13613c9f94acSFelipe Balbi return 0; 13623c9f94acSFelipe Balbi } 13633c9f94acSFelipe Balbi 13645f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13655f94adfeSFelipe Balbi { 13665f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13675f94adfeSFelipe Balbi int ret; 13685f94adfeSFelipe Balbi 13695f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13705f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 137141ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1372958d1a4cSFelipe Balbi 1373958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1374958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1375958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1376644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1377958d1a4cSFelipe Balbi 13785f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13790c0a20f6SAndy Shevchenko if (ret) 13800c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13815f94adfeSFelipe Balbi break; 13825f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 138341ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1384958d1a4cSFelipe Balbi 1385958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1386958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1387958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1388644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1389958d1a4cSFelipe Balbi 13905f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13910c0a20f6SAndy Shevchenko if (ret) 13920c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13935f94adfeSFelipe Balbi break; 13945f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 139541ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13969840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13970c0a20f6SAndy Shevchenko if (ret) 13980c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13995f94adfeSFelipe Balbi break; 14005f94adfeSFelipe Balbi default: 14015f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 14025f94adfeSFelipe Balbi return -EINVAL; 14035f94adfeSFelipe Balbi } 14045f94adfeSFelipe Balbi 14055f94adfeSFelipe Balbi return 0; 14065f94adfeSFelipe Balbi } 14075f94adfeSFelipe Balbi 14085f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 14095f94adfeSFelipe Balbi { 14105f94adfeSFelipe Balbi switch (dwc->dr_mode) { 14115f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 14125f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 14135f94adfeSFelipe Balbi break; 14145f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 14155f94adfeSFelipe Balbi dwc3_host_exit(dwc); 14165f94adfeSFelipe Balbi break; 14175f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 14189840354fSRoger Quadros dwc3_drd_exit(dwc); 14195f94adfeSFelipe Balbi break; 14205f94adfeSFelipe Balbi default: 14215f94adfeSFelipe Balbi /* do nothing */ 14225f94adfeSFelipe Balbi break; 14235f94adfeSFelipe Balbi } 142409ed259fSBin Liu 142509ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 142609ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 14275f94adfeSFelipe Balbi } 14285f94adfeSFelipe Balbi 1429c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 14303c9f94acSFelipe Balbi { 1431c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 143280caf7d2SHuang Rui u8 lpm_nyet_threshold; 14336b6a0c9aSHuang Rui u8 tx_de_emphasis; 1434460d098cSHuang Rui u8 hird_threshold; 1435f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0; 1436f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0; 1437f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0; 1438f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0; 14399f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 14406f0764b5SRay Chi const char *usb_psy_name; 14416f0764b5SRay Chi int ret; 14423c9f94acSFelipe Balbi 144380caf7d2SHuang Rui /* default to highest possible threshold */ 14448d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 144580caf7d2SHuang Rui 14466b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 14476b6a0c9aSHuang Rui tx_de_emphasis = 1; 14486b6a0c9aSHuang Rui 1449460d098cSHuang Rui /* 1450460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1451460d098cSHuang Rui * threshold value of 0b1100 1452460d098cSHuang Rui */ 1453460d098cSHuang Rui hird_threshold = 12; 1454460d098cSHuang Rui 14559f607a30SWesley Cheng /* 14569f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 14579f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14589f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14599f607a30SWesley Cheng */ 14609f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14619f607a30SWesley Cheng 146263863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 146367848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 146406e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 146532f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 146663863b98SHeikki Krogerus 1467d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1468d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1469d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1470d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1471d64ff406SArnd Bergmann else 1472d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1473d64ff406SArnd Bergmann 14746f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14756f0764b5SRay Chi if (ret >= 0) { 14766f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14776f0764b5SRay Chi if (!dwc->usb_psy) 14786f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14796f0764b5SRay Chi } 14806f0764b5SRay Chi 14813d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 148280caf7d2SHuang Rui "snps,has-lpm-erratum"); 14833d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 148480caf7d2SHuang Rui &lpm_nyet_threshold); 14853d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1486460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14873d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1488460d098cSHuang Rui &hird_threshold); 1489d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1490d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14913d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1492eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1493022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1494022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1495475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1496475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1497938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1498938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1499938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1500938a5ad1SThinh Nguyen &rx_max_burst_prd); 1501938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1502938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1503938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1504938a5ad1SThinh Nguyen &tx_max_burst_prd); 15059f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 15069f607a30SWesley Cheng "tx-fifo-resize"); 15079f607a30SWesley Cheng if (dwc->do_fifo_resize) 15089f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 15099f607a30SWesley Cheng &tx_fifo_resize_max_num); 15103c9f94acSFelipe Balbi 15113d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 15123b81221aSHuang Rui "snps,disable_scramble_quirk"); 15133d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 15149a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 15153d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1516b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 15173d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1518df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 15193d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1520a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 15213d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 152241c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 15233d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1524fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 15253d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 152614f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 15273d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 152859acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 15293d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 15300effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1531ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1532ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1533729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1534729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1535729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1536729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1537e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1538e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 153916199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 154016199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 154100fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 154200fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 154365db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 154465db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 154563d7f981SPiyush Mehta dwc->resume_hs_terminations = device_property_read_bool(dev, 154663d7f981SPiyush Mehta "snps,resume-hs-terminations"); 15477ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 15487ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 1549a6fc2f1bSAlexander Stein dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1550a6fc2f1bSAlexander Stein "snps,gfladj-refclk-lpm-sel-quirk"); 15516b6a0c9aSHuang Rui 15523d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 15536b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 15543d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 15556b6a0c9aSHuang Rui &tx_de_emphasis); 15563d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 15573e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 15583d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1559bcdb3272SFelipe Balbi &dwc->fladj); 15607bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 15617bee3188SBalaji Prakash J &dwc->ref_clk_per); 15623d128919SHeikki Krogerus 156342bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 156442bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 156542bf02ecSRoger Quadros 1566f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1567f580170fSYu Chen "snps,dis-split-quirk"); 1568f580170fSYu Chen 156980caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15706b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 157180caf7d2SHuang Rui 157216fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1573460d098cSHuang Rui 1574938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1575938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1576938a5ad1SThinh Nguyen 1577938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1578938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1579938a5ad1SThinh Nguyen 1580cf40b86bSJohn Youn dwc->imod_interval = 0; 15819f607a30SWesley Cheng 15829f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1583cf40b86bSJohn Youn } 1584cf40b86bSJohn Youn 1585cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1586cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1587cf40b86bSJohn Youn { 15889af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15899af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15909af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1591c5ac6116SFelipe Balbi } 1592c5ac6116SFelipe Balbi 15937ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15947ac51a12SJohn Youn { 15957ac51a12SJohn Youn struct device *dev = dwc->dev; 1596b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1597b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15987ac51a12SJohn Youn 1599cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1600cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1601cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1602cf40b86bSJohn Youn dwc->imod_interval = 0; 1603cf40b86bSJohn Youn } 1604cf40b86bSJohn Youn 160528632b44SJohn Youn /* 160628632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 160728632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 160828632b44SJohn Youn * interrupt from being masked while handling events. IMOD 160928632b44SJohn Youn * allows us to work around this issue. Enable it for the 161028632b44SJohn Youn * affected version. 161128632b44SJohn Youn */ 161228632b44SJohn Youn if (!dwc->imod_interval && 16139af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 161428632b44SJohn Youn dwc->imod_interval = 1; 161528632b44SJohn Youn 16167ac51a12SJohn Youn /* Check the maximum_speed parameter */ 16177ac51a12SJohn Youn switch (dwc->maximum_speed) { 16187ac51a12SJohn Youn case USB_SPEED_FULL: 16197ac51a12SJohn Youn case USB_SPEED_HIGH: 1620e518bdd9SThinh Nguyen break; 16217ac51a12SJohn Youn case USB_SPEED_SUPER: 1622e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1623e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1624e518bdd9SThinh Nguyen break; 16257ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1626e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1627e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1628e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1629e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1630e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 16317ac51a12SJohn Youn break; 16327ac51a12SJohn Youn default: 16337ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 16347ac51a12SJohn Youn dwc->maximum_speed); 1635df561f66SGustavo A. R. Silva fallthrough; 16367ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1637b574ce3eSThinh Nguyen switch (hwparam_gen) { 1638b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 16397ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1640b574ce3eSThinh Nguyen break; 1641b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1642b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1643b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1644b574ce3eSThinh Nguyen else 1645b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1646b574ce3eSThinh Nguyen break; 1647b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1648b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1649b574ce3eSThinh Nguyen break; 1650b574ce3eSThinh Nguyen default: 1651b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1652b574ce3eSThinh Nguyen break; 1653b574ce3eSThinh Nguyen } 16547ac51a12SJohn Youn break; 16557ac51a12SJohn Youn } 165667848146SThinh Nguyen 165767848146SThinh Nguyen /* 165867848146SThinh Nguyen * Currently the controller does not have visibility into the HW 165967848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 166067848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 166167848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 166267848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 166367848146SThinh Nguyen */ 166467848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 166567848146SThinh Nguyen switch (dwc->max_ssp_rate) { 166667848146SThinh Nguyen case USB_SSP_GEN_2x1: 166767848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 166867848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 166967848146SThinh Nguyen break; 167067848146SThinh Nguyen case USB_SSP_GEN_1x2: 167167848146SThinh Nguyen case USB_SSP_GEN_2x2: 167267848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 167367848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 167467848146SThinh Nguyen break; 167567848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 167667848146SThinh Nguyen default: 167767848146SThinh Nguyen switch (hwparam_gen) { 167867848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 167967848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 168067848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 168167848146SThinh Nguyen else 168267848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 168367848146SThinh Nguyen break; 168467848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 168567848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 168667848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 168767848146SThinh Nguyen break; 168867848146SThinh Nguyen } 168967848146SThinh Nguyen break; 169067848146SThinh Nguyen } 169167848146SThinh Nguyen } 16927ac51a12SJohn Youn } 16937ac51a12SJohn Youn 1694d182c2e1SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1695d182c2e1SAndrey Smirnov { 1696d182c2e1SAndrey Smirnov struct device *dev = dwc->dev; 1697d182c2e1SAndrey Smirnov struct device_node *np_phy; 1698d182c2e1SAndrey Smirnov struct extcon_dev *edev = NULL; 1699d182c2e1SAndrey Smirnov const char *name; 1700d182c2e1SAndrey Smirnov 1701d182c2e1SAndrey Smirnov if (device_property_read_bool(dev, "extcon")) 1702d182c2e1SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0); 1703d182c2e1SAndrey Smirnov 1704d182c2e1SAndrey Smirnov /* 1705d182c2e1SAndrey Smirnov * Device tree platforms should get extcon via phandle. 1706d182c2e1SAndrey Smirnov * On ACPI platforms, we get the name from a device property. 1707d182c2e1SAndrey Smirnov * This device property is for kernel internal use only and 1708d182c2e1SAndrey Smirnov * is expected to be set by the glue code. 1709d182c2e1SAndrey Smirnov */ 1710d182c2e1SAndrey Smirnov if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1711d182c2e1SAndrey Smirnov return extcon_get_extcon_dev(name); 1712d182c2e1SAndrey Smirnov 1713d182c2e1SAndrey Smirnov /* 1714*d68cc25bSJanne Grunau * Check explicitly if "usb-role-switch" is used since 1715*d68cc25bSJanne Grunau * extcon_find_edev_by_node() can not be used to check the absence of 1716*d68cc25bSJanne Grunau * an extcon device. In the absence of an device it will always return 1717*d68cc25bSJanne Grunau * EPROBE_DEFER. 1718*d68cc25bSJanne Grunau */ 1719*d68cc25bSJanne Grunau if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1720*d68cc25bSJanne Grunau device_property_read_bool(dev, "usb-role-switch")) 1721*d68cc25bSJanne Grunau return NULL; 1722*d68cc25bSJanne Grunau 1723*d68cc25bSJanne Grunau /* 1724d182c2e1SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port" 1725d182c2e1SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the 1726d182c2e1SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon 1727d182c2e1SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch" 1728d182c2e1SAndrey Smirnov * or OTG mode. 1729d182c2e1SAndrey Smirnov */ 1730d182c2e1SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1731d182c2e1SAndrey Smirnov if (of_graph_is_present(np_phy)) { 1732d182c2e1SAndrey Smirnov struct device_node *np_conn; 1733d182c2e1SAndrey Smirnov 1734d182c2e1SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1735d182c2e1SAndrey Smirnov if (np_conn) 1736d182c2e1SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn); 1737d182c2e1SAndrey Smirnov of_node_put(np_conn); 1738d182c2e1SAndrey Smirnov } 1739d182c2e1SAndrey Smirnov of_node_put(np_phy); 1740d182c2e1SAndrey Smirnov 1741d182c2e1SAndrey Smirnov return edev; 1742d182c2e1SAndrey Smirnov } 1743d182c2e1SAndrey Smirnov 1744c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1745c5ac6116SFelipe Balbi { 1746c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 174744feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1748c5ac6116SFelipe Balbi struct dwc3 *dwc; 1749c5ac6116SFelipe Balbi 1750c5ac6116SFelipe Balbi int ret; 1751c5ac6116SFelipe Balbi 1752c5ac6116SFelipe Balbi void __iomem *regs; 1753c5ac6116SFelipe Balbi 1754c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1755c5ac6116SFelipe Balbi if (!dwc) 1756c5ac6116SFelipe Balbi return -ENOMEM; 1757c5ac6116SFelipe Balbi 1758c5ac6116SFelipe Balbi dwc->dev = dev; 1759c5ac6116SFelipe Balbi 1760c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1761c5ac6116SFelipe Balbi if (!res) { 1762c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1763c5ac6116SFelipe Balbi return -ENODEV; 1764c5ac6116SFelipe Balbi } 1765c5ac6116SFelipe Balbi 1766c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1767c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1768c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1769c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1770c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1771c5ac6116SFelipe Balbi 1772c5ac6116SFelipe Balbi /* 1773c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1774c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1775c5ac6116SFelipe Balbi */ 177644feb8e6SMasahiro Yamada dwc_res = *res; 177744feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 177844feb8e6SMasahiro Yamada 177944feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 178044feb8e6SMasahiro Yamada if (IS_ERR(regs)) 178144feb8e6SMasahiro Yamada return PTR_ERR(regs); 1782c5ac6116SFelipe Balbi 1783c5ac6116SFelipe Balbi dwc->regs = regs; 178444feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1785c5ac6116SFelipe Balbi 1786c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1787c5ac6116SFelipe Balbi 1788babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 17892a735e4bSDan Carpenter if (IS_ERR(dwc->reset)) { 17902a735e4bSDan Carpenter ret = PTR_ERR(dwc->reset); 17912a735e4bSDan Carpenter goto put_usb_psy; 17922a735e4bSDan Carpenter } 1793fe8abf33SMasahiro Yamada 179461527777SHans de Goede if (dev->of_node) { 1795fe8abf33SMasahiro Yamada /* 179661527777SHans de Goede * Clocks are optional, but new DT platforms should support all 179761527777SHans de Goede * clocks as required by the DT-binding. 17984e64cd77SPeter Geis * Some devices have different clock names in legacy device trees, 17994e64cd77SPeter Geis * check for them to retain backwards compatibility. 1800fe8abf33SMasahiro Yamada */ 180133fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 18022a735e4bSDan Carpenter if (IS_ERR(dwc->bus_clk)) { 18032a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 180433fb697eSSean Anderson "could not get bus clock\n"); 18052a735e4bSDan Carpenter goto put_usb_psy; 18062a735e4bSDan Carpenter } 18070d3a9708SJohn Stultz 18084e64cd77SPeter Geis if (dwc->bus_clk == NULL) { 18094e64cd77SPeter Geis dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 18102a735e4bSDan Carpenter if (IS_ERR(dwc->bus_clk)) { 18112a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 18124e64cd77SPeter Geis "could not get bus clock\n"); 18132a735e4bSDan Carpenter goto put_usb_psy; 18142a735e4bSDan Carpenter } 18154e64cd77SPeter Geis } 18164e64cd77SPeter Geis 181733fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 18182a735e4bSDan Carpenter if (IS_ERR(dwc->ref_clk)) { 18192a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 182033fb697eSSean Anderson "could not get ref clock\n"); 18212a735e4bSDan Carpenter goto put_usb_psy; 18222a735e4bSDan Carpenter } 182333fb697eSSean Anderson 18244e64cd77SPeter Geis if (dwc->ref_clk == NULL) { 18254e64cd77SPeter Geis dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 18262a735e4bSDan Carpenter if (IS_ERR(dwc->ref_clk)) { 18272a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 18284e64cd77SPeter Geis "could not get ref clock\n"); 18292a735e4bSDan Carpenter goto put_usb_psy; 18302a735e4bSDan Carpenter } 18314e64cd77SPeter Geis } 18324e64cd77SPeter Geis 183333fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 18342a735e4bSDan Carpenter if (IS_ERR(dwc->susp_clk)) { 18352a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 183633fb697eSSean Anderson "could not get suspend clock\n"); 18372a735e4bSDan Carpenter goto put_usb_psy; 18382a735e4bSDan Carpenter } 18394e64cd77SPeter Geis 18404e64cd77SPeter Geis if (dwc->susp_clk == NULL) { 18414e64cd77SPeter Geis dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 18422a735e4bSDan Carpenter if (IS_ERR(dwc->susp_clk)) { 18432a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 18444e64cd77SPeter Geis "could not get suspend clock\n"); 18452a735e4bSDan Carpenter goto put_usb_psy; 18462a735e4bSDan Carpenter } 18474e64cd77SPeter Geis } 184861527777SHans de Goede } 1849fe8abf33SMasahiro Yamada 1850fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1851fe8abf33SMasahiro Yamada if (ret) 18522a735e4bSDan Carpenter goto put_usb_psy; 1853fe8abf33SMasahiro Yamada 185433fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1855fe8abf33SMasahiro Yamada if (ret) 1856fe8abf33SMasahiro Yamada goto assert_reset; 1857fe8abf33SMasahiro Yamada 1858dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1859dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1860dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1861dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1862dc1b5d9aSEnric Balletbo i Serra } 1863dc1b5d9aSEnric Balletbo i Serra 18646c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 18652917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 18666c89cce0SHeikki Krogerus 186791062e66SWilliam Wu if (!dwc->sysdev_is_parent && 186891062e66SWilliam Wu DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 186991062e66SWilliam Wu ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 187091062e66SWilliam Wu if (ret) 187191062e66SWilliam Wu goto disable_clks; 187291062e66SWilliam Wu } 187391062e66SWilliam Wu 187472246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1875f88359e1SYu Chen mutex_init(&dwc->mutex); 187672246da4SFelipe Balbi 1877fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1878fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1879fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1880802ca850SChanho Park pm_runtime_enable(dev); 188132808237SRoger Quadros ret = pm_runtime_get_sync(dev); 188232808237SRoger Quadros if (ret < 0) 188332808237SRoger Quadros goto err1; 188432808237SRoger Quadros 1885802ca850SChanho Park pm_runtime_forbid(dev); 188672246da4SFelipe Balbi 18873921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 18883921426bSFelipe Balbi if (ret) { 18893921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 18903921426bSFelipe Balbi ret = -ENOMEM; 189132808237SRoger Quadros goto err2; 18923921426bSFelipe Balbi } 18933921426bSFelipe Balbi 1894d182c2e1SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc); 1895d182c2e1SAndrey Smirnov if (IS_ERR(dwc->edev)) { 1896d182c2e1SAndrey Smirnov ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1897d182c2e1SAndrey Smirnov goto err3; 1898d182c2e1SAndrey Smirnov } 1899d182c2e1SAndrey Smirnov 19009d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 19019d6173e1SThinh Nguyen if (ret) 19029d6173e1SThinh Nguyen goto err3; 190332a4a135SFelipe Balbi 1904c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1905c499ff71SFelipe Balbi if (ret) 190632808237SRoger Quadros goto err3; 1907c499ff71SFelipe Balbi 190872246da4SFelipe Balbi ret = dwc3_core_init(dwc); 190972246da4SFelipe Balbi if (ret) { 19100c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 191132808237SRoger Quadros goto err4; 191272246da4SFelipe Balbi } 191372246da4SFelipe Balbi 19147ac51a12SJohn Youn dwc3_check_params(dwc); 191584524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 19162c7f1bd9SJohn Youn 19175f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 19185f94adfeSFelipe Balbi if (ret) 191932808237SRoger Quadros goto err5; 192072246da4SFelipe Balbi 1921fc8bb91bSFelipe Balbi pm_runtime_put(dev); 192272246da4SFelipe Balbi 192372246da4SFelipe Balbi return 0; 192472246da4SFelipe Balbi 192532808237SRoger Quadros err5: 192684524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1927f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 192803c1fd62SLi Jun 192903c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 193003c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 193103c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 193203c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 193303c1fd62SLi Jun 1934d2ac7befSJohan Hovold usb_phy_shutdown(dwc->usb2_phy); 1935d2ac7befSJohan Hovold usb_phy_shutdown(dwc->usb3_phy); 1936d2ac7befSJohan Hovold phy_exit(dwc->usb2_generic_phy); 1937d2ac7befSJohan Hovold phy_exit(dwc->usb3_generic_phy); 1938d2ac7befSJohan Hovold 193908fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1940f122d33eSFelipe Balbi 194132808237SRoger Quadros err4: 1942c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 194372246da4SFelipe Balbi 194432808237SRoger Quadros err3: 19453921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 19463921426bSFelipe Balbi 194732808237SRoger Quadros err2: 194832808237SRoger Quadros pm_runtime_allow(&pdev->dev); 194932808237SRoger Quadros 195032808237SRoger Quadros err1: 195132808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 195232808237SRoger Quadros pm_runtime_disable(&pdev->dev); 195332808237SRoger Quadros 1954dc1b5d9aSEnric Balletbo i Serra disable_clks: 195533fb697eSSean Anderson dwc3_clk_disable(dwc); 1956fe8abf33SMasahiro Yamada assert_reset: 1957fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 19582a735e4bSDan Carpenter put_usb_psy: 1959b0bf77cdSColin Ian King if (dwc->usb_psy) 19606f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19616f0764b5SRay Chi 196272246da4SFelipe Balbi return ret; 196372246da4SFelipe Balbi } 196472246da4SFelipe Balbi 1965fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 196672246da4SFelipe Balbi { 196772246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 19683da1f6eeSFelipe Balbi 1969fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 197072246da4SFelipe Balbi 1971dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 19722a042767SPeter Chen dwc3_debugfs_exit(dwc); 19738ba007a9SKishon Vijay Abraham I 197472246da4SFelipe Balbi dwc3_core_exit(dwc); 197588bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 197672246da4SFelipe Balbi 1977fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1978266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1979266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1980fc8bb91bSFelipe Balbi 1981c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1982c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1983c499ff71SFelipe Balbi 1984b0bf77cdSColin Ian King if (dwc->usb_psy) 19856f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19866f0764b5SRay Chi 198772246da4SFelipe Balbi return 0; 198872246da4SFelipe Balbi } 198972246da4SFelipe Balbi 1990fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1991fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1992fe8abf33SMasahiro Yamada { 1993fe8abf33SMasahiro Yamada int ret; 1994fe8abf33SMasahiro Yamada 1995fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1996fe8abf33SMasahiro Yamada if (ret) 1997fe8abf33SMasahiro Yamada return ret; 1998fe8abf33SMasahiro Yamada 199933fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 2000fe8abf33SMasahiro Yamada if (ret) 2001fe8abf33SMasahiro Yamada goto assert_reset; 2002fe8abf33SMasahiro Yamada 2003fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 2004fe8abf33SMasahiro Yamada if (ret) 2005fe8abf33SMasahiro Yamada goto disable_clks; 2006fe8abf33SMasahiro Yamada 2007fe8abf33SMasahiro Yamada return 0; 2008fe8abf33SMasahiro Yamada 2009fe8abf33SMasahiro Yamada disable_clks: 201033fb697eSSean Anderson dwc3_clk_disable(dwc); 2011fe8abf33SMasahiro Yamada assert_reset: 2012fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 2013fe8abf33SMasahiro Yamada 2014fe8abf33SMasahiro Yamada return ret; 2015fe8abf33SMasahiro Yamada } 2016fe8abf33SMasahiro Yamada 2017c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 20187415f17cSFelipe Balbi { 2019fc8bb91bSFelipe Balbi unsigned long flags; 2020bcb12877SManu Gautam u32 reg; 20217415f17cSFelipe Balbi 2022689bf72cSManu Gautam switch (dwc->current_dr_role) { 2023689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 20240227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 20250227cc84SLi Jun break; 20267415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 202741a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2028689bf72cSManu Gautam dwc3_core_exit(dwc); 202951f5d49aSFelipe Balbi break; 2030689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2031e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2032c4a5153eSManu Gautam dwc3_core_exit(dwc); 2033c4a5153eSManu Gautam break; 2034bcb12877SManu Gautam } 2035bcb12877SManu Gautam 2036bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 2037bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 2038bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 2039bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2040bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2041bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 2042bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2043bcb12877SManu Gautam 2044bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 2045bcb12877SManu Gautam usleep_range(5000, 6000); 2046bcb12877SManu Gautam } 2047bcb12877SManu Gautam 2048bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2049bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2050bcb12877SManu Gautam break; 2051f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2052f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 2053f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2054f09cc79bSRoger Quadros break; 2055f09cc79bSRoger Quadros 2056f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2057f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2058f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 2059f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 206041a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2061f09cc79bSRoger Quadros } 2062f09cc79bSRoger Quadros 2063f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 2064f09cc79bSRoger Quadros dwc3_core_exit(dwc); 2065f09cc79bSRoger Quadros break; 20667415f17cSFelipe Balbi default: 206751f5d49aSFelipe Balbi /* do nothing */ 20687415f17cSFelipe Balbi break; 20697415f17cSFelipe Balbi } 20707415f17cSFelipe Balbi 2071fc8bb91bSFelipe Balbi return 0; 2072fc8bb91bSFelipe Balbi } 2073fc8bb91bSFelipe Balbi 2074c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2075fc8bb91bSFelipe Balbi { 2076fc8bb91bSFelipe Balbi unsigned long flags; 2077fc8bb91bSFelipe Balbi int ret; 2078bcb12877SManu Gautam u32 reg; 2079fc8bb91bSFelipe Balbi 2080689bf72cSManu Gautam switch (dwc->current_dr_role) { 2081689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2082fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2083fc8bb91bSFelipe Balbi if (ret) 2084fc8bb91bSFelipe Balbi return ret; 2085fc8bb91bSFelipe Balbi 20867d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2087fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 2088689bf72cSManu Gautam break; 2089689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2090e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2091fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2092c4a5153eSManu Gautam if (ret) 2093c4a5153eSManu Gautam return ret; 20947d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2095bcb12877SManu Gautam break; 2096c4a5153eSManu Gautam } 2097bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2098bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2099bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 2100bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2101bcb12877SManu Gautam 2102bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 2103bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2104bcb12877SManu Gautam 2105bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2106bcb12877SManu Gautam 2107bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2108bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2109c4a5153eSManu Gautam break; 2110f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2111f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 2112f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2113f09cc79bSRoger Quadros break; 2114f09cc79bSRoger Quadros 21150e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 2116f09cc79bSRoger Quadros if (ret) 2117f09cc79bSRoger Quadros return ret; 2118f09cc79bSRoger Quadros 2119f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 2120f09cc79bSRoger Quadros 2121f09cc79bSRoger Quadros dwc3_otg_init(dwc); 2122f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2123f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 2124f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2125f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2126f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 2127f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 2128f09cc79bSRoger Quadros } 2129f09cc79bSRoger Quadros 2130f09cc79bSRoger Quadros break; 2131fc8bb91bSFelipe Balbi default: 2132fc8bb91bSFelipe Balbi /* do nothing */ 2133fc8bb91bSFelipe Balbi break; 2134fc8bb91bSFelipe Balbi } 2135fc8bb91bSFelipe Balbi 2136fc8bb91bSFelipe Balbi return 0; 2137fc8bb91bSFelipe Balbi } 2138fc8bb91bSFelipe Balbi 2139fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 2140fc8bb91bSFelipe Balbi { 2141689bf72cSManu Gautam switch (dwc->current_dr_role) { 2142c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2143fc8bb91bSFelipe Balbi if (dwc->connected) 2144fc8bb91bSFelipe Balbi return -EBUSY; 2145fc8bb91bSFelipe Balbi break; 2146c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2147fc8bb91bSFelipe Balbi default: 2148fc8bb91bSFelipe Balbi /* do nothing */ 2149fc8bb91bSFelipe Balbi break; 2150fc8bb91bSFelipe Balbi } 2151fc8bb91bSFelipe Balbi 2152fc8bb91bSFelipe Balbi return 0; 2153fc8bb91bSFelipe Balbi } 2154fc8bb91bSFelipe Balbi 2155fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2156fc8bb91bSFelipe Balbi { 2157fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2158fc8bb91bSFelipe Balbi int ret; 2159fc8bb91bSFelipe Balbi 2160fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2161fc8bb91bSFelipe Balbi return -EBUSY; 2162fc8bb91bSFelipe Balbi 2163c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2164fc8bb91bSFelipe Balbi if (ret) 2165fc8bb91bSFelipe Balbi return ret; 2166fc8bb91bSFelipe Balbi 2167fc8bb91bSFelipe Balbi return 0; 2168fc8bb91bSFelipe Balbi } 2169fc8bb91bSFelipe Balbi 2170fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2171fc8bb91bSFelipe Balbi { 2172fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2173fc8bb91bSFelipe Balbi int ret; 2174fc8bb91bSFelipe Balbi 2175c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2176fc8bb91bSFelipe Balbi if (ret) 2177fc8bb91bSFelipe Balbi return ret; 2178fc8bb91bSFelipe Balbi 2179689bf72cSManu Gautam switch (dwc->current_dr_role) { 2180689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2181fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2182fc8bb91bSFelipe Balbi break; 2183689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2184fc8bb91bSFelipe Balbi default: 2185fc8bb91bSFelipe Balbi /* do nothing */ 2186fc8bb91bSFelipe Balbi break; 2187fc8bb91bSFelipe Balbi } 2188fc8bb91bSFelipe Balbi 2189fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2190fc8bb91bSFelipe Balbi 2191fc8bb91bSFelipe Balbi return 0; 2192fc8bb91bSFelipe Balbi } 2193fc8bb91bSFelipe Balbi 2194fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2195fc8bb91bSFelipe Balbi { 2196fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2197fc8bb91bSFelipe Balbi 2198689bf72cSManu Gautam switch (dwc->current_dr_role) { 2199689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2200fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2201fc8bb91bSFelipe Balbi return -EBUSY; 2202fc8bb91bSFelipe Balbi break; 2203689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2204fc8bb91bSFelipe Balbi default: 2205fc8bb91bSFelipe Balbi /* do nothing */ 2206fc8bb91bSFelipe Balbi break; 2207fc8bb91bSFelipe Balbi } 2208fc8bb91bSFelipe Balbi 2209fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2210fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2211fc8bb91bSFelipe Balbi 2212fc8bb91bSFelipe Balbi return 0; 2213fc8bb91bSFelipe Balbi } 2214fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2215fc8bb91bSFelipe Balbi 2216fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2217fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2218fc8bb91bSFelipe Balbi { 2219fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2220fc8bb91bSFelipe Balbi int ret; 2221fc8bb91bSFelipe Balbi 2222c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2223fc8bb91bSFelipe Balbi if (ret) 2224fc8bb91bSFelipe Balbi return ret; 2225fc8bb91bSFelipe Balbi 22266344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 22276344475fSSekhar Nori 22287415f17cSFelipe Balbi return 0; 22297415f17cSFelipe Balbi } 22307415f17cSFelipe Balbi 22317415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 22327415f17cSFelipe Balbi { 22337415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 223457303488SKishon Vijay Abraham I int ret; 22357415f17cSFelipe Balbi 22366344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 22376344475fSSekhar Nori 2238c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 223951f5d49aSFelipe Balbi if (ret) 22405c4ad318SFelipe Balbi return ret; 22415c4ad318SFelipe Balbi 22427415f17cSFelipe Balbi pm_runtime_disable(dev); 22437415f17cSFelipe Balbi pm_runtime_set_active(dev); 22447415f17cSFelipe Balbi pm_runtime_enable(dev); 22457415f17cSFelipe Balbi 22467415f17cSFelipe Balbi return 0; 22477415f17cSFelipe Balbi } 2248f580170fSYu Chen 2249f580170fSYu Chen static void dwc3_complete(struct device *dev) 2250f580170fSYu Chen { 2251f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2252f580170fSYu Chen u32 reg; 2253f580170fSYu Chen 2254f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2255f580170fSYu Chen dwc->dis_split_quirk) { 2256f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2257f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2258f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2259f580170fSYu Chen } 2260f580170fSYu Chen } 2261f580170fSYu Chen #else 2262f580170fSYu Chen #define dwc3_complete NULL 22637f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 22647415f17cSFelipe Balbi 22657415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 22667415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2267f580170fSYu Chen .complete = dwc3_complete, 2268fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2269fc8bb91bSFelipe Balbi dwc3_runtime_idle) 22707415f17cSFelipe Balbi }; 22717415f17cSFelipe Balbi 22725088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 22735088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 22745088b6f5SKishon Vijay Abraham I { 227522a5aa17SFelipe Balbi .compatible = "snps,dwc3" 227622a5aa17SFelipe Balbi }, 227722a5aa17SFelipe Balbi { 22785088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 22795088b6f5SKishon Vijay Abraham I }, 22805088b6f5SKishon Vijay Abraham I { }, 22815088b6f5SKishon Vijay Abraham I }; 22825088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 22835088b6f5SKishon Vijay Abraham I #endif 22845088b6f5SKishon Vijay Abraham I 2285404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2286404905a6SHeikki Krogerus 2287404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2288404905a6SHeikki Krogerus 2289404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2290404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2291404905a6SHeikki Krogerus { }, 2292404905a6SHeikki Krogerus }; 2293404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2294404905a6SHeikki Krogerus #endif 2295404905a6SHeikki Krogerus 229672246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 229772246da4SFelipe Balbi .probe = dwc3_probe, 22987690417dSBill Pemberton .remove = dwc3_remove, 229972246da4SFelipe Balbi .driver = { 230072246da4SFelipe Balbi .name = "dwc3", 23015088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2302404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 23037f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 230472246da4SFelipe Balbi }, 230572246da4SFelipe Balbi }; 230672246da4SFelipe Balbi 2307b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2308b1116dccSTobias Klauser 23097ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 231072246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 23115945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 231272246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2313