15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 260f010171SAndrey Smirnov #include <linux/of_graph.h> 27404905a6SHeikki Krogerus #include <linux/acpi.h> 286344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 29fe8abf33SMasahiro Yamada #include <linux/reset.h> 307bee3188SBalaji Prakash J #include <linux/bitfield.h> 3172246da4SFelipe Balbi 3272246da4SFelipe Balbi #include <linux/usb/ch9.h> 3372246da4SFelipe Balbi #include <linux/usb/gadget.h> 34f7e846f0SFelipe Balbi #include <linux/usb/of.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3672246da4SFelipe Balbi 3772246da4SFelipe Balbi #include "core.h" 3872246da4SFelipe Balbi #include "gadget.h" 3972246da4SFelipe Balbi #include "io.h" 4072246da4SFelipe Balbi 4172246da4SFelipe Balbi #include "debug.h" 4272246da4SFelipe Balbi 43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 448300dd23SFelipe Balbi 459d6173e1SThinh Nguyen /** 469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 479d6173e1SThinh Nguyen * @dwc: pointer to our context structure 489d6173e1SThinh Nguyen */ 499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 509d6173e1SThinh Nguyen { 519d6173e1SThinh Nguyen enum usb_dr_mode mode; 529d6173e1SThinh Nguyen struct device *dev = dwc->dev; 539d6173e1SThinh Nguyen unsigned int hw_mode; 549d6173e1SThinh Nguyen 559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 579d6173e1SThinh Nguyen 589d6173e1SThinh Nguyen mode = dwc->dr_mode; 599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 609d6173e1SThinh Nguyen 619d6173e1SThinh Nguyen switch (hw_mode) { 629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 649d6173e1SThinh Nguyen dev_err(dev, 659d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 669d6173e1SThinh Nguyen return -EINVAL; 679d6173e1SThinh Nguyen } 689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 699d6173e1SThinh Nguyen break; 709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 729d6173e1SThinh Nguyen dev_err(dev, 739d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 749d6173e1SThinh Nguyen return -EINVAL; 759d6173e1SThinh Nguyen } 769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 779d6173e1SThinh Nguyen break; 789d6173e1SThinh Nguyen default: 799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 83a7700468SThinh Nguyen 84a7700468SThinh Nguyen /* 8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 88a7700468SThinh Nguyen */ 890f010171SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev && 908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 949d6173e1SThinh Nguyen } 959d6173e1SThinh Nguyen 969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 979d6173e1SThinh Nguyen dev_warn(dev, 989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 1009d6173e1SThinh Nguyen 1019d6173e1SThinh Nguyen dwc->dr_mode = mode; 1029d6173e1SThinh Nguyen } 1039d6173e1SThinh Nguyen 1049d6173e1SThinh Nguyen return 0; 1059d6173e1SThinh Nguyen } 1069d6173e1SThinh Nguyen 107f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1083140e8cbSSebastian Andrzej Siewior { 1093140e8cbSSebastian Andrzej Siewior u32 reg; 1103140e8cbSSebastian Andrzej Siewior 1113140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1123140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1133140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1143140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115c4a5153eSManu Gautam 116c4a5153eSManu Gautam dwc->current_dr_role = mode; 11741ce1456SRoger Quadros } 1186b3261a2SRoger Quadros 11941ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12041ce1456SRoger Quadros { 12141ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12241ce1456SRoger Quadros unsigned long flags; 12341ce1456SRoger Quadros int ret; 124f580170fSYu Chen u32 reg; 12541ce1456SRoger Quadros 126f88359e1SYu Chen mutex_lock(&dwc->mutex); 127f88359e1SYu Chen 128c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 129c2cd3452SMartin Kepplinger 130f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 131f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 132f09cc79bSRoger Quadros 13341ce1456SRoger Quadros if (!dwc->desired_dr_role) 134c2cd3452SMartin Kepplinger goto out; 13541ce1456SRoger Quadros 13641ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 137c2cd3452SMartin Kepplinger goto out; 13841ce1456SRoger Quadros 139f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 140c2cd3452SMartin Kepplinger goto out; 14141ce1456SRoger Quadros 14241ce1456SRoger Quadros switch (dwc->current_dr_role) { 14341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14441ce1456SRoger Quadros dwc3_host_exit(dwc); 14541ce1456SRoger Quadros break; 14641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14741ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14841ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14941ce1456SRoger Quadros break; 150f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 151f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 152f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 153f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 154f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 155f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 156f09cc79bSRoger Quadros break; 15741ce1456SRoger Quadros default: 15841ce1456SRoger Quadros break; 15941ce1456SRoger Quadros } 16041ce1456SRoger Quadros 161f88359e1SYu Chen /* For DRD host or device mode only */ 162f88359e1SYu Chen if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { 163f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 164f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 165f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 166f88359e1SYu Chen 167f88359e1SYu Chen /* 168f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 169f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 170f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 171f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 172f88359e1SYu Chen */ 173f88359e1SYu Chen msleep(100); 174f88359e1SYu Chen 175f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 176f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 177f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 178f88359e1SYu Chen } 179f88359e1SYu Chen 18041ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18141ce1456SRoger Quadros 18241ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18341ce1456SRoger Quadros 18441ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 18541ce1456SRoger Quadros 18641ce1456SRoger Quadros switch (dwc->desired_dr_role) { 18741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 18841ce1456SRoger Quadros ret = dwc3_host_init(dwc); 189958d1a4cSFelipe Balbi if (ret) { 19041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 191958d1a4cSFelipe Balbi } else { 192958d1a4cSFelipe Balbi if (dwc->usb2_phy) 193958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 194958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 195644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 196f580170fSYu Chen if (dwc->dis_split_quirk) { 197f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 198f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 199f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 200f580170fSYu Chen } 201958d1a4cSFelipe Balbi } 20241ce1456SRoger Quadros break; 20341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 204f88359e1SYu Chen dwc3_core_soft_reset(dwc); 205f88359e1SYu Chen 20641ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 207958d1a4cSFelipe Balbi 208958d1a4cSFelipe Balbi if (dwc->usb2_phy) 209958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 210958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 211644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 212958d1a4cSFelipe Balbi 21341ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21441ce1456SRoger Quadros if (ret) 21541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 21641ce1456SRoger Quadros break; 217f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 218f09cc79bSRoger Quadros dwc3_otg_init(dwc); 219f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 220f09cc79bSRoger Quadros break; 22141ce1456SRoger Quadros default: 22241ce1456SRoger Quadros break; 22341ce1456SRoger Quadros } 224f09cc79bSRoger Quadros 225c2cd3452SMartin Kepplinger out: 226c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 227c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 228f88359e1SYu Chen mutex_unlock(&dwc->mutex); 22941ce1456SRoger Quadros } 23041ce1456SRoger Quadros 23141ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23241ce1456SRoger Quadros { 23341ce1456SRoger Quadros unsigned long flags; 23441ce1456SRoger Quadros 235dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 236dc336b19SLi Jun return; 237dc336b19SLi Jun 23841ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 23941ce1456SRoger Quadros dwc->desired_dr_role = mode; 24041ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24141ce1456SRoger Quadros 242084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2433140e8cbSSebastian Andrzej Siewior } 2448300dd23SFelipe Balbi 245cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 246cf6d867dSFelipe Balbi { 247cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 248cf6d867dSFelipe Balbi u32 reg; 249cf6d867dSFelipe Balbi 250cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 251cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 252cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 253cf6d867dSFelipe Balbi 254cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 255cf6d867dSFelipe Balbi 256cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 257cf6d867dSFelipe Balbi } 258cf6d867dSFelipe Balbi 25972246da4SFelipe Balbi /** 26072246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26172246da4SFelipe Balbi * @dwc: pointer to our context structure 26272246da4SFelipe Balbi */ 2630066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 26472246da4SFelipe Balbi { 26572246da4SFelipe Balbi u32 reg; 266f59dcab1SFelipe Balbi int retries = 1000; 26772246da4SFelipe Balbi 268f59dcab1SFelipe Balbi /* 269f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 270f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 271f59dcab1SFelipe Balbi * host-only mode, then we can return early. 272f59dcab1SFelipe Balbi */ 273c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27457303488SKishon Vijay Abraham I return 0; 275f59dcab1SFelipe Balbi 276f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 277f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 278f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP; 279f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg); 280f59dcab1SFelipe Balbi 2814749e0e6SThinh Nguyen /* 2824749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2834749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2844749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2854749e0e6SThinh Nguyen * for 10 times instead. 2864749e0e6SThinh Nguyen */ 2879af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2884749e0e6SThinh Nguyen retries = 10; 2894749e0e6SThinh Nguyen 290f59dcab1SFelipe Balbi do { 291f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 292f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 293fab38333SThinh Nguyen goto done; 294f59dcab1SFelipe Balbi 2959af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2964749e0e6SThinh Nguyen msleep(20); 2974749e0e6SThinh Nguyen else 298f59dcab1SFelipe Balbi udelay(1); 299f59dcab1SFelipe Balbi } while (--retries); 300f59dcab1SFelipe Balbi 301f59dcab1SFelipe Balbi return -ETIMEDOUT; 302fab38333SThinh Nguyen 303fab38333SThinh Nguyen done: 304fab38333SThinh Nguyen /* 3054749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3064749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3074749e0e6SThinh Nguyen * domain (synchronization delay). 308fab38333SThinh Nguyen */ 3099af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 310fab38333SThinh Nguyen msleep(50); 311fab38333SThinh Nguyen 312fab38333SThinh Nguyen return 0; 31372246da4SFelipe Balbi } 31472246da4SFelipe Balbi 315db2be4e9SNikhil Badola /* 316db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 317db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 318db2be4e9SNikhil Badola */ 319bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 320db2be4e9SNikhil Badola { 321db2be4e9SNikhil Badola u32 reg; 322db2be4e9SNikhil Badola u32 dft; 323db2be4e9SNikhil Badola 3249af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 325db2be4e9SNikhil Badola return; 326db2be4e9SNikhil Badola 327bcdb3272SFelipe Balbi if (dwc->fladj == 0) 328db2be4e9SNikhil Badola return; 329db2be4e9SNikhil Badola 330db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 331db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 332a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 333db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 334bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 335db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 336db2be4e9SNikhil Badola } 337db2be4e9SNikhil Badola } 338db2be4e9SNikhil Badola 339c5cc74e8SHeikki Krogerus /** 3407bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3417bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3427bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3437bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3447bee3188SBalaji Prakash J * register. 3457bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3467bee3188SBalaji Prakash J */ 3477bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3487bee3188SBalaji Prakash J { 3495114c3eeSSean Anderson unsigned long period; 350596c8785SSean Anderson unsigned long fladj; 351596c8785SSean Anderson unsigned long decr; 3525114c3eeSSean Anderson unsigned long rate; 3537bee3188SBalaji Prakash J u32 reg; 3547bee3188SBalaji Prakash J 3555114c3eeSSean Anderson if (dwc->ref_clk) { 3565114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3575114c3eeSSean Anderson if (!rate) 3587bee3188SBalaji Prakash J return; 3595114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3605114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3615114c3eeSSean Anderson period = dwc->ref_clk_per; 362596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3635114c3eeSSean Anderson } else { 3645114c3eeSSean Anderson return; 3655114c3eeSSean Anderson } 3667bee3188SBalaji Prakash J 3677bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3687bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3695114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3707bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3717bee3188SBalaji Prakash J 372596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 373596c8785SSean Anderson return; 374596c8785SSean Anderson 375596c8785SSean Anderson /* 376596c8785SSean Anderson * The calculation below is 377596c8785SSean Anderson * 378596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 379596c8785SSean Anderson * 380596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 381596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 382596c8785SSean Anderson * neither does rate * period). 383596c8785SSean Anderson * 384596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 385596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 386596c8785SSean Anderson * the division when calculating rate or period (whichever one was 387596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 388596c8785SSean Anderson * scale it to units of 8 ppm. 389596c8785SSean Anderson */ 390596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 391596c8785SSean Anderson fladj -= 125000; 392596c8785SSean Anderson 393596c8785SSean Anderson /* 394596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 395596c8785SSean Anderson */ 396596c8785SSean Anderson decr = 480000000 / rate; 397596c8785SSean Anderson 398596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 399596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 400596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 401596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 402596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 403596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 404596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 405596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 406596c8785SSean Anderson } 4077bee3188SBalaji Prakash J 4087bee3188SBalaji Prakash J /** 40972246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 41072246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 41172246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 41272246da4SFelipe Balbi */ 41372246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 41472246da4SFelipe Balbi struct dwc3_event_buffer *evt) 41572246da4SFelipe Balbi { 416d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 41772246da4SFelipe Balbi } 41872246da4SFelipe Balbi 41972246da4SFelipe Balbi /** 4201d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 42172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42272246da4SFelipe Balbi * @length: size of the event buffer 42372246da4SFelipe Balbi * 4241d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 42572246da4SFelipe Balbi * otherwise ERR_PTR(errno). 42672246da4SFelipe Balbi */ 42767d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 42867d0b500SFelipe Balbi unsigned length) 42972246da4SFelipe Balbi { 43072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43172246da4SFelipe Balbi 432380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 43372246da4SFelipe Balbi if (!evt) 43472246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 43572246da4SFelipe Balbi 43672246da4SFelipe Balbi evt->dwc = dwc; 43772246da4SFelipe Balbi evt->length = length; 438d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 439d9fa4c63SJohn Youn if (!evt->cache) 440d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 441d9fa4c63SJohn Youn 442d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 44372246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 444e32672f0SFelipe Balbi if (!evt->buf) 44572246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44672246da4SFelipe Balbi 44772246da4SFelipe Balbi return evt; 44872246da4SFelipe Balbi } 44972246da4SFelipe Balbi 45072246da4SFelipe Balbi /** 45172246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 45272246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 45372246da4SFelipe Balbi */ 45472246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 45572246da4SFelipe Balbi { 45672246da4SFelipe Balbi struct dwc3_event_buffer *evt; 45772246da4SFelipe Balbi 458696c8b12SFelipe Balbi evt = dwc->ev_buf; 45964b6c8a7SAnton Tikhomirov if (evt) 46072246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 46172246da4SFelipe Balbi } 46272246da4SFelipe Balbi 46372246da4SFelipe Balbi /** 46472246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4651d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 46672246da4SFelipe Balbi * @length: size of event buffer 46772246da4SFelipe Balbi * 4681d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 46972246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 47072246da4SFelipe Balbi */ 47141ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 47272246da4SFelipe Balbi { 47372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 47472246da4SFelipe Balbi 47572246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 47672246da4SFelipe Balbi if (IS_ERR(evt)) { 47772246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 47872246da4SFelipe Balbi return PTR_ERR(evt); 47972246da4SFelipe Balbi } 480696c8b12SFelipe Balbi dwc->ev_buf = evt; 48172246da4SFelipe Balbi 48272246da4SFelipe Balbi return 0; 48372246da4SFelipe Balbi } 48472246da4SFelipe Balbi 48572246da4SFelipe Balbi /** 48672246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4871d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 48872246da4SFelipe Balbi * 48972246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 49072246da4SFelipe Balbi */ 491f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 49272246da4SFelipe Balbi { 49372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 49472246da4SFelipe Balbi 495696c8b12SFelipe Balbi evt = dwc->ev_buf; 4967acd85e0SPaul Zimmerman evt->lpos = 0; 497660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 49872246da4SFelipe Balbi lower_32_bits(evt->dma)); 499660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 50072246da4SFelipe Balbi upper_32_bits(evt->dma)); 501660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 50268d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 503660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 50472246da4SFelipe Balbi 50572246da4SFelipe Balbi return 0; 50672246da4SFelipe Balbi } 50772246da4SFelipe Balbi 508f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 50972246da4SFelipe Balbi { 51072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 51172246da4SFelipe Balbi 512696c8b12SFelipe Balbi evt = dwc->ev_buf; 5137acd85e0SPaul Zimmerman 5147acd85e0SPaul Zimmerman evt->lpos = 0; 5157acd85e0SPaul Zimmerman 516660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 517660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 518660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 51968d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 520660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 52172246da4SFelipe Balbi } 52272246da4SFelipe Balbi 5230ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5240ffcaf37SFelipe Balbi { 5250ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5260ffcaf37SFelipe Balbi return 0; 5270ffcaf37SFelipe Balbi 5280ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5290ffcaf37SFelipe Balbi return 0; 5300ffcaf37SFelipe Balbi 5310ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5320ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5330ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5340ffcaf37SFelipe Balbi return -ENOMEM; 5350ffcaf37SFelipe Balbi 5360ffcaf37SFelipe Balbi return 0; 5370ffcaf37SFelipe Balbi } 5380ffcaf37SFelipe Balbi 5390ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5400ffcaf37SFelipe Balbi { 5410ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5420ffcaf37SFelipe Balbi u32 param; 5430ffcaf37SFelipe Balbi int ret; 5440ffcaf37SFelipe Balbi 5450ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5460ffcaf37SFelipe Balbi return 0; 5470ffcaf37SFelipe Balbi 5480ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5490ffcaf37SFelipe Balbi return 0; 5500ffcaf37SFelipe Balbi 5510ffcaf37SFelipe Balbi /* should never fall here */ 5520ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5530ffcaf37SFelipe Balbi return 0; 5540ffcaf37SFelipe Balbi 555d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5560ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5570ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 558d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 559d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5600ffcaf37SFelipe Balbi ret = -EFAULT; 5610ffcaf37SFelipe Balbi goto err0; 5620ffcaf37SFelipe Balbi } 5630ffcaf37SFelipe Balbi 5640ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5650ffcaf37SFelipe Balbi 5660ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5670ffcaf37SFelipe Balbi 5680ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5690ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5700ffcaf37SFelipe Balbi if (ret < 0) 5710ffcaf37SFelipe Balbi goto err1; 5720ffcaf37SFelipe Balbi 5730ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5740ffcaf37SFelipe Balbi 5750ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5760ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5770ffcaf37SFelipe Balbi if (ret < 0) 5780ffcaf37SFelipe Balbi goto err1; 5790ffcaf37SFelipe Balbi 5800ffcaf37SFelipe Balbi return 0; 5810ffcaf37SFelipe Balbi 5820ffcaf37SFelipe Balbi err1: 583d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5840ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5850ffcaf37SFelipe Balbi 5860ffcaf37SFelipe Balbi err0: 5870ffcaf37SFelipe Balbi return ret; 5880ffcaf37SFelipe Balbi } 5890ffcaf37SFelipe Balbi 5900ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5910ffcaf37SFelipe Balbi { 5920ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5930ffcaf37SFelipe Balbi return; 5940ffcaf37SFelipe Balbi 5950ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5960ffcaf37SFelipe Balbi return; 5970ffcaf37SFelipe Balbi 5980ffcaf37SFelipe Balbi /* should never fall here */ 5990ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6000ffcaf37SFelipe Balbi return; 6010ffcaf37SFelipe Balbi 602d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6030ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6040ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6050ffcaf37SFelipe Balbi } 6060ffcaf37SFelipe Balbi 607789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 608789451f6SFelipe Balbi { 609789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 610789451f6SFelipe Balbi 61147d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 612789451f6SFelipe Balbi } 613789451f6SFelipe Balbi 61441ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 61526ceca97SFelipe Balbi { 61626ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 61726ceca97SFelipe Balbi 61826ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 61926ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 62026ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 62126ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 62226ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 62326ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 62426ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 62526ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 62626ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 62716710380SThinh Nguyen 62816710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 62916710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 63026ceca97SFelipe Balbi } 63126ceca97SFelipe Balbi 63298112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 63398112041SRoger Quadros { 63498112041SRoger Quadros int intf; 63598112041SRoger Quadros int ret = 0; 63698112041SRoger Quadros 63798112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 63898112041SRoger Quadros 63998112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 64098112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 64198112041SRoger Quadros dwc->hsphy_interface && 64298112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 64398112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 64498112041SRoger Quadros 64598112041SRoger Quadros return ret; 64698112041SRoger Quadros } 64798112041SRoger Quadros 64872246da4SFelipe Balbi /** 649b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 650b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 65188bc9d19SHeikki Krogerus * 65288bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 65388bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 65488bc9d19SHeikki Krogerus * the core in dwc3_core_init. 655b5a65c40SHuang Rui */ 65688bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 657b5a65c40SHuang Rui { 6589ba3aca8SThinh Nguyen unsigned int hw_mode; 659b5a65c40SHuang Rui u32 reg; 660b5a65c40SHuang Rui 6619ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6629ba3aca8SThinh Nguyen 663b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 664b5a65c40SHuang Rui 6652164a476SHuang Rui /* 6661966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6671966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6681966b865SFelipe Balbi */ 6691966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6701966b865SFelipe Balbi 6711966b865SFelipe Balbi /* 6722164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6732164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6742164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6752164a476SHuang Rui * to '1' after the core initialization is completed. 6762164a476SHuang Rui */ 6779af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6782164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6792164a476SHuang Rui 6809ba3aca8SThinh Nguyen /* 6819ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6829ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6839ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6849ba3aca8SThinh Nguyen */ 6859ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6869ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6879ba3aca8SThinh Nguyen 688b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 689b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 690b5a65c40SHuang Rui 691e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 692e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 693e58dd357SRajesh Bhagat 694df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 695df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 696df31f5b3SHuang Rui 697a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 698a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 699a2a1d0f5SHuang Rui 70041c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 70141c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 70241c06ffdSHuang Rui 703fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 704fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 705fb67afcaSHuang Rui 70614f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 70714f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 70814f4ac53SHuang Rui 7096b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7106b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7116b6a0c9aSHuang Rui 712cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 71359acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 71459acfa20SHuang Rui 71500fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 71600fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 71700fe081dSWilliam Wu 718b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 719b5a65c40SHuang Rui 7202164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7212164a476SHuang Rui 7223e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7233e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7243e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 72543cacb03SFelipe Balbi if (dwc->hsphy_interface && 72643cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7273e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 72888bc9d19SHeikki Krogerus break; 72943cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 73043cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7313e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 73288bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7333e10a2ceSHeikki Krogerus } else { 73488bc9d19SHeikki Krogerus /* Relying on default value. */ 73588bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7363e10a2ceSHeikki Krogerus break; 7373e10a2ceSHeikki Krogerus } 738df561f66SGustavo A. R. Silva fallthrough; 73988bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7403e10a2ceSHeikki Krogerus default: 7413e10a2ceSHeikki Krogerus break; 7423e10a2ceSHeikki Krogerus } 7433e10a2ceSHeikki Krogerus 74432f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 74532f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 74632f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 74732f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 74832f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 74932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 75032f2ed86SWilliam Wu break; 75132f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 75232f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75332f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75432f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 75532f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 75632f2ed86SWilliam Wu break; 75732f2ed86SWilliam Wu default: 75832f2ed86SWilliam Wu break; 75932f2ed86SWilliam Wu } 76032f2ed86SWilliam Wu 7612164a476SHuang Rui /* 7622164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7632164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7642164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7652164a476SHuang Rui * '1' after the core initialization is completed. 7662164a476SHuang Rui */ 7679af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7682164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7692164a476SHuang Rui 7709ba3aca8SThinh Nguyen /* 7719ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7729ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7739ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7749ba3aca8SThinh Nguyen */ 7759ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7769ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7779ba3aca8SThinh Nguyen 778cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7790effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7800effe0a3SHuang Rui 781ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 782ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 783eafeacf1SThinh Nguyen else 784eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 785ec791d14SJohn Youn 78616199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 78716199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 78816199f33SWilliam Wu 7892164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79088bc9d19SHeikki Krogerus 79188bc9d19SHeikki Krogerus return 0; 792b5a65c40SHuang Rui } 793b5a65c40SHuang Rui 79433fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 79533fb697eSSean Anderson { 79633fb697eSSean Anderson int ret; 79733fb697eSSean Anderson 79833fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 79933fb697eSSean Anderson if (ret) 80033fb697eSSean Anderson return ret; 80133fb697eSSean Anderson 80233fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 80333fb697eSSean Anderson if (ret) 80433fb697eSSean Anderson goto disable_bus_clk; 80533fb697eSSean Anderson 80633fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 80733fb697eSSean Anderson if (ret) 80833fb697eSSean Anderson goto disable_ref_clk; 80933fb697eSSean Anderson 81033fb697eSSean Anderson return 0; 81133fb697eSSean Anderson 81233fb697eSSean Anderson disable_ref_clk: 81333fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 81433fb697eSSean Anderson disable_bus_clk: 81533fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 81633fb697eSSean Anderson return ret; 81733fb697eSSean Anderson } 81833fb697eSSean Anderson 81933fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 82033fb697eSSean Anderson { 82133fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 82233fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82333fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82433fb697eSSean Anderson } 82533fb697eSSean Anderson 826c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 827c499ff71SFelipe Balbi { 828c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 829c499ff71SFelipe Balbi 830c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 831c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 832c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 833c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 834c499ff71SFelipe Balbi 835c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 836c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 837c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 838c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 83933fb697eSSean Anderson dwc3_clk_disable(dwc); 840fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 841c499ff71SFelipe Balbi } 842c499ff71SFelipe Balbi 8430759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 84472246da4SFelipe Balbi { 84572246da4SFelipe Balbi u32 reg; 84672246da4SFelipe Balbi 8477650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8489af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8490759956fSFelipe Balbi 8507650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8519af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 852690fb371SJohn Youn dwc->revision = reg; 8539af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 854690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 855475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 856690fb371SJohn Youn } else { 8570759956fSFelipe Balbi return false; 8587650bd74SSebastian Andrzej Siewior } 8597650bd74SSebastian Andrzej Siewior 8600759956fSFelipe Balbi return true; 8610e1e5c47SPaul Zimmerman } 8620e1e5c47SPaul Zimmerman 863941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 86472246da4SFelipe Balbi { 86572246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 86672246da4SFelipe Balbi u32 reg; 867c499ff71SFelipe Balbi 8684878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8693e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8704878a028SSebastian Andrzej Siewior 871164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8724878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87332a4a135SFelipe Balbi /** 87432a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 87532a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 87632a4a135SFelipe Balbi * 87732a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 87832a4a135SFelipe Balbi * configurations. 87932a4a135SFelipe Balbi * 88032a4a135SFelipe Balbi * Refers to: 88132a4a135SFelipe Balbi * 88232a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 88332a4a135SFelipe Balbi * SOF/ITP Mode Used 88432a4a135SFelipe Balbi */ 88532a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 88632a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8879af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 88832a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 88932a4a135SFelipe Balbi else 8904878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 8914878a028SSebastian Andrzej Siewior break; 8920ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 8930ffcaf37SFelipe Balbi /* enable hibernation here */ 8940ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 8952eac3992SHuang Rui 8962eac3992SHuang Rui /* 8972eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 8982eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 8992eac3992SHuang Rui */ 9002eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9010ffcaf37SFelipe Balbi break; 9024878a028SSebastian Andrzej Siewior default: 9035eb30cedSFelipe Balbi /* nothing */ 9045eb30cedSFelipe Balbi break; 9054878a028SSebastian Andrzej Siewior } 9064878a028SSebastian Andrzej Siewior 907946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 908946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9096af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 910946bd579SHuang Rui dwc->is_fpga = true; 911946bd579SHuang Rui } 912946bd579SHuang Rui 9133b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9143b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9153b81221aSHuang Rui 9163b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9173b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9183b81221aSHuang Rui else 9193b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9203b81221aSHuang Rui 9219a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9229a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9239a5b2f31SHuang Rui 9244878a028SSebastian Andrzej Siewior /* 9254878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9261d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9274878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9281d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9294878a028SSebastian Andrzej Siewior */ 9309af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9314878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9324878a028SSebastian Andrzej Siewior 9334878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 934941f918eSFelipe Balbi } 9354878a028SSebastian Andrzej Siewior 936f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 93798112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 938f54edb53SFelipe Balbi 939d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 940d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 941d9612c2fSPengbo Mu { 942d9612c2fSPengbo Mu struct device *dev = dwc->dev; 943d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 944d9612c2fSPengbo Mu bool incrx_mode; 945d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 946d9612c2fSPengbo Mu u32 incrx_size; 947d9612c2fSPengbo Mu u32 *vals; 948d9612c2fSPengbo Mu u32 cfg; 949d9612c2fSPengbo Mu int ntype; 950d9612c2fSPengbo Mu int ret; 951d9612c2fSPengbo Mu int i; 952d9612c2fSPengbo Mu 953d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 954d9612c2fSPengbo Mu 955d9612c2fSPengbo Mu /* 956d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 957d9612c2fSPengbo Mu * Get the number of value from this property: 958d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 959d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 960d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 961d9612c2fSPengbo Mu */ 962a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 963d9612c2fSPengbo Mu if (ntype <= 0) 964d9612c2fSPengbo Mu return; 965d9612c2fSPengbo Mu 966d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 9674ea15088SKushagra Verma if (!vals) 968d9612c2fSPengbo Mu return; 969d9612c2fSPengbo Mu 970d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 971d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 972d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 973d9612c2fSPengbo Mu if (ret) { 97475ecb9ddSAndy Shevchenko kfree(vals); 975d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 976d9612c2fSPengbo Mu return; 977d9612c2fSPengbo Mu } 978d9612c2fSPengbo Mu 979d9612c2fSPengbo Mu incrx_size = *vals; 980d9612c2fSPengbo Mu 981d9612c2fSPengbo Mu if (ntype > 1) { 982d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 983d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 984d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 985d9612c2fSPengbo Mu if (vals[i] > incrx_size) 986d9612c2fSPengbo Mu incrx_size = vals[i]; 987d9612c2fSPengbo Mu } 988d9612c2fSPengbo Mu } else { 989d9612c2fSPengbo Mu /* INCRX burst mode */ 990d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 991d9612c2fSPengbo Mu } 992d9612c2fSPengbo Mu 99375ecb9ddSAndy Shevchenko kfree(vals); 99475ecb9ddSAndy Shevchenko 995d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 996d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 997d9612c2fSPengbo Mu if (incrx_mode) 998d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 999d9612c2fSPengbo Mu switch (incrx_size) { 1000d9612c2fSPengbo Mu case 256: 1001d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1002d9612c2fSPengbo Mu break; 1003d9612c2fSPengbo Mu case 128: 1004d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1005d9612c2fSPengbo Mu break; 1006d9612c2fSPengbo Mu case 64: 1007d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1008d9612c2fSPengbo Mu break; 1009d9612c2fSPengbo Mu case 32: 1010d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1011d9612c2fSPengbo Mu break; 1012d9612c2fSPengbo Mu case 16: 1013d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1014d9612c2fSPengbo Mu break; 1015d9612c2fSPengbo Mu case 8: 1016d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1017d9612c2fSPengbo Mu break; 1018d9612c2fSPengbo Mu case 4: 1019d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1020d9612c2fSPengbo Mu break; 1021d9612c2fSPengbo Mu case 1: 1022d9612c2fSPengbo Mu break; 1023d9612c2fSPengbo Mu default: 1024d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1025d9612c2fSPengbo Mu break; 1026d9612c2fSPengbo Mu } 1027d9612c2fSPengbo Mu 1028d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1029d9612c2fSPengbo Mu } 1030d9612c2fSPengbo Mu 1031941f918eSFelipe Balbi /** 1032941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1033941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1034941f918eSFelipe Balbi * 1035941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1036941f918eSFelipe Balbi */ 1037941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1038941f918eSFelipe Balbi { 10399ba3aca8SThinh Nguyen unsigned int hw_mode; 1040941f918eSFelipe Balbi u32 reg; 1041941f918eSFelipe Balbi int ret; 1042941f918eSFelipe Balbi 10439ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10449ba3aca8SThinh Nguyen 1045941f918eSFelipe Balbi /* 1046941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1047941f918eSFelipe Balbi * out which kernel version a bug was found. 1048941f918eSFelipe Balbi */ 1049941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1050941f918eSFelipe Balbi 1051941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1052941f918eSFelipe Balbi if (ret) 1053941f918eSFelipe Balbi goto err0; 1054941f918eSFelipe Balbi 105598112041SRoger Quadros if (!dwc->ulpi_ready) { 105698112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 105798112041SRoger Quadros if (ret) 105898112041SRoger Quadros goto err0; 105998112041SRoger Quadros dwc->ulpi_ready = true; 106098112041SRoger Quadros } 106198112041SRoger Quadros 106298112041SRoger Quadros if (!dwc->phys_ready) { 106398112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 106498112041SRoger Quadros if (ret) 106598112041SRoger Quadros goto err0a; 106698112041SRoger Quadros dwc->phys_ready = true; 106798112041SRoger Quadros } 106898112041SRoger Quadros 10698cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 10708cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 10718cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 10728cfac9a6SLi Jun if (ret < 0) 10738cfac9a6SLi Jun goto err0a; 10748cfac9a6SLi Jun 10758cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 10768cfac9a6SLi Jun if (ret < 0) { 10778cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 10788cfac9a6SLi Jun goto err0a; 10798cfac9a6SLi Jun } 10808cfac9a6SLi Jun 108198112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 108298112041SRoger Quadros if (ret) 10838cfac9a6SLi Jun goto err1; 108498112041SRoger Quadros 10859ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 10869af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 10879ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 10889ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 10899ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 10909ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 10919ba3aca8SThinh Nguyen } 10929ba3aca8SThinh Nguyen 10939ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 10949ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 10959ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 10969ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 10979ba3aca8SThinh Nguyen } 10989ba3aca8SThinh Nguyen } 10999ba3aca8SThinh Nguyen 1100941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1101c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11020ffcaf37SFelipe Balbi 11030ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11040ffcaf37SFelipe Balbi if (ret) 1105c499ff71SFelipe Balbi goto err1; 1106c499ff71SFelipe Balbi 1107c499ff71SFelipe Balbi /* Adjust Frame Length */ 1108c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1109c499ff71SFelipe Balbi 11107bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11117bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11127bee3188SBalaji Prakash J 1113d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1114d9612c2fSPengbo Mu 1115c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1116c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1117c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1118c499ff71SFelipe Balbi if (ret < 0) 11190ffcaf37SFelipe Balbi goto err2; 11200ffcaf37SFelipe Balbi 1121c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1122c499ff71SFelipe Balbi if (ret < 0) 1123c499ff71SFelipe Balbi goto err3; 1124c499ff71SFelipe Balbi 1125c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1126c499ff71SFelipe Balbi if (ret) { 1127c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1128c499ff71SFelipe Balbi goto err4; 1129c499ff71SFelipe Balbi } 1130c499ff71SFelipe Balbi 113106281d46SJohn Youn /* 113206281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 113306281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 113406281d46SJohn Youn * DWC_usb31 controller. 113506281d46SJohn Youn */ 11369af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 113706281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 113806281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 113906281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 114006281d46SJohn Youn } 114106281d46SJohn Youn 11429af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 11430bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 114465db7a0cSWilliam Wu 114565db7a0cSWilliam Wu /* 114665db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 114765db7a0cSWilliam Wu * in HS when the device is in the L1 state. 114865db7a0cSWilliam Wu */ 11499af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 11500bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 115165db7a0cSWilliam Wu 1152843714bbSJack Pham /* 1153843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1154843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1155843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1156843714bbSJack Pham * from interrupting the driver. 1157843714bbSJack Pham */ 1158843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1159843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1160843714bbSJack Pham 116165db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 116265db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 116365db7a0cSWilliam Wu 11647ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 11657ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 11667ba6b09fSNeil Armstrong 116762b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 116862b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 116962b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 117062b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 117162b20e6eSBin Yang 11720bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 11730bb39ca1SJohn Youn } 11740bb39ca1SJohn Youn 1175b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1176b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1177b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1178b138e23dSAnurag Kumar Vulisha 1179b138e23dSAnurag Kumar Vulisha /* 1180b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1181b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1182b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1183b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1184b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1185b138e23dSAnurag Kumar Vulisha */ 1186b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1187b138e23dSAnurag Kumar Vulisha 1188b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1189b138e23dSAnurag Kumar Vulisha } 1190b138e23dSAnurag Kumar Vulisha 1191938a5ad1SThinh Nguyen /* 1192938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1193938a5ad1SThinh Nguyen * RX and/or TX threshold. 1194938a5ad1SThinh Nguyen */ 11959af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1196938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1197938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1198938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1199938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1200938a5ad1SThinh Nguyen 1201938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1202938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1203938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1204938a5ad1SThinh Nguyen 1205938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1206938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1207938a5ad1SThinh Nguyen 1208938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1209938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1210938a5ad1SThinh Nguyen 1211938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1212938a5ad1SThinh Nguyen } 1213938a5ad1SThinh Nguyen 1214938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1215938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1216938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1217938a5ad1SThinh Nguyen 1218938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1219938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1220938a5ad1SThinh Nguyen 1221938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1222938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1223938a5ad1SThinh Nguyen 1224938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1225938a5ad1SThinh Nguyen } 1226938a5ad1SThinh Nguyen } 1227938a5ad1SThinh Nguyen 122872246da4SFelipe Balbi return 0; 122972246da4SFelipe Balbi 1230c499ff71SFelipe Balbi err4: 12319b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1232c499ff71SFelipe Balbi 1233c499ff71SFelipe Balbi err3: 12349b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1235c499ff71SFelipe Balbi 12360ffcaf37SFelipe Balbi err2: 1237c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1238c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12390ffcaf37SFelipe Balbi 12400ffcaf37SFelipe Balbi err1: 12410ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 12420ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 124357303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 124457303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 12450ffcaf37SFelipe Balbi 124698112041SRoger Quadros err0a: 124798112041SRoger Quadros dwc3_ulpi_exit(dwc); 124898112041SRoger Quadros 124972246da4SFelipe Balbi err0: 125072246da4SFelipe Balbi return ret; 125172246da4SFelipe Balbi } 125272246da4SFelipe Balbi 12533c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 125472246da4SFelipe Balbi { 12553c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1256941ea361SFelipe Balbi struct device_node *node = dev->of_node; 12573c9f94acSFelipe Balbi int ret; 125872246da4SFelipe Balbi 12595088b6f5SKishon Vijay Abraham I if (node) { 12605088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 12615088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1262bb674907SFelipe Balbi } else { 1263bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1264bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 12655088b6f5SKishon Vijay Abraham I } 12665088b6f5SKishon Vijay Abraham I 1267d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1268d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1269*d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1270122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1271*d090c7a2SKushagra Verma else 12720c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1273122f06e6SKishon Vijay Abraham I } 127451e1e7bcSFelipe Balbi 1275d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1276315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1277*d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1278122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1279*d090c7a2SKushagra Verma else 12800c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1281122f06e6SKishon Vijay Abraham I } 128251e1e7bcSFelipe Balbi 128357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 128457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 128557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 1286*d090c7a2SKushagra Verma if (ret == -ENOSYS || ret == -ENODEV) 128757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 1288*d090c7a2SKushagra Verma else 12890c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 129057303488SKishon Vijay Abraham I } 129157303488SKishon Vijay Abraham I 129257303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 129357303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 129457303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 1295*d090c7a2SKushagra Verma if (ret == -ENOSYS || ret == -ENODEV) 129657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 1297*d090c7a2SKushagra Verma else 12980c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 129957303488SKishon Vijay Abraham I } 130057303488SKishon Vijay Abraham I 13013c9f94acSFelipe Balbi return 0; 13023c9f94acSFelipe Balbi } 13033c9f94acSFelipe Balbi 13045f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13055f94adfeSFelipe Balbi { 13065f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13075f94adfeSFelipe Balbi int ret; 13085f94adfeSFelipe Balbi 13095f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13105f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 131141ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1312958d1a4cSFelipe Balbi 1313958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1314958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1315958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1316644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1317958d1a4cSFelipe Balbi 13185f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13190c0a20f6SAndy Shevchenko if (ret) 13200c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13215f94adfeSFelipe Balbi break; 13225f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 132341ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1324958d1a4cSFelipe Balbi 1325958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1326958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1327958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1328644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1329958d1a4cSFelipe Balbi 13305f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13310c0a20f6SAndy Shevchenko if (ret) 13320c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13335f94adfeSFelipe Balbi break; 13345f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 133541ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13369840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13370c0a20f6SAndy Shevchenko if (ret) 13380c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13395f94adfeSFelipe Balbi break; 13405f94adfeSFelipe Balbi default: 13415f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 13425f94adfeSFelipe Balbi return -EINVAL; 13435f94adfeSFelipe Balbi } 13445f94adfeSFelipe Balbi 13455f94adfeSFelipe Balbi return 0; 13465f94adfeSFelipe Balbi } 13475f94adfeSFelipe Balbi 13485f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 13495f94adfeSFelipe Balbi { 13505f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13515f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 13525f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 13535f94adfeSFelipe Balbi break; 13545f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 13555f94adfeSFelipe Balbi dwc3_host_exit(dwc); 13565f94adfeSFelipe Balbi break; 13575f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 13589840354fSRoger Quadros dwc3_drd_exit(dwc); 13595f94adfeSFelipe Balbi break; 13605f94adfeSFelipe Balbi default: 13615f94adfeSFelipe Balbi /* do nothing */ 13625f94adfeSFelipe Balbi break; 13635f94adfeSFelipe Balbi } 136409ed259fSBin Liu 136509ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 136609ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 13675f94adfeSFelipe Balbi } 13685f94adfeSFelipe Balbi 1369c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 13703c9f94acSFelipe Balbi { 1371c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 137280caf7d2SHuang Rui u8 lpm_nyet_threshold; 13736b6a0c9aSHuang Rui u8 tx_de_emphasis; 1374460d098cSHuang Rui u8 hird_threshold; 1375f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0; 1376f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0; 1377f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0; 1378f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0; 13799f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 13806f0764b5SRay Chi const char *usb_psy_name; 13816f0764b5SRay Chi int ret; 13823c9f94acSFelipe Balbi 138380caf7d2SHuang Rui /* default to highest possible threshold */ 13848d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 138580caf7d2SHuang Rui 13866b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 13876b6a0c9aSHuang Rui tx_de_emphasis = 1; 13886b6a0c9aSHuang Rui 1389460d098cSHuang Rui /* 1390460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1391460d098cSHuang Rui * threshold value of 0b1100 1392460d098cSHuang Rui */ 1393460d098cSHuang Rui hird_threshold = 12; 1394460d098cSHuang Rui 13959f607a30SWesley Cheng /* 13969f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 13979f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 13989f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 13999f607a30SWesley Cheng */ 14009f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14019f607a30SWesley Cheng 140263863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 140367848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 140406e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 140532f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 140663863b98SHeikki Krogerus 1407d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1408d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1409d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1410d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1411d64ff406SArnd Bergmann else 1412d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1413d64ff406SArnd Bergmann 14146f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14156f0764b5SRay Chi if (ret >= 0) { 14166f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14176f0764b5SRay Chi if (!dwc->usb_psy) 14186f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14196f0764b5SRay Chi } 14206f0764b5SRay Chi 14213d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 142280caf7d2SHuang Rui "snps,has-lpm-erratum"); 14233d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 142480caf7d2SHuang Rui &lpm_nyet_threshold); 14253d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1426460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14273d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1428460d098cSHuang Rui &hird_threshold); 1429d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1430d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14313d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1432eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1433022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1434022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1435475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1436475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1437938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1438938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1439938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1440938a5ad1SThinh Nguyen &rx_max_burst_prd); 1441938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1442938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1443938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1444938a5ad1SThinh Nguyen &tx_max_burst_prd); 14459f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 14469f607a30SWesley Cheng "tx-fifo-resize"); 14479f607a30SWesley Cheng if (dwc->do_fifo_resize) 14489f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 14499f607a30SWesley Cheng &tx_fifo_resize_max_num); 14503c9f94acSFelipe Balbi 14513d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 14523b81221aSHuang Rui "snps,disable_scramble_quirk"); 14533d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 14549a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 14553d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1456b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 14573d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1458df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 14593d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1460a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 14613d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 146241c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 14633d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1464fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 14653d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 146614f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 14673d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 146859acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 14693d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 14700effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1471ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1472ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1473729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1474729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1475729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1476729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1477e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1478e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 147916199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 148016199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 148100fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 148200fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 148365db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 148465db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 14857ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 14867ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 14876b6a0c9aSHuang Rui 14883d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 14896b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 14903d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 14916b6a0c9aSHuang Rui &tx_de_emphasis); 14923d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 14933e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 14943d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1495bcdb3272SFelipe Balbi &dwc->fladj); 14967bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 14977bee3188SBalaji Prakash J &dwc->ref_clk_per); 14983d128919SHeikki Krogerus 149942bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 150042bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 150142bf02ecSRoger Quadros 1502f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1503f580170fSYu Chen "snps,dis-split-quirk"); 1504f580170fSYu Chen 150580caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15066b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 150780caf7d2SHuang Rui 150816fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1509460d098cSHuang Rui 1510938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1511938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1512938a5ad1SThinh Nguyen 1513938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1514938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1515938a5ad1SThinh Nguyen 1516cf40b86bSJohn Youn dwc->imod_interval = 0; 15179f607a30SWesley Cheng 15189f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1519cf40b86bSJohn Youn } 1520cf40b86bSJohn Youn 1521cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1522cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1523cf40b86bSJohn Youn { 15249af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15259af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15269af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1527c5ac6116SFelipe Balbi } 1528c5ac6116SFelipe Balbi 15297ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15307ac51a12SJohn Youn { 15317ac51a12SJohn Youn struct device *dev = dwc->dev; 1532b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1533b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15347ac51a12SJohn Youn 1535cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1536cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1537cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1538cf40b86bSJohn Youn dwc->imod_interval = 0; 1539cf40b86bSJohn Youn } 1540cf40b86bSJohn Youn 154128632b44SJohn Youn /* 154228632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 154328632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 154428632b44SJohn Youn * interrupt from being masked while handling events. IMOD 154528632b44SJohn Youn * allows us to work around this issue. Enable it for the 154628632b44SJohn Youn * affected version. 154728632b44SJohn Youn */ 154828632b44SJohn Youn if (!dwc->imod_interval && 15499af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 155028632b44SJohn Youn dwc->imod_interval = 1; 155128632b44SJohn Youn 15527ac51a12SJohn Youn /* Check the maximum_speed parameter */ 15537ac51a12SJohn Youn switch (dwc->maximum_speed) { 15547ac51a12SJohn Youn case USB_SPEED_FULL: 15557ac51a12SJohn Youn case USB_SPEED_HIGH: 1556e518bdd9SThinh Nguyen break; 15577ac51a12SJohn Youn case USB_SPEED_SUPER: 1558e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1559e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1560e518bdd9SThinh Nguyen break; 15617ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1562e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1563e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1564e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1565e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1566e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 15677ac51a12SJohn Youn break; 15687ac51a12SJohn Youn default: 15697ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 15707ac51a12SJohn Youn dwc->maximum_speed); 1571df561f66SGustavo A. R. Silva fallthrough; 15727ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1573b574ce3eSThinh Nguyen switch (hwparam_gen) { 1574b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 15757ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1576b574ce3eSThinh Nguyen break; 1577b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1578b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1579b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1580b574ce3eSThinh Nguyen else 1581b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1582b574ce3eSThinh Nguyen break; 1583b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1584b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1585b574ce3eSThinh Nguyen break; 1586b574ce3eSThinh Nguyen default: 1587b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1588b574ce3eSThinh Nguyen break; 1589b574ce3eSThinh Nguyen } 15907ac51a12SJohn Youn break; 15917ac51a12SJohn Youn } 159267848146SThinh Nguyen 159367848146SThinh Nguyen /* 159467848146SThinh Nguyen * Currently the controller does not have visibility into the HW 159567848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 159667848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 159767848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 159867848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 159967848146SThinh Nguyen */ 160067848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 160167848146SThinh Nguyen switch (dwc->max_ssp_rate) { 160267848146SThinh Nguyen case USB_SSP_GEN_2x1: 160367848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 160467848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 160567848146SThinh Nguyen break; 160667848146SThinh Nguyen case USB_SSP_GEN_1x2: 160767848146SThinh Nguyen case USB_SSP_GEN_2x2: 160867848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 160967848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 161067848146SThinh Nguyen break; 161167848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 161267848146SThinh Nguyen default: 161367848146SThinh Nguyen switch (hwparam_gen) { 161467848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 161567848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 161667848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 161767848146SThinh Nguyen else 161867848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 161967848146SThinh Nguyen break; 162067848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 162167848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 162267848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 162367848146SThinh Nguyen break; 162467848146SThinh Nguyen } 162567848146SThinh Nguyen break; 162667848146SThinh Nguyen } 162767848146SThinh Nguyen } 16287ac51a12SJohn Youn } 16297ac51a12SJohn Youn 16300f010171SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 16310f010171SAndrey Smirnov { 16320f010171SAndrey Smirnov struct device *dev = dwc->dev; 16330f010171SAndrey Smirnov struct device_node *np_phy; 16340f010171SAndrey Smirnov struct extcon_dev *edev = NULL; 16350f010171SAndrey Smirnov const char *name; 16360f010171SAndrey Smirnov 16370f010171SAndrey Smirnov if (device_property_read_bool(dev, "extcon")) 16380f010171SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0); 16390f010171SAndrey Smirnov 16400f010171SAndrey Smirnov /* 16410f010171SAndrey Smirnov * Device tree platforms should get extcon via phandle. 16420f010171SAndrey Smirnov * On ACPI platforms, we get the name from a device property. 16430f010171SAndrey Smirnov * This device property is for kernel internal use only and 16440f010171SAndrey Smirnov * is expected to be set by the glue code. 16450f010171SAndrey Smirnov */ 16460f010171SAndrey Smirnov if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) { 16470f010171SAndrey Smirnov edev = extcon_get_extcon_dev(name); 16480f010171SAndrey Smirnov if (!edev) 16490f010171SAndrey Smirnov return ERR_PTR(-EPROBE_DEFER); 16500f010171SAndrey Smirnov 16510f010171SAndrey Smirnov return edev; 16520f010171SAndrey Smirnov } 16530f010171SAndrey Smirnov 16540f010171SAndrey Smirnov /* 16550f010171SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port" 16560f010171SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the 16570f010171SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon 16580f010171SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch" 16590f010171SAndrey Smirnov * or OTG mode. 16600f010171SAndrey Smirnov */ 16610f010171SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0); 16620f010171SAndrey Smirnov if (of_graph_is_present(np_phy)) { 16630f010171SAndrey Smirnov struct device_node *np_conn; 16640f010171SAndrey Smirnov 16650f010171SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1); 16660f010171SAndrey Smirnov if (np_conn) 16670f010171SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn); 16680f010171SAndrey Smirnov of_node_put(np_conn); 16690f010171SAndrey Smirnov } 16700f010171SAndrey Smirnov of_node_put(np_phy); 16710f010171SAndrey Smirnov 16720f010171SAndrey Smirnov return edev; 16730f010171SAndrey Smirnov } 16740f010171SAndrey Smirnov 1675c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1676c5ac6116SFelipe Balbi { 1677c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 167844feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1679c5ac6116SFelipe Balbi struct dwc3 *dwc; 1680c5ac6116SFelipe Balbi 1681c5ac6116SFelipe Balbi int ret; 1682c5ac6116SFelipe Balbi 1683c5ac6116SFelipe Balbi void __iomem *regs; 1684c5ac6116SFelipe Balbi 1685c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1686c5ac6116SFelipe Balbi if (!dwc) 1687c5ac6116SFelipe Balbi return -ENOMEM; 1688c5ac6116SFelipe Balbi 1689c5ac6116SFelipe Balbi dwc->dev = dev; 1690c5ac6116SFelipe Balbi 1691c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1692c5ac6116SFelipe Balbi if (!res) { 1693c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1694c5ac6116SFelipe Balbi return -ENODEV; 1695c5ac6116SFelipe Balbi } 1696c5ac6116SFelipe Balbi 1697c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1698c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1699c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1700c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1701c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1702c5ac6116SFelipe Balbi 1703c5ac6116SFelipe Balbi /* 1704c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1705c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1706c5ac6116SFelipe Balbi */ 170744feb8e6SMasahiro Yamada dwc_res = *res; 170844feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 170944feb8e6SMasahiro Yamada 171044feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 171144feb8e6SMasahiro Yamada if (IS_ERR(regs)) 171244feb8e6SMasahiro Yamada return PTR_ERR(regs); 1713c5ac6116SFelipe Balbi 1714c5ac6116SFelipe Balbi dwc->regs = regs; 171544feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1716c5ac6116SFelipe Balbi 1717c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1718c5ac6116SFelipe Balbi 171947ce4590SFabio Aiuto if (!dwc->sysdev_is_parent) { 172045d39448SSven Peter ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 172145d39448SSven Peter if (ret) 172245d39448SSven Peter return ret; 172347ce4590SFabio Aiuto } 172445d39448SSven Peter 1725babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1726fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1727fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1728fe8abf33SMasahiro Yamada 172961527777SHans de Goede if (dev->of_node) { 1730fe8abf33SMasahiro Yamada /* 173161527777SHans de Goede * Clocks are optional, but new DT platforms should support all 173261527777SHans de Goede * clocks as required by the DT-binding. 17334e64cd77SPeter Geis * Some devices have different clock names in legacy device trees, 17344e64cd77SPeter Geis * check for them to retain backwards compatibility. 1735fe8abf33SMasahiro Yamada */ 173633fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 173733fb697eSSean Anderson if (IS_ERR(dwc->bus_clk)) 173833fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 173933fb697eSSean Anderson "could not get bus clock\n"); 17400d3a9708SJohn Stultz 17414e64cd77SPeter Geis if (dwc->bus_clk == NULL) { 17424e64cd77SPeter Geis dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 17434e64cd77SPeter Geis if (IS_ERR(dwc->bus_clk)) 17444e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 17454e64cd77SPeter Geis "could not get bus clock\n"); 17464e64cd77SPeter Geis } 17474e64cd77SPeter Geis 174833fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 174933fb697eSSean Anderson if (IS_ERR(dwc->ref_clk)) 175033fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 175133fb697eSSean Anderson "could not get ref clock\n"); 175233fb697eSSean Anderson 17534e64cd77SPeter Geis if (dwc->ref_clk == NULL) { 17544e64cd77SPeter Geis dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 17554e64cd77SPeter Geis if (IS_ERR(dwc->ref_clk)) 17564e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 17574e64cd77SPeter Geis "could not get ref clock\n"); 17584e64cd77SPeter Geis } 17594e64cd77SPeter Geis 176033fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 176133fb697eSSean Anderson if (IS_ERR(dwc->susp_clk)) 176233fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 176333fb697eSSean Anderson "could not get suspend clock\n"); 17644e64cd77SPeter Geis 17654e64cd77SPeter Geis if (dwc->susp_clk == NULL) { 17664e64cd77SPeter Geis dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 17674e64cd77SPeter Geis if (IS_ERR(dwc->susp_clk)) 17684e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 17694e64cd77SPeter Geis "could not get suspend clock\n"); 17704e64cd77SPeter Geis } 177161527777SHans de Goede } 1772fe8abf33SMasahiro Yamada 1773fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1774fe8abf33SMasahiro Yamada if (ret) 177503bf32bbSAndrey Smirnov return ret; 1776fe8abf33SMasahiro Yamada 177733fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1778fe8abf33SMasahiro Yamada if (ret) 1779fe8abf33SMasahiro Yamada goto assert_reset; 1780fe8abf33SMasahiro Yamada 1781dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1782dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1783dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1784dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1785dc1b5d9aSEnric Balletbo i Serra } 1786dc1b5d9aSEnric Balletbo i Serra 17876c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 17882917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 17896c89cce0SHeikki Krogerus 179072246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1791f88359e1SYu Chen mutex_init(&dwc->mutex); 179272246da4SFelipe Balbi 1793fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1794fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1795fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1796802ca850SChanho Park pm_runtime_enable(dev); 179732808237SRoger Quadros ret = pm_runtime_get_sync(dev); 179832808237SRoger Quadros if (ret < 0) 179932808237SRoger Quadros goto err1; 180032808237SRoger Quadros 1801802ca850SChanho Park pm_runtime_forbid(dev); 180272246da4SFelipe Balbi 18033921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 18043921426bSFelipe Balbi if (ret) { 18053921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 18063921426bSFelipe Balbi ret = -ENOMEM; 180732808237SRoger Quadros goto err2; 18083921426bSFelipe Balbi } 18093921426bSFelipe Balbi 18100f010171SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc); 18110f010171SAndrey Smirnov if (IS_ERR(dwc->edev)) { 18120f010171SAndrey Smirnov ret = PTR_ERR(dwc->edev); 18130f010171SAndrey Smirnov dev_err_probe(dwc->dev, ret, "failed to get extcon\n"); 18140f010171SAndrey Smirnov goto err3; 18150f010171SAndrey Smirnov } 18160f010171SAndrey Smirnov 18179d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 18189d6173e1SThinh Nguyen if (ret) 18199d6173e1SThinh Nguyen goto err3; 182032a4a135SFelipe Balbi 1821c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1822c499ff71SFelipe Balbi if (ret) 182332808237SRoger Quadros goto err3; 1824c499ff71SFelipe Balbi 182572246da4SFelipe Balbi ret = dwc3_core_init(dwc); 182672246da4SFelipe Balbi if (ret) { 18270c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 182832808237SRoger Quadros goto err4; 182972246da4SFelipe Balbi } 183072246da4SFelipe Balbi 18317ac51a12SJohn Youn dwc3_check_params(dwc); 183284524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 18332c7f1bd9SJohn Youn 18345f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 18355f94adfeSFelipe Balbi if (ret) 183632808237SRoger Quadros goto err5; 183772246da4SFelipe Balbi 1838fc8bb91bSFelipe Balbi pm_runtime_put(dev); 183972246da4SFelipe Balbi 184072246da4SFelipe Balbi return 0; 184172246da4SFelipe Balbi 184232808237SRoger Quadros err5: 184384524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1844f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 184503c1fd62SLi Jun 184603c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 184703c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 184803c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 184903c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 185003c1fd62SLi Jun 185103c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 185203c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 185303c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 185403c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 185503c1fd62SLi Jun 185608fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1857f122d33eSFelipe Balbi 185832808237SRoger Quadros err4: 1859c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 186072246da4SFelipe Balbi 186132808237SRoger Quadros err3: 18623921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 18633921426bSFelipe Balbi 186432808237SRoger Quadros err2: 186532808237SRoger Quadros pm_runtime_allow(&pdev->dev); 186632808237SRoger Quadros 186732808237SRoger Quadros err1: 186832808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 186932808237SRoger Quadros pm_runtime_disable(&pdev->dev); 187032808237SRoger Quadros 1871dc1b5d9aSEnric Balletbo i Serra disable_clks: 187233fb697eSSean Anderson dwc3_clk_disable(dwc); 1873fe8abf33SMasahiro Yamada assert_reset: 1874fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1875fe8abf33SMasahiro Yamada 1876b0bf77cdSColin Ian King if (dwc->usb_psy) 18776f0764b5SRay Chi power_supply_put(dwc->usb_psy); 18786f0764b5SRay Chi 187972246da4SFelipe Balbi return ret; 188072246da4SFelipe Balbi } 188172246da4SFelipe Balbi 1882fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 188372246da4SFelipe Balbi { 188472246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 18853da1f6eeSFelipe Balbi 1886fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 188772246da4SFelipe Balbi 1888dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 18892a042767SPeter Chen dwc3_debugfs_exit(dwc); 18908ba007a9SKishon Vijay Abraham I 189172246da4SFelipe Balbi dwc3_core_exit(dwc); 189288bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 189372246da4SFelipe Balbi 1894fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1895266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1896266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1897fc8bb91bSFelipe Balbi 1898c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1899c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1900c499ff71SFelipe Balbi 1901b0bf77cdSColin Ian King if (dwc->usb_psy) 19026f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19036f0764b5SRay Chi 190472246da4SFelipe Balbi return 0; 190572246da4SFelipe Balbi } 190672246da4SFelipe Balbi 1907fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1908fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1909fe8abf33SMasahiro Yamada { 1910fe8abf33SMasahiro Yamada int ret; 1911fe8abf33SMasahiro Yamada 1912fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1913fe8abf33SMasahiro Yamada if (ret) 1914fe8abf33SMasahiro Yamada return ret; 1915fe8abf33SMasahiro Yamada 191633fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1917fe8abf33SMasahiro Yamada if (ret) 1918fe8abf33SMasahiro Yamada goto assert_reset; 1919fe8abf33SMasahiro Yamada 1920fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1921fe8abf33SMasahiro Yamada if (ret) 1922fe8abf33SMasahiro Yamada goto disable_clks; 1923fe8abf33SMasahiro Yamada 1924fe8abf33SMasahiro Yamada return 0; 1925fe8abf33SMasahiro Yamada 1926fe8abf33SMasahiro Yamada disable_clks: 192733fb697eSSean Anderson dwc3_clk_disable(dwc); 1928fe8abf33SMasahiro Yamada assert_reset: 1929fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1930fe8abf33SMasahiro Yamada 1931fe8abf33SMasahiro Yamada return ret; 1932fe8abf33SMasahiro Yamada } 1933fe8abf33SMasahiro Yamada 1934c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 19357415f17cSFelipe Balbi { 1936fc8bb91bSFelipe Balbi unsigned long flags; 1937bcb12877SManu Gautam u32 reg; 19387415f17cSFelipe Balbi 1939689bf72cSManu Gautam switch (dwc->current_dr_role) { 1940689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 19410227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 19420227cc84SLi Jun break; 1943fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 19447415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1945fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 194641a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1947689bf72cSManu Gautam dwc3_core_exit(dwc); 194851f5d49aSFelipe Balbi break; 1949689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1950bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1951c4a5153eSManu Gautam dwc3_core_exit(dwc); 1952c4a5153eSManu Gautam break; 1953bcb12877SManu Gautam } 1954bcb12877SManu Gautam 1955bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1956bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1957bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1958bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1959bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1960bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1961bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1962bcb12877SManu Gautam 1963bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1964bcb12877SManu Gautam usleep_range(5000, 6000); 1965bcb12877SManu Gautam } 1966bcb12877SManu Gautam 1967bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1968bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1969bcb12877SManu Gautam break; 1970f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1971f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1972f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1973f09cc79bSRoger Quadros break; 1974f09cc79bSRoger Quadros 1975f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1976f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1977f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1978f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 197941a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1980f09cc79bSRoger Quadros } 1981f09cc79bSRoger Quadros 1982f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1983f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1984f09cc79bSRoger Quadros break; 19857415f17cSFelipe Balbi default: 198651f5d49aSFelipe Balbi /* do nothing */ 19877415f17cSFelipe Balbi break; 19887415f17cSFelipe Balbi } 19897415f17cSFelipe Balbi 1990fc8bb91bSFelipe Balbi return 0; 1991fc8bb91bSFelipe Balbi } 1992fc8bb91bSFelipe Balbi 1993c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1994fc8bb91bSFelipe Balbi { 1995fc8bb91bSFelipe Balbi unsigned long flags; 1996fc8bb91bSFelipe Balbi int ret; 1997bcb12877SManu Gautam u32 reg; 1998fc8bb91bSFelipe Balbi 1999689bf72cSManu Gautam switch (dwc->current_dr_role) { 2000689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2001fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2002fc8bb91bSFelipe Balbi if (ret) 2003fc8bb91bSFelipe Balbi return ret; 2004fc8bb91bSFelipe Balbi 20057d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2006fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 2007fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 2008fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 2009689bf72cSManu Gautam break; 2010689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2011c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 2012fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2013c4a5153eSManu Gautam if (ret) 2014c4a5153eSManu Gautam return ret; 20157d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2016bcb12877SManu Gautam break; 2017c4a5153eSManu Gautam } 2018bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2019bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2020bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 2021bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2022bcb12877SManu Gautam 2023bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 2024bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2025bcb12877SManu Gautam 2026bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2027bcb12877SManu Gautam 2028bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2029bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2030c4a5153eSManu Gautam break; 2031f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2032f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 2033f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2034f09cc79bSRoger Quadros break; 2035f09cc79bSRoger Quadros 20360e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 2037f09cc79bSRoger Quadros if (ret) 2038f09cc79bSRoger Quadros return ret; 2039f09cc79bSRoger Quadros 2040f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 2041f09cc79bSRoger Quadros 2042f09cc79bSRoger Quadros dwc3_otg_init(dwc); 2043f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2044f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 2045f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2046f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2047f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 2048f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 2049f09cc79bSRoger Quadros } 2050f09cc79bSRoger Quadros 2051f09cc79bSRoger Quadros break; 2052fc8bb91bSFelipe Balbi default: 2053fc8bb91bSFelipe Balbi /* do nothing */ 2054fc8bb91bSFelipe Balbi break; 2055fc8bb91bSFelipe Balbi } 2056fc8bb91bSFelipe Balbi 2057fc8bb91bSFelipe Balbi return 0; 2058fc8bb91bSFelipe Balbi } 2059fc8bb91bSFelipe Balbi 2060fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 2061fc8bb91bSFelipe Balbi { 2062689bf72cSManu Gautam switch (dwc->current_dr_role) { 2063c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2064fc8bb91bSFelipe Balbi if (dwc->connected) 2065fc8bb91bSFelipe Balbi return -EBUSY; 2066fc8bb91bSFelipe Balbi break; 2067c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2068fc8bb91bSFelipe Balbi default: 2069fc8bb91bSFelipe Balbi /* do nothing */ 2070fc8bb91bSFelipe Balbi break; 2071fc8bb91bSFelipe Balbi } 2072fc8bb91bSFelipe Balbi 2073fc8bb91bSFelipe Balbi return 0; 2074fc8bb91bSFelipe Balbi } 2075fc8bb91bSFelipe Balbi 2076fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2077fc8bb91bSFelipe Balbi { 2078fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2079fc8bb91bSFelipe Balbi int ret; 2080fc8bb91bSFelipe Balbi 2081fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2082fc8bb91bSFelipe Balbi return -EBUSY; 2083fc8bb91bSFelipe Balbi 2084c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2085fc8bb91bSFelipe Balbi if (ret) 2086fc8bb91bSFelipe Balbi return ret; 2087fc8bb91bSFelipe Balbi 2088fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 2089fc8bb91bSFelipe Balbi 2090fc8bb91bSFelipe Balbi return 0; 2091fc8bb91bSFelipe Balbi } 2092fc8bb91bSFelipe Balbi 2093fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2094fc8bb91bSFelipe Balbi { 2095fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2096fc8bb91bSFelipe Balbi int ret; 2097fc8bb91bSFelipe Balbi 2098fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 2099fc8bb91bSFelipe Balbi 2100c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2101fc8bb91bSFelipe Balbi if (ret) 2102fc8bb91bSFelipe Balbi return ret; 2103fc8bb91bSFelipe Balbi 2104689bf72cSManu Gautam switch (dwc->current_dr_role) { 2105689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2106fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2107fc8bb91bSFelipe Balbi break; 2108689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2109fc8bb91bSFelipe Balbi default: 2110fc8bb91bSFelipe Balbi /* do nothing */ 2111fc8bb91bSFelipe Balbi break; 2112fc8bb91bSFelipe Balbi } 2113fc8bb91bSFelipe Balbi 2114fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2115fc8bb91bSFelipe Balbi 2116fc8bb91bSFelipe Balbi return 0; 2117fc8bb91bSFelipe Balbi } 2118fc8bb91bSFelipe Balbi 2119fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2120fc8bb91bSFelipe Balbi { 2121fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2122fc8bb91bSFelipe Balbi 2123689bf72cSManu Gautam switch (dwc->current_dr_role) { 2124689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2125fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2126fc8bb91bSFelipe Balbi return -EBUSY; 2127fc8bb91bSFelipe Balbi break; 2128689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2129fc8bb91bSFelipe Balbi default: 2130fc8bb91bSFelipe Balbi /* do nothing */ 2131fc8bb91bSFelipe Balbi break; 2132fc8bb91bSFelipe Balbi } 2133fc8bb91bSFelipe Balbi 2134fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2135fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2136fc8bb91bSFelipe Balbi 2137fc8bb91bSFelipe Balbi return 0; 2138fc8bb91bSFelipe Balbi } 2139fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2140fc8bb91bSFelipe Balbi 2141fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2142fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2143fc8bb91bSFelipe Balbi { 2144fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2145fc8bb91bSFelipe Balbi int ret; 2146fc8bb91bSFelipe Balbi 2147c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2148fc8bb91bSFelipe Balbi if (ret) 2149fc8bb91bSFelipe Balbi return ret; 2150fc8bb91bSFelipe Balbi 21516344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 21526344475fSSekhar Nori 21537415f17cSFelipe Balbi return 0; 21547415f17cSFelipe Balbi } 21557415f17cSFelipe Balbi 21567415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 21577415f17cSFelipe Balbi { 21587415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 215957303488SKishon Vijay Abraham I int ret; 21607415f17cSFelipe Balbi 21616344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 21626344475fSSekhar Nori 2163c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 216451f5d49aSFelipe Balbi if (ret) 21655c4ad318SFelipe Balbi return ret; 21665c4ad318SFelipe Balbi 21677415f17cSFelipe Balbi pm_runtime_disable(dev); 21687415f17cSFelipe Balbi pm_runtime_set_active(dev); 21697415f17cSFelipe Balbi pm_runtime_enable(dev); 21707415f17cSFelipe Balbi 21717415f17cSFelipe Balbi return 0; 21727415f17cSFelipe Balbi } 2173f580170fSYu Chen 2174f580170fSYu Chen static void dwc3_complete(struct device *dev) 2175f580170fSYu Chen { 2176f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2177f580170fSYu Chen u32 reg; 2178f580170fSYu Chen 2179f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2180f580170fSYu Chen dwc->dis_split_quirk) { 2181f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2182f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2183f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2184f580170fSYu Chen } 2185f580170fSYu Chen } 2186f580170fSYu Chen #else 2187f580170fSYu Chen #define dwc3_complete NULL 21887f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 21897415f17cSFelipe Balbi 21907415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 21917415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2192f580170fSYu Chen .complete = dwc3_complete, 2193fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2194fc8bb91bSFelipe Balbi dwc3_runtime_idle) 21957415f17cSFelipe Balbi }; 21967415f17cSFelipe Balbi 21975088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 21985088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 21995088b6f5SKishon Vijay Abraham I { 220022a5aa17SFelipe Balbi .compatible = "snps,dwc3" 220122a5aa17SFelipe Balbi }, 220222a5aa17SFelipe Balbi { 22035088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 22045088b6f5SKishon Vijay Abraham I }, 22055088b6f5SKishon Vijay Abraham I { }, 22065088b6f5SKishon Vijay Abraham I }; 22075088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 22085088b6f5SKishon Vijay Abraham I #endif 22095088b6f5SKishon Vijay Abraham I 2210404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2211404905a6SHeikki Krogerus 2212404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2213404905a6SHeikki Krogerus 2214404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2215404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2216404905a6SHeikki Krogerus { }, 2217404905a6SHeikki Krogerus }; 2218404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2219404905a6SHeikki Krogerus #endif 2220404905a6SHeikki Krogerus 222172246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 222272246da4SFelipe Balbi .probe = dwc3_probe, 22237690417dSBill Pemberton .remove = dwc3_remove, 222472246da4SFelipe Balbi .driver = { 222572246da4SFelipe Balbi .name = "dwc3", 22265088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2227404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 22287f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 222972246da4SFelipe Balbi }, 223072246da4SFelipe Balbi }; 223172246da4SFelipe Balbi 2232b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2233b1116dccSTobias Klauser 22347ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 223572246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 22365945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 223772246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 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