15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 272246da4SFelipe Balbi /** 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 572246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32f7e846f0SFelipe Balbi #include <linux/usb/of.h> 33a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3472246da4SFelipe Balbi 3572246da4SFelipe Balbi #include "core.h" 3672246da4SFelipe Balbi #include "gadget.h" 3772246da4SFelipe Balbi #include "io.h" 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #include "debug.h" 4072246da4SFelipe Balbi 41fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 428300dd23SFelipe Balbi 439d6173e1SThinh Nguyen /** 449d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 459d6173e1SThinh Nguyen * @dwc: pointer to our context structure 469d6173e1SThinh Nguyen */ 479d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 489d6173e1SThinh Nguyen { 499d6173e1SThinh Nguyen enum usb_dr_mode mode; 509d6173e1SThinh Nguyen struct device *dev = dwc->dev; 519d6173e1SThinh Nguyen unsigned int hw_mode; 529d6173e1SThinh Nguyen 539d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 549d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 559d6173e1SThinh Nguyen 569d6173e1SThinh Nguyen mode = dwc->dr_mode; 579d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 589d6173e1SThinh Nguyen 599d6173e1SThinh Nguyen switch (hw_mode) { 609d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 619d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 629d6173e1SThinh Nguyen dev_err(dev, 639d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 649d6173e1SThinh Nguyen return -EINVAL; 659d6173e1SThinh Nguyen } 669d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 679d6173e1SThinh Nguyen break; 689d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 699d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 709d6173e1SThinh Nguyen dev_err(dev, 719d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 729d6173e1SThinh Nguyen return -EINVAL; 739d6173e1SThinh Nguyen } 749d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 759d6173e1SThinh Nguyen break; 769d6173e1SThinh Nguyen default: 779d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 789d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 799d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 81a7700468SThinh Nguyen 82a7700468SThinh Nguyen /* 8389a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8489a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8589a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 86a7700468SThinh Nguyen */ 8789a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 888bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 898bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 9089a9cc47SThinh Nguyen dwc->revision >= DWC3_REVISION_330A) 91a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 929d6173e1SThinh Nguyen } 939d6173e1SThinh Nguyen 949d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 959d6173e1SThinh Nguyen dev_warn(dev, 969d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 979d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 989d6173e1SThinh Nguyen 999d6173e1SThinh Nguyen dwc->dr_mode = mode; 1009d6173e1SThinh Nguyen } 1019d6173e1SThinh Nguyen 1029d6173e1SThinh Nguyen return 0; 1039d6173e1SThinh Nguyen } 1049d6173e1SThinh Nguyen 105f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1063140e8cbSSebastian Andrzej Siewior { 1073140e8cbSSebastian Andrzej Siewior u32 reg; 1083140e8cbSSebastian Andrzej Siewior 1093140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1103140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1113140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1123140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113c4a5153eSManu Gautam 114c4a5153eSManu Gautam dwc->current_dr_role = mode; 11541ce1456SRoger Quadros } 1166b3261a2SRoger Quadros 11741ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 11841ce1456SRoger Quadros { 11941ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12041ce1456SRoger Quadros unsigned long flags; 12141ce1456SRoger Quadros int ret; 12241ce1456SRoger Quadros 123f09cc79bSRoger Quadros if (dwc->dr_mode != USB_DR_MODE_OTG) 124f09cc79bSRoger Quadros return; 125f09cc79bSRoger Quadros 126c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 127c2cd3452SMartin Kepplinger 128f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 129f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 130f09cc79bSRoger Quadros 13141ce1456SRoger Quadros if (!dwc->desired_dr_role) 132c2cd3452SMartin Kepplinger goto out; 13341ce1456SRoger Quadros 13441ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 135c2cd3452SMartin Kepplinger goto out; 13641ce1456SRoger Quadros 137f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 138c2cd3452SMartin Kepplinger goto out; 13941ce1456SRoger Quadros 14041ce1456SRoger Quadros switch (dwc->current_dr_role) { 14141ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14241ce1456SRoger Quadros dwc3_host_exit(dwc); 14341ce1456SRoger Quadros break; 14441ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14541ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14641ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14741ce1456SRoger Quadros break; 148f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 149f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 150f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 151f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 152f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 153f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 154f09cc79bSRoger Quadros break; 15541ce1456SRoger Quadros default: 15641ce1456SRoger Quadros break; 15741ce1456SRoger Quadros } 15841ce1456SRoger Quadros 15941ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 16041ce1456SRoger Quadros 16141ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 16241ce1456SRoger Quadros 16341ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 16441ce1456SRoger Quadros 16541ce1456SRoger Quadros switch (dwc->desired_dr_role) { 16641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 16741ce1456SRoger Quadros ret = dwc3_host_init(dwc); 168958d1a4cSFelipe Balbi if (ret) { 16941ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 170958d1a4cSFelipe Balbi } else { 171958d1a4cSFelipe Balbi if (dwc->usb2_phy) 172958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 173958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 174644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 175958d1a4cSFelipe Balbi } 17641ce1456SRoger Quadros break; 17741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 17841ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 179958d1a4cSFelipe Balbi 180958d1a4cSFelipe Balbi if (dwc->usb2_phy) 181958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 182958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 183644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 184958d1a4cSFelipe Balbi 18541ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 18641ce1456SRoger Quadros if (ret) 18741ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 18841ce1456SRoger Quadros break; 189f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 190f09cc79bSRoger Quadros dwc3_otg_init(dwc); 191f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 192f09cc79bSRoger Quadros break; 19341ce1456SRoger Quadros default: 19441ce1456SRoger Quadros break; 19541ce1456SRoger Quadros } 196f09cc79bSRoger Quadros 197c2cd3452SMartin Kepplinger out: 198c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 199c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 20041ce1456SRoger Quadros } 20141ce1456SRoger Quadros 20241ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 20341ce1456SRoger Quadros { 20441ce1456SRoger Quadros unsigned long flags; 20541ce1456SRoger Quadros 20641ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 20741ce1456SRoger Quadros dwc->desired_dr_role = mode; 20841ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 20941ce1456SRoger Quadros 210084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2113140e8cbSSebastian Andrzej Siewior } 2128300dd23SFelipe Balbi 213cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 214cf6d867dSFelipe Balbi { 215cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 216cf6d867dSFelipe Balbi u32 reg; 217cf6d867dSFelipe Balbi 218cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 219cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 220cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 221cf6d867dSFelipe Balbi 222cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 223cf6d867dSFelipe Balbi 224cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 225cf6d867dSFelipe Balbi } 226cf6d867dSFelipe Balbi 22772246da4SFelipe Balbi /** 22872246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 22972246da4SFelipe Balbi * @dwc: pointer to our context structure 23072246da4SFelipe Balbi */ 23157303488SKishon Vijay Abraham I static int dwc3_core_soft_reset(struct dwc3 *dwc) 23272246da4SFelipe Balbi { 23372246da4SFelipe Balbi u32 reg; 234f59dcab1SFelipe Balbi int retries = 1000; 23557303488SKishon Vijay Abraham I int ret; 23672246da4SFelipe Balbi 23751e1e7bcSFelipe Balbi usb_phy_init(dwc->usb2_phy); 23851e1e7bcSFelipe Balbi usb_phy_init(dwc->usb3_phy); 23957303488SKishon Vijay Abraham I ret = phy_init(dwc->usb2_generic_phy); 24057303488SKishon Vijay Abraham I if (ret < 0) 24157303488SKishon Vijay Abraham I return ret; 24257303488SKishon Vijay Abraham I 24357303488SKishon Vijay Abraham I ret = phy_init(dwc->usb3_generic_phy); 24457303488SKishon Vijay Abraham I if (ret < 0) { 24557303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 24657303488SKishon Vijay Abraham I return ret; 24757303488SKishon Vijay Abraham I } 24872246da4SFelipe Balbi 249f59dcab1SFelipe Balbi /* 250f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 251f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 252f59dcab1SFelipe Balbi * host-only mode, then we can return early. 253f59dcab1SFelipe Balbi */ 254c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 25557303488SKishon Vijay Abraham I return 0; 256f59dcab1SFelipe Balbi 257f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 258f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 259f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 260f59dcab1SFelipe Balbi 2614749e0e6SThinh Nguyen /* 2624749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2634749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2644749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2654749e0e6SThinh Nguyen * for 10 times instead. 2664749e0e6SThinh Nguyen */ 2674749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A) 2684749e0e6SThinh Nguyen retries = 10; 2694749e0e6SThinh Nguyen 270f59dcab1SFelipe Balbi do { 271f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 272f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 273fab38333SThinh Nguyen goto done; 274f59dcab1SFelipe Balbi 2754749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && 2764749e0e6SThinh Nguyen dwc->revision >= DWC3_USB31_REVISION_190A) 2774749e0e6SThinh Nguyen msleep(20); 2784749e0e6SThinh Nguyen else 279f59dcab1SFelipe Balbi udelay(1); 280f59dcab1SFelipe Balbi } while (--retries); 281f59dcab1SFelipe Balbi 28200b42170SBrian Norris phy_exit(dwc->usb3_generic_phy); 28300b42170SBrian Norris phy_exit(dwc->usb2_generic_phy); 28400b42170SBrian Norris 285f59dcab1SFelipe Balbi return -ETIMEDOUT; 286fab38333SThinh Nguyen 287fab38333SThinh Nguyen done: 288fab38333SThinh Nguyen /* 2894749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 2904749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 2914749e0e6SThinh Nguyen * domain (synchronization delay). 292fab38333SThinh Nguyen */ 2934749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A) 294fab38333SThinh Nguyen msleep(50); 295fab38333SThinh Nguyen 296fab38333SThinh Nguyen return 0; 29772246da4SFelipe Balbi } 29872246da4SFelipe Balbi 299db2be4e9SNikhil Badola /* 300db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 301db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 302db2be4e9SNikhil Badola */ 303bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 304db2be4e9SNikhil Badola { 305db2be4e9SNikhil Badola u32 reg; 306db2be4e9SNikhil Badola u32 dft; 307db2be4e9SNikhil Badola 308db2be4e9SNikhil Badola if (dwc->revision < DWC3_REVISION_250A) 309db2be4e9SNikhil Badola return; 310db2be4e9SNikhil Badola 311bcdb3272SFelipe Balbi if (dwc->fladj == 0) 312db2be4e9SNikhil Badola return; 313db2be4e9SNikhil Badola 314db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 315db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 316a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 317db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 318bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 319db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 320db2be4e9SNikhil Badola } 321db2be4e9SNikhil Badola } 322db2be4e9SNikhil Badola 323c5cc74e8SHeikki Krogerus /** 32472246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 32572246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 32672246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 32772246da4SFelipe Balbi */ 32872246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 32972246da4SFelipe Balbi struct dwc3_event_buffer *evt) 33072246da4SFelipe Balbi { 331d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 33272246da4SFelipe Balbi } 33372246da4SFelipe Balbi 33472246da4SFelipe Balbi /** 3351d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 33672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 33772246da4SFelipe Balbi * @length: size of the event buffer 33872246da4SFelipe Balbi * 3391d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 34072246da4SFelipe Balbi * otherwise ERR_PTR(errno). 34172246da4SFelipe Balbi */ 34267d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 34367d0b500SFelipe Balbi unsigned length) 34472246da4SFelipe Balbi { 34572246da4SFelipe Balbi struct dwc3_event_buffer *evt; 34672246da4SFelipe Balbi 347380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 34872246da4SFelipe Balbi if (!evt) 34972246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 35072246da4SFelipe Balbi 35172246da4SFelipe Balbi evt->dwc = dwc; 35272246da4SFelipe Balbi evt->length = length; 353d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 354d9fa4c63SJohn Youn if (!evt->cache) 355d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 356d9fa4c63SJohn Youn 357d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 35872246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 359e32672f0SFelipe Balbi if (!evt->buf) 36072246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 36172246da4SFelipe Balbi 36272246da4SFelipe Balbi return evt; 36372246da4SFelipe Balbi } 36472246da4SFelipe Balbi 36572246da4SFelipe Balbi /** 36672246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 36772246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 36872246da4SFelipe Balbi */ 36972246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 37072246da4SFelipe Balbi { 37172246da4SFelipe Balbi struct dwc3_event_buffer *evt; 37272246da4SFelipe Balbi 373696c8b12SFelipe Balbi evt = dwc->ev_buf; 37464b6c8a7SAnton Tikhomirov if (evt) 37572246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 37672246da4SFelipe Balbi } 37772246da4SFelipe Balbi 37872246da4SFelipe Balbi /** 37972246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 3801d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 38172246da4SFelipe Balbi * @length: size of event buffer 38272246da4SFelipe Balbi * 3831d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 38472246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 38572246da4SFelipe Balbi */ 38641ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 38772246da4SFelipe Balbi { 38872246da4SFelipe Balbi struct dwc3_event_buffer *evt; 38972246da4SFelipe Balbi 39072246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 39172246da4SFelipe Balbi if (IS_ERR(evt)) { 39272246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 39372246da4SFelipe Balbi return PTR_ERR(evt); 39472246da4SFelipe Balbi } 395696c8b12SFelipe Balbi dwc->ev_buf = evt; 39672246da4SFelipe Balbi 39772246da4SFelipe Balbi return 0; 39872246da4SFelipe Balbi } 39972246da4SFelipe Balbi 40072246da4SFelipe Balbi /** 40172246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4021d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 40372246da4SFelipe Balbi * 40472246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 40572246da4SFelipe Balbi */ 406f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 40772246da4SFelipe Balbi { 40872246da4SFelipe Balbi struct dwc3_event_buffer *evt; 40972246da4SFelipe Balbi 410696c8b12SFelipe Balbi evt = dwc->ev_buf; 4117acd85e0SPaul Zimmerman evt->lpos = 0; 412660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 41372246da4SFelipe Balbi lower_32_bits(evt->dma)); 414660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 41572246da4SFelipe Balbi upper_32_bits(evt->dma)); 416660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 41768d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 418660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 41972246da4SFelipe Balbi 42072246da4SFelipe Balbi return 0; 42172246da4SFelipe Balbi } 42272246da4SFelipe Balbi 423f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 42472246da4SFelipe Balbi { 42572246da4SFelipe Balbi struct dwc3_event_buffer *evt; 42672246da4SFelipe Balbi 427696c8b12SFelipe Balbi evt = dwc->ev_buf; 4287acd85e0SPaul Zimmerman 4297acd85e0SPaul Zimmerman evt->lpos = 0; 4307acd85e0SPaul Zimmerman 431660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 432660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 433660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 43468d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 435660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 43672246da4SFelipe Balbi } 43772246da4SFelipe Balbi 4380ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 4390ffcaf37SFelipe Balbi { 4400ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4410ffcaf37SFelipe Balbi return 0; 4420ffcaf37SFelipe Balbi 4430ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4440ffcaf37SFelipe Balbi return 0; 4450ffcaf37SFelipe Balbi 4460ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 4470ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 4480ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 4490ffcaf37SFelipe Balbi return -ENOMEM; 4500ffcaf37SFelipe Balbi 4510ffcaf37SFelipe Balbi return 0; 4520ffcaf37SFelipe Balbi } 4530ffcaf37SFelipe Balbi 4540ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 4550ffcaf37SFelipe Balbi { 4560ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 4570ffcaf37SFelipe Balbi u32 param; 4580ffcaf37SFelipe Balbi int ret; 4590ffcaf37SFelipe Balbi 4600ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4610ffcaf37SFelipe Balbi return 0; 4620ffcaf37SFelipe Balbi 4630ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4640ffcaf37SFelipe Balbi return 0; 4650ffcaf37SFelipe Balbi 4660ffcaf37SFelipe Balbi /* should never fall here */ 4670ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 4680ffcaf37SFelipe Balbi return 0; 4690ffcaf37SFelipe Balbi 470d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 4710ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 4720ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 473d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 474d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 4750ffcaf37SFelipe Balbi ret = -EFAULT; 4760ffcaf37SFelipe Balbi goto err0; 4770ffcaf37SFelipe Balbi } 4780ffcaf37SFelipe Balbi 4790ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 4800ffcaf37SFelipe Balbi 4810ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 4820ffcaf37SFelipe Balbi 4830ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4840ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 4850ffcaf37SFelipe Balbi if (ret < 0) 4860ffcaf37SFelipe Balbi goto err1; 4870ffcaf37SFelipe Balbi 4880ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 4890ffcaf37SFelipe Balbi 4900ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4910ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 4920ffcaf37SFelipe Balbi if (ret < 0) 4930ffcaf37SFelipe Balbi goto err1; 4940ffcaf37SFelipe Balbi 4950ffcaf37SFelipe Balbi return 0; 4960ffcaf37SFelipe Balbi 4970ffcaf37SFelipe Balbi err1: 498d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 4990ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5000ffcaf37SFelipe Balbi 5010ffcaf37SFelipe Balbi err0: 5020ffcaf37SFelipe Balbi return ret; 5030ffcaf37SFelipe Balbi } 5040ffcaf37SFelipe Balbi 5050ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5060ffcaf37SFelipe Balbi { 5070ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5080ffcaf37SFelipe Balbi return; 5090ffcaf37SFelipe Balbi 5100ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5110ffcaf37SFelipe Balbi return; 5120ffcaf37SFelipe Balbi 5130ffcaf37SFelipe Balbi /* should never fall here */ 5140ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5150ffcaf37SFelipe Balbi return; 5160ffcaf37SFelipe Balbi 517d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5180ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5190ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 5200ffcaf37SFelipe Balbi } 5210ffcaf37SFelipe Balbi 522789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 523789451f6SFelipe Balbi { 524789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 525789451f6SFelipe Balbi 52647d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 527789451f6SFelipe Balbi } 528789451f6SFelipe Balbi 52941ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 53026ceca97SFelipe Balbi { 53126ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 53226ceca97SFelipe Balbi 53326ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 53426ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 53526ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 53626ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 53726ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 53826ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 53926ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 54026ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 54126ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 54226ceca97SFelipe Balbi } 54326ceca97SFelipe Balbi 54498112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 54598112041SRoger Quadros { 54698112041SRoger Quadros int intf; 54798112041SRoger Quadros int ret = 0; 54898112041SRoger Quadros 54998112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 55098112041SRoger Quadros 55198112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 55298112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 55398112041SRoger Quadros dwc->hsphy_interface && 55498112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 55598112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 55698112041SRoger Quadros 55798112041SRoger Quadros return ret; 55898112041SRoger Quadros } 55998112041SRoger Quadros 56072246da4SFelipe Balbi /** 561b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 562b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 56388bc9d19SHeikki Krogerus * 56488bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 56588bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 56688bc9d19SHeikki Krogerus * the core in dwc3_core_init. 567b5a65c40SHuang Rui */ 56888bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 569b5a65c40SHuang Rui { 5709ba3aca8SThinh Nguyen unsigned int hw_mode; 571b5a65c40SHuang Rui u32 reg; 572b5a65c40SHuang Rui 5739ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 5749ba3aca8SThinh Nguyen 575b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 576b5a65c40SHuang Rui 5772164a476SHuang Rui /* 5781966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 5791966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 5801966b865SFelipe Balbi */ 5811966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 5821966b865SFelipe Balbi 5831966b865SFelipe Balbi /* 5842164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 5852164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 5862164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 5872164a476SHuang Rui * to '1' after the core initialization is completed. 5882164a476SHuang Rui */ 5892164a476SHuang Rui if (dwc->revision > DWC3_REVISION_194A) 5902164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 5912164a476SHuang Rui 5929ba3aca8SThinh Nguyen /* 5939ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 5949ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 5959ba3aca8SThinh Nguyen * after device soft-reset during initialization. 5969ba3aca8SThinh Nguyen */ 5979ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 5989ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 5999ba3aca8SThinh Nguyen 600b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 601b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 602b5a65c40SHuang Rui 603e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 604e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 605e58dd357SRajesh Bhagat 606df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 607df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 608df31f5b3SHuang Rui 609a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 610a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 611a2a1d0f5SHuang Rui 61241c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 61341c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 61441c06ffdSHuang Rui 615fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 616fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 617fb67afcaSHuang Rui 61814f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 61914f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 62014f4ac53SHuang Rui 6216b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 6226b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 6236b6a0c9aSHuang Rui 624cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 62559acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 62659acfa20SHuang Rui 62700fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 62800fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 62900fe081dSWilliam Wu 630b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 631b5a65c40SHuang Rui 6322164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 6332164a476SHuang Rui 6343e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 6353e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 6363e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 63743cacb03SFelipe Balbi if (dwc->hsphy_interface && 63843cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 6393e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 64088bc9d19SHeikki Krogerus break; 64143cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 64243cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 6433e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 64488bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 6453e10a2ceSHeikki Krogerus } else { 64688bc9d19SHeikki Krogerus /* Relying on default value. */ 64788bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 6483e10a2ceSHeikki Krogerus break; 6493e10a2ceSHeikki Krogerus } 6503e10a2ceSHeikki Krogerus /* FALLTHROUGH */ 65188bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 65288bc9d19SHeikki Krogerus /* FALLTHROUGH */ 6533e10a2ceSHeikki Krogerus default: 6543e10a2ceSHeikki Krogerus break; 6553e10a2ceSHeikki Krogerus } 6563e10a2ceSHeikki Krogerus 65732f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 65832f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 65932f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 66032f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66132f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 66232f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 66332f2ed86SWilliam Wu break; 66432f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 66532f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 66632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66732f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 66832f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 66932f2ed86SWilliam Wu break; 67032f2ed86SWilliam Wu default: 67132f2ed86SWilliam Wu break; 67232f2ed86SWilliam Wu } 67332f2ed86SWilliam Wu 6742164a476SHuang Rui /* 6752164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 6762164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 6772164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 6782164a476SHuang Rui * '1' after the core initialization is completed. 6792164a476SHuang Rui */ 6802164a476SHuang Rui if (dwc->revision > DWC3_REVISION_194A) 6812164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 6822164a476SHuang Rui 6839ba3aca8SThinh Nguyen /* 6849ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 6859ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6869ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6879ba3aca8SThinh Nguyen */ 6889ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6899ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6909ba3aca8SThinh Nguyen 691cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 6920effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6930effe0a3SHuang Rui 694ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 695ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 696eafeacf1SThinh Nguyen else 697eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 698ec791d14SJohn Youn 69916199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 70016199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 70116199f33SWilliam Wu 7022164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 70388bc9d19SHeikki Krogerus 70488bc9d19SHeikki Krogerus return 0; 705b5a65c40SHuang Rui } 706b5a65c40SHuang Rui 707c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 708c499ff71SFelipe Balbi { 709c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 710c499ff71SFelipe Balbi 711c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 712c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 713c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 714c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 715c499ff71SFelipe Balbi 716c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 717c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 718c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 719c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 720240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 721fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 722c499ff71SFelipe Balbi } 723c499ff71SFelipe Balbi 7240759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 72572246da4SFelipe Balbi { 72672246da4SFelipe Balbi u32 reg; 72772246da4SFelipe Balbi 7287650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 7290759956fSFelipe Balbi 7307650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 731690fb371SJohn Youn if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 732690fb371SJohn Youn /* Detected DWC_usb3 IP */ 733690fb371SJohn Youn dwc->revision = reg; 734690fb371SJohn Youn } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 735690fb371SJohn Youn /* Detected DWC_usb31 IP */ 736690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 737690fb371SJohn Youn dwc->revision |= DWC3_REVISION_IS_DWC31; 738475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 739690fb371SJohn Youn } else { 7400759956fSFelipe Balbi return false; 7417650bd74SSebastian Andrzej Siewior } 7427650bd74SSebastian Andrzej Siewior 7430759956fSFelipe Balbi return true; 7440e1e5c47SPaul Zimmerman } 7450e1e5c47SPaul Zimmerman 746941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 74772246da4SFelipe Balbi { 74872246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 74972246da4SFelipe Balbi u32 reg; 750c499ff71SFelipe Balbi 7514878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 7523e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 7534878a028SSebastian Andrzej Siewior 754164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 7554878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 75632a4a135SFelipe Balbi /** 75732a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 75832a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 75932a4a135SFelipe Balbi * 76032a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 76132a4a135SFelipe Balbi * configurations. 76232a4a135SFelipe Balbi * 76332a4a135SFelipe Balbi * Refers to: 76432a4a135SFelipe Balbi * 76532a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 76632a4a135SFelipe Balbi * SOF/ITP Mode Used 76732a4a135SFelipe Balbi */ 76832a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 76932a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 77032a4a135SFelipe Balbi (dwc->revision >= DWC3_REVISION_210A && 77132a4a135SFelipe Balbi dwc->revision <= DWC3_REVISION_250A)) 77232a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 77332a4a135SFelipe Balbi else 7744878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 7754878a028SSebastian Andrzej Siewior break; 7760ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 7770ffcaf37SFelipe Balbi /* enable hibernation here */ 7780ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 7792eac3992SHuang Rui 7802eac3992SHuang Rui /* 7812eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 7822eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 7832eac3992SHuang Rui */ 7842eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 7850ffcaf37SFelipe Balbi break; 7864878a028SSebastian Andrzej Siewior default: 7875eb30cedSFelipe Balbi /* nothing */ 7885eb30cedSFelipe Balbi break; 7894878a028SSebastian Andrzej Siewior } 7904878a028SSebastian Andrzej Siewior 791946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 792946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 7936af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 794946bd579SHuang Rui dwc->is_fpga = true; 795946bd579SHuang Rui } 796946bd579SHuang Rui 7973b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 7983b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 7993b81221aSHuang Rui 8003b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 8013b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 8023b81221aSHuang Rui else 8033b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 8043b81221aSHuang Rui 8059a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 8069a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 8079a5b2f31SHuang Rui 8084878a028SSebastian Andrzej Siewior /* 8094878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 8101d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 8114878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 8121d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 8134878a028SSebastian Andrzej Siewior */ 8144878a028SSebastian Andrzej Siewior if (dwc->revision < DWC3_REVISION_190A) 8154878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 8164878a028SSebastian Andrzej Siewior 8174878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 818941f918eSFelipe Balbi } 8194878a028SSebastian Andrzej Siewior 820f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 82198112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 822f54edb53SFelipe Balbi 823d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 824d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 825d9612c2fSPengbo Mu { 826d9612c2fSPengbo Mu struct device *dev = dwc->dev; 827d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 828d9612c2fSPengbo Mu bool incrx_mode; 829d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 830d9612c2fSPengbo Mu u32 incrx_size; 831d9612c2fSPengbo Mu u32 *vals; 832d9612c2fSPengbo Mu u32 cfg; 833d9612c2fSPengbo Mu int ntype; 834d9612c2fSPengbo Mu int ret; 835d9612c2fSPengbo Mu int i; 836d9612c2fSPengbo Mu 837d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 838d9612c2fSPengbo Mu 839d9612c2fSPengbo Mu /* 840d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 841d9612c2fSPengbo Mu * Get the number of value from this property: 842d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 843d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 844d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 845d9612c2fSPengbo Mu */ 846a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 847d9612c2fSPengbo Mu if (ntype <= 0) 848d9612c2fSPengbo Mu return; 849d9612c2fSPengbo Mu 850d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 851d9612c2fSPengbo Mu if (!vals) { 852d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 853d9612c2fSPengbo Mu return; 854d9612c2fSPengbo Mu } 855d9612c2fSPengbo Mu 856d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 857d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 858d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 859d9612c2fSPengbo Mu if (ret) { 86075ecb9ddSAndy Shevchenko kfree(vals); 861d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 862d9612c2fSPengbo Mu return; 863d9612c2fSPengbo Mu } 864d9612c2fSPengbo Mu 865d9612c2fSPengbo Mu incrx_size = *vals; 866d9612c2fSPengbo Mu 867d9612c2fSPengbo Mu if (ntype > 1) { 868d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 869d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 870d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 871d9612c2fSPengbo Mu if (vals[i] > incrx_size) 872d9612c2fSPengbo Mu incrx_size = vals[i]; 873d9612c2fSPengbo Mu } 874d9612c2fSPengbo Mu } else { 875d9612c2fSPengbo Mu /* INCRX burst mode */ 876d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 877d9612c2fSPengbo Mu } 878d9612c2fSPengbo Mu 87975ecb9ddSAndy Shevchenko kfree(vals); 88075ecb9ddSAndy Shevchenko 881d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 882d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 883d9612c2fSPengbo Mu if (incrx_mode) 884d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 885d9612c2fSPengbo Mu switch (incrx_size) { 886d9612c2fSPengbo Mu case 256: 887d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 888d9612c2fSPengbo Mu break; 889d9612c2fSPengbo Mu case 128: 890d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 891d9612c2fSPengbo Mu break; 892d9612c2fSPengbo Mu case 64: 893d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 894d9612c2fSPengbo Mu break; 895d9612c2fSPengbo Mu case 32: 896d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 897d9612c2fSPengbo Mu break; 898d9612c2fSPengbo Mu case 16: 899d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 900d9612c2fSPengbo Mu break; 901d9612c2fSPengbo Mu case 8: 902d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 903d9612c2fSPengbo Mu break; 904d9612c2fSPengbo Mu case 4: 905d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 906d9612c2fSPengbo Mu break; 907d9612c2fSPengbo Mu case 1: 908d9612c2fSPengbo Mu break; 909d9612c2fSPengbo Mu default: 910d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 911d9612c2fSPengbo Mu break; 912d9612c2fSPengbo Mu } 913d9612c2fSPengbo Mu 914d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 915d9612c2fSPengbo Mu } 916d9612c2fSPengbo Mu 917941f918eSFelipe Balbi /** 918941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 919941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 920941f918eSFelipe Balbi * 921941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 922941f918eSFelipe Balbi */ 923941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 924941f918eSFelipe Balbi { 9259ba3aca8SThinh Nguyen unsigned int hw_mode; 926941f918eSFelipe Balbi u32 reg; 927941f918eSFelipe Balbi int ret; 928941f918eSFelipe Balbi 9299ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 9309ba3aca8SThinh Nguyen 931941f918eSFelipe Balbi /* 932941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 933941f918eSFelipe Balbi * out which kernel version a bug was found. 934941f918eSFelipe Balbi */ 935941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 936941f918eSFelipe Balbi 937941f918eSFelipe Balbi /* Handle USB2.0-only core configuration */ 938941f918eSFelipe Balbi if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 939941f918eSFelipe Balbi DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 940941f918eSFelipe Balbi if (dwc->maximum_speed == USB_SPEED_SUPER) 941941f918eSFelipe Balbi dwc->maximum_speed = USB_SPEED_HIGH; 942941f918eSFelipe Balbi } 943941f918eSFelipe Balbi 944941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 945941f918eSFelipe Balbi if (ret) 946941f918eSFelipe Balbi goto err0; 947941f918eSFelipe Balbi 94898112041SRoger Quadros if (!dwc->ulpi_ready) { 94998112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 95098112041SRoger Quadros if (ret) 95198112041SRoger Quadros goto err0; 95298112041SRoger Quadros dwc->ulpi_ready = true; 95398112041SRoger Quadros } 95498112041SRoger Quadros 95598112041SRoger Quadros if (!dwc->phys_ready) { 95698112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 95798112041SRoger Quadros if (ret) 95898112041SRoger Quadros goto err0a; 95998112041SRoger Quadros dwc->phys_ready = true; 96098112041SRoger Quadros } 96198112041SRoger Quadros 96298112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 96398112041SRoger Quadros if (ret) 96498112041SRoger Quadros goto err0a; 96598112041SRoger Quadros 9669ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 9679ba3aca8SThinh Nguyen dwc->revision > DWC3_REVISION_194A) { 9689ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 9699ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 9709ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 9719ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 9729ba3aca8SThinh Nguyen } 9739ba3aca8SThinh Nguyen 9749ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 9759ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 9769ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 9779ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 9789ba3aca8SThinh Nguyen } 9799ba3aca8SThinh Nguyen } 9809ba3aca8SThinh Nguyen 981941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 982c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 9830ffcaf37SFelipe Balbi 9840ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 9850ffcaf37SFelipe Balbi if (ret) 986c499ff71SFelipe Balbi goto err1; 987c499ff71SFelipe Balbi 988c499ff71SFelipe Balbi /* Adjust Frame Length */ 989c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 990c499ff71SFelipe Balbi 991d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 992d9612c2fSPengbo Mu 993c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 994c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 995c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 996c499ff71SFelipe Balbi if (ret < 0) 9970ffcaf37SFelipe Balbi goto err2; 9980ffcaf37SFelipe Balbi 999c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1000c499ff71SFelipe Balbi if (ret < 0) 1001c499ff71SFelipe Balbi goto err3; 1002c499ff71SFelipe Balbi 1003c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1004c499ff71SFelipe Balbi if (ret) { 1005c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1006c499ff71SFelipe Balbi goto err4; 1007c499ff71SFelipe Balbi } 1008c499ff71SFelipe Balbi 100906281d46SJohn Youn /* 101006281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 101106281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 101206281d46SJohn Youn * DWC_usb31 controller. 101306281d46SJohn Youn */ 101406281d46SJohn Youn if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 101506281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 101606281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 101706281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 101806281d46SJohn Youn } 101906281d46SJohn Youn 102065db7a0cSWilliam Wu if (dwc->revision >= DWC3_REVISION_250A) { 10210bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 102265db7a0cSWilliam Wu 102365db7a0cSWilliam Wu /* 102465db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 102565db7a0cSWilliam Wu * in HS when the device is in the L1 state. 102665db7a0cSWilliam Wu */ 102765db7a0cSWilliam Wu if (dwc->revision >= DWC3_REVISION_290A) 10280bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 102965db7a0cSWilliam Wu 103065db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 103165db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 103265db7a0cSWilliam Wu 10337ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 10347ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 10357ba6b09fSNeil Armstrong 10360bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 10370bb39ca1SJohn Youn } 10380bb39ca1SJohn Youn 1039b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1040b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1041b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1042b138e23dSAnurag Kumar Vulisha 1043b138e23dSAnurag Kumar Vulisha /* 1044b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1045b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1046b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1047b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1048b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1049b138e23dSAnurag Kumar Vulisha */ 1050b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1051b138e23dSAnurag Kumar Vulisha 1052b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1053b138e23dSAnurag Kumar Vulisha } 1054b138e23dSAnurag Kumar Vulisha 1055938a5ad1SThinh Nguyen /* 1056938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1057938a5ad1SThinh Nguyen * RX and/or TX threshold. 1058938a5ad1SThinh Nguyen */ 1059938a5ad1SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { 1060938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1061938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1062938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1063938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1064938a5ad1SThinh Nguyen 1065938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1066938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1067938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1068938a5ad1SThinh Nguyen 1069938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1070938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1071938a5ad1SThinh Nguyen 1072938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1073938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1074938a5ad1SThinh Nguyen 1075938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1076938a5ad1SThinh Nguyen } 1077938a5ad1SThinh Nguyen 1078938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1079938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1080938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1081938a5ad1SThinh Nguyen 1082938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1083938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1084938a5ad1SThinh Nguyen 1085938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1086938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1087938a5ad1SThinh Nguyen 1088938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1089938a5ad1SThinh Nguyen } 1090938a5ad1SThinh Nguyen } 1091938a5ad1SThinh Nguyen 109272246da4SFelipe Balbi return 0; 109372246da4SFelipe Balbi 1094c499ff71SFelipe Balbi err4: 10959b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1096c499ff71SFelipe Balbi 1097c499ff71SFelipe Balbi err3: 10989b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1099c499ff71SFelipe Balbi 11000ffcaf37SFelipe Balbi err2: 1101c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1102c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 11030ffcaf37SFelipe Balbi 11040ffcaf37SFelipe Balbi err1: 11050ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 11060ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 110757303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 110857303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 11090ffcaf37SFelipe Balbi 111098112041SRoger Quadros err0a: 111198112041SRoger Quadros dwc3_ulpi_exit(dwc); 111298112041SRoger Quadros 111372246da4SFelipe Balbi err0: 111472246da4SFelipe Balbi return ret; 111572246da4SFelipe Balbi } 111672246da4SFelipe Balbi 11173c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 111872246da4SFelipe Balbi { 11193c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1120941ea361SFelipe Balbi struct device_node *node = dev->of_node; 11213c9f94acSFelipe Balbi int ret; 112272246da4SFelipe Balbi 11235088b6f5SKishon Vijay Abraham I if (node) { 11245088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 11255088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1126bb674907SFelipe Balbi } else { 1127bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1128bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 11295088b6f5SKishon Vijay Abraham I } 11305088b6f5SKishon Vijay Abraham I 1131d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1132d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1133122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1134122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1135122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1136d105e7f8SFelipe Balbi return ret; 1137122f06e6SKishon Vijay Abraham I } else { 113851e1e7bcSFelipe Balbi dev_err(dev, "no usb2 phy configured\n"); 1139122f06e6SKishon Vijay Abraham I return ret; 1140122f06e6SKishon Vijay Abraham I } 114151e1e7bcSFelipe Balbi } 114251e1e7bcSFelipe Balbi 1143d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1144315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1145122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1146122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1147122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1148d105e7f8SFelipe Balbi return ret; 1149122f06e6SKishon Vijay Abraham I } else { 115051e1e7bcSFelipe Balbi dev_err(dev, "no usb3 phy configured\n"); 1151122f06e6SKishon Vijay Abraham I return ret; 1152122f06e6SKishon Vijay Abraham I } 115351e1e7bcSFelipe Balbi } 115451e1e7bcSFelipe Balbi 115557303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 115657303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 115757303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 115857303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 115957303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 116057303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 116157303488SKishon Vijay Abraham I return ret; 116257303488SKishon Vijay Abraham I } else { 116357303488SKishon Vijay Abraham I dev_err(dev, "no usb2 phy configured\n"); 116457303488SKishon Vijay Abraham I return ret; 116557303488SKishon Vijay Abraham I } 116657303488SKishon Vijay Abraham I } 116757303488SKishon Vijay Abraham I 116857303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 116957303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 117057303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 117157303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 117257303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 117357303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 117457303488SKishon Vijay Abraham I return ret; 117557303488SKishon Vijay Abraham I } else { 117657303488SKishon Vijay Abraham I dev_err(dev, "no usb3 phy configured\n"); 117757303488SKishon Vijay Abraham I return ret; 117857303488SKishon Vijay Abraham I } 117957303488SKishon Vijay Abraham I } 118057303488SKishon Vijay Abraham I 11813c9f94acSFelipe Balbi return 0; 11823c9f94acSFelipe Balbi } 11833c9f94acSFelipe Balbi 11845f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 11855f94adfeSFelipe Balbi { 11865f94adfeSFelipe Balbi struct device *dev = dwc->dev; 11875f94adfeSFelipe Balbi int ret; 11885f94adfeSFelipe Balbi 11895f94adfeSFelipe Balbi switch (dwc->dr_mode) { 11905f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 119141ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1192958d1a4cSFelipe Balbi 1193958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1194958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1195958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1196644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1197958d1a4cSFelipe Balbi 11985f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 11995f94adfeSFelipe Balbi if (ret) { 12009522def4SRoger Quadros if (ret != -EPROBE_DEFER) 12015f94adfeSFelipe Balbi dev_err(dev, "failed to initialize gadget\n"); 12025f94adfeSFelipe Balbi return ret; 12035f94adfeSFelipe Balbi } 12045f94adfeSFelipe Balbi break; 12055f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 120641ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1207958d1a4cSFelipe Balbi 1208958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1209958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1210958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1211644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1212958d1a4cSFelipe Balbi 12135f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 12145f94adfeSFelipe Balbi if (ret) { 12159522def4SRoger Quadros if (ret != -EPROBE_DEFER) 12165f94adfeSFelipe Balbi dev_err(dev, "failed to initialize host\n"); 12175f94adfeSFelipe Balbi return ret; 12185f94adfeSFelipe Balbi } 12195f94adfeSFelipe Balbi break; 12205f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 122141ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 12229840354fSRoger Quadros ret = dwc3_drd_init(dwc); 12239840354fSRoger Quadros if (ret) { 12249840354fSRoger Quadros if (ret != -EPROBE_DEFER) 12259840354fSRoger Quadros dev_err(dev, "failed to initialize dual-role\n"); 12269840354fSRoger Quadros return ret; 12279840354fSRoger Quadros } 12285f94adfeSFelipe Balbi break; 12295f94adfeSFelipe Balbi default: 12305f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 12315f94adfeSFelipe Balbi return -EINVAL; 12325f94adfeSFelipe Balbi } 12335f94adfeSFelipe Balbi 12345f94adfeSFelipe Balbi return 0; 12355f94adfeSFelipe Balbi } 12365f94adfeSFelipe Balbi 12375f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 12385f94adfeSFelipe Balbi { 12395f94adfeSFelipe Balbi switch (dwc->dr_mode) { 12405f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 12415f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 12425f94adfeSFelipe Balbi break; 12435f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 12445f94adfeSFelipe Balbi dwc3_host_exit(dwc); 12455f94adfeSFelipe Balbi break; 12465f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 12479840354fSRoger Quadros dwc3_drd_exit(dwc); 12485f94adfeSFelipe Balbi break; 12495f94adfeSFelipe Balbi default: 12505f94adfeSFelipe Balbi /* do nothing */ 12515f94adfeSFelipe Balbi break; 12525f94adfeSFelipe Balbi } 125309ed259fSBin Liu 125409ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 125509ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 12565f94adfeSFelipe Balbi } 12575f94adfeSFelipe Balbi 1258c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 12593c9f94acSFelipe Balbi { 1260c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 126180caf7d2SHuang Rui u8 lpm_nyet_threshold; 12626b6a0c9aSHuang Rui u8 tx_de_emphasis; 1263460d098cSHuang Rui u8 hird_threshold; 1264938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1265938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1266938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1267938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 12683c9f94acSFelipe Balbi 126980caf7d2SHuang Rui /* default to highest possible threshold */ 12708d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 127180caf7d2SHuang Rui 12726b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 12736b6a0c9aSHuang Rui tx_de_emphasis = 1; 12746b6a0c9aSHuang Rui 1275460d098cSHuang Rui /* 1276460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1277460d098cSHuang Rui * threshold value of 0b1100 1278460d098cSHuang Rui */ 1279460d098cSHuang Rui hird_threshold = 12; 1280460d098cSHuang Rui 128163863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 128206e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 128332f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 128463863b98SHeikki Krogerus 1285d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1286d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1287d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1288d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1289d64ff406SArnd Bergmann else 1290d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1291d64ff406SArnd Bergmann 12923d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 129380caf7d2SHuang Rui "snps,has-lpm-erratum"); 12943d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 129580caf7d2SHuang Rui &lpm_nyet_threshold); 12963d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1297460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 12983d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1299460d098cSHuang Rui &hird_threshold); 1300d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1301d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 13023d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1303eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1304022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1305022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1306938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1307938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1308938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1309938a5ad1SThinh Nguyen &rx_max_burst_prd); 1310938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1311938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1312938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1313938a5ad1SThinh Nguyen &tx_max_burst_prd); 13143c9f94acSFelipe Balbi 13153d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 13163b81221aSHuang Rui "snps,disable_scramble_quirk"); 13173d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 13189a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 13193d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1320b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 13213d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1322df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 13233d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1324a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 13253d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 132641c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 13273d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1328fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 13293d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 133014f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 13313d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 133259acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 13333d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 13340effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1335ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1336ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1337729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1338729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1339729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1340729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1341e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1342e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 134316199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 134416199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 134500fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 134600fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 134765db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 134865db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 13497ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 13507ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 13516b6a0c9aSHuang Rui 13523d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 13536b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 13543d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 13556b6a0c9aSHuang Rui &tx_de_emphasis); 13563d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 13573e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 13583d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1359bcdb3272SFelipe Balbi &dwc->fladj); 13603d128919SHeikki Krogerus 136142bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 136242bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 136342bf02ecSRoger Quadros 136480caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 13656b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 136680caf7d2SHuang Rui 136716fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1368460d098cSHuang Rui 1369938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1370938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1371938a5ad1SThinh Nguyen 1372938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1373938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1374938a5ad1SThinh Nguyen 1375cf40b86bSJohn Youn dwc->imod_interval = 0; 1376cf40b86bSJohn Youn } 1377cf40b86bSJohn Youn 1378cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1379cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1380cf40b86bSJohn Youn { 1381cf40b86bSJohn Youn return ((dwc3_is_usb3(dwc) && 1382cf40b86bSJohn Youn dwc->revision >= DWC3_REVISION_300A) || 1383cf40b86bSJohn Youn (dwc3_is_usb31(dwc) && 1384cf40b86bSJohn Youn dwc->revision >= DWC3_USB31_REVISION_120A)); 1385c5ac6116SFelipe Balbi } 1386c5ac6116SFelipe Balbi 13877ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 13887ac51a12SJohn Youn { 13897ac51a12SJohn Youn struct device *dev = dwc->dev; 13907ac51a12SJohn Youn 1391cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1392cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1393cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1394cf40b86bSJohn Youn dwc->imod_interval = 0; 1395cf40b86bSJohn Youn } 1396cf40b86bSJohn Youn 139728632b44SJohn Youn /* 139828632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 139928632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 140028632b44SJohn Youn * interrupt from being masked while handling events. IMOD 140128632b44SJohn Youn * allows us to work around this issue. Enable it for the 140228632b44SJohn Youn * affected version. 140328632b44SJohn Youn */ 140428632b44SJohn Youn if (!dwc->imod_interval && 140528632b44SJohn Youn (dwc->revision == DWC3_REVISION_300A)) 140628632b44SJohn Youn dwc->imod_interval = 1; 140728632b44SJohn Youn 14087ac51a12SJohn Youn /* Check the maximum_speed parameter */ 14097ac51a12SJohn Youn switch (dwc->maximum_speed) { 14107ac51a12SJohn Youn case USB_SPEED_LOW: 14117ac51a12SJohn Youn case USB_SPEED_FULL: 14127ac51a12SJohn Youn case USB_SPEED_HIGH: 14137ac51a12SJohn Youn case USB_SPEED_SUPER: 14147ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 14157ac51a12SJohn Youn break; 14167ac51a12SJohn Youn default: 14177ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 14187ac51a12SJohn Youn dwc->maximum_speed); 14197ac51a12SJohn Youn /* fall through */ 14207ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 14217ac51a12SJohn Youn /* default to superspeed */ 14227ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER; 14237ac51a12SJohn Youn 14247ac51a12SJohn Youn /* 14257ac51a12SJohn Youn * default to superspeed plus if we are capable. 14267ac51a12SJohn Youn */ 14277ac51a12SJohn Youn if (dwc3_is_usb31(dwc) && 14287ac51a12SJohn Youn (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 14297ac51a12SJohn Youn DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 14307ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 14317ac51a12SJohn Youn 14327ac51a12SJohn Youn break; 14337ac51a12SJohn Youn } 14347ac51a12SJohn Youn } 14357ac51a12SJohn Youn 1436c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1437c5ac6116SFelipe Balbi { 1438c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 143944feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1440c5ac6116SFelipe Balbi struct dwc3 *dwc; 1441c5ac6116SFelipe Balbi 1442c5ac6116SFelipe Balbi int ret; 1443c5ac6116SFelipe Balbi 1444c5ac6116SFelipe Balbi void __iomem *regs; 1445c5ac6116SFelipe Balbi 1446c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1447c5ac6116SFelipe Balbi if (!dwc) 1448c5ac6116SFelipe Balbi return -ENOMEM; 1449c5ac6116SFelipe Balbi 1450c5ac6116SFelipe Balbi dwc->dev = dev; 1451c5ac6116SFelipe Balbi 1452c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1453c5ac6116SFelipe Balbi if (!res) { 1454c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1455c5ac6116SFelipe Balbi return -ENODEV; 1456c5ac6116SFelipe Balbi } 1457c5ac6116SFelipe Balbi 1458c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1459c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1460c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1461c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1462c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1463c5ac6116SFelipe Balbi 1464c5ac6116SFelipe Balbi /* 1465c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1466c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1467c5ac6116SFelipe Balbi */ 146844feb8e6SMasahiro Yamada dwc_res = *res; 146944feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 147044feb8e6SMasahiro Yamada 147144feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 147244feb8e6SMasahiro Yamada if (IS_ERR(regs)) 147344feb8e6SMasahiro Yamada return PTR_ERR(regs); 1474c5ac6116SFelipe Balbi 1475c5ac6116SFelipe Balbi dwc->regs = regs; 147644feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1477c5ac6116SFelipe Balbi 1478c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1479c5ac6116SFelipe Balbi 14804a1d042aSJohn Stultz dwc->reset = devm_reset_control_array_get(dev, true, true); 1481fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1482fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1483fe8abf33SMasahiro Yamada 148461527777SHans de Goede if (dev->of_node) { 14850d3a9708SJohn Stultz ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1486fe8abf33SMasahiro Yamada if (ret == -EPROBE_DEFER) 1487fe8abf33SMasahiro Yamada return ret; 1488fe8abf33SMasahiro Yamada /* 148961527777SHans de Goede * Clocks are optional, but new DT platforms should support all 149061527777SHans de Goede * clocks as required by the DT-binding. 1491fe8abf33SMasahiro Yamada */ 14920d3a9708SJohn Stultz if (ret < 0) 1493fe8abf33SMasahiro Yamada dwc->num_clks = 0; 14940d3a9708SJohn Stultz else 14950d3a9708SJohn Stultz dwc->num_clks = ret; 14960d3a9708SJohn Stultz 149761527777SHans de Goede } 1498fe8abf33SMasahiro Yamada 1499fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1500fe8abf33SMasahiro Yamada if (ret) 150103bf32bbSAndrey Smirnov return ret; 1502fe8abf33SMasahiro Yamada 1503240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1504fe8abf33SMasahiro Yamada if (ret) 1505fe8abf33SMasahiro Yamada goto assert_reset; 1506fe8abf33SMasahiro Yamada 1507dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1508dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1509dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1510dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1511dc1b5d9aSEnric Balletbo i Serra } 1512dc1b5d9aSEnric Balletbo i Serra 15136c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 15142917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 15156c89cce0SHeikki Krogerus 151672246da4SFelipe Balbi spin_lock_init(&dwc->lock); 151772246da4SFelipe Balbi 1518fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1519fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1520fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1521802ca850SChanho Park pm_runtime_enable(dev); 152232808237SRoger Quadros ret = pm_runtime_get_sync(dev); 152332808237SRoger Quadros if (ret < 0) 152432808237SRoger Quadros goto err1; 152532808237SRoger Quadros 1526802ca850SChanho Park pm_runtime_forbid(dev); 152772246da4SFelipe Balbi 15283921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 15293921426bSFelipe Balbi if (ret) { 15303921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 15313921426bSFelipe Balbi ret = -ENOMEM; 153232808237SRoger Quadros goto err2; 15333921426bSFelipe Balbi } 15343921426bSFelipe Balbi 15359d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 15369d6173e1SThinh Nguyen if (ret) 15379d6173e1SThinh Nguyen goto err3; 153832a4a135SFelipe Balbi 1539c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1540c499ff71SFelipe Balbi if (ret) 154132808237SRoger Quadros goto err3; 1542c499ff71SFelipe Balbi 154372246da4SFelipe Balbi ret = dwc3_core_init(dwc); 154472246da4SFelipe Balbi if (ret) { 1545408d3ba0SBrian Norris if (ret != -EPROBE_DEFER) 1546408d3ba0SBrian Norris dev_err(dev, "failed to initialize core: %d\n", ret); 154732808237SRoger Quadros goto err4; 154872246da4SFelipe Balbi } 154972246da4SFelipe Balbi 15507ac51a12SJohn Youn dwc3_check_params(dwc); 15512c7f1bd9SJohn Youn 15525f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 15535f94adfeSFelipe Balbi if (ret) 155432808237SRoger Quadros goto err5; 155572246da4SFelipe Balbi 15564e9f3118SDu, Changbin dwc3_debugfs_init(dwc); 1557fc8bb91bSFelipe Balbi pm_runtime_put(dev); 155872246da4SFelipe Balbi 155972246da4SFelipe Balbi return 0; 156072246da4SFelipe Balbi 156132808237SRoger Quadros err5: 1562f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 156308fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1564f122d33eSFelipe Balbi 156532808237SRoger Quadros err4: 1566c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 156772246da4SFelipe Balbi 156832808237SRoger Quadros err3: 15693921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 15703921426bSFelipe Balbi 157132808237SRoger Quadros err2: 157232808237SRoger Quadros pm_runtime_allow(&pdev->dev); 157332808237SRoger Quadros 157432808237SRoger Quadros err1: 157532808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 157632808237SRoger Quadros pm_runtime_disable(&pdev->dev); 157732808237SRoger Quadros 1578dc1b5d9aSEnric Balletbo i Serra disable_clks: 1579240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1580fe8abf33SMasahiro Yamada assert_reset: 1581fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1582fe8abf33SMasahiro Yamada 158372246da4SFelipe Balbi return ret; 158472246da4SFelipe Balbi } 158572246da4SFelipe Balbi 1586fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 158772246da4SFelipe Balbi { 158872246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 15893da1f6eeSFelipe Balbi 1590fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 159172246da4SFelipe Balbi 1592dc99f16fSFelipe Balbi dwc3_debugfs_exit(dwc); 1593dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 15948ba007a9SKishon Vijay Abraham I 159572246da4SFelipe Balbi dwc3_core_exit(dwc); 159688bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 159772246da4SFelipe Balbi 1598fc8bb91bSFelipe Balbi pm_runtime_put_sync(&pdev->dev); 1599fc8bb91bSFelipe Balbi pm_runtime_allow(&pdev->dev); 1600fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1601fc8bb91bSFelipe Balbi 1602c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1603c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1604c499ff71SFelipe Balbi 160572246da4SFelipe Balbi return 0; 160672246da4SFelipe Balbi } 160772246da4SFelipe Balbi 1608fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1609fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1610fe8abf33SMasahiro Yamada { 1611fe8abf33SMasahiro Yamada int ret; 1612fe8abf33SMasahiro Yamada 1613fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1614fe8abf33SMasahiro Yamada if (ret) 1615fe8abf33SMasahiro Yamada return ret; 1616fe8abf33SMasahiro Yamada 1617240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1618fe8abf33SMasahiro Yamada if (ret) 1619fe8abf33SMasahiro Yamada goto assert_reset; 1620fe8abf33SMasahiro Yamada 1621fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1622fe8abf33SMasahiro Yamada if (ret) 1623fe8abf33SMasahiro Yamada goto disable_clks; 1624fe8abf33SMasahiro Yamada 1625fe8abf33SMasahiro Yamada return 0; 1626fe8abf33SMasahiro Yamada 1627fe8abf33SMasahiro Yamada disable_clks: 1628240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1629fe8abf33SMasahiro Yamada assert_reset: 1630fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1631fe8abf33SMasahiro Yamada 1632fe8abf33SMasahiro Yamada return ret; 1633fe8abf33SMasahiro Yamada } 1634fe8abf33SMasahiro Yamada 1635c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 16367415f17cSFelipe Balbi { 1637fc8bb91bSFelipe Balbi unsigned long flags; 1638bcb12877SManu Gautam u32 reg; 16397415f17cSFelipe Balbi 1640689bf72cSManu Gautam switch (dwc->current_dr_role) { 1641689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 16420227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 16430227cc84SLi Jun break; 1644fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 16457415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1646fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 164741a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1648689bf72cSManu Gautam dwc3_core_exit(dwc); 164951f5d49aSFelipe Balbi break; 1650689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1651bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1652c4a5153eSManu Gautam dwc3_core_exit(dwc); 1653c4a5153eSManu Gautam break; 1654bcb12877SManu Gautam } 1655bcb12877SManu Gautam 1656bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1657bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1658bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1659bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1660bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1661bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1662bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1663bcb12877SManu Gautam 1664bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1665bcb12877SManu Gautam usleep_range(5000, 6000); 1666bcb12877SManu Gautam } 1667bcb12877SManu Gautam 1668bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1669bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1670bcb12877SManu Gautam break; 1671f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1672f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1673f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1674f09cc79bSRoger Quadros break; 1675f09cc79bSRoger Quadros 1676f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1677f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1678f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1679f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 168041a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1681f09cc79bSRoger Quadros } 1682f09cc79bSRoger Quadros 1683f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1684f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1685f09cc79bSRoger Quadros break; 16867415f17cSFelipe Balbi default: 168751f5d49aSFelipe Balbi /* do nothing */ 16887415f17cSFelipe Balbi break; 16897415f17cSFelipe Balbi } 16907415f17cSFelipe Balbi 1691fc8bb91bSFelipe Balbi return 0; 1692fc8bb91bSFelipe Balbi } 1693fc8bb91bSFelipe Balbi 1694c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1695fc8bb91bSFelipe Balbi { 1696fc8bb91bSFelipe Balbi unsigned long flags; 1697fc8bb91bSFelipe Balbi int ret; 1698bcb12877SManu Gautam u32 reg; 1699fc8bb91bSFelipe Balbi 1700689bf72cSManu Gautam switch (dwc->current_dr_role) { 1701689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1702fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1703fc8bb91bSFelipe Balbi if (ret) 1704fc8bb91bSFelipe Balbi return ret; 1705fc8bb91bSFelipe Balbi 17067d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1707fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1708fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1709fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1710689bf72cSManu Gautam break; 1711689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1712c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1713fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1714c4a5153eSManu Gautam if (ret) 1715c4a5153eSManu Gautam return ret; 17167d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1717bcb12877SManu Gautam break; 1718c4a5153eSManu Gautam } 1719bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1720bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1721bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1722bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1723bcb12877SManu Gautam 1724bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1725bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1726bcb12877SManu Gautam 1727bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1728bcb12877SManu Gautam 1729bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1730bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1731c4a5153eSManu Gautam break; 1732f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1733f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1734f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1735f09cc79bSRoger Quadros break; 1736f09cc79bSRoger Quadros 1737f09cc79bSRoger Quadros ret = dwc3_core_init(dwc); 1738f09cc79bSRoger Quadros if (ret) 1739f09cc79bSRoger Quadros return ret; 1740f09cc79bSRoger Quadros 1741f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1742f09cc79bSRoger Quadros 1743f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1744f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1745f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1746f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1747f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1748f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1749f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1750f09cc79bSRoger Quadros } 1751f09cc79bSRoger Quadros 1752f09cc79bSRoger Quadros break; 1753fc8bb91bSFelipe Balbi default: 1754fc8bb91bSFelipe Balbi /* do nothing */ 1755fc8bb91bSFelipe Balbi break; 1756fc8bb91bSFelipe Balbi } 1757fc8bb91bSFelipe Balbi 1758fc8bb91bSFelipe Balbi return 0; 1759fc8bb91bSFelipe Balbi } 1760fc8bb91bSFelipe Balbi 1761fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1762fc8bb91bSFelipe Balbi { 1763689bf72cSManu Gautam switch (dwc->current_dr_role) { 1764c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1765fc8bb91bSFelipe Balbi if (dwc->connected) 1766fc8bb91bSFelipe Balbi return -EBUSY; 1767fc8bb91bSFelipe Balbi break; 1768c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1769fc8bb91bSFelipe Balbi default: 1770fc8bb91bSFelipe Balbi /* do nothing */ 1771fc8bb91bSFelipe Balbi break; 1772fc8bb91bSFelipe Balbi } 1773fc8bb91bSFelipe Balbi 1774fc8bb91bSFelipe Balbi return 0; 1775fc8bb91bSFelipe Balbi } 1776fc8bb91bSFelipe Balbi 1777fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 1778fc8bb91bSFelipe Balbi { 1779fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1780fc8bb91bSFelipe Balbi int ret; 1781fc8bb91bSFelipe Balbi 1782fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1783fc8bb91bSFelipe Balbi return -EBUSY; 1784fc8bb91bSFelipe Balbi 1785c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1786fc8bb91bSFelipe Balbi if (ret) 1787fc8bb91bSFelipe Balbi return ret; 1788fc8bb91bSFelipe Balbi 1789fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 1790fc8bb91bSFelipe Balbi 1791fc8bb91bSFelipe Balbi return 0; 1792fc8bb91bSFelipe Balbi } 1793fc8bb91bSFelipe Balbi 1794fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 1795fc8bb91bSFelipe Balbi { 1796fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1797fc8bb91bSFelipe Balbi int ret; 1798fc8bb91bSFelipe Balbi 1799fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 1800fc8bb91bSFelipe Balbi 1801c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1802fc8bb91bSFelipe Balbi if (ret) 1803fc8bb91bSFelipe Balbi return ret; 1804fc8bb91bSFelipe Balbi 1805689bf72cSManu Gautam switch (dwc->current_dr_role) { 1806689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1807fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 1808fc8bb91bSFelipe Balbi break; 1809689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1810fc8bb91bSFelipe Balbi default: 1811fc8bb91bSFelipe Balbi /* do nothing */ 1812fc8bb91bSFelipe Balbi break; 1813fc8bb91bSFelipe Balbi } 1814fc8bb91bSFelipe Balbi 1815fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1816fc8bb91bSFelipe Balbi 1817fc8bb91bSFelipe Balbi return 0; 1818fc8bb91bSFelipe Balbi } 1819fc8bb91bSFelipe Balbi 1820fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 1821fc8bb91bSFelipe Balbi { 1822fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1823fc8bb91bSFelipe Balbi 1824689bf72cSManu Gautam switch (dwc->current_dr_role) { 1825689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1826fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1827fc8bb91bSFelipe Balbi return -EBUSY; 1828fc8bb91bSFelipe Balbi break; 1829689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1830fc8bb91bSFelipe Balbi default: 1831fc8bb91bSFelipe Balbi /* do nothing */ 1832fc8bb91bSFelipe Balbi break; 1833fc8bb91bSFelipe Balbi } 1834fc8bb91bSFelipe Balbi 1835fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1836fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 1837fc8bb91bSFelipe Balbi 1838fc8bb91bSFelipe Balbi return 0; 1839fc8bb91bSFelipe Balbi } 1840fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 1841fc8bb91bSFelipe Balbi 1842fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 1843fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 1844fc8bb91bSFelipe Balbi { 1845fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1846fc8bb91bSFelipe Balbi int ret; 1847fc8bb91bSFelipe Balbi 1848c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1849fc8bb91bSFelipe Balbi if (ret) 1850fc8bb91bSFelipe Balbi return ret; 1851fc8bb91bSFelipe Balbi 18526344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 18536344475fSSekhar Nori 18547415f17cSFelipe Balbi return 0; 18557415f17cSFelipe Balbi } 18567415f17cSFelipe Balbi 18577415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 18587415f17cSFelipe Balbi { 18597415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 186057303488SKishon Vijay Abraham I int ret; 18617415f17cSFelipe Balbi 18626344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 18636344475fSSekhar Nori 1864c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 186551f5d49aSFelipe Balbi if (ret) 18665c4ad318SFelipe Balbi return ret; 18675c4ad318SFelipe Balbi 18687415f17cSFelipe Balbi pm_runtime_disable(dev); 18697415f17cSFelipe Balbi pm_runtime_set_active(dev); 18707415f17cSFelipe Balbi pm_runtime_enable(dev); 18717415f17cSFelipe Balbi 18727415f17cSFelipe Balbi return 0; 18737415f17cSFelipe Balbi } 18747f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 18757415f17cSFelipe Balbi 18767415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 18777415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1878fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1879fc8bb91bSFelipe Balbi dwc3_runtime_idle) 18807415f17cSFelipe Balbi }; 18817415f17cSFelipe Balbi 18825088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 18835088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 18845088b6f5SKishon Vijay Abraham I { 188522a5aa17SFelipe Balbi .compatible = "snps,dwc3" 188622a5aa17SFelipe Balbi }, 188722a5aa17SFelipe Balbi { 18885088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 18895088b6f5SKishon Vijay Abraham I }, 18905088b6f5SKishon Vijay Abraham I { }, 18915088b6f5SKishon Vijay Abraham I }; 18925088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 18935088b6f5SKishon Vijay Abraham I #endif 18945088b6f5SKishon Vijay Abraham I 1895404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 1896404905a6SHeikki Krogerus 1897404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 1898404905a6SHeikki Krogerus 1899404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 1900404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 1901404905a6SHeikki Krogerus { }, 1902404905a6SHeikki Krogerus }; 1903404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1904404905a6SHeikki Krogerus #endif 1905404905a6SHeikki Krogerus 190672246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 190772246da4SFelipe Balbi .probe = dwc3_probe, 19087690417dSBill Pemberton .remove = dwc3_remove, 190972246da4SFelipe Balbi .driver = { 191072246da4SFelipe Balbi .name = "dwc3", 19115088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 1912404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 19137f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 191472246da4SFelipe Balbi }, 191572246da4SFelipe Balbi }; 191672246da4SFelipe Balbi 1917b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 1918b1116dccSTobias Klauser 19197ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 192072246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 19215945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 192272246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1923