15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 272246da4SFelipe Balbi /** 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 572246da4SFelipe Balbi * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32f7e846f0SFelipe Balbi #include <linux/usb/of.h> 33a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3472246da4SFelipe Balbi 3572246da4SFelipe Balbi #include "core.h" 3672246da4SFelipe Balbi #include "gadget.h" 3772246da4SFelipe Balbi #include "io.h" 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #include "debug.h" 4072246da4SFelipe Balbi 41fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 428300dd23SFelipe Balbi 439d6173e1SThinh Nguyen /** 449d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 459d6173e1SThinh Nguyen * @dwc: pointer to our context structure 469d6173e1SThinh Nguyen */ 479d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 489d6173e1SThinh Nguyen { 499d6173e1SThinh Nguyen enum usb_dr_mode mode; 509d6173e1SThinh Nguyen struct device *dev = dwc->dev; 519d6173e1SThinh Nguyen unsigned int hw_mode; 529d6173e1SThinh Nguyen 539d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 549d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 559d6173e1SThinh Nguyen 569d6173e1SThinh Nguyen mode = dwc->dr_mode; 579d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 589d6173e1SThinh Nguyen 599d6173e1SThinh Nguyen switch (hw_mode) { 609d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 619d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 629d6173e1SThinh Nguyen dev_err(dev, 639d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 649d6173e1SThinh Nguyen return -EINVAL; 659d6173e1SThinh Nguyen } 669d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 679d6173e1SThinh Nguyen break; 689d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 699d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 709d6173e1SThinh Nguyen dev_err(dev, 719d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 729d6173e1SThinh Nguyen return -EINVAL; 739d6173e1SThinh Nguyen } 749d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 759d6173e1SThinh Nguyen break; 769d6173e1SThinh Nguyen default: 779d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 789d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 799d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 81a7700468SThinh Nguyen 82a7700468SThinh Nguyen /* 8389a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8489a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8589a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 86a7700468SThinh Nguyen */ 8789a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 8889a9cc47SThinh Nguyen dwc->revision >= DWC3_REVISION_330A) 89a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 909d6173e1SThinh Nguyen } 919d6173e1SThinh Nguyen 929d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 939d6173e1SThinh Nguyen dev_warn(dev, 949d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 959d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 969d6173e1SThinh Nguyen 979d6173e1SThinh Nguyen dwc->dr_mode = mode; 989d6173e1SThinh Nguyen } 999d6173e1SThinh Nguyen 1009d6173e1SThinh Nguyen return 0; 1019d6173e1SThinh Nguyen } 1029d6173e1SThinh Nguyen 103f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1043140e8cbSSebastian Andrzej Siewior { 1053140e8cbSSebastian Andrzej Siewior u32 reg; 1063140e8cbSSebastian Andrzej Siewior 1073140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1083140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1093140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1103140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 111c4a5153eSManu Gautam 112c4a5153eSManu Gautam dwc->current_dr_role = mode; 11341ce1456SRoger Quadros } 1146b3261a2SRoger Quadros 11541ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 11641ce1456SRoger Quadros { 11741ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 11841ce1456SRoger Quadros unsigned long flags; 11941ce1456SRoger Quadros int ret; 12041ce1456SRoger Quadros 121f09cc79bSRoger Quadros if (dwc->dr_mode != USB_DR_MODE_OTG) 122f09cc79bSRoger Quadros return; 123f09cc79bSRoger Quadros 124f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 125f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 126f09cc79bSRoger Quadros 12741ce1456SRoger Quadros if (!dwc->desired_dr_role) 12841ce1456SRoger Quadros return; 12941ce1456SRoger Quadros 13041ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 13141ce1456SRoger Quadros return; 13241ce1456SRoger Quadros 133f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 13441ce1456SRoger Quadros return; 13541ce1456SRoger Quadros 13641ce1456SRoger Quadros switch (dwc->current_dr_role) { 13741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 13841ce1456SRoger Quadros dwc3_host_exit(dwc); 13941ce1456SRoger Quadros break; 14041ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14141ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14241ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14341ce1456SRoger Quadros break; 144f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 145f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 146f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 147f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 148f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 149f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 150f09cc79bSRoger Quadros break; 15141ce1456SRoger Quadros default: 15241ce1456SRoger Quadros break; 15341ce1456SRoger Quadros } 15441ce1456SRoger Quadros 15541ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 15641ce1456SRoger Quadros 15741ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 15841ce1456SRoger Quadros 15941ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 16041ce1456SRoger Quadros 16141ce1456SRoger Quadros switch (dwc->desired_dr_role) { 16241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 16341ce1456SRoger Quadros ret = dwc3_host_init(dwc); 164958d1a4cSFelipe Balbi if (ret) { 16541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 166958d1a4cSFelipe Balbi } else { 167958d1a4cSFelipe Balbi if (dwc->usb2_phy) 168958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 169958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 170644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 171958d1a4cSFelipe Balbi } 17241ce1456SRoger Quadros break; 17341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 17441ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 175958d1a4cSFelipe Balbi 176958d1a4cSFelipe Balbi if (dwc->usb2_phy) 177958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 178958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 179644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 180958d1a4cSFelipe Balbi 18141ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 18241ce1456SRoger Quadros if (ret) 18341ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 18441ce1456SRoger Quadros break; 185f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 186f09cc79bSRoger Quadros dwc3_otg_init(dwc); 187f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 188f09cc79bSRoger Quadros break; 18941ce1456SRoger Quadros default: 19041ce1456SRoger Quadros break; 19141ce1456SRoger Quadros } 192f09cc79bSRoger Quadros 19341ce1456SRoger Quadros } 19441ce1456SRoger Quadros 19541ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 19641ce1456SRoger Quadros { 19741ce1456SRoger Quadros unsigned long flags; 19841ce1456SRoger Quadros 19941ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 20041ce1456SRoger Quadros dwc->desired_dr_role = mode; 20141ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 20241ce1456SRoger Quadros 203084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2043140e8cbSSebastian Andrzej Siewior } 2058300dd23SFelipe Balbi 206cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 207cf6d867dSFelipe Balbi { 208cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 209cf6d867dSFelipe Balbi u32 reg; 210cf6d867dSFelipe Balbi 211cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 212cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 213cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 214cf6d867dSFelipe Balbi 215cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 216cf6d867dSFelipe Balbi 217cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 218cf6d867dSFelipe Balbi } 219cf6d867dSFelipe Balbi 22072246da4SFelipe Balbi /** 22172246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 22272246da4SFelipe Balbi * @dwc: pointer to our context structure 22372246da4SFelipe Balbi */ 22457303488SKishon Vijay Abraham I static int dwc3_core_soft_reset(struct dwc3 *dwc) 22572246da4SFelipe Balbi { 22672246da4SFelipe Balbi u32 reg; 227f59dcab1SFelipe Balbi int retries = 1000; 22857303488SKishon Vijay Abraham I int ret; 22972246da4SFelipe Balbi 23051e1e7bcSFelipe Balbi usb_phy_init(dwc->usb2_phy); 23151e1e7bcSFelipe Balbi usb_phy_init(dwc->usb3_phy); 23257303488SKishon Vijay Abraham I ret = phy_init(dwc->usb2_generic_phy); 23357303488SKishon Vijay Abraham I if (ret < 0) 23457303488SKishon Vijay Abraham I return ret; 23557303488SKishon Vijay Abraham I 23657303488SKishon Vijay Abraham I ret = phy_init(dwc->usb3_generic_phy); 23757303488SKishon Vijay Abraham I if (ret < 0) { 23857303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 23957303488SKishon Vijay Abraham I return ret; 24057303488SKishon Vijay Abraham I } 24172246da4SFelipe Balbi 242f59dcab1SFelipe Balbi /* 243f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 244f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 245f59dcab1SFelipe Balbi * host-only mode, then we can return early. 246f59dcab1SFelipe Balbi */ 247c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 24857303488SKishon Vijay Abraham I return 0; 249f59dcab1SFelipe Balbi 250f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 251f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 252f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 253f59dcab1SFelipe Balbi 2544749e0e6SThinh Nguyen /* 2554749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2564749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2574749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2584749e0e6SThinh Nguyen * for 10 times instead. 2594749e0e6SThinh Nguyen */ 2604749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A) 2614749e0e6SThinh Nguyen retries = 10; 2624749e0e6SThinh Nguyen 263f59dcab1SFelipe Balbi do { 264f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 265f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 266fab38333SThinh Nguyen goto done; 267f59dcab1SFelipe Balbi 2684749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && 2694749e0e6SThinh Nguyen dwc->revision >= DWC3_USB31_REVISION_190A) 2704749e0e6SThinh Nguyen msleep(20); 2714749e0e6SThinh Nguyen else 272f59dcab1SFelipe Balbi udelay(1); 273f59dcab1SFelipe Balbi } while (--retries); 274f59dcab1SFelipe Balbi 27500b42170SBrian Norris phy_exit(dwc->usb3_generic_phy); 27600b42170SBrian Norris phy_exit(dwc->usb2_generic_phy); 27700b42170SBrian Norris 278f59dcab1SFelipe Balbi return -ETIMEDOUT; 279fab38333SThinh Nguyen 280fab38333SThinh Nguyen done: 281fab38333SThinh Nguyen /* 2824749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 2834749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 2844749e0e6SThinh Nguyen * domain (synchronization delay). 285fab38333SThinh Nguyen */ 2864749e0e6SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A) 287fab38333SThinh Nguyen msleep(50); 288fab38333SThinh Nguyen 289fab38333SThinh Nguyen return 0; 29072246da4SFelipe Balbi } 29172246da4SFelipe Balbi 292fe8abf33SMasahiro Yamada static const struct clk_bulk_data dwc3_core_clks[] = { 293fe8abf33SMasahiro Yamada { .id = "ref" }, 294fe8abf33SMasahiro Yamada { .id = "bus_early" }, 295fe8abf33SMasahiro Yamada { .id = "suspend" }, 296fe8abf33SMasahiro Yamada }; 297fe8abf33SMasahiro Yamada 298db2be4e9SNikhil Badola /* 299db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 300db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 301db2be4e9SNikhil Badola */ 302bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 303db2be4e9SNikhil Badola { 304db2be4e9SNikhil Badola u32 reg; 305db2be4e9SNikhil Badola u32 dft; 306db2be4e9SNikhil Badola 307db2be4e9SNikhil Badola if (dwc->revision < DWC3_REVISION_250A) 308db2be4e9SNikhil Badola return; 309db2be4e9SNikhil Badola 310bcdb3272SFelipe Balbi if (dwc->fladj == 0) 311db2be4e9SNikhil Badola return; 312db2be4e9SNikhil Badola 313db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 314db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 315a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 316db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 317bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 318db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 319db2be4e9SNikhil Badola } 320db2be4e9SNikhil Badola } 321db2be4e9SNikhil Badola 322c5cc74e8SHeikki Krogerus /** 32372246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 32472246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 32572246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 32672246da4SFelipe Balbi */ 32772246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 32872246da4SFelipe Balbi struct dwc3_event_buffer *evt) 32972246da4SFelipe Balbi { 330d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 33172246da4SFelipe Balbi } 33272246da4SFelipe Balbi 33372246da4SFelipe Balbi /** 3341d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 33572246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 33672246da4SFelipe Balbi * @length: size of the event buffer 33772246da4SFelipe Balbi * 3381d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 33972246da4SFelipe Balbi * otherwise ERR_PTR(errno). 34072246da4SFelipe Balbi */ 34167d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 34267d0b500SFelipe Balbi unsigned length) 34372246da4SFelipe Balbi { 34472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 34572246da4SFelipe Balbi 346380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 34772246da4SFelipe Balbi if (!evt) 34872246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 34972246da4SFelipe Balbi 35072246da4SFelipe Balbi evt->dwc = dwc; 35172246da4SFelipe Balbi evt->length = length; 352d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 353d9fa4c63SJohn Youn if (!evt->cache) 354d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 355d9fa4c63SJohn Youn 356d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 35772246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 358e32672f0SFelipe Balbi if (!evt->buf) 35972246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 36072246da4SFelipe Balbi 36172246da4SFelipe Balbi return evt; 36272246da4SFelipe Balbi } 36372246da4SFelipe Balbi 36472246da4SFelipe Balbi /** 36572246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 36672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 36772246da4SFelipe Balbi */ 36872246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 36972246da4SFelipe Balbi { 37072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 37172246da4SFelipe Balbi 372696c8b12SFelipe Balbi evt = dwc->ev_buf; 37364b6c8a7SAnton Tikhomirov if (evt) 37472246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 37572246da4SFelipe Balbi } 37672246da4SFelipe Balbi 37772246da4SFelipe Balbi /** 37872246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 3791d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 38072246da4SFelipe Balbi * @length: size of event buffer 38172246da4SFelipe Balbi * 3821d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 38372246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 38472246da4SFelipe Balbi */ 38541ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 38672246da4SFelipe Balbi { 38772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 38872246da4SFelipe Balbi 38972246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 39072246da4SFelipe Balbi if (IS_ERR(evt)) { 39172246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 39272246da4SFelipe Balbi return PTR_ERR(evt); 39372246da4SFelipe Balbi } 394696c8b12SFelipe Balbi dwc->ev_buf = evt; 39572246da4SFelipe Balbi 39672246da4SFelipe Balbi return 0; 39772246da4SFelipe Balbi } 39872246da4SFelipe Balbi 39972246da4SFelipe Balbi /** 40072246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4011d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 40272246da4SFelipe Balbi * 40372246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 40472246da4SFelipe Balbi */ 405f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 40672246da4SFelipe Balbi { 40772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 40872246da4SFelipe Balbi 409696c8b12SFelipe Balbi evt = dwc->ev_buf; 4107acd85e0SPaul Zimmerman evt->lpos = 0; 411660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 41272246da4SFelipe Balbi lower_32_bits(evt->dma)); 413660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 41472246da4SFelipe Balbi upper_32_bits(evt->dma)); 415660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 41668d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 417660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 41872246da4SFelipe Balbi 41972246da4SFelipe Balbi return 0; 42072246da4SFelipe Balbi } 42172246da4SFelipe Balbi 422f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 42372246da4SFelipe Balbi { 42472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 42572246da4SFelipe Balbi 426696c8b12SFelipe Balbi evt = dwc->ev_buf; 4277acd85e0SPaul Zimmerman 4287acd85e0SPaul Zimmerman evt->lpos = 0; 4297acd85e0SPaul Zimmerman 430660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 431660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 432660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 43368d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 434660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 43572246da4SFelipe Balbi } 43672246da4SFelipe Balbi 4370ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 4380ffcaf37SFelipe Balbi { 4390ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4400ffcaf37SFelipe Balbi return 0; 4410ffcaf37SFelipe Balbi 4420ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4430ffcaf37SFelipe Balbi return 0; 4440ffcaf37SFelipe Balbi 4450ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 4460ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 4470ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 4480ffcaf37SFelipe Balbi return -ENOMEM; 4490ffcaf37SFelipe Balbi 4500ffcaf37SFelipe Balbi return 0; 4510ffcaf37SFelipe Balbi } 4520ffcaf37SFelipe Balbi 4530ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 4540ffcaf37SFelipe Balbi { 4550ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 4560ffcaf37SFelipe Balbi u32 param; 4570ffcaf37SFelipe Balbi int ret; 4580ffcaf37SFelipe Balbi 4590ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4600ffcaf37SFelipe Balbi return 0; 4610ffcaf37SFelipe Balbi 4620ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4630ffcaf37SFelipe Balbi return 0; 4640ffcaf37SFelipe Balbi 4650ffcaf37SFelipe Balbi /* should never fall here */ 4660ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 4670ffcaf37SFelipe Balbi return 0; 4680ffcaf37SFelipe Balbi 469d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 4700ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 4710ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 472d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 473d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 4740ffcaf37SFelipe Balbi ret = -EFAULT; 4750ffcaf37SFelipe Balbi goto err0; 4760ffcaf37SFelipe Balbi } 4770ffcaf37SFelipe Balbi 4780ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 4790ffcaf37SFelipe Balbi 4800ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 4810ffcaf37SFelipe Balbi 4820ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4830ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 4840ffcaf37SFelipe Balbi if (ret < 0) 4850ffcaf37SFelipe Balbi goto err1; 4860ffcaf37SFelipe Balbi 4870ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 4880ffcaf37SFelipe Balbi 4890ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4900ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 4910ffcaf37SFelipe Balbi if (ret < 0) 4920ffcaf37SFelipe Balbi goto err1; 4930ffcaf37SFelipe Balbi 4940ffcaf37SFelipe Balbi return 0; 4950ffcaf37SFelipe Balbi 4960ffcaf37SFelipe Balbi err1: 497d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 4980ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 4990ffcaf37SFelipe Balbi 5000ffcaf37SFelipe Balbi err0: 5010ffcaf37SFelipe Balbi return ret; 5020ffcaf37SFelipe Balbi } 5030ffcaf37SFelipe Balbi 5040ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5050ffcaf37SFelipe Balbi { 5060ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5070ffcaf37SFelipe Balbi return; 5080ffcaf37SFelipe Balbi 5090ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5100ffcaf37SFelipe Balbi return; 5110ffcaf37SFelipe Balbi 5120ffcaf37SFelipe Balbi /* should never fall here */ 5130ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5140ffcaf37SFelipe Balbi return; 5150ffcaf37SFelipe Balbi 516d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5170ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5180ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 5190ffcaf37SFelipe Balbi } 5200ffcaf37SFelipe Balbi 521789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 522789451f6SFelipe Balbi { 523789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 524789451f6SFelipe Balbi 52547d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 526789451f6SFelipe Balbi } 527789451f6SFelipe Balbi 52841ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 52926ceca97SFelipe Balbi { 53026ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 53126ceca97SFelipe Balbi 53226ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 53326ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 53426ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 53526ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 53626ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 53726ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 53826ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 53926ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 54026ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 54126ceca97SFelipe Balbi } 54226ceca97SFelipe Balbi 54398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 54498112041SRoger Quadros { 54598112041SRoger Quadros int intf; 54698112041SRoger Quadros int ret = 0; 54798112041SRoger Quadros 54898112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 54998112041SRoger Quadros 55098112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 55198112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 55298112041SRoger Quadros dwc->hsphy_interface && 55398112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 55498112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 55598112041SRoger Quadros 55698112041SRoger Quadros return ret; 55798112041SRoger Quadros } 55898112041SRoger Quadros 55972246da4SFelipe Balbi /** 560b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 561b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 56288bc9d19SHeikki Krogerus * 56388bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 56488bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 56588bc9d19SHeikki Krogerus * the core in dwc3_core_init. 566b5a65c40SHuang Rui */ 56788bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 568b5a65c40SHuang Rui { 5699ba3aca8SThinh Nguyen unsigned int hw_mode; 570b5a65c40SHuang Rui u32 reg; 571b5a65c40SHuang Rui 5729ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 5739ba3aca8SThinh Nguyen 574b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 575b5a65c40SHuang Rui 5762164a476SHuang Rui /* 5771966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 5781966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 5791966b865SFelipe Balbi */ 5801966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 5811966b865SFelipe Balbi 5821966b865SFelipe Balbi /* 5832164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 5842164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 5852164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 5862164a476SHuang Rui * to '1' after the core initialization is completed. 5872164a476SHuang Rui */ 5882164a476SHuang Rui if (dwc->revision > DWC3_REVISION_194A) 5892164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 5902164a476SHuang Rui 5919ba3aca8SThinh Nguyen /* 5929ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 5939ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 5949ba3aca8SThinh Nguyen * after device soft-reset during initialization. 5959ba3aca8SThinh Nguyen */ 5969ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 5979ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 5989ba3aca8SThinh Nguyen 599b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 600b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 601b5a65c40SHuang Rui 602e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 603e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 604e58dd357SRajesh Bhagat 605df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 606df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 607df31f5b3SHuang Rui 608a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 609a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 610a2a1d0f5SHuang Rui 61141c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 61241c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 61341c06ffdSHuang Rui 614fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 615fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 616fb67afcaSHuang Rui 61714f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 61814f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 61914f4ac53SHuang Rui 6206b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 6216b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 6226b6a0c9aSHuang Rui 623cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 62459acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 62559acfa20SHuang Rui 62600fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 62700fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 62800fe081dSWilliam Wu 629b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 630b5a65c40SHuang Rui 6312164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 6322164a476SHuang Rui 6333e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 6343e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 6353e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 63643cacb03SFelipe Balbi if (dwc->hsphy_interface && 63743cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 6383e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 63988bc9d19SHeikki Krogerus break; 64043cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 64143cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 6423e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 64388bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 6443e10a2ceSHeikki Krogerus } else { 64588bc9d19SHeikki Krogerus /* Relying on default value. */ 64688bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 6473e10a2ceSHeikki Krogerus break; 6483e10a2ceSHeikki Krogerus } 6493e10a2ceSHeikki Krogerus /* FALLTHROUGH */ 65088bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 65188bc9d19SHeikki Krogerus /* FALLTHROUGH */ 6523e10a2ceSHeikki Krogerus default: 6533e10a2ceSHeikki Krogerus break; 6543e10a2ceSHeikki Krogerus } 6553e10a2ceSHeikki Krogerus 65632f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 65732f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 65832f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 65932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66032f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 66132f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 66232f2ed86SWilliam Wu break; 66332f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 66432f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 66532f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66632f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 66732f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 66832f2ed86SWilliam Wu break; 66932f2ed86SWilliam Wu default: 67032f2ed86SWilliam Wu break; 67132f2ed86SWilliam Wu } 67232f2ed86SWilliam Wu 6732164a476SHuang Rui /* 6742164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 6752164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 6762164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 6772164a476SHuang Rui * '1' after the core initialization is completed. 6782164a476SHuang Rui */ 6792164a476SHuang Rui if (dwc->revision > DWC3_REVISION_194A) 6802164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 6812164a476SHuang Rui 6829ba3aca8SThinh Nguyen /* 6839ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 6849ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6859ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6869ba3aca8SThinh Nguyen */ 6879ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6889ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6899ba3aca8SThinh Nguyen 690cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 6910effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6920effe0a3SHuang Rui 693ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 694ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 695eafeacf1SThinh Nguyen else 696eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 697ec791d14SJohn Youn 69816199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 69916199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 70016199f33SWilliam Wu 7012164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 70288bc9d19SHeikki Krogerus 70388bc9d19SHeikki Krogerus return 0; 704b5a65c40SHuang Rui } 705b5a65c40SHuang Rui 706c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 707c499ff71SFelipe Balbi { 708c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 709c499ff71SFelipe Balbi 710c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 711c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 712c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 713c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 714c499ff71SFelipe Balbi 715c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 716c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 717c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 718c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 719240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 720fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 721c499ff71SFelipe Balbi } 722c499ff71SFelipe Balbi 7230759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 72472246da4SFelipe Balbi { 72572246da4SFelipe Balbi u32 reg; 72672246da4SFelipe Balbi 7277650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 7280759956fSFelipe Balbi 7297650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 730690fb371SJohn Youn if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) { 731690fb371SJohn Youn /* Detected DWC_usb3 IP */ 732690fb371SJohn Youn dwc->revision = reg; 733690fb371SJohn Youn } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) { 734690fb371SJohn Youn /* Detected DWC_usb31 IP */ 735690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 736690fb371SJohn Youn dwc->revision |= DWC3_REVISION_IS_DWC31; 737475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 738690fb371SJohn Youn } else { 7390759956fSFelipe Balbi return false; 7407650bd74SSebastian Andrzej Siewior } 7417650bd74SSebastian Andrzej Siewior 7420759956fSFelipe Balbi return true; 7430e1e5c47SPaul Zimmerman } 7440e1e5c47SPaul Zimmerman 745941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 74672246da4SFelipe Balbi { 74772246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 74872246da4SFelipe Balbi u32 reg; 749c499ff71SFelipe Balbi 7504878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 7513e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 7524878a028SSebastian Andrzej Siewior 753164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 7544878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 75532a4a135SFelipe Balbi /** 75632a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 75732a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 75832a4a135SFelipe Balbi * 75932a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 76032a4a135SFelipe Balbi * configurations. 76132a4a135SFelipe Balbi * 76232a4a135SFelipe Balbi * Refers to: 76332a4a135SFelipe Balbi * 76432a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 76532a4a135SFelipe Balbi * SOF/ITP Mode Used 76632a4a135SFelipe Balbi */ 76732a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 76832a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 76932a4a135SFelipe Balbi (dwc->revision >= DWC3_REVISION_210A && 77032a4a135SFelipe Balbi dwc->revision <= DWC3_REVISION_250A)) 77132a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 77232a4a135SFelipe Balbi else 7734878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 7744878a028SSebastian Andrzej Siewior break; 7750ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 7760ffcaf37SFelipe Balbi /* enable hibernation here */ 7770ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 7782eac3992SHuang Rui 7792eac3992SHuang Rui /* 7802eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 7812eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 7822eac3992SHuang Rui */ 7832eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 7840ffcaf37SFelipe Balbi break; 7854878a028SSebastian Andrzej Siewior default: 7865eb30cedSFelipe Balbi /* nothing */ 7875eb30cedSFelipe Balbi break; 7884878a028SSebastian Andrzej Siewior } 7894878a028SSebastian Andrzej Siewior 790946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 791946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 7926af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 793946bd579SHuang Rui dwc->is_fpga = true; 794946bd579SHuang Rui } 795946bd579SHuang Rui 7963b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 7973b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 7983b81221aSHuang Rui 7993b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 8003b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 8013b81221aSHuang Rui else 8023b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 8033b81221aSHuang Rui 8049a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 8059a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 8069a5b2f31SHuang Rui 8074878a028SSebastian Andrzej Siewior /* 8084878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 8091d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 8104878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 8111d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 8124878a028SSebastian Andrzej Siewior */ 8134878a028SSebastian Andrzej Siewior if (dwc->revision < DWC3_REVISION_190A) 8144878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 8154878a028SSebastian Andrzej Siewior 8164878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 817941f918eSFelipe Balbi } 8184878a028SSebastian Andrzej Siewior 819f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 82098112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 821f54edb53SFelipe Balbi 822d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 823d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 824d9612c2fSPengbo Mu { 825d9612c2fSPengbo Mu struct device *dev = dwc->dev; 826d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 827d9612c2fSPengbo Mu bool incrx_mode; 828d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 829d9612c2fSPengbo Mu u32 incrx_size; 830d9612c2fSPengbo Mu u32 *vals; 831d9612c2fSPengbo Mu u32 cfg; 832d9612c2fSPengbo Mu int ntype; 833d9612c2fSPengbo Mu int ret; 834d9612c2fSPengbo Mu int i; 835d9612c2fSPengbo Mu 836d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 837d9612c2fSPengbo Mu 838d9612c2fSPengbo Mu /* 839d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 840d9612c2fSPengbo Mu * Get the number of value from this property: 841d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 842d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 843d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 844d9612c2fSPengbo Mu */ 845a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 846d9612c2fSPengbo Mu if (ntype <= 0) 847d9612c2fSPengbo Mu return; 848d9612c2fSPengbo Mu 849d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 850d9612c2fSPengbo Mu if (!vals) { 851d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 852d9612c2fSPengbo Mu return; 853d9612c2fSPengbo Mu } 854d9612c2fSPengbo Mu 855d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 856d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 857d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 858d9612c2fSPengbo Mu if (ret) { 85975ecb9ddSAndy Shevchenko kfree(vals); 860d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 861d9612c2fSPengbo Mu return; 862d9612c2fSPengbo Mu } 863d9612c2fSPengbo Mu 864d9612c2fSPengbo Mu incrx_size = *vals; 865d9612c2fSPengbo Mu 866d9612c2fSPengbo Mu if (ntype > 1) { 867d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 868d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 869d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 870d9612c2fSPengbo Mu if (vals[i] > incrx_size) 871d9612c2fSPengbo Mu incrx_size = vals[i]; 872d9612c2fSPengbo Mu } 873d9612c2fSPengbo Mu } else { 874d9612c2fSPengbo Mu /* INCRX burst mode */ 875d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 876d9612c2fSPengbo Mu } 877d9612c2fSPengbo Mu 87875ecb9ddSAndy Shevchenko kfree(vals); 87975ecb9ddSAndy Shevchenko 880d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 881d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 882d9612c2fSPengbo Mu if (incrx_mode) 883d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 884d9612c2fSPengbo Mu switch (incrx_size) { 885d9612c2fSPengbo Mu case 256: 886d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 887d9612c2fSPengbo Mu break; 888d9612c2fSPengbo Mu case 128: 889d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 890d9612c2fSPengbo Mu break; 891d9612c2fSPengbo Mu case 64: 892d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 893d9612c2fSPengbo Mu break; 894d9612c2fSPengbo Mu case 32: 895d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 896d9612c2fSPengbo Mu break; 897d9612c2fSPengbo Mu case 16: 898d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 899d9612c2fSPengbo Mu break; 900d9612c2fSPengbo Mu case 8: 901d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 902d9612c2fSPengbo Mu break; 903d9612c2fSPengbo Mu case 4: 904d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 905d9612c2fSPengbo Mu break; 906d9612c2fSPengbo Mu case 1: 907d9612c2fSPengbo Mu break; 908d9612c2fSPengbo Mu default: 909d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 910d9612c2fSPengbo Mu break; 911d9612c2fSPengbo Mu } 912d9612c2fSPengbo Mu 913d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 914d9612c2fSPengbo Mu } 915d9612c2fSPengbo Mu 916941f918eSFelipe Balbi /** 917941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 918941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 919941f918eSFelipe Balbi * 920941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 921941f918eSFelipe Balbi */ 922941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 923941f918eSFelipe Balbi { 9249ba3aca8SThinh Nguyen unsigned int hw_mode; 925941f918eSFelipe Balbi u32 reg; 926941f918eSFelipe Balbi int ret; 927941f918eSFelipe Balbi 9289ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 9299ba3aca8SThinh Nguyen 930941f918eSFelipe Balbi /* 931941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 932941f918eSFelipe Balbi * out which kernel version a bug was found. 933941f918eSFelipe Balbi */ 934941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 935941f918eSFelipe Balbi 936941f918eSFelipe Balbi /* Handle USB2.0-only core configuration */ 937941f918eSFelipe Balbi if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 938941f918eSFelipe Balbi DWC3_GHWPARAMS3_SSPHY_IFC_DIS) { 939941f918eSFelipe Balbi if (dwc->maximum_speed == USB_SPEED_SUPER) 940941f918eSFelipe Balbi dwc->maximum_speed = USB_SPEED_HIGH; 941941f918eSFelipe Balbi } 942941f918eSFelipe Balbi 943941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 944941f918eSFelipe Balbi if (ret) 945941f918eSFelipe Balbi goto err0; 946941f918eSFelipe Balbi 94798112041SRoger Quadros if (!dwc->ulpi_ready) { 94898112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 94998112041SRoger Quadros if (ret) 95098112041SRoger Quadros goto err0; 95198112041SRoger Quadros dwc->ulpi_ready = true; 95298112041SRoger Quadros } 95398112041SRoger Quadros 95498112041SRoger Quadros if (!dwc->phys_ready) { 95598112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 95698112041SRoger Quadros if (ret) 95798112041SRoger Quadros goto err0a; 95898112041SRoger Quadros dwc->phys_ready = true; 95998112041SRoger Quadros } 96098112041SRoger Quadros 96198112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 96298112041SRoger Quadros if (ret) 96398112041SRoger Quadros goto err0a; 96498112041SRoger Quadros 9659ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 9669ba3aca8SThinh Nguyen dwc->revision > DWC3_REVISION_194A) { 9679ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 9689ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 9699ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 9709ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 9719ba3aca8SThinh Nguyen } 9729ba3aca8SThinh Nguyen 9739ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 9749ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 9759ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 9769ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 9779ba3aca8SThinh Nguyen } 9789ba3aca8SThinh Nguyen } 9799ba3aca8SThinh Nguyen 980941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 981c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 9820ffcaf37SFelipe Balbi 9830ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 9840ffcaf37SFelipe Balbi if (ret) 985c499ff71SFelipe Balbi goto err1; 986c499ff71SFelipe Balbi 987c499ff71SFelipe Balbi /* Adjust Frame Length */ 988c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 989c499ff71SFelipe Balbi 990d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 991d9612c2fSPengbo Mu 992c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 993c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 994c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 995c499ff71SFelipe Balbi if (ret < 0) 9960ffcaf37SFelipe Balbi goto err2; 9970ffcaf37SFelipe Balbi 998c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 999c499ff71SFelipe Balbi if (ret < 0) 1000c499ff71SFelipe Balbi goto err3; 1001c499ff71SFelipe Balbi 1002c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1003c499ff71SFelipe Balbi if (ret) { 1004c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1005c499ff71SFelipe Balbi goto err4; 1006c499ff71SFelipe Balbi } 1007c499ff71SFelipe Balbi 100806281d46SJohn Youn /* 100906281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 101006281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 101106281d46SJohn Youn * DWC_usb31 controller. 101206281d46SJohn Youn */ 101306281d46SJohn Youn if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) { 101406281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 101506281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 101606281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 101706281d46SJohn Youn } 101806281d46SJohn Youn 101965db7a0cSWilliam Wu if (dwc->revision >= DWC3_REVISION_250A) { 10200bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 102165db7a0cSWilliam Wu 102265db7a0cSWilliam Wu /* 102365db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 102465db7a0cSWilliam Wu * in HS when the device is in the L1 state. 102565db7a0cSWilliam Wu */ 102665db7a0cSWilliam Wu if (dwc->revision >= DWC3_REVISION_290A) 10270bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 102865db7a0cSWilliam Wu 102965db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 103065db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 103165db7a0cSWilliam Wu 10327ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 10337ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 10347ba6b09fSNeil Armstrong 10350bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 10360bb39ca1SJohn Youn } 10370bb39ca1SJohn Youn 1038b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1039b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1040b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1041b138e23dSAnurag Kumar Vulisha 1042b138e23dSAnurag Kumar Vulisha /* 1043b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1044b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1045b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1046b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1047b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1048b138e23dSAnurag Kumar Vulisha */ 1049b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1050b138e23dSAnurag Kumar Vulisha 1051b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1052b138e23dSAnurag Kumar Vulisha } 1053b138e23dSAnurag Kumar Vulisha 1054938a5ad1SThinh Nguyen /* 1055938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1056938a5ad1SThinh Nguyen * RX and/or TX threshold. 1057938a5ad1SThinh Nguyen */ 1058938a5ad1SThinh Nguyen if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) { 1059938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1060938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1061938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1062938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1063938a5ad1SThinh Nguyen 1064938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1065938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1066938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1067938a5ad1SThinh Nguyen 1068938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1069938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1070938a5ad1SThinh Nguyen 1071938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1072938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1073938a5ad1SThinh Nguyen 1074938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1075938a5ad1SThinh Nguyen } 1076938a5ad1SThinh Nguyen 1077938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1078938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1079938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1080938a5ad1SThinh Nguyen 1081938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1082938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1083938a5ad1SThinh Nguyen 1084938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1085938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1086938a5ad1SThinh Nguyen 1087938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1088938a5ad1SThinh Nguyen } 1089938a5ad1SThinh Nguyen } 1090938a5ad1SThinh Nguyen 109172246da4SFelipe Balbi return 0; 109272246da4SFelipe Balbi 1093c499ff71SFelipe Balbi err4: 10949b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1095c499ff71SFelipe Balbi 1096c499ff71SFelipe Balbi err3: 10979b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1098c499ff71SFelipe Balbi 10990ffcaf37SFelipe Balbi err2: 1100c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1101c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 11020ffcaf37SFelipe Balbi 11030ffcaf37SFelipe Balbi err1: 11040ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 11050ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 110657303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 110757303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 11080ffcaf37SFelipe Balbi 110998112041SRoger Quadros err0a: 111098112041SRoger Quadros dwc3_ulpi_exit(dwc); 111198112041SRoger Quadros 111272246da4SFelipe Balbi err0: 111372246da4SFelipe Balbi return ret; 111472246da4SFelipe Balbi } 111572246da4SFelipe Balbi 11163c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 111772246da4SFelipe Balbi { 11183c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1119941ea361SFelipe Balbi struct device_node *node = dev->of_node; 11203c9f94acSFelipe Balbi int ret; 112172246da4SFelipe Balbi 11225088b6f5SKishon Vijay Abraham I if (node) { 11235088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 11245088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1125bb674907SFelipe Balbi } else { 1126bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1127bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 11285088b6f5SKishon Vijay Abraham I } 11295088b6f5SKishon Vijay Abraham I 1130d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1131d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1132122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1133122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1134122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1135d105e7f8SFelipe Balbi return ret; 1136122f06e6SKishon Vijay Abraham I } else { 113751e1e7bcSFelipe Balbi dev_err(dev, "no usb2 phy configured\n"); 1138122f06e6SKishon Vijay Abraham I return ret; 1139122f06e6SKishon Vijay Abraham I } 114051e1e7bcSFelipe Balbi } 114151e1e7bcSFelipe Balbi 1142d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1143315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1144122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1145122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1146122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1147d105e7f8SFelipe Balbi return ret; 1148122f06e6SKishon Vijay Abraham I } else { 114951e1e7bcSFelipe Balbi dev_err(dev, "no usb3 phy configured\n"); 1150122f06e6SKishon Vijay Abraham I return ret; 1151122f06e6SKishon Vijay Abraham I } 115251e1e7bcSFelipe Balbi } 115351e1e7bcSFelipe Balbi 115457303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 115557303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 115657303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 115757303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 115857303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 115957303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 116057303488SKishon Vijay Abraham I return ret; 116157303488SKishon Vijay Abraham I } else { 116257303488SKishon Vijay Abraham I dev_err(dev, "no usb2 phy configured\n"); 116357303488SKishon Vijay Abraham I return ret; 116457303488SKishon Vijay Abraham I } 116557303488SKishon Vijay Abraham I } 116657303488SKishon Vijay Abraham I 116757303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 116857303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 116957303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 117057303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 117157303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 117257303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 117357303488SKishon Vijay Abraham I return ret; 117457303488SKishon Vijay Abraham I } else { 117557303488SKishon Vijay Abraham I dev_err(dev, "no usb3 phy configured\n"); 117657303488SKishon Vijay Abraham I return ret; 117757303488SKishon Vijay Abraham I } 117857303488SKishon Vijay Abraham I } 117957303488SKishon Vijay Abraham I 11803c9f94acSFelipe Balbi return 0; 11813c9f94acSFelipe Balbi } 11823c9f94acSFelipe Balbi 11835f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 11845f94adfeSFelipe Balbi { 11855f94adfeSFelipe Balbi struct device *dev = dwc->dev; 11865f94adfeSFelipe Balbi int ret; 11875f94adfeSFelipe Balbi 11885f94adfeSFelipe Balbi switch (dwc->dr_mode) { 11895f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 119041ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1191958d1a4cSFelipe Balbi 1192958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1193958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1194958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1195644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1196958d1a4cSFelipe Balbi 11975f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 11985f94adfeSFelipe Balbi if (ret) { 11999522def4SRoger Quadros if (ret != -EPROBE_DEFER) 12005f94adfeSFelipe Balbi dev_err(dev, "failed to initialize gadget\n"); 12015f94adfeSFelipe Balbi return ret; 12025f94adfeSFelipe Balbi } 12035f94adfeSFelipe Balbi break; 12045f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 120541ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1206958d1a4cSFelipe Balbi 1207958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1208958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1209958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1210644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1211958d1a4cSFelipe Balbi 12125f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 12135f94adfeSFelipe Balbi if (ret) { 12149522def4SRoger Quadros if (ret != -EPROBE_DEFER) 12155f94adfeSFelipe Balbi dev_err(dev, "failed to initialize host\n"); 12165f94adfeSFelipe Balbi return ret; 12175f94adfeSFelipe Balbi } 12185f94adfeSFelipe Balbi break; 12195f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 122041ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 12219840354fSRoger Quadros ret = dwc3_drd_init(dwc); 12229840354fSRoger Quadros if (ret) { 12239840354fSRoger Quadros if (ret != -EPROBE_DEFER) 12249840354fSRoger Quadros dev_err(dev, "failed to initialize dual-role\n"); 12259840354fSRoger Quadros return ret; 12269840354fSRoger Quadros } 12275f94adfeSFelipe Balbi break; 12285f94adfeSFelipe Balbi default: 12295f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 12305f94adfeSFelipe Balbi return -EINVAL; 12315f94adfeSFelipe Balbi } 12325f94adfeSFelipe Balbi 12335f94adfeSFelipe Balbi return 0; 12345f94adfeSFelipe Balbi } 12355f94adfeSFelipe Balbi 12365f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 12375f94adfeSFelipe Balbi { 12385f94adfeSFelipe Balbi switch (dwc->dr_mode) { 12395f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 12405f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 12415f94adfeSFelipe Balbi break; 12425f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 12435f94adfeSFelipe Balbi dwc3_host_exit(dwc); 12445f94adfeSFelipe Balbi break; 12455f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 12469840354fSRoger Quadros dwc3_drd_exit(dwc); 12475f94adfeSFelipe Balbi break; 12485f94adfeSFelipe Balbi default: 12495f94adfeSFelipe Balbi /* do nothing */ 12505f94adfeSFelipe Balbi break; 12515f94adfeSFelipe Balbi } 125209ed259fSBin Liu 125309ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 125409ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 12555f94adfeSFelipe Balbi } 12565f94adfeSFelipe Balbi 1257c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 12583c9f94acSFelipe Balbi { 1259c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 126080caf7d2SHuang Rui u8 lpm_nyet_threshold; 12616b6a0c9aSHuang Rui u8 tx_de_emphasis; 1262460d098cSHuang Rui u8 hird_threshold; 1263938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1264938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1265938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1266938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 12673c9f94acSFelipe Balbi 126880caf7d2SHuang Rui /* default to highest possible threshold */ 12698d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 127080caf7d2SHuang Rui 12716b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 12726b6a0c9aSHuang Rui tx_de_emphasis = 1; 12736b6a0c9aSHuang Rui 1274460d098cSHuang Rui /* 1275460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1276460d098cSHuang Rui * threshold value of 0b1100 1277460d098cSHuang Rui */ 1278460d098cSHuang Rui hird_threshold = 12; 1279460d098cSHuang Rui 128063863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 128106e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 128232f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 128363863b98SHeikki Krogerus 1284d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1285d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1286d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1287d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1288d64ff406SArnd Bergmann else 1289d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1290d64ff406SArnd Bergmann 12913d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 129280caf7d2SHuang Rui "snps,has-lpm-erratum"); 12933d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 129480caf7d2SHuang Rui &lpm_nyet_threshold); 12953d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1296460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 12973d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1298460d098cSHuang Rui &hird_threshold); 1299d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1300d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 13013d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1302eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1303022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1304022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1305938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1306938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1307938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1308938a5ad1SThinh Nguyen &rx_max_burst_prd); 1309938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1310938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1311938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1312938a5ad1SThinh Nguyen &tx_max_burst_prd); 13133c9f94acSFelipe Balbi 13143d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 13153b81221aSHuang Rui "snps,disable_scramble_quirk"); 13163d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 13179a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 13183d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1319b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 13203d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1321df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 13223d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1323a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 13243d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 132541c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 13263d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1327fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 13283d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 132914f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 13303d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 133159acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 13323d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 13330effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1334ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1335ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1336729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1337729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1338729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1339729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1340e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1341e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 134216199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 134316199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 134400fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 134500fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 134665db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 134765db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 13487ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 13497ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 13506b6a0c9aSHuang Rui 13513d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 13526b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 13533d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 13546b6a0c9aSHuang Rui &tx_de_emphasis); 13553d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 13563e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 13573d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1358bcdb3272SFelipe Balbi &dwc->fladj); 13593d128919SHeikki Krogerus 136042bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 136142bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 136242bf02ecSRoger Quadros 136380caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 13646b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 136580caf7d2SHuang Rui 136616fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1367460d098cSHuang Rui 1368938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1369938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1370938a5ad1SThinh Nguyen 1371938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1372938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1373938a5ad1SThinh Nguyen 1374cf40b86bSJohn Youn dwc->imod_interval = 0; 1375cf40b86bSJohn Youn } 1376cf40b86bSJohn Youn 1377cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1378cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1379cf40b86bSJohn Youn { 1380cf40b86bSJohn Youn return ((dwc3_is_usb3(dwc) && 1381cf40b86bSJohn Youn dwc->revision >= DWC3_REVISION_300A) || 1382cf40b86bSJohn Youn (dwc3_is_usb31(dwc) && 1383cf40b86bSJohn Youn dwc->revision >= DWC3_USB31_REVISION_120A)); 1384c5ac6116SFelipe Balbi } 1385c5ac6116SFelipe Balbi 13867ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 13877ac51a12SJohn Youn { 13887ac51a12SJohn Youn struct device *dev = dwc->dev; 13897ac51a12SJohn Youn 1390cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1391cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1392cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1393cf40b86bSJohn Youn dwc->imod_interval = 0; 1394cf40b86bSJohn Youn } 1395cf40b86bSJohn Youn 139628632b44SJohn Youn /* 139728632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 139828632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 139928632b44SJohn Youn * interrupt from being masked while handling events. IMOD 140028632b44SJohn Youn * allows us to work around this issue. Enable it for the 140128632b44SJohn Youn * affected version. 140228632b44SJohn Youn */ 140328632b44SJohn Youn if (!dwc->imod_interval && 140428632b44SJohn Youn (dwc->revision == DWC3_REVISION_300A)) 140528632b44SJohn Youn dwc->imod_interval = 1; 140628632b44SJohn Youn 14077ac51a12SJohn Youn /* Check the maximum_speed parameter */ 14087ac51a12SJohn Youn switch (dwc->maximum_speed) { 14097ac51a12SJohn Youn case USB_SPEED_LOW: 14107ac51a12SJohn Youn case USB_SPEED_FULL: 14117ac51a12SJohn Youn case USB_SPEED_HIGH: 14127ac51a12SJohn Youn case USB_SPEED_SUPER: 14137ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 14147ac51a12SJohn Youn break; 14157ac51a12SJohn Youn default: 14167ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 14177ac51a12SJohn Youn dwc->maximum_speed); 14187ac51a12SJohn Youn /* fall through */ 14197ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 14207ac51a12SJohn Youn /* default to superspeed */ 14217ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER; 14227ac51a12SJohn Youn 14237ac51a12SJohn Youn /* 14247ac51a12SJohn Youn * default to superspeed plus if we are capable. 14257ac51a12SJohn Youn */ 14267ac51a12SJohn Youn if (dwc3_is_usb31(dwc) && 14277ac51a12SJohn Youn (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) == 14287ac51a12SJohn Youn DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 14297ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 14307ac51a12SJohn Youn 14317ac51a12SJohn Youn break; 14327ac51a12SJohn Youn } 14337ac51a12SJohn Youn } 14347ac51a12SJohn Youn 1435c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1436c5ac6116SFelipe Balbi { 1437c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 143844feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1439c5ac6116SFelipe Balbi struct dwc3 *dwc; 1440c5ac6116SFelipe Balbi 1441c5ac6116SFelipe Balbi int ret; 1442c5ac6116SFelipe Balbi 1443c5ac6116SFelipe Balbi void __iomem *regs; 1444c5ac6116SFelipe Balbi 1445c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1446c5ac6116SFelipe Balbi if (!dwc) 1447c5ac6116SFelipe Balbi return -ENOMEM; 1448c5ac6116SFelipe Balbi 1449fe8abf33SMasahiro Yamada dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks), 1450fe8abf33SMasahiro Yamada GFP_KERNEL); 1451fe8abf33SMasahiro Yamada if (!dwc->clks) 1452fe8abf33SMasahiro Yamada return -ENOMEM; 1453fe8abf33SMasahiro Yamada 1454c5ac6116SFelipe Balbi dwc->dev = dev; 1455c5ac6116SFelipe Balbi 1456c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1457c5ac6116SFelipe Balbi if (!res) { 1458c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1459c5ac6116SFelipe Balbi return -ENODEV; 1460c5ac6116SFelipe Balbi } 1461c5ac6116SFelipe Balbi 1462c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1463c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1464c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1465c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1466c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1467c5ac6116SFelipe Balbi 1468c5ac6116SFelipe Balbi /* 1469c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1470c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1471c5ac6116SFelipe Balbi */ 147244feb8e6SMasahiro Yamada dwc_res = *res; 147344feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 147444feb8e6SMasahiro Yamada 147544feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 147644feb8e6SMasahiro Yamada if (IS_ERR(regs)) 147744feb8e6SMasahiro Yamada return PTR_ERR(regs); 1478c5ac6116SFelipe Balbi 1479c5ac6116SFelipe Balbi dwc->regs = regs; 148044feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1481c5ac6116SFelipe Balbi 1482c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1483c5ac6116SFelipe Balbi 1484fe8abf33SMasahiro Yamada dwc->reset = devm_reset_control_get_optional_shared(dev, NULL); 1485fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1486fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1487fe8abf33SMasahiro Yamada 148861527777SHans de Goede if (dev->of_node) { 148961527777SHans de Goede dwc->num_clks = ARRAY_SIZE(dwc3_core_clks); 149061527777SHans de Goede 149103bf32bbSAndrey Smirnov ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks); 1492fe8abf33SMasahiro Yamada if (ret == -EPROBE_DEFER) 1493fe8abf33SMasahiro Yamada return ret; 1494fe8abf33SMasahiro Yamada /* 149561527777SHans de Goede * Clocks are optional, but new DT platforms should support all 149661527777SHans de Goede * clocks as required by the DT-binding. 1497fe8abf33SMasahiro Yamada */ 1498fe8abf33SMasahiro Yamada if (ret) 1499fe8abf33SMasahiro Yamada dwc->num_clks = 0; 150061527777SHans de Goede } 1501fe8abf33SMasahiro Yamada 1502fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1503fe8abf33SMasahiro Yamada if (ret) 150403bf32bbSAndrey Smirnov return ret; 1505fe8abf33SMasahiro Yamada 1506240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1507fe8abf33SMasahiro Yamada if (ret) 1508fe8abf33SMasahiro Yamada goto assert_reset; 1509fe8abf33SMasahiro Yamada 1510dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1511dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1512dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1513dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1514dc1b5d9aSEnric Balletbo i Serra } 1515dc1b5d9aSEnric Balletbo i Serra 15166c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 15172917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 15186c89cce0SHeikki Krogerus 151972246da4SFelipe Balbi spin_lock_init(&dwc->lock); 152072246da4SFelipe Balbi 1521fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1522fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1523fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1524802ca850SChanho Park pm_runtime_enable(dev); 152532808237SRoger Quadros ret = pm_runtime_get_sync(dev); 152632808237SRoger Quadros if (ret < 0) 152732808237SRoger Quadros goto err1; 152832808237SRoger Quadros 1529802ca850SChanho Park pm_runtime_forbid(dev); 153072246da4SFelipe Balbi 15313921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 15323921426bSFelipe Balbi if (ret) { 15333921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 15343921426bSFelipe Balbi ret = -ENOMEM; 153532808237SRoger Quadros goto err2; 15363921426bSFelipe Balbi } 15373921426bSFelipe Balbi 15389d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 15399d6173e1SThinh Nguyen if (ret) 15409d6173e1SThinh Nguyen goto err3; 154132a4a135SFelipe Balbi 1542c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1543c499ff71SFelipe Balbi if (ret) 154432808237SRoger Quadros goto err3; 1545c499ff71SFelipe Balbi 154672246da4SFelipe Balbi ret = dwc3_core_init(dwc); 154772246da4SFelipe Balbi if (ret) { 1548408d3ba0SBrian Norris if (ret != -EPROBE_DEFER) 1549408d3ba0SBrian Norris dev_err(dev, "failed to initialize core: %d\n", ret); 155032808237SRoger Quadros goto err4; 155172246da4SFelipe Balbi } 155272246da4SFelipe Balbi 15537ac51a12SJohn Youn dwc3_check_params(dwc); 15542c7f1bd9SJohn Youn 15555f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 15565f94adfeSFelipe Balbi if (ret) 155732808237SRoger Quadros goto err5; 155872246da4SFelipe Balbi 15594e9f3118SDu, Changbin dwc3_debugfs_init(dwc); 1560fc8bb91bSFelipe Balbi pm_runtime_put(dev); 156172246da4SFelipe Balbi 156272246da4SFelipe Balbi return 0; 156372246da4SFelipe Balbi 156432808237SRoger Quadros err5: 1565f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 156608fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1567f122d33eSFelipe Balbi 156832808237SRoger Quadros err4: 1569c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 157072246da4SFelipe Balbi 157132808237SRoger Quadros err3: 15723921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 15733921426bSFelipe Balbi 157432808237SRoger Quadros err2: 157532808237SRoger Quadros pm_runtime_allow(&pdev->dev); 157632808237SRoger Quadros 157732808237SRoger Quadros err1: 157832808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 157932808237SRoger Quadros pm_runtime_disable(&pdev->dev); 158032808237SRoger Quadros 1581dc1b5d9aSEnric Balletbo i Serra disable_clks: 1582240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1583fe8abf33SMasahiro Yamada assert_reset: 1584fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1585fe8abf33SMasahiro Yamada 158672246da4SFelipe Balbi return ret; 158772246da4SFelipe Balbi } 158872246da4SFelipe Balbi 1589fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 159072246da4SFelipe Balbi { 159172246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 15923da1f6eeSFelipe Balbi 1593fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 159472246da4SFelipe Balbi 1595dc99f16fSFelipe Balbi dwc3_debugfs_exit(dwc); 1596dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 15978ba007a9SKishon Vijay Abraham I 159872246da4SFelipe Balbi dwc3_core_exit(dwc); 159988bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 160072246da4SFelipe Balbi 1601fc8bb91bSFelipe Balbi pm_runtime_put_sync(&pdev->dev); 1602fc8bb91bSFelipe Balbi pm_runtime_allow(&pdev->dev); 1603fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1604fc8bb91bSFelipe Balbi 1605c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1606c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1607c499ff71SFelipe Balbi 160872246da4SFelipe Balbi return 0; 160972246da4SFelipe Balbi } 161072246da4SFelipe Balbi 1611fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1612fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1613fe8abf33SMasahiro Yamada { 1614fe8abf33SMasahiro Yamada int ret; 1615fe8abf33SMasahiro Yamada 1616fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1617fe8abf33SMasahiro Yamada if (ret) 1618fe8abf33SMasahiro Yamada return ret; 1619fe8abf33SMasahiro Yamada 1620240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1621fe8abf33SMasahiro Yamada if (ret) 1622fe8abf33SMasahiro Yamada goto assert_reset; 1623fe8abf33SMasahiro Yamada 1624fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1625fe8abf33SMasahiro Yamada if (ret) 1626fe8abf33SMasahiro Yamada goto disable_clks; 1627fe8abf33SMasahiro Yamada 1628fe8abf33SMasahiro Yamada return 0; 1629fe8abf33SMasahiro Yamada 1630fe8abf33SMasahiro Yamada disable_clks: 1631240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1632fe8abf33SMasahiro Yamada assert_reset: 1633fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1634fe8abf33SMasahiro Yamada 1635fe8abf33SMasahiro Yamada return ret; 1636fe8abf33SMasahiro Yamada } 1637fe8abf33SMasahiro Yamada 1638c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 16397415f17cSFelipe Balbi { 1640fc8bb91bSFelipe Balbi unsigned long flags; 1641bcb12877SManu Gautam u32 reg; 16427415f17cSFelipe Balbi 1643689bf72cSManu Gautam switch (dwc->current_dr_role) { 1644689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1645fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 16467415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1647fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 164841a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1649689bf72cSManu Gautam dwc3_core_exit(dwc); 165051f5d49aSFelipe Balbi break; 1651689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1652bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1653c4a5153eSManu Gautam dwc3_core_exit(dwc); 1654c4a5153eSManu Gautam break; 1655bcb12877SManu Gautam } 1656bcb12877SManu Gautam 1657bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1658bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1659bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1660bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1661bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1662bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1663bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1664bcb12877SManu Gautam 1665bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1666bcb12877SManu Gautam usleep_range(5000, 6000); 1667bcb12877SManu Gautam } 1668bcb12877SManu Gautam 1669bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1670bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1671bcb12877SManu Gautam break; 1672f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1673f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1674f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1675f09cc79bSRoger Quadros break; 1676f09cc79bSRoger Quadros 1677f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1678f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1679f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1680f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 168141a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1682f09cc79bSRoger Quadros } 1683f09cc79bSRoger Quadros 1684f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1685f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1686f09cc79bSRoger Quadros break; 16877415f17cSFelipe Balbi default: 168851f5d49aSFelipe Balbi /* do nothing */ 16897415f17cSFelipe Balbi break; 16907415f17cSFelipe Balbi } 16917415f17cSFelipe Balbi 1692fc8bb91bSFelipe Balbi return 0; 1693fc8bb91bSFelipe Balbi } 1694fc8bb91bSFelipe Balbi 1695c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1696fc8bb91bSFelipe Balbi { 1697fc8bb91bSFelipe Balbi unsigned long flags; 1698fc8bb91bSFelipe Balbi int ret; 1699bcb12877SManu Gautam u32 reg; 1700fc8bb91bSFelipe Balbi 1701689bf72cSManu Gautam switch (dwc->current_dr_role) { 1702689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1703fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1704fc8bb91bSFelipe Balbi if (ret) 1705fc8bb91bSFelipe Balbi return ret; 1706fc8bb91bSFelipe Balbi 17077d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1708fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1709fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1710fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1711689bf72cSManu Gautam break; 1712689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1713c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1714fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1715c4a5153eSManu Gautam if (ret) 1716c4a5153eSManu Gautam return ret; 17177d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1718bcb12877SManu Gautam break; 1719c4a5153eSManu Gautam } 1720bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1721bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1722bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1723bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1724bcb12877SManu Gautam 1725bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1726bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1727bcb12877SManu Gautam 1728bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1729bcb12877SManu Gautam 1730bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1731bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1732c4a5153eSManu Gautam break; 1733f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1734f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1735f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1736f09cc79bSRoger Quadros break; 1737f09cc79bSRoger Quadros 1738f09cc79bSRoger Quadros ret = dwc3_core_init(dwc); 1739f09cc79bSRoger Quadros if (ret) 1740f09cc79bSRoger Quadros return ret; 1741f09cc79bSRoger Quadros 1742f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1743f09cc79bSRoger Quadros 1744f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1745f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1746f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1747f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1748f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1749f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1750f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1751f09cc79bSRoger Quadros } 1752f09cc79bSRoger Quadros 1753f09cc79bSRoger Quadros break; 1754fc8bb91bSFelipe Balbi default: 1755fc8bb91bSFelipe Balbi /* do nothing */ 1756fc8bb91bSFelipe Balbi break; 1757fc8bb91bSFelipe Balbi } 1758fc8bb91bSFelipe Balbi 1759fc8bb91bSFelipe Balbi return 0; 1760fc8bb91bSFelipe Balbi } 1761fc8bb91bSFelipe Balbi 1762fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1763fc8bb91bSFelipe Balbi { 1764689bf72cSManu Gautam switch (dwc->current_dr_role) { 1765c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1766fc8bb91bSFelipe Balbi if (dwc->connected) 1767fc8bb91bSFelipe Balbi return -EBUSY; 1768fc8bb91bSFelipe Balbi break; 1769c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1770fc8bb91bSFelipe Balbi default: 1771fc8bb91bSFelipe Balbi /* do nothing */ 1772fc8bb91bSFelipe Balbi break; 1773fc8bb91bSFelipe Balbi } 1774fc8bb91bSFelipe Balbi 1775fc8bb91bSFelipe Balbi return 0; 1776fc8bb91bSFelipe Balbi } 1777fc8bb91bSFelipe Balbi 1778fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 1779fc8bb91bSFelipe Balbi { 1780fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1781fc8bb91bSFelipe Balbi int ret; 1782fc8bb91bSFelipe Balbi 1783fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1784fc8bb91bSFelipe Balbi return -EBUSY; 1785fc8bb91bSFelipe Balbi 1786c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1787fc8bb91bSFelipe Balbi if (ret) 1788fc8bb91bSFelipe Balbi return ret; 1789fc8bb91bSFelipe Balbi 1790fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 1791fc8bb91bSFelipe Balbi 1792fc8bb91bSFelipe Balbi return 0; 1793fc8bb91bSFelipe Balbi } 1794fc8bb91bSFelipe Balbi 1795fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 1796fc8bb91bSFelipe Balbi { 1797fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1798fc8bb91bSFelipe Balbi int ret; 1799fc8bb91bSFelipe Balbi 1800fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 1801fc8bb91bSFelipe Balbi 1802c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1803fc8bb91bSFelipe Balbi if (ret) 1804fc8bb91bSFelipe Balbi return ret; 1805fc8bb91bSFelipe Balbi 1806689bf72cSManu Gautam switch (dwc->current_dr_role) { 1807689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1808fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 1809fc8bb91bSFelipe Balbi break; 1810689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1811fc8bb91bSFelipe Balbi default: 1812fc8bb91bSFelipe Balbi /* do nothing */ 1813fc8bb91bSFelipe Balbi break; 1814fc8bb91bSFelipe Balbi } 1815fc8bb91bSFelipe Balbi 1816fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1817fc8bb91bSFelipe Balbi 1818fc8bb91bSFelipe Balbi return 0; 1819fc8bb91bSFelipe Balbi } 1820fc8bb91bSFelipe Balbi 1821fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 1822fc8bb91bSFelipe Balbi { 1823fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1824fc8bb91bSFelipe Balbi 1825689bf72cSManu Gautam switch (dwc->current_dr_role) { 1826689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1827fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1828fc8bb91bSFelipe Balbi return -EBUSY; 1829fc8bb91bSFelipe Balbi break; 1830689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1831fc8bb91bSFelipe Balbi default: 1832fc8bb91bSFelipe Balbi /* do nothing */ 1833fc8bb91bSFelipe Balbi break; 1834fc8bb91bSFelipe Balbi } 1835fc8bb91bSFelipe Balbi 1836fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1837fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 1838fc8bb91bSFelipe Balbi 1839fc8bb91bSFelipe Balbi return 0; 1840fc8bb91bSFelipe Balbi } 1841fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 1842fc8bb91bSFelipe Balbi 1843fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 1844fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 1845fc8bb91bSFelipe Balbi { 1846fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1847fc8bb91bSFelipe Balbi int ret; 1848fc8bb91bSFelipe Balbi 1849c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1850fc8bb91bSFelipe Balbi if (ret) 1851fc8bb91bSFelipe Balbi return ret; 1852fc8bb91bSFelipe Balbi 18536344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 18546344475fSSekhar Nori 18557415f17cSFelipe Balbi return 0; 18567415f17cSFelipe Balbi } 18577415f17cSFelipe Balbi 18587415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 18597415f17cSFelipe Balbi { 18607415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 186157303488SKishon Vijay Abraham I int ret; 18627415f17cSFelipe Balbi 18636344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 18646344475fSSekhar Nori 1865c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 186651f5d49aSFelipe Balbi if (ret) 18675c4ad318SFelipe Balbi return ret; 18685c4ad318SFelipe Balbi 18697415f17cSFelipe Balbi pm_runtime_disable(dev); 18707415f17cSFelipe Balbi pm_runtime_set_active(dev); 18717415f17cSFelipe Balbi pm_runtime_enable(dev); 18727415f17cSFelipe Balbi 18737415f17cSFelipe Balbi return 0; 18747415f17cSFelipe Balbi } 18757f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 18767415f17cSFelipe Balbi 18777415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 18787415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1879fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1880fc8bb91bSFelipe Balbi dwc3_runtime_idle) 18817415f17cSFelipe Balbi }; 18827415f17cSFelipe Balbi 18835088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 18845088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 18855088b6f5SKishon Vijay Abraham I { 188622a5aa17SFelipe Balbi .compatible = "snps,dwc3" 188722a5aa17SFelipe Balbi }, 188822a5aa17SFelipe Balbi { 18895088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 18905088b6f5SKishon Vijay Abraham I }, 18915088b6f5SKishon Vijay Abraham I { }, 18925088b6f5SKishon Vijay Abraham I }; 18935088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 18945088b6f5SKishon Vijay Abraham I #endif 18955088b6f5SKishon Vijay Abraham I 1896404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 1897404905a6SHeikki Krogerus 1898404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 1899404905a6SHeikki Krogerus 1900404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 1901404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 1902404905a6SHeikki Krogerus { }, 1903404905a6SHeikki Krogerus }; 1904404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1905404905a6SHeikki Krogerus #endif 1906404905a6SHeikki Krogerus 190772246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 190872246da4SFelipe Balbi .probe = dwc3_probe, 19097690417dSBill Pemberton .remove = dwc3_remove, 191072246da4SFelipe Balbi .driver = { 191172246da4SFelipe Balbi .name = "dwc3", 19125088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 1913404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 19147f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 191572246da4SFelipe Balbi }, 191672246da4SFelipe Balbi }; 191772246da4SFelipe Balbi 1918b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 1919b1116dccSTobias Klauser 19207ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 192172246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 19225945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 192372246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1924