15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26d182c2e1SAndrey Smirnov #include <linux/of_graph.h> 27404905a6SHeikki Krogerus #include <linux/acpi.h> 286344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 29fe8abf33SMasahiro Yamada #include <linux/reset.h> 307bee3188SBalaji Prakash J #include <linux/bitfield.h> 3172246da4SFelipe Balbi 3272246da4SFelipe Balbi #include <linux/usb/ch9.h> 3372246da4SFelipe Balbi #include <linux/usb/gadget.h> 34f7e846f0SFelipe Balbi #include <linux/usb/of.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3672246da4SFelipe Balbi 3772246da4SFelipe Balbi #include "core.h" 3872246da4SFelipe Balbi #include "gadget.h" 3972246da4SFelipe Balbi #include "io.h" 4072246da4SFelipe Balbi 4172246da4SFelipe Balbi #include "debug.h" 4272246da4SFelipe Balbi 43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 448300dd23SFelipe Balbi 459d6173e1SThinh Nguyen /** 469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 479d6173e1SThinh Nguyen * @dwc: pointer to our context structure 489d6173e1SThinh Nguyen */ 499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 509d6173e1SThinh Nguyen { 519d6173e1SThinh Nguyen enum usb_dr_mode mode; 529d6173e1SThinh Nguyen struct device *dev = dwc->dev; 539d6173e1SThinh Nguyen unsigned int hw_mode; 549d6173e1SThinh Nguyen 559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 579d6173e1SThinh Nguyen 589d6173e1SThinh Nguyen mode = dwc->dr_mode; 599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 609d6173e1SThinh Nguyen 619d6173e1SThinh Nguyen switch (hw_mode) { 629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 649d6173e1SThinh Nguyen dev_err(dev, 659d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 669d6173e1SThinh Nguyen return -EINVAL; 679d6173e1SThinh Nguyen } 689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 699d6173e1SThinh Nguyen break; 709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 729d6173e1SThinh Nguyen dev_err(dev, 739d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 749d6173e1SThinh Nguyen return -EINVAL; 759d6173e1SThinh Nguyen } 769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 779d6173e1SThinh Nguyen break; 789d6173e1SThinh Nguyen default: 799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 83a7700468SThinh Nguyen 84a7700468SThinh Nguyen /* 8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 88a7700468SThinh Nguyen */ 89d182c2e1SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev && 908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 949d6173e1SThinh Nguyen } 959d6173e1SThinh Nguyen 969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 979d6173e1SThinh Nguyen dev_warn(dev, 989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 1009d6173e1SThinh Nguyen 1019d6173e1SThinh Nguyen dwc->dr_mode = mode; 1029d6173e1SThinh Nguyen } 1039d6173e1SThinh Nguyen 1049d6173e1SThinh Nguyen return 0; 1059d6173e1SThinh Nguyen } 1069d6173e1SThinh Nguyen 107f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1083140e8cbSSebastian Andrzej Siewior { 1093140e8cbSSebastian Andrzej Siewior u32 reg; 1103140e8cbSSebastian Andrzej Siewior 1113140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1123140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1133140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1143140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115c4a5153eSManu Gautam 116c4a5153eSManu Gautam dwc->current_dr_role = mode; 11741ce1456SRoger Quadros } 1186b3261a2SRoger Quadros 11941ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12041ce1456SRoger Quadros { 12141ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12241ce1456SRoger Quadros unsigned long flags; 12341ce1456SRoger Quadros int ret; 124f580170fSYu Chen u32 reg; 12562c73bfeSSven Peter u32 desired_dr_role; 12641ce1456SRoger Quadros 127f88359e1SYu Chen mutex_lock(&dwc->mutex); 12862c73bfeSSven Peter spin_lock_irqsave(&dwc->lock, flags); 12962c73bfeSSven Peter desired_dr_role = dwc->desired_dr_role; 13062c73bfeSSven Peter spin_unlock_irqrestore(&dwc->lock, flags); 131f88359e1SYu Chen 132c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 133c2cd3452SMartin Kepplinger 134f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 135f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 136f09cc79bSRoger Quadros 13762c73bfeSSven Peter if (!desired_dr_role) 138c2cd3452SMartin Kepplinger goto out; 13941ce1456SRoger Quadros 14062c73bfeSSven Peter if (desired_dr_role == dwc->current_dr_role) 141c2cd3452SMartin Kepplinger goto out; 14241ce1456SRoger Quadros 14362c73bfeSSven Peter if (desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 144c2cd3452SMartin Kepplinger goto out; 14541ce1456SRoger Quadros 14641ce1456SRoger Quadros switch (dwc->current_dr_role) { 14741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14841ce1456SRoger Quadros dwc3_host_exit(dwc); 14941ce1456SRoger Quadros break; 15041ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 15141ce1456SRoger Quadros dwc3_gadget_exit(dwc); 15241ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 15341ce1456SRoger Quadros break; 154f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 155f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 156f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 157f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 158f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 159f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 160f09cc79bSRoger Quadros break; 16141ce1456SRoger Quadros default: 16241ce1456SRoger Quadros break; 16341ce1456SRoger Quadros } 16441ce1456SRoger Quadros 16507903626SRohith Kollalsi /* 16607903626SRohith Kollalsi * When current_dr_role is not set, there's no role switching. 16707903626SRohith Kollalsi * Only perform GCTL.CoreSoftReset when there's DRD role switching. 16807903626SRohith Kollalsi */ 16907903626SRohith Kollalsi if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 17007903626SRohith Kollalsi DWC3_VER_IS_PRIOR(DWC31, 190A)) && 17162c73bfeSSven Peter desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 172f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 173f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 174f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 175f88359e1SYu Chen 176f88359e1SYu Chen /* 177f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 178f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 179f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 180f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 181f88359e1SYu Chen */ 182f88359e1SYu Chen msleep(100); 183f88359e1SYu Chen 184f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 185f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 186f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 187f88359e1SYu Chen } 188f88359e1SYu Chen 18941ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 19041ce1456SRoger Quadros 19162c73bfeSSven Peter dwc3_set_prtcap(dwc, desired_dr_role); 19241ce1456SRoger Quadros 19341ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 19441ce1456SRoger Quadros 19562c73bfeSSven Peter switch (desired_dr_role) { 19641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 19741ce1456SRoger Quadros ret = dwc3_host_init(dwc); 198958d1a4cSFelipe Balbi if (ret) { 19941ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 200958d1a4cSFelipe Balbi } else { 201958d1a4cSFelipe Balbi if (dwc->usb2_phy) 202958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 203958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 204644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 205f580170fSYu Chen if (dwc->dis_split_quirk) { 206f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 207f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 208f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 209f580170fSYu Chen } 210958d1a4cSFelipe Balbi } 21141ce1456SRoger Quadros break; 21241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 213f88359e1SYu Chen dwc3_core_soft_reset(dwc); 214f88359e1SYu Chen 21541ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 216958d1a4cSFelipe Balbi 217958d1a4cSFelipe Balbi if (dwc->usb2_phy) 218958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 219958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 220644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 221958d1a4cSFelipe Balbi 22241ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 22341ce1456SRoger Quadros if (ret) 22441ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 22541ce1456SRoger Quadros break; 226f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 227f09cc79bSRoger Quadros dwc3_otg_init(dwc); 228f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 229f09cc79bSRoger Quadros break; 23041ce1456SRoger Quadros default: 23141ce1456SRoger Quadros break; 23241ce1456SRoger Quadros } 233f09cc79bSRoger Quadros 234c2cd3452SMartin Kepplinger out: 235c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 236c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 237f88359e1SYu Chen mutex_unlock(&dwc->mutex); 23841ce1456SRoger Quadros } 23941ce1456SRoger Quadros 24041ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 24141ce1456SRoger Quadros { 24241ce1456SRoger Quadros unsigned long flags; 24341ce1456SRoger Quadros 244dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 245dc336b19SLi Jun return; 246dc336b19SLi Jun 24741ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 24841ce1456SRoger Quadros dwc->desired_dr_role = mode; 24941ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 25041ce1456SRoger Quadros 251084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2523140e8cbSSebastian Andrzej Siewior } 2538300dd23SFelipe Balbi 254cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 255cf6d867dSFelipe Balbi { 256cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 257cf6d867dSFelipe Balbi u32 reg; 258cf6d867dSFelipe Balbi 259cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 260cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 261cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 262cf6d867dSFelipe Balbi 263cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 264cf6d867dSFelipe Balbi 265cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 266cf6d867dSFelipe Balbi } 267cf6d867dSFelipe Balbi 26872246da4SFelipe Balbi /** 26972246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 27072246da4SFelipe Balbi * @dwc: pointer to our context structure 27172246da4SFelipe Balbi */ 2720066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 27372246da4SFelipe Balbi { 27472246da4SFelipe Balbi u32 reg; 275f59dcab1SFelipe Balbi int retries = 1000; 27672246da4SFelipe Balbi 277f59dcab1SFelipe Balbi /* 278f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 279f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 280f59dcab1SFelipe Balbi * host-only mode, then we can return early. 281f59dcab1SFelipe Balbi */ 282c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 28357303488SKishon Vijay Abraham I return 0; 284f59dcab1SFelipe Balbi 285f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 286f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 287f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP; 288f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg); 289f59dcab1SFelipe Balbi 2904749e0e6SThinh Nguyen /* 2914749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2924749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2934749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2944749e0e6SThinh Nguyen * for 10 times instead. 2954749e0e6SThinh Nguyen */ 2969af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2974749e0e6SThinh Nguyen retries = 10; 2984749e0e6SThinh Nguyen 299f59dcab1SFelipe Balbi do { 300f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 301f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 302fab38333SThinh Nguyen goto done; 303f59dcab1SFelipe Balbi 3049af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 3054749e0e6SThinh Nguyen msleep(20); 3064749e0e6SThinh Nguyen else 307f59dcab1SFelipe Balbi udelay(1); 308f59dcab1SFelipe Balbi } while (--retries); 309f59dcab1SFelipe Balbi 310859bdc35SMayank Rana dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 311f59dcab1SFelipe Balbi return -ETIMEDOUT; 312fab38333SThinh Nguyen 313fab38333SThinh Nguyen done: 314fab38333SThinh Nguyen /* 3154749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3164749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3174749e0e6SThinh Nguyen * domain (synchronization delay). 318fab38333SThinh Nguyen */ 3199af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 320fab38333SThinh Nguyen msleep(50); 321fab38333SThinh Nguyen 322fab38333SThinh Nguyen return 0; 32372246da4SFelipe Balbi } 32472246da4SFelipe Balbi 325db2be4e9SNikhil Badola /* 326db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 327db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 328db2be4e9SNikhil Badola */ 329bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 330db2be4e9SNikhil Badola { 331db2be4e9SNikhil Badola u32 reg; 332db2be4e9SNikhil Badola u32 dft; 333db2be4e9SNikhil Badola 3349af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 335db2be4e9SNikhil Badola return; 336db2be4e9SNikhil Badola 337bcdb3272SFelipe Balbi if (dwc->fladj == 0) 338db2be4e9SNikhil Badola return; 339db2be4e9SNikhil Badola 340db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 341db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 342a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 343db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 344bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 345db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 346db2be4e9SNikhil Badola } 347db2be4e9SNikhil Badola } 348db2be4e9SNikhil Badola 349c5cc74e8SHeikki Krogerus /** 3507bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3517bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3527bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3537bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3547bee3188SBalaji Prakash J * register. 3557bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3567bee3188SBalaji Prakash J */ 3577bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3587bee3188SBalaji Prakash J { 3595114c3eeSSean Anderson unsigned long period; 360596c8785SSean Anderson unsigned long fladj; 361596c8785SSean Anderson unsigned long decr; 3625114c3eeSSean Anderson unsigned long rate; 3637bee3188SBalaji Prakash J u32 reg; 3647bee3188SBalaji Prakash J 3655114c3eeSSean Anderson if (dwc->ref_clk) { 3665114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3675114c3eeSSean Anderson if (!rate) 3687bee3188SBalaji Prakash J return; 3695114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3705114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3715114c3eeSSean Anderson period = dwc->ref_clk_per; 372596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3735114c3eeSSean Anderson } else { 3745114c3eeSSean Anderson return; 3755114c3eeSSean Anderson } 3767bee3188SBalaji Prakash J 3777bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3787bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3795114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3807bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3817bee3188SBalaji Prakash J 382596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 383596c8785SSean Anderson return; 384596c8785SSean Anderson 385596c8785SSean Anderson /* 386596c8785SSean Anderson * The calculation below is 387596c8785SSean Anderson * 388596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 389596c8785SSean Anderson * 390596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 391596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 392596c8785SSean Anderson * neither does rate * period). 393596c8785SSean Anderson * 394596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 395596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 396596c8785SSean Anderson * the division when calculating rate or period (whichever one was 397596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 398596c8785SSean Anderson * scale it to units of 8 ppm. 399596c8785SSean Anderson */ 400596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 401596c8785SSean Anderson fladj -= 125000; 402596c8785SSean Anderson 403596c8785SSean Anderson /* 404596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 405596c8785SSean Anderson */ 406596c8785SSean Anderson decr = 480000000 / rate; 407596c8785SSean Anderson 408596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 409596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 410596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 411596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 412596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 413596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 414596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 415a6fc2f1bSAlexander Stein 416a6fc2f1bSAlexander Stein if (dwc->gfladj_refclk_lpm_sel) 417a6fc2f1bSAlexander Stein reg |= DWC3_GFLADJ_REFCLK_LPM_SEL; 418a6fc2f1bSAlexander Stein 419596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 420596c8785SSean Anderson } 4217bee3188SBalaji Prakash J 4227bee3188SBalaji Prakash J /** 42372246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 42472246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42572246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 42672246da4SFelipe Balbi */ 42772246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 42872246da4SFelipe Balbi struct dwc3_event_buffer *evt) 42972246da4SFelipe Balbi { 430d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 43172246da4SFelipe Balbi } 43272246da4SFelipe Balbi 43372246da4SFelipe Balbi /** 4341d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 43572246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 43672246da4SFelipe Balbi * @length: size of the event buffer 43772246da4SFelipe Balbi * 4381d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 43972246da4SFelipe Balbi * otherwise ERR_PTR(errno). 44072246da4SFelipe Balbi */ 44167d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 442ca80ca61SKushagra Verma unsigned int length) 44372246da4SFelipe Balbi { 44472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 44572246da4SFelipe Balbi 446380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 44772246da4SFelipe Balbi if (!evt) 44872246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44972246da4SFelipe Balbi 45072246da4SFelipe Balbi evt->dwc = dwc; 45172246da4SFelipe Balbi evt->length = length; 452d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 453d9fa4c63SJohn Youn if (!evt->cache) 454d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 455d9fa4c63SJohn Youn 456d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 45772246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 458e32672f0SFelipe Balbi if (!evt->buf) 45972246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 46072246da4SFelipe Balbi 46172246da4SFelipe Balbi return evt; 46272246da4SFelipe Balbi } 46372246da4SFelipe Balbi 46472246da4SFelipe Balbi /** 46572246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 46672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 46772246da4SFelipe Balbi */ 46872246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 46972246da4SFelipe Balbi { 47072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 47172246da4SFelipe Balbi 472696c8b12SFelipe Balbi evt = dwc->ev_buf; 47364b6c8a7SAnton Tikhomirov if (evt) 47472246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 47572246da4SFelipe Balbi } 47672246da4SFelipe Balbi 47772246da4SFelipe Balbi /** 47872246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4791d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 48072246da4SFelipe Balbi * @length: size of event buffer 48172246da4SFelipe Balbi * 4821d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 48372246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 48472246da4SFelipe Balbi */ 485ca80ca61SKushagra Verma static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 48672246da4SFelipe Balbi { 48772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 48872246da4SFelipe Balbi 48972246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 49072246da4SFelipe Balbi if (IS_ERR(evt)) { 49172246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 49272246da4SFelipe Balbi return PTR_ERR(evt); 49372246da4SFelipe Balbi } 494696c8b12SFelipe Balbi dwc->ev_buf = evt; 49572246da4SFelipe Balbi 49672246da4SFelipe Balbi return 0; 49772246da4SFelipe Balbi } 49872246da4SFelipe Balbi 49972246da4SFelipe Balbi /** 50072246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 5011d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 50272246da4SFelipe Balbi * 50372246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 50472246da4SFelipe Balbi */ 505f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 50672246da4SFelipe Balbi { 50772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 50872246da4SFelipe Balbi 509696c8b12SFelipe Balbi evt = dwc->ev_buf; 5107acd85e0SPaul Zimmerman evt->lpos = 0; 511660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 51272246da4SFelipe Balbi lower_32_bits(evt->dma)); 513660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 51472246da4SFelipe Balbi upper_32_bits(evt->dma)); 515660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 51668d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 517660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 51872246da4SFelipe Balbi 51972246da4SFelipe Balbi return 0; 52072246da4SFelipe Balbi } 52172246da4SFelipe Balbi 522f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 52372246da4SFelipe Balbi { 52472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 52572246da4SFelipe Balbi 526696c8b12SFelipe Balbi evt = dwc->ev_buf; 5277acd85e0SPaul Zimmerman 5287acd85e0SPaul Zimmerman evt->lpos = 0; 5297acd85e0SPaul Zimmerman 530660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 531660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 532660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 53368d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 534660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 53572246da4SFelipe Balbi } 53672246da4SFelipe Balbi 5370ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5380ffcaf37SFelipe Balbi { 5390ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5400ffcaf37SFelipe Balbi return 0; 5410ffcaf37SFelipe Balbi 5420ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5430ffcaf37SFelipe Balbi return 0; 5440ffcaf37SFelipe Balbi 5450ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5460ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5470ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5480ffcaf37SFelipe Balbi return -ENOMEM; 5490ffcaf37SFelipe Balbi 5500ffcaf37SFelipe Balbi return 0; 5510ffcaf37SFelipe Balbi } 5520ffcaf37SFelipe Balbi 5530ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5540ffcaf37SFelipe Balbi { 5550ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5560ffcaf37SFelipe Balbi u32 param; 5570ffcaf37SFelipe Balbi int ret; 5580ffcaf37SFelipe Balbi 5590ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5600ffcaf37SFelipe Balbi return 0; 5610ffcaf37SFelipe Balbi 5620ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5630ffcaf37SFelipe Balbi return 0; 5640ffcaf37SFelipe Balbi 5650ffcaf37SFelipe Balbi /* should never fall here */ 5660ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5670ffcaf37SFelipe Balbi return 0; 5680ffcaf37SFelipe Balbi 569d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5700ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5710ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 572d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 573d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5740ffcaf37SFelipe Balbi ret = -EFAULT; 5750ffcaf37SFelipe Balbi goto err0; 5760ffcaf37SFelipe Balbi } 5770ffcaf37SFelipe Balbi 5780ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5790ffcaf37SFelipe Balbi 5800ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5810ffcaf37SFelipe Balbi 5820ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5830ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5840ffcaf37SFelipe Balbi if (ret < 0) 5850ffcaf37SFelipe Balbi goto err1; 5860ffcaf37SFelipe Balbi 5870ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5880ffcaf37SFelipe Balbi 5890ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5900ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5910ffcaf37SFelipe Balbi if (ret < 0) 5920ffcaf37SFelipe Balbi goto err1; 5930ffcaf37SFelipe Balbi 5940ffcaf37SFelipe Balbi return 0; 5950ffcaf37SFelipe Balbi 5960ffcaf37SFelipe Balbi err1: 597d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5980ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5990ffcaf37SFelipe Balbi 6000ffcaf37SFelipe Balbi err0: 6010ffcaf37SFelipe Balbi return ret; 6020ffcaf37SFelipe Balbi } 6030ffcaf37SFelipe Balbi 6040ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 6050ffcaf37SFelipe Balbi { 6060ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 6070ffcaf37SFelipe Balbi return; 6080ffcaf37SFelipe Balbi 6090ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 6100ffcaf37SFelipe Balbi return; 6110ffcaf37SFelipe Balbi 6120ffcaf37SFelipe Balbi /* should never fall here */ 6130ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6140ffcaf37SFelipe Balbi return; 6150ffcaf37SFelipe Balbi 616d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6170ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6180ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6190ffcaf37SFelipe Balbi } 6200ffcaf37SFelipe Balbi 621789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 622789451f6SFelipe Balbi { 623789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 624789451f6SFelipe Balbi 62547d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 626789451f6SFelipe Balbi } 627789451f6SFelipe Balbi 62841ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 62926ceca97SFelipe Balbi { 63026ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 63126ceca97SFelipe Balbi 63226ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 63326ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 63426ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 63526ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 63626ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 63726ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 63826ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 63926ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 64026ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 64116710380SThinh Nguyen 64216710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 64316710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 64426ceca97SFelipe Balbi } 64526ceca97SFelipe Balbi 64698112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 64798112041SRoger Quadros { 64898112041SRoger Quadros int intf; 64998112041SRoger Quadros int ret = 0; 65098112041SRoger Quadros 65198112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 65298112041SRoger Quadros 65398112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 65498112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 65598112041SRoger Quadros dwc->hsphy_interface && 65698112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 65798112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 65898112041SRoger Quadros 65998112041SRoger Quadros return ret; 66098112041SRoger Quadros } 66198112041SRoger Quadros 66272246da4SFelipe Balbi /** 663b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 664b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 66588bc9d19SHeikki Krogerus * 66688bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 66788bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 66888bc9d19SHeikki Krogerus * the core in dwc3_core_init. 669b5a65c40SHuang Rui */ 67088bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 671b5a65c40SHuang Rui { 6729ba3aca8SThinh Nguyen unsigned int hw_mode; 673b5a65c40SHuang Rui u32 reg; 674b5a65c40SHuang Rui 6759ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6769ba3aca8SThinh Nguyen 677b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 678b5a65c40SHuang Rui 6792164a476SHuang Rui /* 6801966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6811966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6821966b865SFelipe Balbi */ 6831966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6841966b865SFelipe Balbi 6851966b865SFelipe Balbi /* 6862164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6872164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6882164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6892164a476SHuang Rui * to '1' after the core initialization is completed. 6902164a476SHuang Rui */ 6919af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6922164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6932164a476SHuang Rui 6949ba3aca8SThinh Nguyen /* 6959ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6969ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6979ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6989ba3aca8SThinh Nguyen */ 6999ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7009ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 7019ba3aca8SThinh Nguyen 702b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 703b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 704b5a65c40SHuang Rui 705e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 706e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 707e58dd357SRajesh Bhagat 708df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 709df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 710df31f5b3SHuang Rui 711a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 712a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 713a2a1d0f5SHuang Rui 71441c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 71541c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 71641c06ffdSHuang Rui 717fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 718fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 719fb67afcaSHuang Rui 72014f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 72114f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 72214f4ac53SHuang Rui 7236b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7246b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7256b6a0c9aSHuang Rui 726cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 72759acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 72859acfa20SHuang Rui 72900fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 73000fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 73100fe081dSWilliam Wu 732b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 733b5a65c40SHuang Rui 7342164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7352164a476SHuang Rui 7363e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7373e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7383e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 73943cacb03SFelipe Balbi if (dwc->hsphy_interface && 74043cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7413e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 74288bc9d19SHeikki Krogerus break; 74343cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 74443cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7453e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 74688bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7473e10a2ceSHeikki Krogerus } else { 74888bc9d19SHeikki Krogerus /* Relying on default value. */ 74988bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7503e10a2ceSHeikki Krogerus break; 7513e10a2ceSHeikki Krogerus } 752df561f66SGustavo A. R. Silva fallthrough; 75388bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7543e10a2ceSHeikki Krogerus default: 7553e10a2ceSHeikki Krogerus break; 7563e10a2ceSHeikki Krogerus } 7573e10a2ceSHeikki Krogerus 75832f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 75932f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 76032f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 76132f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 76232f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 76332f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 76432f2ed86SWilliam Wu break; 76532f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 76632f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 76732f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 76832f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 76932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 77032f2ed86SWilliam Wu break; 77132f2ed86SWilliam Wu default: 77232f2ed86SWilliam Wu break; 77332f2ed86SWilliam Wu } 77432f2ed86SWilliam Wu 7752164a476SHuang Rui /* 7762164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7772164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7782164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7792164a476SHuang Rui * '1' after the core initialization is completed. 7802164a476SHuang Rui */ 7819af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7822164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7832164a476SHuang Rui 7849ba3aca8SThinh Nguyen /* 7859ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7869ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7879ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7889ba3aca8SThinh Nguyen */ 7899ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7909ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7919ba3aca8SThinh Nguyen 792cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7930effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7940effe0a3SHuang Rui 795ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 796ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 797eafeacf1SThinh Nguyen else 798eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 799ec791d14SJohn Youn 800a6fc2f1bSAlexander Stein if (dwc->dis_u2_freeclk_exists_quirk || dwc->gfladj_refclk_lpm_sel) 80116199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 80216199f33SWilliam Wu 803b84ba26cSPiyush Mehta /* 804b84ba26cSPiyush Mehta * Some ULPI USB PHY does not support internal VBUS supply, to drive 805b84ba26cSPiyush Mehta * the CPEN pin requires the configuration of the ULPI DRVVBUSEXTERNAL 806b84ba26cSPiyush Mehta * bit of OTG_CTRL register. Controller configures the USB2 PHY 807b84ba26cSPiyush Mehta * ULPIEXTVBUSDRV bit[17] of the GUSB2PHYCFG register to drive vBus 808b84ba26cSPiyush Mehta * with an external supply. 809b84ba26cSPiyush Mehta */ 810b84ba26cSPiyush Mehta if (dwc->ulpi_ext_vbus_drv) 811b84ba26cSPiyush Mehta reg |= DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV; 812b84ba26cSPiyush Mehta 8132164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 81488bc9d19SHeikki Krogerus 81588bc9d19SHeikki Krogerus return 0; 816b5a65c40SHuang Rui } 817b5a65c40SHuang Rui 81833fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 81933fb697eSSean Anderson { 82033fb697eSSean Anderson int ret; 82133fb697eSSean Anderson 82233fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 82333fb697eSSean Anderson if (ret) 82433fb697eSSean Anderson return ret; 82533fb697eSSean Anderson 82633fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 82733fb697eSSean Anderson if (ret) 82833fb697eSSean Anderson goto disable_bus_clk; 82933fb697eSSean Anderson 83033fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 83133fb697eSSean Anderson if (ret) 83233fb697eSSean Anderson goto disable_ref_clk; 83333fb697eSSean Anderson 83433fb697eSSean Anderson return 0; 83533fb697eSSean Anderson 83633fb697eSSean Anderson disable_ref_clk: 83733fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 83833fb697eSSean Anderson disable_bus_clk: 83933fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 84033fb697eSSean Anderson return ret; 84133fb697eSSean Anderson } 84233fb697eSSean Anderson 84333fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 84433fb697eSSean Anderson { 84533fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 84633fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 84733fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 84833fb697eSSean Anderson } 84933fb697eSSean Anderson 850c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 851c499ff71SFelipe Balbi { 852c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 853c499ff71SFelipe Balbi 854d2ac7befSJohan Hovold usb_phy_set_suspend(dwc->usb2_phy, 1); 855d2ac7befSJohan Hovold usb_phy_set_suspend(dwc->usb3_phy, 1); 856d2ac7befSJohan Hovold phy_power_off(dwc->usb2_generic_phy); 857d2ac7befSJohan Hovold phy_power_off(dwc->usb3_generic_phy); 858d2ac7befSJohan Hovold 859c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 860c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 861c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 862c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 863c499ff71SFelipe Balbi 86433fb697eSSean Anderson dwc3_clk_disable(dwc); 865fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 866c499ff71SFelipe Balbi } 867c499ff71SFelipe Balbi 8680759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 86972246da4SFelipe Balbi { 87072246da4SFelipe Balbi u32 reg; 87172246da4SFelipe Balbi 8727650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8739af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8740759956fSFelipe Balbi 8757650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8769af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 877690fb371SJohn Youn dwc->revision = reg; 8789af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 879690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 880475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 881690fb371SJohn Youn } else { 8820759956fSFelipe Balbi return false; 8837650bd74SSebastian Andrzej Siewior } 8847650bd74SSebastian Andrzej Siewior 8850759956fSFelipe Balbi return true; 8860e1e5c47SPaul Zimmerman } 8870e1e5c47SPaul Zimmerman 888941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 88972246da4SFelipe Balbi { 89072246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 89172246da4SFelipe Balbi u32 reg; 892c499ff71SFelipe Balbi 8934878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8943e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8954878a028SSebastian Andrzej Siewior 896164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8974878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 89832a4a135SFelipe Balbi /** 89932a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 90032a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 90132a4a135SFelipe Balbi * 90232a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 90332a4a135SFelipe Balbi * configurations. 90432a4a135SFelipe Balbi * 90532a4a135SFelipe Balbi * Refers to: 90632a4a135SFelipe Balbi * 90732a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 90832a4a135SFelipe Balbi * SOF/ITP Mode Used 90932a4a135SFelipe Balbi */ 91032a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 91132a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 9129af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 91332a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 91432a4a135SFelipe Balbi else 9154878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 9164878a028SSebastian Andrzej Siewior break; 9170ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 9180ffcaf37SFelipe Balbi /* enable hibernation here */ 9190ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 9202eac3992SHuang Rui 9212eac3992SHuang Rui /* 9222eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 9232eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 9242eac3992SHuang Rui */ 9252eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9260ffcaf37SFelipe Balbi break; 9274878a028SSebastian Andrzej Siewior default: 9285eb30cedSFelipe Balbi /* nothing */ 9295eb30cedSFelipe Balbi break; 9304878a028SSebastian Andrzej Siewior } 9314878a028SSebastian Andrzej Siewior 932946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 933946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9346af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 935946bd579SHuang Rui dwc->is_fpga = true; 936946bd579SHuang Rui } 937946bd579SHuang Rui 9383b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9393b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9403b81221aSHuang Rui 9413b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9423b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9433b81221aSHuang Rui else 9443b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9453b81221aSHuang Rui 9469a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9479a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9489a5b2f31SHuang Rui 9494878a028SSebastian Andrzej Siewior /* 9504878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9511d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9524878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9531d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9544878a028SSebastian Andrzej Siewior */ 9559af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9564878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9574878a028SSebastian Andrzej Siewior 9584878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 959941f918eSFelipe Balbi } 9604878a028SSebastian Andrzej Siewior 961f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 96298112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 963f54edb53SFelipe Balbi 964d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 965d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 966d9612c2fSPengbo Mu { 967d9612c2fSPengbo Mu struct device *dev = dwc->dev; 968d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 969d9612c2fSPengbo Mu bool incrx_mode; 970d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 971d9612c2fSPengbo Mu u32 incrx_size; 972d9612c2fSPengbo Mu u32 *vals; 973d9612c2fSPengbo Mu u32 cfg; 974d9612c2fSPengbo Mu int ntype; 975d9612c2fSPengbo Mu int ret; 976d9612c2fSPengbo Mu int i; 977d9612c2fSPengbo Mu 978d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 979d9612c2fSPengbo Mu 980d9612c2fSPengbo Mu /* 981d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 982d9612c2fSPengbo Mu * Get the number of value from this property: 983d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 984d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 985d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 986d9612c2fSPengbo Mu */ 987a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 988d9612c2fSPengbo Mu if (ntype <= 0) 989d9612c2fSPengbo Mu return; 990d9612c2fSPengbo Mu 991d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 9924ea15088SKushagra Verma if (!vals) 993d9612c2fSPengbo Mu return; 994d9612c2fSPengbo Mu 995d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 996d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 997d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 998d9612c2fSPengbo Mu if (ret) { 99975ecb9ddSAndy Shevchenko kfree(vals); 1000d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 1001d9612c2fSPengbo Mu return; 1002d9612c2fSPengbo Mu } 1003d9612c2fSPengbo Mu 1004d9612c2fSPengbo Mu incrx_size = *vals; 1005d9612c2fSPengbo Mu 1006d9612c2fSPengbo Mu if (ntype > 1) { 1007d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 1008d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 1009d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 1010d9612c2fSPengbo Mu if (vals[i] > incrx_size) 1011d9612c2fSPengbo Mu incrx_size = vals[i]; 1012d9612c2fSPengbo Mu } 1013d9612c2fSPengbo Mu } else { 1014d9612c2fSPengbo Mu /* INCRX burst mode */ 1015d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 1016d9612c2fSPengbo Mu } 1017d9612c2fSPengbo Mu 101875ecb9ddSAndy Shevchenko kfree(vals); 101975ecb9ddSAndy Shevchenko 1020d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1021d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1022d9612c2fSPengbo Mu if (incrx_mode) 1023d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1024d9612c2fSPengbo Mu switch (incrx_size) { 1025d9612c2fSPengbo Mu case 256: 1026d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1027d9612c2fSPengbo Mu break; 1028d9612c2fSPengbo Mu case 128: 1029d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1030d9612c2fSPengbo Mu break; 1031d9612c2fSPengbo Mu case 64: 1032d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1033d9612c2fSPengbo Mu break; 1034d9612c2fSPengbo Mu case 32: 1035d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1036d9612c2fSPengbo Mu break; 1037d9612c2fSPengbo Mu case 16: 1038d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1039d9612c2fSPengbo Mu break; 1040d9612c2fSPengbo Mu case 8: 1041d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1042d9612c2fSPengbo Mu break; 1043d9612c2fSPengbo Mu case 4: 1044d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1045d9612c2fSPengbo Mu break; 1046d9612c2fSPengbo Mu case 1: 1047d9612c2fSPengbo Mu break; 1048d9612c2fSPengbo Mu default: 1049d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1050d9612c2fSPengbo Mu break; 1051d9612c2fSPengbo Mu } 1052d9612c2fSPengbo Mu 1053d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1054d9612c2fSPengbo Mu } 1055d9612c2fSPengbo Mu 10563497b9a5SLi Jun static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 10573497b9a5SLi Jun { 10583497b9a5SLi Jun u32 scale; 10593497b9a5SLi Jun u32 reg; 10603497b9a5SLi Jun 10613497b9a5SLi Jun if (!dwc->susp_clk) 10623497b9a5SLi Jun return; 10633497b9a5SLi Jun 10643497b9a5SLi Jun /* 10653497b9a5SLi Jun * The power down scale field specifies how many suspend_clk 10663497b9a5SLi Jun * periods fit into a 16KHz clock period. When performing 10673497b9a5SLi Jun * the division, round up the remainder. 10683497b9a5SLi Jun * 10693497b9a5SLi Jun * The power down scale value is calculated using the fastest 10703497b9a5SLi Jun * frequency of the suspend_clk. If it isn't fixed (but within 10713497b9a5SLi Jun * the accuracy requirement), the driver may not know the max 10723497b9a5SLi Jun * rate of the suspend_clk, so only update the power down scale 10733497b9a5SLi Jun * if the default is less than the calculated value from 10743497b9a5SLi Jun * clk_get_rate() or if the default is questionably high 10753497b9a5SLi Jun * (3x or more) to be within the requirement. 10763497b9a5SLi Jun */ 10773497b9a5SLi Jun scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 10783497b9a5SLi Jun reg = dwc3_readl(dwc->regs, DWC3_GCTL); 10793497b9a5SLi Jun if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 10803497b9a5SLi Jun (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 10813497b9a5SLi Jun reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 10823497b9a5SLi Jun reg |= DWC3_GCTL_PWRDNSCALE(scale); 10833497b9a5SLi Jun dwc3_writel(dwc->regs, DWC3_GCTL, reg); 10843497b9a5SLi Jun } 10853497b9a5SLi Jun } 10863497b9a5SLi Jun 1087941f918eSFelipe Balbi /** 1088941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1089941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1090941f918eSFelipe Balbi * 1091941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1092941f918eSFelipe Balbi */ 1093941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1094941f918eSFelipe Balbi { 10959ba3aca8SThinh Nguyen unsigned int hw_mode; 1096941f918eSFelipe Balbi u32 reg; 1097941f918eSFelipe Balbi int ret; 1098941f918eSFelipe Balbi 10999ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 11009ba3aca8SThinh Nguyen 1101941f918eSFelipe Balbi /* 1102941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1103941f918eSFelipe Balbi * out which kernel version a bug was found. 1104941f918eSFelipe Balbi */ 1105941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1106941f918eSFelipe Balbi 1107941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1108941f918eSFelipe Balbi if (ret) 1109941f918eSFelipe Balbi goto err0; 1110941f918eSFelipe Balbi 111198112041SRoger Quadros if (!dwc->ulpi_ready) { 111298112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 111363130462SFerry Toth if (ret) { 111463130462SFerry Toth if (ret == -ETIMEDOUT) { 111563130462SFerry Toth dwc3_core_soft_reset(dwc); 111663130462SFerry Toth ret = -EPROBE_DEFER; 111763130462SFerry Toth } 111898112041SRoger Quadros goto err0; 111963130462SFerry Toth } 112098112041SRoger Quadros dwc->ulpi_ready = true; 112198112041SRoger Quadros } 112298112041SRoger Quadros 112398112041SRoger Quadros if (!dwc->phys_ready) { 112498112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 112598112041SRoger Quadros if (ret) 112698112041SRoger Quadros goto err0a; 112798112041SRoger Quadros dwc->phys_ready = true; 112898112041SRoger Quadros } 112998112041SRoger Quadros 11308cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 11318cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 11328cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 11338cfac9a6SLi Jun if (ret < 0) 11348cfac9a6SLi Jun goto err0a; 11358cfac9a6SLi Jun 11368cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 11378cfac9a6SLi Jun if (ret < 0) { 11388cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 11398cfac9a6SLi Jun goto err0a; 11408cfac9a6SLi Jun } 11418cfac9a6SLi Jun 114298112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 114398112041SRoger Quadros if (ret) 11448cfac9a6SLi Jun goto err1; 114598112041SRoger Quadros 11469ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 11479af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 11489ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 11499ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 11509ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 11519ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 11529ba3aca8SThinh Nguyen } 11539ba3aca8SThinh Nguyen 11549ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 11559ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 11569ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 11579ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 11589ba3aca8SThinh Nguyen } 11599ba3aca8SThinh Nguyen } 11609ba3aca8SThinh Nguyen 1161941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1162c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11630ffcaf37SFelipe Balbi 11640ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11650ffcaf37SFelipe Balbi if (ret) 1166c499ff71SFelipe Balbi goto err1; 1167c499ff71SFelipe Balbi 11683497b9a5SLi Jun /* Set power down scale of suspend_clk */ 11693497b9a5SLi Jun dwc3_set_power_down_clk_scale(dwc); 11703497b9a5SLi Jun 1171c499ff71SFelipe Balbi /* Adjust Frame Length */ 1172c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1173c499ff71SFelipe Balbi 11747bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11757bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11767bee3188SBalaji Prakash J 1177d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1178d9612c2fSPengbo Mu 1179c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1180c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1181c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1182c499ff71SFelipe Balbi if (ret < 0) 11830ffcaf37SFelipe Balbi goto err2; 11840ffcaf37SFelipe Balbi 1185c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1186c499ff71SFelipe Balbi if (ret < 0) 1187c499ff71SFelipe Balbi goto err3; 1188c499ff71SFelipe Balbi 1189c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1190c499ff71SFelipe Balbi if (ret) { 1191c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1192c499ff71SFelipe Balbi goto err4; 1193c499ff71SFelipe Balbi } 1194c499ff71SFelipe Balbi 119506281d46SJohn Youn /* 119606281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 119706281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 119806281d46SJohn Youn * DWC_usb31 controller. 119906281d46SJohn Youn */ 12009af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 120106281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 120206281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 120306281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 120406281d46SJohn Youn } 120506281d46SJohn Youn 120663d7f981SPiyush Mehta /* 120763d7f981SPiyush Mehta * When configured in HOST mode, after issuing U3/L2 exit controller 120863d7f981SPiyush Mehta * fails to send proper CRC checksum in CRC5 feild. Because of this 120963d7f981SPiyush Mehta * behaviour Transaction Error is generated, resulting in reset and 121063d7f981SPiyush Mehta * re-enumeration of usb device attached. All the termsel, xcvrsel, 121163d7f981SPiyush Mehta * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 121263d7f981SPiyush Mehta * will correct this problem. This option is to support certain 121363d7f981SPiyush Mehta * legacy ULPI PHYs. 121463d7f981SPiyush Mehta */ 121563d7f981SPiyush Mehta if (dwc->resume_hs_terminations) { 121663d7f981SPiyush Mehta reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 121763d7f981SPiyush Mehta reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; 121863d7f981SPiyush Mehta dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 121963d7f981SPiyush Mehta } 122063d7f981SPiyush Mehta 12219af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 12220bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 122365db7a0cSWilliam Wu 122465db7a0cSWilliam Wu /* 122565db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 122665db7a0cSWilliam Wu * in HS when the device is in the L1 state. 122765db7a0cSWilliam Wu */ 12289af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 12290bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 123065db7a0cSWilliam Wu 1231843714bbSJack Pham /* 1232843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1233843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1234843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1235843714bbSJack Pham * from interrupting the driver. 1236843714bbSJack Pham */ 1237843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1238843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1239843714bbSJack Pham 124065db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 124165db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 124265db7a0cSWilliam Wu 12437ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 12447ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 12457ba6b09fSNeil Armstrong 124662b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 124762b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 124862b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 124962b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 125062b20e6eSBin Yang 12510bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 12520bb39ca1SJohn Youn } 12530bb39ca1SJohn Youn 1254b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1255b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1256b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1257b138e23dSAnurag Kumar Vulisha 1258b138e23dSAnurag Kumar Vulisha /* 1259b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1260b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1261b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1262b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1263b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1264b138e23dSAnurag Kumar Vulisha */ 1265b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1266b138e23dSAnurag Kumar Vulisha 1267b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1268b138e23dSAnurag Kumar Vulisha } 1269b138e23dSAnurag Kumar Vulisha 1270938a5ad1SThinh Nguyen /* 1271938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1272938a5ad1SThinh Nguyen * RX and/or TX threshold. 1273938a5ad1SThinh Nguyen */ 12749af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1275938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1276938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1277938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1278938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1279938a5ad1SThinh Nguyen 1280938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1281938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1282938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1283938a5ad1SThinh Nguyen 1284938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1285938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1286938a5ad1SThinh Nguyen 1287938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1288938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1289938a5ad1SThinh Nguyen 1290938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1291938a5ad1SThinh Nguyen } 1292938a5ad1SThinh Nguyen 1293938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1294938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1295938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1296938a5ad1SThinh Nguyen 1297938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1298938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1299938a5ad1SThinh Nguyen 1300938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1301938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1302938a5ad1SThinh Nguyen 1303938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1304938a5ad1SThinh Nguyen } 1305938a5ad1SThinh Nguyen } 1306938a5ad1SThinh Nguyen 130772246da4SFelipe Balbi return 0; 130872246da4SFelipe Balbi 1309c499ff71SFelipe Balbi err4: 13109b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1311c499ff71SFelipe Balbi 1312c499ff71SFelipe Balbi err3: 13139b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1314c499ff71SFelipe Balbi 13150ffcaf37SFelipe Balbi err2: 1316c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1317c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 13180ffcaf37SFelipe Balbi 13190ffcaf37SFelipe Balbi err1: 13200ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 13210ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 132257303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 132357303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 13240ffcaf37SFelipe Balbi 132598112041SRoger Quadros err0a: 132698112041SRoger Quadros dwc3_ulpi_exit(dwc); 132798112041SRoger Quadros 132872246da4SFelipe Balbi err0: 132972246da4SFelipe Balbi return ret; 133072246da4SFelipe Balbi } 133172246da4SFelipe Balbi 13323c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 133372246da4SFelipe Balbi { 13343c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1335941ea361SFelipe Balbi struct device_node *node = dev->of_node; 13363c9f94acSFelipe Balbi int ret; 133772246da4SFelipe Balbi 13385088b6f5SKishon Vijay Abraham I if (node) { 13395088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 13405088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1341bb674907SFelipe Balbi } else { 1342bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1343bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 13445088b6f5SKishon Vijay Abraham I } 13455088b6f5SKishon Vijay Abraham I 1346d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1347d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1348d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1349122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1350d090c7a2SKushagra Verma else 13510c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1352122f06e6SKishon Vijay Abraham I } 135351e1e7bcSFelipe Balbi 1354d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1355315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1356d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1357122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1358d090c7a2SKushagra Verma else 13590c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1360122f06e6SKishon Vijay Abraham I } 136151e1e7bcSFelipe Balbi 136257303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 136357303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 136457303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 1365fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 136657303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 1367d090c7a2SKushagra Verma else 13680c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 136957303488SKishon Vijay Abraham I } 137057303488SKishon Vijay Abraham I 137157303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 137257303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 137357303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 1374fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 137557303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 1376d090c7a2SKushagra Verma else 13770c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 137857303488SKishon Vijay Abraham I } 137957303488SKishon Vijay Abraham I 13803c9f94acSFelipe Balbi return 0; 13813c9f94acSFelipe Balbi } 13823c9f94acSFelipe Balbi 13835f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13845f94adfeSFelipe Balbi { 13855f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13865f94adfeSFelipe Balbi int ret; 13875f94adfeSFelipe Balbi 13885f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13895f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 139041ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1391958d1a4cSFelipe Balbi 1392958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1393958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1394958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1395644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1396958d1a4cSFelipe Balbi 13975f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13980c0a20f6SAndy Shevchenko if (ret) 13990c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 14005f94adfeSFelipe Balbi break; 14015f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 140241ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1403958d1a4cSFelipe Balbi 1404958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1405958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1406958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1407644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1408958d1a4cSFelipe Balbi 14095f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 14100c0a20f6SAndy Shevchenko if (ret) 14110c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 14125f94adfeSFelipe Balbi break; 14135f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 141441ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 14159840354fSRoger Quadros ret = dwc3_drd_init(dwc); 14160c0a20f6SAndy Shevchenko if (ret) 14170c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 14185f94adfeSFelipe Balbi break; 14195f94adfeSFelipe Balbi default: 14205f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 14215f94adfeSFelipe Balbi return -EINVAL; 14225f94adfeSFelipe Balbi } 14235f94adfeSFelipe Balbi 14245f94adfeSFelipe Balbi return 0; 14255f94adfeSFelipe Balbi } 14265f94adfeSFelipe Balbi 14275f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 14285f94adfeSFelipe Balbi { 14295f94adfeSFelipe Balbi switch (dwc->dr_mode) { 14305f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 14315f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 14325f94adfeSFelipe Balbi break; 14335f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 14345f94adfeSFelipe Balbi dwc3_host_exit(dwc); 14355f94adfeSFelipe Balbi break; 14365f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 14379840354fSRoger Quadros dwc3_drd_exit(dwc); 14385f94adfeSFelipe Balbi break; 14395f94adfeSFelipe Balbi default: 14405f94adfeSFelipe Balbi /* do nothing */ 14415f94adfeSFelipe Balbi break; 14425f94adfeSFelipe Balbi } 144309ed259fSBin Liu 144409ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 144509ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 14465f94adfeSFelipe Balbi } 14475f94adfeSFelipe Balbi 1448c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 14493c9f94acSFelipe Balbi { 1450c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 145180caf7d2SHuang Rui u8 lpm_nyet_threshold; 14526b6a0c9aSHuang Rui u8 tx_de_emphasis; 1453460d098cSHuang Rui u8 hird_threshold; 1454f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0; 1455f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0; 1456f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0; 1457f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0; 14589f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 14596f0764b5SRay Chi const char *usb_psy_name; 14606f0764b5SRay Chi int ret; 14613c9f94acSFelipe Balbi 146280caf7d2SHuang Rui /* default to highest possible threshold */ 14638d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 146480caf7d2SHuang Rui 14656b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 14666b6a0c9aSHuang Rui tx_de_emphasis = 1; 14676b6a0c9aSHuang Rui 1468460d098cSHuang Rui /* 1469460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1470460d098cSHuang Rui * threshold value of 0b1100 1471460d098cSHuang Rui */ 1472460d098cSHuang Rui hird_threshold = 12; 1473460d098cSHuang Rui 14749f607a30SWesley Cheng /* 14759f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 14769f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14779f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14789f607a30SWesley Cheng */ 14799f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14809f607a30SWesley Cheng 148163863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 148267848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 148306e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 148432f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 148563863b98SHeikki Krogerus 1486d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1487d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1488d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1489d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1490d64ff406SArnd Bergmann else 1491d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1492d64ff406SArnd Bergmann 14936f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14946f0764b5SRay Chi if (ret >= 0) { 14956f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14966f0764b5SRay Chi if (!dwc->usb_psy) 14976f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14986f0764b5SRay Chi } 14996f0764b5SRay Chi 15003d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 150180caf7d2SHuang Rui "snps,has-lpm-erratum"); 15023d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 150380caf7d2SHuang Rui &lpm_nyet_threshold); 15043d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1505460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 15063d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1507460d098cSHuang Rui &hird_threshold); 1508d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1509d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 15103d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1511eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1512022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1513022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1514475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1515475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1516938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1517938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1518938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1519938a5ad1SThinh Nguyen &rx_max_burst_prd); 1520938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1521938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1522938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1523938a5ad1SThinh Nguyen &tx_max_burst_prd); 15249f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 15259f607a30SWesley Cheng "tx-fifo-resize"); 15269f607a30SWesley Cheng if (dwc->do_fifo_resize) 15279f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 15289f607a30SWesley Cheng &tx_fifo_resize_max_num); 15293c9f94acSFelipe Balbi 15303d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 15313b81221aSHuang Rui "snps,disable_scramble_quirk"); 15323d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 15339a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 15343d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1535b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 15363d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1537df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 15383d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1539a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 15403d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 154141c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 15423d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1543fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 15443d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 154514f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 15463d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 154759acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 15483d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 15490effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1550ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1551ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1552729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1553729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1554729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1555729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1556e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1557e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 155816199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 155916199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 156000fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 156100fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 156265db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 156365db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 156463d7f981SPiyush Mehta dwc->resume_hs_terminations = device_property_read_bool(dev, 156563d7f981SPiyush Mehta "snps,resume-hs-terminations"); 1566b84ba26cSPiyush Mehta dwc->ulpi_ext_vbus_drv = device_property_read_bool(dev, 1567b84ba26cSPiyush Mehta "snps,ulpi-ext-vbus-drv"); 15687ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 15697ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 1570a6fc2f1bSAlexander Stein dwc->gfladj_refclk_lpm_sel = device_property_read_bool(dev, 1571a6fc2f1bSAlexander Stein "snps,gfladj-refclk-lpm-sel-quirk"); 15726b6a0c9aSHuang Rui 15733d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 15746b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 15753d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 15766b6a0c9aSHuang Rui &tx_de_emphasis); 15773d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 15783e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 15793d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1580bcdb3272SFelipe Balbi &dwc->fladj); 15817bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 15827bee3188SBalaji Prakash J &dwc->ref_clk_per); 15833d128919SHeikki Krogerus 158442bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 158542bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 158642bf02ecSRoger Quadros 1587f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1588f580170fSYu Chen "snps,dis-split-quirk"); 1589f580170fSYu Chen 159080caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15916b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 159280caf7d2SHuang Rui 159316fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1594460d098cSHuang Rui 1595938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1596938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1597938a5ad1SThinh Nguyen 1598938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1599938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1600938a5ad1SThinh Nguyen 1601cf40b86bSJohn Youn dwc->imod_interval = 0; 16029f607a30SWesley Cheng 16039f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1604cf40b86bSJohn Youn } 1605cf40b86bSJohn Youn 1606cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1607cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1608cf40b86bSJohn Youn { 16099af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 16109af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 16119af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1612c5ac6116SFelipe Balbi } 1613c5ac6116SFelipe Balbi 16147ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 16157ac51a12SJohn Youn { 16167ac51a12SJohn Youn struct device *dev = dwc->dev; 1617b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1618b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 16197ac51a12SJohn Youn 1620cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1621cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1622cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1623cf40b86bSJohn Youn dwc->imod_interval = 0; 1624cf40b86bSJohn Youn } 1625cf40b86bSJohn Youn 162628632b44SJohn Youn /* 162728632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 162828632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 162928632b44SJohn Youn * interrupt from being masked while handling events. IMOD 163028632b44SJohn Youn * allows us to work around this issue. Enable it for the 163128632b44SJohn Youn * affected version. 163228632b44SJohn Youn */ 163328632b44SJohn Youn if (!dwc->imod_interval && 16349af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 163528632b44SJohn Youn dwc->imod_interval = 1; 163628632b44SJohn Youn 16377ac51a12SJohn Youn /* Check the maximum_speed parameter */ 16387ac51a12SJohn Youn switch (dwc->maximum_speed) { 16397ac51a12SJohn Youn case USB_SPEED_FULL: 16407ac51a12SJohn Youn case USB_SPEED_HIGH: 1641e518bdd9SThinh Nguyen break; 16427ac51a12SJohn Youn case USB_SPEED_SUPER: 1643e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1644e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1645e518bdd9SThinh Nguyen break; 16467ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1647e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1648e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1649e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1650e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1651e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 16527ac51a12SJohn Youn break; 16537ac51a12SJohn Youn default: 16547ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 16557ac51a12SJohn Youn dwc->maximum_speed); 1656df561f66SGustavo A. R. Silva fallthrough; 16577ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1658b574ce3eSThinh Nguyen switch (hwparam_gen) { 1659b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 16607ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1661b574ce3eSThinh Nguyen break; 1662b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1663b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1664b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1665b574ce3eSThinh Nguyen else 1666b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1667b574ce3eSThinh Nguyen break; 1668b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1669b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1670b574ce3eSThinh Nguyen break; 1671b574ce3eSThinh Nguyen default: 1672b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1673b574ce3eSThinh Nguyen break; 1674b574ce3eSThinh Nguyen } 16757ac51a12SJohn Youn break; 16767ac51a12SJohn Youn } 167767848146SThinh Nguyen 167867848146SThinh Nguyen /* 167967848146SThinh Nguyen * Currently the controller does not have visibility into the HW 168067848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 168167848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 168267848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 168367848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 168467848146SThinh Nguyen */ 168567848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 168667848146SThinh Nguyen switch (dwc->max_ssp_rate) { 168767848146SThinh Nguyen case USB_SSP_GEN_2x1: 168867848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 168967848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 169067848146SThinh Nguyen break; 169167848146SThinh Nguyen case USB_SSP_GEN_1x2: 169267848146SThinh Nguyen case USB_SSP_GEN_2x2: 169367848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 169467848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 169567848146SThinh Nguyen break; 169667848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 169767848146SThinh Nguyen default: 169867848146SThinh Nguyen switch (hwparam_gen) { 169967848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 170067848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 170167848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 170267848146SThinh Nguyen else 170367848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 170467848146SThinh Nguyen break; 170567848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 170667848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 170767848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 170867848146SThinh Nguyen break; 170967848146SThinh Nguyen } 171067848146SThinh Nguyen break; 171167848146SThinh Nguyen } 171267848146SThinh Nguyen } 17137ac51a12SJohn Youn } 17147ac51a12SJohn Youn 1715d182c2e1SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 1716d182c2e1SAndrey Smirnov { 1717d182c2e1SAndrey Smirnov struct device *dev = dwc->dev; 1718d182c2e1SAndrey Smirnov struct device_node *np_phy; 1719d182c2e1SAndrey Smirnov struct extcon_dev *edev = NULL; 1720d182c2e1SAndrey Smirnov const char *name; 1721d182c2e1SAndrey Smirnov 1722d182c2e1SAndrey Smirnov if (device_property_read_bool(dev, "extcon")) 1723d182c2e1SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0); 1724d182c2e1SAndrey Smirnov 1725d182c2e1SAndrey Smirnov /* 1726d182c2e1SAndrey Smirnov * Device tree platforms should get extcon via phandle. 1727d182c2e1SAndrey Smirnov * On ACPI platforms, we get the name from a device property. 1728d182c2e1SAndrey Smirnov * This device property is for kernel internal use only and 1729d182c2e1SAndrey Smirnov * is expected to be set by the glue code. 1730d182c2e1SAndrey Smirnov */ 1731d182c2e1SAndrey Smirnov if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 1732d182c2e1SAndrey Smirnov return extcon_get_extcon_dev(name); 1733d182c2e1SAndrey Smirnov 1734d182c2e1SAndrey Smirnov /* 1735d68cc25bSJanne Grunau * Check explicitly if "usb-role-switch" is used since 1736d68cc25bSJanne Grunau * extcon_find_edev_by_node() can not be used to check the absence of 1737d68cc25bSJanne Grunau * an extcon device. In the absence of an device it will always return 1738d68cc25bSJanne Grunau * EPROBE_DEFER. 1739d68cc25bSJanne Grunau */ 1740d68cc25bSJanne Grunau if (IS_ENABLED(CONFIG_USB_ROLE_SWITCH) && 1741d68cc25bSJanne Grunau device_property_read_bool(dev, "usb-role-switch")) 1742d68cc25bSJanne Grunau return NULL; 1743d68cc25bSJanne Grunau 1744d68cc25bSJanne Grunau /* 1745d182c2e1SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port" 1746d182c2e1SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the 1747d182c2e1SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon 1748d182c2e1SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch" 1749d182c2e1SAndrey Smirnov * or OTG mode. 1750d182c2e1SAndrey Smirnov */ 1751d182c2e1SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0); 1752d182c2e1SAndrey Smirnov if (of_graph_is_present(np_phy)) { 1753d182c2e1SAndrey Smirnov struct device_node *np_conn; 1754d182c2e1SAndrey Smirnov 1755d182c2e1SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1); 1756d182c2e1SAndrey Smirnov if (np_conn) 1757d182c2e1SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn); 1758d182c2e1SAndrey Smirnov of_node_put(np_conn); 1759d182c2e1SAndrey Smirnov } 1760d182c2e1SAndrey Smirnov of_node_put(np_phy); 1761d182c2e1SAndrey Smirnov 1762d182c2e1SAndrey Smirnov return edev; 1763d182c2e1SAndrey Smirnov } 1764d182c2e1SAndrey Smirnov 1765c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1766c5ac6116SFelipe Balbi { 1767c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 176844feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1769c5ac6116SFelipe Balbi struct dwc3 *dwc; 1770c5ac6116SFelipe Balbi 1771c5ac6116SFelipe Balbi int ret; 1772c5ac6116SFelipe Balbi 1773c5ac6116SFelipe Balbi void __iomem *regs; 1774c5ac6116SFelipe Balbi 1775c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1776c5ac6116SFelipe Balbi if (!dwc) 1777c5ac6116SFelipe Balbi return -ENOMEM; 1778c5ac6116SFelipe Balbi 1779c5ac6116SFelipe Balbi dwc->dev = dev; 1780c5ac6116SFelipe Balbi 1781c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1782c5ac6116SFelipe Balbi if (!res) { 1783c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1784c5ac6116SFelipe Balbi return -ENODEV; 1785c5ac6116SFelipe Balbi } 1786c5ac6116SFelipe Balbi 1787c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1788c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1789c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1790c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1791c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1792c5ac6116SFelipe Balbi 1793c5ac6116SFelipe Balbi /* 1794c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1795c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1796c5ac6116SFelipe Balbi */ 179744feb8e6SMasahiro Yamada dwc_res = *res; 179844feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 179944feb8e6SMasahiro Yamada 180044feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 180144feb8e6SMasahiro Yamada if (IS_ERR(regs)) 180244feb8e6SMasahiro Yamada return PTR_ERR(regs); 1803c5ac6116SFelipe Balbi 1804c5ac6116SFelipe Balbi dwc->regs = regs; 180544feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1806c5ac6116SFelipe Balbi 1807c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1808c5ac6116SFelipe Balbi 1809babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 18102a735e4bSDan Carpenter if (IS_ERR(dwc->reset)) { 18112a735e4bSDan Carpenter ret = PTR_ERR(dwc->reset); 18122a735e4bSDan Carpenter goto put_usb_psy; 18132a735e4bSDan Carpenter } 1814fe8abf33SMasahiro Yamada 181561527777SHans de Goede if (dev->of_node) { 1816fe8abf33SMasahiro Yamada /* 181761527777SHans de Goede * Clocks are optional, but new DT platforms should support all 181861527777SHans de Goede * clocks as required by the DT-binding. 18194e64cd77SPeter Geis * Some devices have different clock names in legacy device trees, 18204e64cd77SPeter Geis * check for them to retain backwards compatibility. 1821fe8abf33SMasahiro Yamada */ 182233fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 18232a735e4bSDan Carpenter if (IS_ERR(dwc->bus_clk)) { 18242a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 182533fb697eSSean Anderson "could not get bus clock\n"); 18262a735e4bSDan Carpenter goto put_usb_psy; 18272a735e4bSDan Carpenter } 18280d3a9708SJohn Stultz 18294e64cd77SPeter Geis if (dwc->bus_clk == NULL) { 18304e64cd77SPeter Geis dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 18312a735e4bSDan Carpenter if (IS_ERR(dwc->bus_clk)) { 18322a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 18334e64cd77SPeter Geis "could not get bus clock\n"); 18342a735e4bSDan Carpenter goto put_usb_psy; 18352a735e4bSDan Carpenter } 18364e64cd77SPeter Geis } 18374e64cd77SPeter Geis 183833fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 18392a735e4bSDan Carpenter if (IS_ERR(dwc->ref_clk)) { 18402a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 184133fb697eSSean Anderson "could not get ref clock\n"); 18422a735e4bSDan Carpenter goto put_usb_psy; 18432a735e4bSDan Carpenter } 184433fb697eSSean Anderson 18454e64cd77SPeter Geis if (dwc->ref_clk == NULL) { 18464e64cd77SPeter Geis dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 18472a735e4bSDan Carpenter if (IS_ERR(dwc->ref_clk)) { 18482a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 18494e64cd77SPeter Geis "could not get ref clock\n"); 18502a735e4bSDan Carpenter goto put_usb_psy; 18512a735e4bSDan Carpenter } 18524e64cd77SPeter Geis } 18534e64cd77SPeter Geis 185433fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 18552a735e4bSDan Carpenter if (IS_ERR(dwc->susp_clk)) { 18562a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 185733fb697eSSean Anderson "could not get suspend clock\n"); 18582a735e4bSDan Carpenter goto put_usb_psy; 18592a735e4bSDan Carpenter } 18604e64cd77SPeter Geis 18614e64cd77SPeter Geis if (dwc->susp_clk == NULL) { 18624e64cd77SPeter Geis dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 18632a735e4bSDan Carpenter if (IS_ERR(dwc->susp_clk)) { 18642a735e4bSDan Carpenter ret = dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 18654e64cd77SPeter Geis "could not get suspend clock\n"); 18662a735e4bSDan Carpenter goto put_usb_psy; 18672a735e4bSDan Carpenter } 18684e64cd77SPeter Geis } 186961527777SHans de Goede } 1870fe8abf33SMasahiro Yamada 1871fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1872fe8abf33SMasahiro Yamada if (ret) 18732a735e4bSDan Carpenter goto put_usb_psy; 1874fe8abf33SMasahiro Yamada 187533fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1876fe8abf33SMasahiro Yamada if (ret) 1877fe8abf33SMasahiro Yamada goto assert_reset; 1878fe8abf33SMasahiro Yamada 1879dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1880dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1881dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1882dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1883dc1b5d9aSEnric Balletbo i Serra } 1884dc1b5d9aSEnric Balletbo i Serra 18856c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 18862917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 18876c89cce0SHeikki Krogerus 188891062e66SWilliam Wu if (!dwc->sysdev_is_parent && 188991062e66SWilliam Wu DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) { 189091062e66SWilliam Wu ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 189191062e66SWilliam Wu if (ret) 189291062e66SWilliam Wu goto disable_clks; 189391062e66SWilliam Wu } 189491062e66SWilliam Wu 189572246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1896f88359e1SYu Chen mutex_init(&dwc->mutex); 189772246da4SFelipe Balbi 18989a8ad10cSJohan Hovold pm_runtime_get_noresume(dev); 1899fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1900fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1901fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1902802ca850SChanho Park pm_runtime_enable(dev); 190332808237SRoger Quadros 1904802ca850SChanho Park pm_runtime_forbid(dev); 190572246da4SFelipe Balbi 19063921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 19073921426bSFelipe Balbi if (ret) { 19083921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 19093921426bSFelipe Balbi ret = -ENOMEM; 191032808237SRoger Quadros goto err2; 19113921426bSFelipe Balbi } 19123921426bSFelipe Balbi 1913d182c2e1SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc); 1914d182c2e1SAndrey Smirnov if (IS_ERR(dwc->edev)) { 1915d182c2e1SAndrey Smirnov ret = dev_err_probe(dwc->dev, PTR_ERR(dwc->edev), "failed to get extcon\n"); 1916d182c2e1SAndrey Smirnov goto err3; 1917d182c2e1SAndrey Smirnov } 1918d182c2e1SAndrey Smirnov 19199d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 19209d6173e1SThinh Nguyen if (ret) 19219d6173e1SThinh Nguyen goto err3; 192232a4a135SFelipe Balbi 1923c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1924c499ff71SFelipe Balbi if (ret) 192532808237SRoger Quadros goto err3; 1926c499ff71SFelipe Balbi 192772246da4SFelipe Balbi ret = dwc3_core_init(dwc); 192872246da4SFelipe Balbi if (ret) { 19290c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 193032808237SRoger Quadros goto err4; 193172246da4SFelipe Balbi } 193272246da4SFelipe Balbi 19337ac51a12SJohn Youn dwc3_check_params(dwc); 193484524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 19352c7f1bd9SJohn Youn 19365f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 19375f94adfeSFelipe Balbi if (ret) 193832808237SRoger Quadros goto err5; 193972246da4SFelipe Balbi 1940fc8bb91bSFelipe Balbi pm_runtime_put(dev); 194172246da4SFelipe Balbi 194272246da4SFelipe Balbi return 0; 194372246da4SFelipe Balbi 194432808237SRoger Quadros err5: 194584524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1946f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 194703c1fd62SLi Jun 194803c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 194903c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 195003c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 195103c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 195203c1fd62SLi Jun 1953d2ac7befSJohan Hovold usb_phy_shutdown(dwc->usb2_phy); 1954d2ac7befSJohan Hovold usb_phy_shutdown(dwc->usb3_phy); 1955d2ac7befSJohan Hovold phy_exit(dwc->usb2_generic_phy); 1956d2ac7befSJohan Hovold phy_exit(dwc->usb3_generic_phy); 1957d2ac7befSJohan Hovold 195808fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1959f122d33eSFelipe Balbi 196032808237SRoger Quadros err4: 1961c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 196272246da4SFelipe Balbi 196332808237SRoger Quadros err3: 19643921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 19653921426bSFelipe Balbi 196632808237SRoger Quadros err2: 19679a8ad10cSJohan Hovold pm_runtime_allow(dev); 19689a8ad10cSJohan Hovold pm_runtime_disable(dev); 1969*6b3b2402SJohan Hovold pm_runtime_dont_use_autosuspend(dev); 19709a8ad10cSJohan Hovold pm_runtime_set_suspended(dev); 19719a8ad10cSJohan Hovold pm_runtime_put_noidle(dev); 1972dc1b5d9aSEnric Balletbo i Serra disable_clks: 197333fb697eSSean Anderson dwc3_clk_disable(dwc); 1974fe8abf33SMasahiro Yamada assert_reset: 1975fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 19762a735e4bSDan Carpenter put_usb_psy: 1977b0bf77cdSColin Ian King if (dwc->usb_psy) 19786f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19796f0764b5SRay Chi 198072246da4SFelipe Balbi return ret; 198172246da4SFelipe Balbi } 198272246da4SFelipe Balbi 1983fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 198472246da4SFelipe Balbi { 198572246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 19863da1f6eeSFelipe Balbi 1987fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 198872246da4SFelipe Balbi 1989dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 19902a042767SPeter Chen dwc3_debugfs_exit(dwc); 19918ba007a9SKishon Vijay Abraham I 199272246da4SFelipe Balbi dwc3_core_exit(dwc); 199388bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 199472246da4SFelipe Balbi 199544d257e9SJohan Hovold pm_runtime_allow(&pdev->dev); 1996fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1997*6b3b2402SJohan Hovold pm_runtime_dont_use_autosuspend(&pdev->dev); 1998266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1999266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 2000fc8bb91bSFelipe Balbi 2001c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 2002c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 2003c499ff71SFelipe Balbi 2004b0bf77cdSColin Ian King if (dwc->usb_psy) 20056f0764b5SRay Chi power_supply_put(dwc->usb_psy); 20066f0764b5SRay Chi 200772246da4SFelipe Balbi return 0; 200872246da4SFelipe Balbi } 200972246da4SFelipe Balbi 2010fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 2011fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 2012fe8abf33SMasahiro Yamada { 2013fe8abf33SMasahiro Yamada int ret; 2014fe8abf33SMasahiro Yamada 2015fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 2016fe8abf33SMasahiro Yamada if (ret) 2017fe8abf33SMasahiro Yamada return ret; 2018fe8abf33SMasahiro Yamada 201933fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 2020fe8abf33SMasahiro Yamada if (ret) 2021fe8abf33SMasahiro Yamada goto assert_reset; 2022fe8abf33SMasahiro Yamada 2023fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 2024fe8abf33SMasahiro Yamada if (ret) 2025fe8abf33SMasahiro Yamada goto disable_clks; 2026fe8abf33SMasahiro Yamada 2027fe8abf33SMasahiro Yamada return 0; 2028fe8abf33SMasahiro Yamada 2029fe8abf33SMasahiro Yamada disable_clks: 203033fb697eSSean Anderson dwc3_clk_disable(dwc); 2031fe8abf33SMasahiro Yamada assert_reset: 2032fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 2033fe8abf33SMasahiro Yamada 2034fe8abf33SMasahiro Yamada return ret; 2035fe8abf33SMasahiro Yamada } 2036fe8abf33SMasahiro Yamada 2037c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 20387415f17cSFelipe Balbi { 2039fc8bb91bSFelipe Balbi unsigned long flags; 2040bcb12877SManu Gautam u32 reg; 20417415f17cSFelipe Balbi 2042689bf72cSManu Gautam switch (dwc->current_dr_role) { 2043689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 20440227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 20450227cc84SLi Jun break; 20467415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 204741a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2048689bf72cSManu Gautam dwc3_core_exit(dwc); 204951f5d49aSFelipe Balbi break; 2050689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2051e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2052c4a5153eSManu Gautam dwc3_core_exit(dwc); 2053c4a5153eSManu Gautam break; 2054bcb12877SManu Gautam } 2055bcb12877SManu Gautam 2056bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 2057bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 2058bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 2059bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2060bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 2061bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 2062bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2063bcb12877SManu Gautam 2064bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 2065bcb12877SManu Gautam usleep_range(5000, 6000); 2066bcb12877SManu Gautam } 2067bcb12877SManu Gautam 2068bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2069bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2070bcb12877SManu Gautam break; 2071f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2072f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 2073f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2074f09cc79bSRoger Quadros break; 2075f09cc79bSRoger Quadros 2076f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2077f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2078f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 2079f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 208041a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2081f09cc79bSRoger Quadros } 2082f09cc79bSRoger Quadros 2083f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 2084f09cc79bSRoger Quadros dwc3_core_exit(dwc); 2085f09cc79bSRoger Quadros break; 20867415f17cSFelipe Balbi default: 208751f5d49aSFelipe Balbi /* do nothing */ 20887415f17cSFelipe Balbi break; 20897415f17cSFelipe Balbi } 20907415f17cSFelipe Balbi 2091fc8bb91bSFelipe Balbi return 0; 2092fc8bb91bSFelipe Balbi } 2093fc8bb91bSFelipe Balbi 2094c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2095fc8bb91bSFelipe Balbi { 2096fc8bb91bSFelipe Balbi unsigned long flags; 2097fc8bb91bSFelipe Balbi int ret; 2098bcb12877SManu Gautam u32 reg; 2099fc8bb91bSFelipe Balbi 2100689bf72cSManu Gautam switch (dwc->current_dr_role) { 2101689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2102fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2103fc8bb91bSFelipe Balbi if (ret) 2104fc8bb91bSFelipe Balbi return ret; 2105fc8bb91bSFelipe Balbi 21067d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2107fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 2108689bf72cSManu Gautam break; 2109689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2110e3fafbd8SJohan Hovold if (!PMSG_IS_AUTO(msg) && !device_may_wakeup(dwc->dev)) { 2111fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2112c4a5153eSManu Gautam if (ret) 2113c4a5153eSManu Gautam return ret; 21147d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2115bcb12877SManu Gautam break; 2116c4a5153eSManu Gautam } 2117bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2118bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2119bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 2120bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2121bcb12877SManu Gautam 2122bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 2123bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2124bcb12877SManu Gautam 2125bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2126bcb12877SManu Gautam 2127bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2128bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2129c4a5153eSManu Gautam break; 2130f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2131f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 2132f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2133f09cc79bSRoger Quadros break; 2134f09cc79bSRoger Quadros 21350e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 2136f09cc79bSRoger Quadros if (ret) 2137f09cc79bSRoger Quadros return ret; 2138f09cc79bSRoger Quadros 2139f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 2140f09cc79bSRoger Quadros 2141f09cc79bSRoger Quadros dwc3_otg_init(dwc); 2142f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2143f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 2144f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2145f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2146f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 2147f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 2148f09cc79bSRoger Quadros } 2149f09cc79bSRoger Quadros 2150f09cc79bSRoger Quadros break; 2151fc8bb91bSFelipe Balbi default: 2152fc8bb91bSFelipe Balbi /* do nothing */ 2153fc8bb91bSFelipe Balbi break; 2154fc8bb91bSFelipe Balbi } 2155fc8bb91bSFelipe Balbi 2156fc8bb91bSFelipe Balbi return 0; 2157fc8bb91bSFelipe Balbi } 2158fc8bb91bSFelipe Balbi 2159fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 2160fc8bb91bSFelipe Balbi { 2161689bf72cSManu Gautam switch (dwc->current_dr_role) { 2162c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2163fc8bb91bSFelipe Balbi if (dwc->connected) 2164fc8bb91bSFelipe Balbi return -EBUSY; 2165fc8bb91bSFelipe Balbi break; 2166c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2167fc8bb91bSFelipe Balbi default: 2168fc8bb91bSFelipe Balbi /* do nothing */ 2169fc8bb91bSFelipe Balbi break; 2170fc8bb91bSFelipe Balbi } 2171fc8bb91bSFelipe Balbi 2172fc8bb91bSFelipe Balbi return 0; 2173fc8bb91bSFelipe Balbi } 2174fc8bb91bSFelipe Balbi 2175fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2176fc8bb91bSFelipe Balbi { 2177fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2178fc8bb91bSFelipe Balbi int ret; 2179fc8bb91bSFelipe Balbi 2180fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2181fc8bb91bSFelipe Balbi return -EBUSY; 2182fc8bb91bSFelipe Balbi 2183c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2184fc8bb91bSFelipe Balbi if (ret) 2185fc8bb91bSFelipe Balbi return ret; 2186fc8bb91bSFelipe Balbi 2187fc8bb91bSFelipe Balbi return 0; 2188fc8bb91bSFelipe Balbi } 2189fc8bb91bSFelipe Balbi 2190fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2191fc8bb91bSFelipe Balbi { 2192fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2193fc8bb91bSFelipe Balbi int ret; 2194fc8bb91bSFelipe Balbi 2195c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2196fc8bb91bSFelipe Balbi if (ret) 2197fc8bb91bSFelipe Balbi return ret; 2198fc8bb91bSFelipe Balbi 2199689bf72cSManu Gautam switch (dwc->current_dr_role) { 2200689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2201fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2202fc8bb91bSFelipe Balbi break; 2203689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2204fc8bb91bSFelipe Balbi default: 2205fc8bb91bSFelipe Balbi /* do nothing */ 2206fc8bb91bSFelipe Balbi break; 2207fc8bb91bSFelipe Balbi } 2208fc8bb91bSFelipe Balbi 2209fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2210fc8bb91bSFelipe Balbi 2211fc8bb91bSFelipe Balbi return 0; 2212fc8bb91bSFelipe Balbi } 2213fc8bb91bSFelipe Balbi 2214fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2215fc8bb91bSFelipe Balbi { 2216fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2217fc8bb91bSFelipe Balbi 2218689bf72cSManu Gautam switch (dwc->current_dr_role) { 2219689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2220fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2221fc8bb91bSFelipe Balbi return -EBUSY; 2222fc8bb91bSFelipe Balbi break; 2223689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2224fc8bb91bSFelipe Balbi default: 2225fc8bb91bSFelipe Balbi /* do nothing */ 2226fc8bb91bSFelipe Balbi break; 2227fc8bb91bSFelipe Balbi } 2228fc8bb91bSFelipe Balbi 2229fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2230fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2231fc8bb91bSFelipe Balbi 2232fc8bb91bSFelipe Balbi return 0; 2233fc8bb91bSFelipe Balbi } 2234fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2235fc8bb91bSFelipe Balbi 2236fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2237fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2238fc8bb91bSFelipe Balbi { 2239fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2240fc8bb91bSFelipe Balbi int ret; 2241fc8bb91bSFelipe Balbi 2242c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2243fc8bb91bSFelipe Balbi if (ret) 2244fc8bb91bSFelipe Balbi return ret; 2245fc8bb91bSFelipe Balbi 22466344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 22476344475fSSekhar Nori 22487415f17cSFelipe Balbi return 0; 22497415f17cSFelipe Balbi } 22507415f17cSFelipe Balbi 22517415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 22527415f17cSFelipe Balbi { 22537415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 225457303488SKishon Vijay Abraham I int ret; 22557415f17cSFelipe Balbi 22566344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 22576344475fSSekhar Nori 2258c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 225951f5d49aSFelipe Balbi if (ret) 22605c4ad318SFelipe Balbi return ret; 22615c4ad318SFelipe Balbi 22627415f17cSFelipe Balbi pm_runtime_disable(dev); 22637415f17cSFelipe Balbi pm_runtime_set_active(dev); 22647415f17cSFelipe Balbi pm_runtime_enable(dev); 22657415f17cSFelipe Balbi 22667415f17cSFelipe Balbi return 0; 22677415f17cSFelipe Balbi } 2268f580170fSYu Chen 2269f580170fSYu Chen static void dwc3_complete(struct device *dev) 2270f580170fSYu Chen { 2271f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2272f580170fSYu Chen u32 reg; 2273f580170fSYu Chen 2274f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2275f580170fSYu Chen dwc->dis_split_quirk) { 2276f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2277f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2278f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2279f580170fSYu Chen } 2280f580170fSYu Chen } 2281f580170fSYu Chen #else 2282f580170fSYu Chen #define dwc3_complete NULL 22837f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 22847415f17cSFelipe Balbi 22857415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 22867415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2287f580170fSYu Chen .complete = dwc3_complete, 2288fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2289fc8bb91bSFelipe Balbi dwc3_runtime_idle) 22907415f17cSFelipe Balbi }; 22917415f17cSFelipe Balbi 22925088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 22935088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 22945088b6f5SKishon Vijay Abraham I { 229522a5aa17SFelipe Balbi .compatible = "snps,dwc3" 229622a5aa17SFelipe Balbi }, 229722a5aa17SFelipe Balbi { 22985088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 22995088b6f5SKishon Vijay Abraham I }, 23005088b6f5SKishon Vijay Abraham I { }, 23015088b6f5SKishon Vijay Abraham I }; 23025088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 23035088b6f5SKishon Vijay Abraham I #endif 23045088b6f5SKishon Vijay Abraham I 2305404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2306404905a6SHeikki Krogerus 2307404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2308404905a6SHeikki Krogerus 2309404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2310404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2311404905a6SHeikki Krogerus { }, 2312404905a6SHeikki Krogerus }; 2313404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2314404905a6SHeikki Krogerus #endif 2315404905a6SHeikki Krogerus 231672246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 231772246da4SFelipe Balbi .probe = dwc3_probe, 23187690417dSBill Pemberton .remove = dwc3_remove, 231972246da4SFelipe Balbi .driver = { 232072246da4SFelipe Balbi .name = "dwc3", 23215088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2322404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 23237f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 232472246da4SFelipe Balbi }, 232572246da4SFelipe Balbi }; 232672246da4SFelipe Balbi 2327b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2328b1116dccSTobias Klauser 23297ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 233072246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 23315945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 233272246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2333