15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 297bee3188SBalaji Prakash J #include <linux/bitfield.h> 3072246da4SFelipe Balbi 3172246da4SFelipe Balbi #include <linux/usb/ch9.h> 3272246da4SFelipe Balbi #include <linux/usb/gadget.h> 33f7e846f0SFelipe Balbi #include <linux/usb/of.h> 34a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3572246da4SFelipe Balbi 3672246da4SFelipe Balbi #include "core.h" 3772246da4SFelipe Balbi #include "gadget.h" 3872246da4SFelipe Balbi #include "io.h" 3972246da4SFelipe Balbi 4072246da4SFelipe Balbi #include "debug.h" 4172246da4SFelipe Balbi 42fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 438300dd23SFelipe Balbi 449d6173e1SThinh Nguyen /** 459d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 469d6173e1SThinh Nguyen * @dwc: pointer to our context structure 479d6173e1SThinh Nguyen */ 489d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 499d6173e1SThinh Nguyen { 509d6173e1SThinh Nguyen enum usb_dr_mode mode; 519d6173e1SThinh Nguyen struct device *dev = dwc->dev; 529d6173e1SThinh Nguyen unsigned int hw_mode; 539d6173e1SThinh Nguyen 549d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 559d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 569d6173e1SThinh Nguyen 579d6173e1SThinh Nguyen mode = dwc->dr_mode; 589d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 599d6173e1SThinh Nguyen 609d6173e1SThinh Nguyen switch (hw_mode) { 619d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 629d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 639d6173e1SThinh Nguyen dev_err(dev, 649d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 659d6173e1SThinh Nguyen return -EINVAL; 669d6173e1SThinh Nguyen } 679d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 689d6173e1SThinh Nguyen break; 699d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 709d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 719d6173e1SThinh Nguyen dev_err(dev, 729d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 739d6173e1SThinh Nguyen return -EINVAL; 749d6173e1SThinh Nguyen } 759d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 769d6173e1SThinh Nguyen break; 779d6173e1SThinh Nguyen default: 789d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 799d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 809d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 819d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 82a7700468SThinh Nguyen 83a7700468SThinh Nguyen /* 8489a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8589a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8689a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 87a7700468SThinh Nguyen */ 8889a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 898bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 908bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 919af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 92a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 939d6173e1SThinh Nguyen } 949d6173e1SThinh Nguyen 959d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 969d6173e1SThinh Nguyen dev_warn(dev, 979d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 989d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 999d6173e1SThinh Nguyen 1009d6173e1SThinh Nguyen dwc->dr_mode = mode; 1019d6173e1SThinh Nguyen } 1029d6173e1SThinh Nguyen 1039d6173e1SThinh Nguyen return 0; 1049d6173e1SThinh Nguyen } 1059d6173e1SThinh Nguyen 106f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1073140e8cbSSebastian Andrzej Siewior { 1083140e8cbSSebastian Andrzej Siewior u32 reg; 1093140e8cbSSebastian Andrzej Siewior 1103140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1113140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1123140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1133140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 114c4a5153eSManu Gautam 115c4a5153eSManu Gautam dwc->current_dr_role = mode; 11641ce1456SRoger Quadros } 1176b3261a2SRoger Quadros 118f88359e1SYu Chen static int dwc3_core_soft_reset(struct dwc3 *dwc); 119f88359e1SYu Chen 12041ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12141ce1456SRoger Quadros { 12241ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12341ce1456SRoger Quadros unsigned long flags; 12441ce1456SRoger Quadros int ret; 125f580170fSYu Chen u32 reg; 12641ce1456SRoger Quadros 127f88359e1SYu Chen mutex_lock(&dwc->mutex); 128f88359e1SYu Chen 129c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 130c2cd3452SMartin Kepplinger 131f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 132f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 133f09cc79bSRoger Quadros 13441ce1456SRoger Quadros if (!dwc->desired_dr_role) 135c2cd3452SMartin Kepplinger goto out; 13641ce1456SRoger Quadros 13741ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 138c2cd3452SMartin Kepplinger goto out; 13941ce1456SRoger Quadros 140f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 141c2cd3452SMartin Kepplinger goto out; 14241ce1456SRoger Quadros 14341ce1456SRoger Quadros switch (dwc->current_dr_role) { 14441ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14541ce1456SRoger Quadros dwc3_host_exit(dwc); 14641ce1456SRoger Quadros break; 14741ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14841ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14941ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 15041ce1456SRoger Quadros break; 151f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 152f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 153f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 154f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 155f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 156f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 157f09cc79bSRoger Quadros break; 15841ce1456SRoger Quadros default: 15941ce1456SRoger Quadros break; 16041ce1456SRoger Quadros } 16141ce1456SRoger Quadros 162f88359e1SYu Chen /* For DRD host or device mode only */ 163f88359e1SYu Chen if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { 164f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 165f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 166f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 167f88359e1SYu Chen 168f88359e1SYu Chen /* 169f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 170f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 171f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 172f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 173f88359e1SYu Chen */ 174f88359e1SYu Chen msleep(100); 175f88359e1SYu Chen 176f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 177f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 178f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 179f88359e1SYu Chen } 180f88359e1SYu Chen 18141ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18241ce1456SRoger Quadros 18341ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18441ce1456SRoger Quadros 18541ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 18641ce1456SRoger Quadros 18741ce1456SRoger Quadros switch (dwc->desired_dr_role) { 18841ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 18941ce1456SRoger Quadros ret = dwc3_host_init(dwc); 190958d1a4cSFelipe Balbi if (ret) { 19141ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 192958d1a4cSFelipe Balbi } else { 193958d1a4cSFelipe Balbi if (dwc->usb2_phy) 194958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 195958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 196644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 197f580170fSYu Chen if (dwc->dis_split_quirk) { 198f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 199f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 200f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 201f580170fSYu Chen } 202958d1a4cSFelipe Balbi } 20341ce1456SRoger Quadros break; 20441ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 205f88359e1SYu Chen dwc3_core_soft_reset(dwc); 206f88359e1SYu Chen 20741ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 208958d1a4cSFelipe Balbi 209958d1a4cSFelipe Balbi if (dwc->usb2_phy) 210958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 211958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 212644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 213958d1a4cSFelipe Balbi 21441ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21541ce1456SRoger Quadros if (ret) 21641ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 21741ce1456SRoger Quadros break; 218f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 219f09cc79bSRoger Quadros dwc3_otg_init(dwc); 220f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 221f09cc79bSRoger Quadros break; 22241ce1456SRoger Quadros default: 22341ce1456SRoger Quadros break; 22441ce1456SRoger Quadros } 225f09cc79bSRoger Quadros 226c2cd3452SMartin Kepplinger out: 227c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 228c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 229f88359e1SYu Chen mutex_unlock(&dwc->mutex); 23041ce1456SRoger Quadros } 23141ce1456SRoger Quadros 23241ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23341ce1456SRoger Quadros { 23441ce1456SRoger Quadros unsigned long flags; 23541ce1456SRoger Quadros 236dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 237dc336b19SLi Jun return; 238dc336b19SLi Jun 23941ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 24041ce1456SRoger Quadros dwc->desired_dr_role = mode; 24141ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24241ce1456SRoger Quadros 243084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2443140e8cbSSebastian Andrzej Siewior } 2458300dd23SFelipe Balbi 246cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 247cf6d867dSFelipe Balbi { 248cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 249cf6d867dSFelipe Balbi u32 reg; 250cf6d867dSFelipe Balbi 251cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 252cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 253cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 254cf6d867dSFelipe Balbi 255cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 256cf6d867dSFelipe Balbi 257cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 258cf6d867dSFelipe Balbi } 259cf6d867dSFelipe Balbi 26072246da4SFelipe Balbi /** 26172246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26272246da4SFelipe Balbi * @dwc: pointer to our context structure 26372246da4SFelipe Balbi */ 26457303488SKishon Vijay Abraham I static int dwc3_core_soft_reset(struct dwc3 *dwc) 26572246da4SFelipe Balbi { 26672246da4SFelipe Balbi u32 reg; 267f59dcab1SFelipe Balbi int retries = 1000; 26872246da4SFelipe Balbi 269f59dcab1SFelipe Balbi /* 270f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 271f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 272f59dcab1SFelipe Balbi * host-only mode, then we can return early. 273f59dcab1SFelipe Balbi */ 274c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27557303488SKishon Vijay Abraham I return 0; 276f59dcab1SFelipe Balbi 277f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 278f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 279f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 280f59dcab1SFelipe Balbi 2814749e0e6SThinh Nguyen /* 2824749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2834749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2844749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2854749e0e6SThinh Nguyen * for 10 times instead. 2864749e0e6SThinh Nguyen */ 2879af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2884749e0e6SThinh Nguyen retries = 10; 2894749e0e6SThinh Nguyen 290f59dcab1SFelipe Balbi do { 291f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 292f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 293fab38333SThinh Nguyen goto done; 294f59dcab1SFelipe Balbi 2959af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2964749e0e6SThinh Nguyen msleep(20); 2974749e0e6SThinh Nguyen else 298f59dcab1SFelipe Balbi udelay(1); 299f59dcab1SFelipe Balbi } while (--retries); 300f59dcab1SFelipe Balbi 301f59dcab1SFelipe Balbi return -ETIMEDOUT; 302fab38333SThinh Nguyen 303fab38333SThinh Nguyen done: 304fab38333SThinh Nguyen /* 3054749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3064749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3074749e0e6SThinh Nguyen * domain (synchronization delay). 308fab38333SThinh Nguyen */ 3099af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 310fab38333SThinh Nguyen msleep(50); 311fab38333SThinh Nguyen 312fab38333SThinh Nguyen return 0; 31372246da4SFelipe Balbi } 31472246da4SFelipe Balbi 315db2be4e9SNikhil Badola /* 316db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 317db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 318db2be4e9SNikhil Badola */ 319bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 320db2be4e9SNikhil Badola { 321db2be4e9SNikhil Badola u32 reg; 322db2be4e9SNikhil Badola u32 dft; 323db2be4e9SNikhil Badola 3249af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 325db2be4e9SNikhil Badola return; 326db2be4e9SNikhil Badola 327bcdb3272SFelipe Balbi if (dwc->fladj == 0) 328db2be4e9SNikhil Badola return; 329db2be4e9SNikhil Badola 330db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 331db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 332a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 333db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 334bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 335db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 336db2be4e9SNikhil Badola } 337db2be4e9SNikhil Badola } 338db2be4e9SNikhil Badola 339c5cc74e8SHeikki Krogerus /** 3407bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3417bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3427bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3437bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3447bee3188SBalaji Prakash J * register. 3457bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3467bee3188SBalaji Prakash J * @ref_clk_per: reference clock period in ns 3477bee3188SBalaji Prakash J */ 3487bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3497bee3188SBalaji Prakash J { 3505114c3eeSSean Anderson unsigned long period; 351*596c8785SSean Anderson unsigned long fladj; 352*596c8785SSean Anderson unsigned long decr; 3535114c3eeSSean Anderson unsigned long rate; 3547bee3188SBalaji Prakash J u32 reg; 3557bee3188SBalaji Prakash J 3565114c3eeSSean Anderson if (dwc->ref_clk) { 3575114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3585114c3eeSSean Anderson if (!rate) 3597bee3188SBalaji Prakash J return; 3605114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3615114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3625114c3eeSSean Anderson period = dwc->ref_clk_per; 363*596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3645114c3eeSSean Anderson } else { 3655114c3eeSSean Anderson return; 3665114c3eeSSean Anderson } 3677bee3188SBalaji Prakash J 3687bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3697bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3705114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3717bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3727bee3188SBalaji Prakash J 373*596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 374*596c8785SSean Anderson return; 375*596c8785SSean Anderson 376*596c8785SSean Anderson /* 377*596c8785SSean Anderson * The calculation below is 378*596c8785SSean Anderson * 379*596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 380*596c8785SSean Anderson * 381*596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 382*596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 383*596c8785SSean Anderson * neither does rate * period). 384*596c8785SSean Anderson * 385*596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 386*596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 387*596c8785SSean Anderson * the division when calculating rate or period (whichever one was 388*596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 389*596c8785SSean Anderson * scale it to units of 8 ppm. 390*596c8785SSean Anderson */ 391*596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 392*596c8785SSean Anderson fladj -= 125000; 393*596c8785SSean Anderson 394*596c8785SSean Anderson /* 395*596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 396*596c8785SSean Anderson */ 397*596c8785SSean Anderson decr = 480000000 / rate; 398*596c8785SSean Anderson 399*596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 400*596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 401*596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 402*596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 403*596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 404*596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 405*596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 406*596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 407*596c8785SSean Anderson } 4087bee3188SBalaji Prakash J 4097bee3188SBalaji Prakash J /** 41072246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 41172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 41272246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 41372246da4SFelipe Balbi */ 41472246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 41572246da4SFelipe Balbi struct dwc3_event_buffer *evt) 41672246da4SFelipe Balbi { 417d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 41872246da4SFelipe Balbi } 41972246da4SFelipe Balbi 42072246da4SFelipe Balbi /** 4211d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 42272246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42372246da4SFelipe Balbi * @length: size of the event buffer 42472246da4SFelipe Balbi * 4251d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 42672246da4SFelipe Balbi * otherwise ERR_PTR(errno). 42772246da4SFelipe Balbi */ 42867d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 42967d0b500SFelipe Balbi unsigned length) 43072246da4SFelipe Balbi { 43172246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43272246da4SFelipe Balbi 433380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 43472246da4SFelipe Balbi if (!evt) 43572246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 43672246da4SFelipe Balbi 43772246da4SFelipe Balbi evt->dwc = dwc; 43872246da4SFelipe Balbi evt->length = length; 439d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 440d9fa4c63SJohn Youn if (!evt->cache) 441d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 442d9fa4c63SJohn Youn 443d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 44472246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 445e32672f0SFelipe Balbi if (!evt->buf) 44672246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44772246da4SFelipe Balbi 44872246da4SFelipe Balbi return evt; 44972246da4SFelipe Balbi } 45072246da4SFelipe Balbi 45172246da4SFelipe Balbi /** 45272246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 45372246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 45472246da4SFelipe Balbi */ 45572246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 45672246da4SFelipe Balbi { 45772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 45872246da4SFelipe Balbi 459696c8b12SFelipe Balbi evt = dwc->ev_buf; 46064b6c8a7SAnton Tikhomirov if (evt) 46172246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 46272246da4SFelipe Balbi } 46372246da4SFelipe Balbi 46472246da4SFelipe Balbi /** 46572246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4661d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 46772246da4SFelipe Balbi * @length: size of event buffer 46872246da4SFelipe Balbi * 4691d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 47072246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 47172246da4SFelipe Balbi */ 47241ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 47372246da4SFelipe Balbi { 47472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 47572246da4SFelipe Balbi 47672246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 47772246da4SFelipe Balbi if (IS_ERR(evt)) { 47872246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 47972246da4SFelipe Balbi return PTR_ERR(evt); 48072246da4SFelipe Balbi } 481696c8b12SFelipe Balbi dwc->ev_buf = evt; 48272246da4SFelipe Balbi 48372246da4SFelipe Balbi return 0; 48472246da4SFelipe Balbi } 48572246da4SFelipe Balbi 48672246da4SFelipe Balbi /** 48772246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4881d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 48972246da4SFelipe Balbi * 49072246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 49172246da4SFelipe Balbi */ 492f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 49372246da4SFelipe Balbi { 49472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 49572246da4SFelipe Balbi 496696c8b12SFelipe Balbi evt = dwc->ev_buf; 4977acd85e0SPaul Zimmerman evt->lpos = 0; 498660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 49972246da4SFelipe Balbi lower_32_bits(evt->dma)); 500660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 50172246da4SFelipe Balbi upper_32_bits(evt->dma)); 502660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 50368d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 504660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 50572246da4SFelipe Balbi 50672246da4SFelipe Balbi return 0; 50772246da4SFelipe Balbi } 50872246da4SFelipe Balbi 509f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 51072246da4SFelipe Balbi { 51172246da4SFelipe Balbi struct dwc3_event_buffer *evt; 51272246da4SFelipe Balbi 513696c8b12SFelipe Balbi evt = dwc->ev_buf; 5147acd85e0SPaul Zimmerman 5157acd85e0SPaul Zimmerman evt->lpos = 0; 5167acd85e0SPaul Zimmerman 517660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 518660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 519660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 52068d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 521660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 52272246da4SFelipe Balbi } 52372246da4SFelipe Balbi 5240ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5250ffcaf37SFelipe Balbi { 5260ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5270ffcaf37SFelipe Balbi return 0; 5280ffcaf37SFelipe Balbi 5290ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5300ffcaf37SFelipe Balbi return 0; 5310ffcaf37SFelipe Balbi 5320ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5330ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5340ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5350ffcaf37SFelipe Balbi return -ENOMEM; 5360ffcaf37SFelipe Balbi 5370ffcaf37SFelipe Balbi return 0; 5380ffcaf37SFelipe Balbi } 5390ffcaf37SFelipe Balbi 5400ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5410ffcaf37SFelipe Balbi { 5420ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5430ffcaf37SFelipe Balbi u32 param; 5440ffcaf37SFelipe Balbi int ret; 5450ffcaf37SFelipe Balbi 5460ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5470ffcaf37SFelipe Balbi return 0; 5480ffcaf37SFelipe Balbi 5490ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5500ffcaf37SFelipe Balbi return 0; 5510ffcaf37SFelipe Balbi 5520ffcaf37SFelipe Balbi /* should never fall here */ 5530ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5540ffcaf37SFelipe Balbi return 0; 5550ffcaf37SFelipe Balbi 556d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5570ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5580ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 559d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 560d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5610ffcaf37SFelipe Balbi ret = -EFAULT; 5620ffcaf37SFelipe Balbi goto err0; 5630ffcaf37SFelipe Balbi } 5640ffcaf37SFelipe Balbi 5650ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5660ffcaf37SFelipe Balbi 5670ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5680ffcaf37SFelipe Balbi 5690ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5700ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5710ffcaf37SFelipe Balbi if (ret < 0) 5720ffcaf37SFelipe Balbi goto err1; 5730ffcaf37SFelipe Balbi 5740ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5750ffcaf37SFelipe Balbi 5760ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5770ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5780ffcaf37SFelipe Balbi if (ret < 0) 5790ffcaf37SFelipe Balbi goto err1; 5800ffcaf37SFelipe Balbi 5810ffcaf37SFelipe Balbi return 0; 5820ffcaf37SFelipe Balbi 5830ffcaf37SFelipe Balbi err1: 584d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5850ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5860ffcaf37SFelipe Balbi 5870ffcaf37SFelipe Balbi err0: 5880ffcaf37SFelipe Balbi return ret; 5890ffcaf37SFelipe Balbi } 5900ffcaf37SFelipe Balbi 5910ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5920ffcaf37SFelipe Balbi { 5930ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5940ffcaf37SFelipe Balbi return; 5950ffcaf37SFelipe Balbi 5960ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5970ffcaf37SFelipe Balbi return; 5980ffcaf37SFelipe Balbi 5990ffcaf37SFelipe Balbi /* should never fall here */ 6000ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6010ffcaf37SFelipe Balbi return; 6020ffcaf37SFelipe Balbi 603d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6040ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6050ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6060ffcaf37SFelipe Balbi } 6070ffcaf37SFelipe Balbi 608789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 609789451f6SFelipe Balbi { 610789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 611789451f6SFelipe Balbi 61247d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 613789451f6SFelipe Balbi } 614789451f6SFelipe Balbi 61541ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 61626ceca97SFelipe Balbi { 61726ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 61826ceca97SFelipe Balbi 61926ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 62026ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 62126ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 62226ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 62326ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 62426ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 62526ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 62626ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 62726ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 62816710380SThinh Nguyen 62916710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 63016710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 63126ceca97SFelipe Balbi } 63226ceca97SFelipe Balbi 63398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 63498112041SRoger Quadros { 63598112041SRoger Quadros int intf; 63698112041SRoger Quadros int ret = 0; 63798112041SRoger Quadros 63898112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 63998112041SRoger Quadros 64098112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 64198112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 64298112041SRoger Quadros dwc->hsphy_interface && 64398112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 64498112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 64598112041SRoger Quadros 64698112041SRoger Quadros return ret; 64798112041SRoger Quadros } 64898112041SRoger Quadros 64972246da4SFelipe Balbi /** 650b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 651b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 65288bc9d19SHeikki Krogerus * 65388bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 65488bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 65588bc9d19SHeikki Krogerus * the core in dwc3_core_init. 656b5a65c40SHuang Rui */ 65788bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 658b5a65c40SHuang Rui { 6599ba3aca8SThinh Nguyen unsigned int hw_mode; 660b5a65c40SHuang Rui u32 reg; 661b5a65c40SHuang Rui 6629ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6639ba3aca8SThinh Nguyen 664b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 665b5a65c40SHuang Rui 6662164a476SHuang Rui /* 6671966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6681966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6691966b865SFelipe Balbi */ 6701966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6711966b865SFelipe Balbi 6721966b865SFelipe Balbi /* 6732164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6742164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6752164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6762164a476SHuang Rui * to '1' after the core initialization is completed. 6772164a476SHuang Rui */ 6789af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6792164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6802164a476SHuang Rui 6819ba3aca8SThinh Nguyen /* 6829ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6839ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6849ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6859ba3aca8SThinh Nguyen */ 6869ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6879ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6889ba3aca8SThinh Nguyen 689b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 690b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 691b5a65c40SHuang Rui 692e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 693e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 694e58dd357SRajesh Bhagat 695df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 696df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 697df31f5b3SHuang Rui 698a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 699a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 700a2a1d0f5SHuang Rui 70141c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 70241c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 70341c06ffdSHuang Rui 704fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 705fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 706fb67afcaSHuang Rui 70714f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 70814f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 70914f4ac53SHuang Rui 7106b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7116b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7126b6a0c9aSHuang Rui 713cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 71459acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 71559acfa20SHuang Rui 71600fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 71700fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 71800fe081dSWilliam Wu 719b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 720b5a65c40SHuang Rui 7212164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7222164a476SHuang Rui 7233e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7243e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7253e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 72643cacb03SFelipe Balbi if (dwc->hsphy_interface && 72743cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7283e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 72988bc9d19SHeikki Krogerus break; 73043cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 73143cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7323e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 73388bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7343e10a2ceSHeikki Krogerus } else { 73588bc9d19SHeikki Krogerus /* Relying on default value. */ 73688bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7373e10a2ceSHeikki Krogerus break; 7383e10a2ceSHeikki Krogerus } 739df561f66SGustavo A. R. Silva fallthrough; 74088bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7413e10a2ceSHeikki Krogerus default: 7423e10a2ceSHeikki Krogerus break; 7433e10a2ceSHeikki Krogerus } 7443e10a2ceSHeikki Krogerus 74532f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 74632f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 74732f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 74832f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 74932f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 75032f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 75132f2ed86SWilliam Wu break; 75232f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 75332f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75432f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75532f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 75632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 75732f2ed86SWilliam Wu break; 75832f2ed86SWilliam Wu default: 75932f2ed86SWilliam Wu break; 76032f2ed86SWilliam Wu } 76132f2ed86SWilliam Wu 7622164a476SHuang Rui /* 7632164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7642164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7652164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7662164a476SHuang Rui * '1' after the core initialization is completed. 7672164a476SHuang Rui */ 7689af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7692164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7702164a476SHuang Rui 7719ba3aca8SThinh Nguyen /* 7729ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7739ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7749ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7759ba3aca8SThinh Nguyen */ 7769ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7779ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7789ba3aca8SThinh Nguyen 779cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7800effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7810effe0a3SHuang Rui 782ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 783ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 784eafeacf1SThinh Nguyen else 785eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 786ec791d14SJohn Youn 78716199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 78816199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 78916199f33SWilliam Wu 7902164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79188bc9d19SHeikki Krogerus 79288bc9d19SHeikki Krogerus return 0; 793b5a65c40SHuang Rui } 794b5a65c40SHuang Rui 79533fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 79633fb697eSSean Anderson { 79733fb697eSSean Anderson int ret; 79833fb697eSSean Anderson 79933fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 80033fb697eSSean Anderson if (ret) 80133fb697eSSean Anderson return ret; 80233fb697eSSean Anderson 80333fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 80433fb697eSSean Anderson if (ret) 80533fb697eSSean Anderson goto disable_bus_clk; 80633fb697eSSean Anderson 80733fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 80833fb697eSSean Anderson if (ret) 80933fb697eSSean Anderson goto disable_ref_clk; 81033fb697eSSean Anderson 81133fb697eSSean Anderson return 0; 81233fb697eSSean Anderson 81333fb697eSSean Anderson disable_ref_clk: 81433fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 81533fb697eSSean Anderson disable_bus_clk: 81633fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 81733fb697eSSean Anderson return ret; 81833fb697eSSean Anderson } 81933fb697eSSean Anderson 82033fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 82133fb697eSSean Anderson { 82233fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 82333fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82433fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82533fb697eSSean Anderson } 82633fb697eSSean Anderson 827c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 828c499ff71SFelipe Balbi { 829c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 830c499ff71SFelipe Balbi 831c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 832c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 833c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 834c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 835c499ff71SFelipe Balbi 836c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 837c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 838c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 839c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 84033fb697eSSean Anderson dwc3_clk_disable(dwc); 841fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 842c499ff71SFelipe Balbi } 843c499ff71SFelipe Balbi 8440759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 84572246da4SFelipe Balbi { 84672246da4SFelipe Balbi u32 reg; 84772246da4SFelipe Balbi 8487650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8499af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8500759956fSFelipe Balbi 8517650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8529af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 853690fb371SJohn Youn dwc->revision = reg; 8549af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 855690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 856475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 857690fb371SJohn Youn } else { 8580759956fSFelipe Balbi return false; 8597650bd74SSebastian Andrzej Siewior } 8607650bd74SSebastian Andrzej Siewior 8610759956fSFelipe Balbi return true; 8620e1e5c47SPaul Zimmerman } 8630e1e5c47SPaul Zimmerman 864941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 86572246da4SFelipe Balbi { 86672246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 86772246da4SFelipe Balbi u32 reg; 868c499ff71SFelipe Balbi 8694878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8703e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8714878a028SSebastian Andrzej Siewior 872164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8734878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87432a4a135SFelipe Balbi /** 87532a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 87632a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 87732a4a135SFelipe Balbi * 87832a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 87932a4a135SFelipe Balbi * configurations. 88032a4a135SFelipe Balbi * 88132a4a135SFelipe Balbi * Refers to: 88232a4a135SFelipe Balbi * 88332a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 88432a4a135SFelipe Balbi * SOF/ITP Mode Used 88532a4a135SFelipe Balbi */ 88632a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 88732a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8889af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 88932a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 89032a4a135SFelipe Balbi else 8914878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 8924878a028SSebastian Andrzej Siewior break; 8930ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 8940ffcaf37SFelipe Balbi /* enable hibernation here */ 8950ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 8962eac3992SHuang Rui 8972eac3992SHuang Rui /* 8982eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 8992eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 9002eac3992SHuang Rui */ 9012eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9020ffcaf37SFelipe Balbi break; 9034878a028SSebastian Andrzej Siewior default: 9045eb30cedSFelipe Balbi /* nothing */ 9055eb30cedSFelipe Balbi break; 9064878a028SSebastian Andrzej Siewior } 9074878a028SSebastian Andrzej Siewior 908946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 909946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9106af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 911946bd579SHuang Rui dwc->is_fpga = true; 912946bd579SHuang Rui } 913946bd579SHuang Rui 9143b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9153b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9163b81221aSHuang Rui 9173b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9183b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9193b81221aSHuang Rui else 9203b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9213b81221aSHuang Rui 9229a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9239a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9249a5b2f31SHuang Rui 9254878a028SSebastian Andrzej Siewior /* 9264878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9271d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9284878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9291d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9304878a028SSebastian Andrzej Siewior */ 9319af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9324878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9334878a028SSebastian Andrzej Siewior 9344878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 935941f918eSFelipe Balbi } 9364878a028SSebastian Andrzej Siewior 937f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 93898112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 939f54edb53SFelipe Balbi 940d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 941d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 942d9612c2fSPengbo Mu { 943d9612c2fSPengbo Mu struct device *dev = dwc->dev; 944d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 945d9612c2fSPengbo Mu bool incrx_mode; 946d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 947d9612c2fSPengbo Mu u32 incrx_size; 948d9612c2fSPengbo Mu u32 *vals; 949d9612c2fSPengbo Mu u32 cfg; 950d9612c2fSPengbo Mu int ntype; 951d9612c2fSPengbo Mu int ret; 952d9612c2fSPengbo Mu int i; 953d9612c2fSPengbo Mu 954d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 955d9612c2fSPengbo Mu 956d9612c2fSPengbo Mu /* 957d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 958d9612c2fSPengbo Mu * Get the number of value from this property: 959d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 960d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 961d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 962d9612c2fSPengbo Mu */ 963a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 964d9612c2fSPengbo Mu if (ntype <= 0) 965d9612c2fSPengbo Mu return; 966d9612c2fSPengbo Mu 967d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 968d9612c2fSPengbo Mu if (!vals) { 969d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 970d9612c2fSPengbo Mu return; 971d9612c2fSPengbo Mu } 972d9612c2fSPengbo Mu 973d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 974d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 975d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 976d9612c2fSPengbo Mu if (ret) { 97775ecb9ddSAndy Shevchenko kfree(vals); 978d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 979d9612c2fSPengbo Mu return; 980d9612c2fSPengbo Mu } 981d9612c2fSPengbo Mu 982d9612c2fSPengbo Mu incrx_size = *vals; 983d9612c2fSPengbo Mu 984d9612c2fSPengbo Mu if (ntype > 1) { 985d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 986d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 987d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 988d9612c2fSPengbo Mu if (vals[i] > incrx_size) 989d9612c2fSPengbo Mu incrx_size = vals[i]; 990d9612c2fSPengbo Mu } 991d9612c2fSPengbo Mu } else { 992d9612c2fSPengbo Mu /* INCRX burst mode */ 993d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 994d9612c2fSPengbo Mu } 995d9612c2fSPengbo Mu 99675ecb9ddSAndy Shevchenko kfree(vals); 99775ecb9ddSAndy Shevchenko 998d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 999d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1000d9612c2fSPengbo Mu if (incrx_mode) 1001d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1002d9612c2fSPengbo Mu switch (incrx_size) { 1003d9612c2fSPengbo Mu case 256: 1004d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1005d9612c2fSPengbo Mu break; 1006d9612c2fSPengbo Mu case 128: 1007d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1008d9612c2fSPengbo Mu break; 1009d9612c2fSPengbo Mu case 64: 1010d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1011d9612c2fSPengbo Mu break; 1012d9612c2fSPengbo Mu case 32: 1013d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1014d9612c2fSPengbo Mu break; 1015d9612c2fSPengbo Mu case 16: 1016d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1017d9612c2fSPengbo Mu break; 1018d9612c2fSPengbo Mu case 8: 1019d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1020d9612c2fSPengbo Mu break; 1021d9612c2fSPengbo Mu case 4: 1022d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1023d9612c2fSPengbo Mu break; 1024d9612c2fSPengbo Mu case 1: 1025d9612c2fSPengbo Mu break; 1026d9612c2fSPengbo Mu default: 1027d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1028d9612c2fSPengbo Mu break; 1029d9612c2fSPengbo Mu } 1030d9612c2fSPengbo Mu 1031d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1032d9612c2fSPengbo Mu } 1033d9612c2fSPengbo Mu 1034941f918eSFelipe Balbi /** 1035941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1036941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1037941f918eSFelipe Balbi * 1038941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1039941f918eSFelipe Balbi */ 1040941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1041941f918eSFelipe Balbi { 10429ba3aca8SThinh Nguyen unsigned int hw_mode; 1043941f918eSFelipe Balbi u32 reg; 1044941f918eSFelipe Balbi int ret; 1045941f918eSFelipe Balbi 10469ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10479ba3aca8SThinh Nguyen 1048941f918eSFelipe Balbi /* 1049941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1050941f918eSFelipe Balbi * out which kernel version a bug was found. 1051941f918eSFelipe Balbi */ 1052941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1053941f918eSFelipe Balbi 1054941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1055941f918eSFelipe Balbi if (ret) 1056941f918eSFelipe Balbi goto err0; 1057941f918eSFelipe Balbi 105898112041SRoger Quadros if (!dwc->ulpi_ready) { 105998112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 106098112041SRoger Quadros if (ret) 106198112041SRoger Quadros goto err0; 106298112041SRoger Quadros dwc->ulpi_ready = true; 106398112041SRoger Quadros } 106498112041SRoger Quadros 106598112041SRoger Quadros if (!dwc->phys_ready) { 106698112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 106798112041SRoger Quadros if (ret) 106898112041SRoger Quadros goto err0a; 106998112041SRoger Quadros dwc->phys_ready = true; 107098112041SRoger Quadros } 107198112041SRoger Quadros 10728cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 10738cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 10748cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 10758cfac9a6SLi Jun if (ret < 0) 10768cfac9a6SLi Jun goto err0a; 10778cfac9a6SLi Jun 10788cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 10798cfac9a6SLi Jun if (ret < 0) { 10808cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 10818cfac9a6SLi Jun goto err0a; 10828cfac9a6SLi Jun } 10838cfac9a6SLi Jun 108498112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 108598112041SRoger Quadros if (ret) 10868cfac9a6SLi Jun goto err1; 108798112041SRoger Quadros 10889ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 10899af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 10909ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 10919ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 10929ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 10939ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 10949ba3aca8SThinh Nguyen } 10959ba3aca8SThinh Nguyen 10969ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 10979ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 10989ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 10999ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 11009ba3aca8SThinh Nguyen } 11019ba3aca8SThinh Nguyen } 11029ba3aca8SThinh Nguyen 1103941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1104c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11050ffcaf37SFelipe Balbi 11060ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11070ffcaf37SFelipe Balbi if (ret) 1108c499ff71SFelipe Balbi goto err1; 1109c499ff71SFelipe Balbi 1110c499ff71SFelipe Balbi /* Adjust Frame Length */ 1111c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1112c499ff71SFelipe Balbi 11137bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11147bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11157bee3188SBalaji Prakash J 1116d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1117d9612c2fSPengbo Mu 1118c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1119c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1120c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1121c499ff71SFelipe Balbi if (ret < 0) 11220ffcaf37SFelipe Balbi goto err2; 11230ffcaf37SFelipe Balbi 1124c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1125c499ff71SFelipe Balbi if (ret < 0) 1126c499ff71SFelipe Balbi goto err3; 1127c499ff71SFelipe Balbi 1128c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1129c499ff71SFelipe Balbi if (ret) { 1130c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1131c499ff71SFelipe Balbi goto err4; 1132c499ff71SFelipe Balbi } 1133c499ff71SFelipe Balbi 113406281d46SJohn Youn /* 113506281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 113606281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 113706281d46SJohn Youn * DWC_usb31 controller. 113806281d46SJohn Youn */ 11399af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 114006281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 114106281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 114206281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 114306281d46SJohn Youn } 114406281d46SJohn Youn 11459af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 11460bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 114765db7a0cSWilliam Wu 114865db7a0cSWilliam Wu /* 114965db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 115065db7a0cSWilliam Wu * in HS when the device is in the L1 state. 115165db7a0cSWilliam Wu */ 11529af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 11530bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 115465db7a0cSWilliam Wu 1155843714bbSJack Pham /* 1156843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1157843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1158843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1159843714bbSJack Pham * from interrupting the driver. 1160843714bbSJack Pham */ 1161843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1162843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1163843714bbSJack Pham 116465db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 116565db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 116665db7a0cSWilliam Wu 11677ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 11687ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 11697ba6b09fSNeil Armstrong 11700bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 11710bb39ca1SJohn Youn } 11720bb39ca1SJohn Youn 1173b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1174b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1175b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1176b138e23dSAnurag Kumar Vulisha 1177b138e23dSAnurag Kumar Vulisha /* 1178b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1179b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1180b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1181b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1182b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1183b138e23dSAnurag Kumar Vulisha */ 1184b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1185b138e23dSAnurag Kumar Vulisha 1186b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1187b138e23dSAnurag Kumar Vulisha } 1188b138e23dSAnurag Kumar Vulisha 1189938a5ad1SThinh Nguyen /* 1190938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1191938a5ad1SThinh Nguyen * RX and/or TX threshold. 1192938a5ad1SThinh Nguyen */ 11939af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1194938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1195938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1196938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1197938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1198938a5ad1SThinh Nguyen 1199938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1200938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1201938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1202938a5ad1SThinh Nguyen 1203938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1204938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1205938a5ad1SThinh Nguyen 1206938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1207938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1208938a5ad1SThinh Nguyen 1209938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1210938a5ad1SThinh Nguyen } 1211938a5ad1SThinh Nguyen 1212938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1213938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1214938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1215938a5ad1SThinh Nguyen 1216938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1217938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1218938a5ad1SThinh Nguyen 1219938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1220938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1221938a5ad1SThinh Nguyen 1222938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1223938a5ad1SThinh Nguyen } 1224938a5ad1SThinh Nguyen } 1225938a5ad1SThinh Nguyen 122672246da4SFelipe Balbi return 0; 122772246da4SFelipe Balbi 1228c499ff71SFelipe Balbi err4: 12299b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1230c499ff71SFelipe Balbi 1231c499ff71SFelipe Balbi err3: 12329b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1233c499ff71SFelipe Balbi 12340ffcaf37SFelipe Balbi err2: 1235c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1236c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12370ffcaf37SFelipe Balbi 12380ffcaf37SFelipe Balbi err1: 12390ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 12400ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 124157303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 124257303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 12430ffcaf37SFelipe Balbi 124498112041SRoger Quadros err0a: 124598112041SRoger Quadros dwc3_ulpi_exit(dwc); 124698112041SRoger Quadros 124772246da4SFelipe Balbi err0: 124872246da4SFelipe Balbi return ret; 124972246da4SFelipe Balbi } 125072246da4SFelipe Balbi 12513c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 125272246da4SFelipe Balbi { 12533c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1254941ea361SFelipe Balbi struct device_node *node = dev->of_node; 12553c9f94acSFelipe Balbi int ret; 125672246da4SFelipe Balbi 12575088b6f5SKishon Vijay Abraham I if (node) { 12585088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 12595088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1260bb674907SFelipe Balbi } else { 1261bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1262bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 12635088b6f5SKishon Vijay Abraham I } 12645088b6f5SKishon Vijay Abraham I 1265d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1266d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1267122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1268122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1269122f06e6SKishon Vijay Abraham I } else { 12700c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1271122f06e6SKishon Vijay Abraham I } 127251e1e7bcSFelipe Balbi } 127351e1e7bcSFelipe Balbi 1274d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1275315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1276122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1277122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1278122f06e6SKishon Vijay Abraham I } else { 12790c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1280122f06e6SKishon Vijay Abraham I } 128151e1e7bcSFelipe Balbi } 128251e1e7bcSFelipe Balbi 128357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 128457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 128557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 128657303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 128757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 128857303488SKishon Vijay Abraham I } else { 12890c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 129057303488SKishon Vijay Abraham I } 129157303488SKishon Vijay Abraham I } 129257303488SKishon Vijay Abraham I 129357303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 129457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 129557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 129657303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 129757303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 129857303488SKishon Vijay Abraham I } else { 12990c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 130057303488SKishon Vijay Abraham I } 130157303488SKishon Vijay Abraham I } 130257303488SKishon Vijay Abraham I 13033c9f94acSFelipe Balbi return 0; 13043c9f94acSFelipe Balbi } 13053c9f94acSFelipe Balbi 13065f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13075f94adfeSFelipe Balbi { 13085f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13095f94adfeSFelipe Balbi int ret; 13105f94adfeSFelipe Balbi 13115f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13125f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 131341ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1314958d1a4cSFelipe Balbi 1315958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1316958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1317958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1318644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1319958d1a4cSFelipe Balbi 13205f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13210c0a20f6SAndy Shevchenko if (ret) 13220c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13235f94adfeSFelipe Balbi break; 13245f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 132541ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1326958d1a4cSFelipe Balbi 1327958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1328958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1329958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1330644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1331958d1a4cSFelipe Balbi 13325f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13330c0a20f6SAndy Shevchenko if (ret) 13340c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13355f94adfeSFelipe Balbi break; 13365f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 133741ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13389840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13390c0a20f6SAndy Shevchenko if (ret) 13400c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13415f94adfeSFelipe Balbi break; 13425f94adfeSFelipe Balbi default: 13435f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 13445f94adfeSFelipe Balbi return -EINVAL; 13455f94adfeSFelipe Balbi } 13465f94adfeSFelipe Balbi 13475f94adfeSFelipe Balbi return 0; 13485f94adfeSFelipe Balbi } 13495f94adfeSFelipe Balbi 13505f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 13515f94adfeSFelipe Balbi { 13525f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13535f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 13545f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 13555f94adfeSFelipe Balbi break; 13565f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 13575f94adfeSFelipe Balbi dwc3_host_exit(dwc); 13585f94adfeSFelipe Balbi break; 13595f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 13609840354fSRoger Quadros dwc3_drd_exit(dwc); 13615f94adfeSFelipe Balbi break; 13625f94adfeSFelipe Balbi default: 13635f94adfeSFelipe Balbi /* do nothing */ 13645f94adfeSFelipe Balbi break; 13655f94adfeSFelipe Balbi } 136609ed259fSBin Liu 136709ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 136809ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 13695f94adfeSFelipe Balbi } 13705f94adfeSFelipe Balbi 1371c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 13723c9f94acSFelipe Balbi { 1373c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 137480caf7d2SHuang Rui u8 lpm_nyet_threshold; 13756b6a0c9aSHuang Rui u8 tx_de_emphasis; 1376460d098cSHuang Rui u8 hird_threshold; 1377938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1378938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1379938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1380938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 13819f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 13826f0764b5SRay Chi const char *usb_psy_name; 13836f0764b5SRay Chi int ret; 13843c9f94acSFelipe Balbi 138580caf7d2SHuang Rui /* default to highest possible threshold */ 13868d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 138780caf7d2SHuang Rui 13886b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 13896b6a0c9aSHuang Rui tx_de_emphasis = 1; 13906b6a0c9aSHuang Rui 1391460d098cSHuang Rui /* 1392460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1393460d098cSHuang Rui * threshold value of 0b1100 1394460d098cSHuang Rui */ 1395460d098cSHuang Rui hird_threshold = 12; 1396460d098cSHuang Rui 13979f607a30SWesley Cheng /* 13989f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 13999f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14009f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14019f607a30SWesley Cheng */ 14029f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14039f607a30SWesley Cheng 140463863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 140567848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 140606e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 140732f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 140863863b98SHeikki Krogerus 1409d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1410d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1411d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1412d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1413d64ff406SArnd Bergmann else 1414d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1415d64ff406SArnd Bergmann 14166f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14176f0764b5SRay Chi if (ret >= 0) { 14186f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14196f0764b5SRay Chi if (!dwc->usb_psy) 14206f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14216f0764b5SRay Chi } 14226f0764b5SRay Chi 14233d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 142480caf7d2SHuang Rui "snps,has-lpm-erratum"); 14253d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 142680caf7d2SHuang Rui &lpm_nyet_threshold); 14273d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1428460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14293d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1430460d098cSHuang Rui &hird_threshold); 1431d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1432d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14333d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1434eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1435022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1436022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1437475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1438475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1439938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1440938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1441938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1442938a5ad1SThinh Nguyen &rx_max_burst_prd); 1443938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1444938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1445938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1446938a5ad1SThinh Nguyen &tx_max_burst_prd); 14479f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 14489f607a30SWesley Cheng "tx-fifo-resize"); 14499f607a30SWesley Cheng if (dwc->do_fifo_resize) 14509f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 14519f607a30SWesley Cheng &tx_fifo_resize_max_num); 14523c9f94acSFelipe Balbi 14533d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 14543b81221aSHuang Rui "snps,disable_scramble_quirk"); 14553d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 14569a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 14573d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1458b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 14593d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1460df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 14613d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1462a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 14633d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 146441c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 14653d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1466fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 14673d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 146814f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 14693d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 147059acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 14713d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 14720effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1473ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1474ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1475729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1476729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1477729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1478729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1479e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1480e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 148116199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 148216199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 148300fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 148400fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 148565db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 148665db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 14877ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 14887ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 14896b6a0c9aSHuang Rui 14903d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 14916b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 14923d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 14936b6a0c9aSHuang Rui &tx_de_emphasis); 14943d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 14953e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 14963d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1497bcdb3272SFelipe Balbi &dwc->fladj); 14987bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 14997bee3188SBalaji Prakash J &dwc->ref_clk_per); 15003d128919SHeikki Krogerus 150142bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 150242bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 150342bf02ecSRoger Quadros 1504f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1505f580170fSYu Chen "snps,dis-split-quirk"); 1506f580170fSYu Chen 150780caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15086b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 150980caf7d2SHuang Rui 151016fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1511460d098cSHuang Rui 1512938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1513938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1514938a5ad1SThinh Nguyen 1515938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1516938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1517938a5ad1SThinh Nguyen 1518cf40b86bSJohn Youn dwc->imod_interval = 0; 15199f607a30SWesley Cheng 15209f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1521cf40b86bSJohn Youn } 1522cf40b86bSJohn Youn 1523cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1524cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1525cf40b86bSJohn Youn { 15269af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15279af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15289af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1529c5ac6116SFelipe Balbi } 1530c5ac6116SFelipe Balbi 15317ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15327ac51a12SJohn Youn { 15337ac51a12SJohn Youn struct device *dev = dwc->dev; 1534b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1535b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15367ac51a12SJohn Youn 1537cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1538cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1539cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1540cf40b86bSJohn Youn dwc->imod_interval = 0; 1541cf40b86bSJohn Youn } 1542cf40b86bSJohn Youn 154328632b44SJohn Youn /* 154428632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 154528632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 154628632b44SJohn Youn * interrupt from being masked while handling events. IMOD 154728632b44SJohn Youn * allows us to work around this issue. Enable it for the 154828632b44SJohn Youn * affected version. 154928632b44SJohn Youn */ 155028632b44SJohn Youn if (!dwc->imod_interval && 15519af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 155228632b44SJohn Youn dwc->imod_interval = 1; 155328632b44SJohn Youn 15547ac51a12SJohn Youn /* Check the maximum_speed parameter */ 15557ac51a12SJohn Youn switch (dwc->maximum_speed) { 15567ac51a12SJohn Youn case USB_SPEED_FULL: 15577ac51a12SJohn Youn case USB_SPEED_HIGH: 1558e518bdd9SThinh Nguyen break; 15597ac51a12SJohn Youn case USB_SPEED_SUPER: 1560e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1561e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1562e518bdd9SThinh Nguyen break; 15637ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1564e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1565e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1566e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1567e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1568e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 15697ac51a12SJohn Youn break; 15707ac51a12SJohn Youn default: 15717ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 15727ac51a12SJohn Youn dwc->maximum_speed); 1573df561f66SGustavo A. R. Silva fallthrough; 15747ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1575b574ce3eSThinh Nguyen switch (hwparam_gen) { 1576b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 15777ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1578b574ce3eSThinh Nguyen break; 1579b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1580b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1581b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1582b574ce3eSThinh Nguyen else 1583b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1584b574ce3eSThinh Nguyen break; 1585b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1586b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1587b574ce3eSThinh Nguyen break; 1588b574ce3eSThinh Nguyen default: 1589b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1590b574ce3eSThinh Nguyen break; 1591b574ce3eSThinh Nguyen } 15927ac51a12SJohn Youn break; 15937ac51a12SJohn Youn } 159467848146SThinh Nguyen 159567848146SThinh Nguyen /* 159667848146SThinh Nguyen * Currently the controller does not have visibility into the HW 159767848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 159867848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 159967848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 160067848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 160167848146SThinh Nguyen */ 160267848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 160367848146SThinh Nguyen switch (dwc->max_ssp_rate) { 160467848146SThinh Nguyen case USB_SSP_GEN_2x1: 160567848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 160667848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 160767848146SThinh Nguyen break; 160867848146SThinh Nguyen case USB_SSP_GEN_1x2: 160967848146SThinh Nguyen case USB_SSP_GEN_2x2: 161067848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 161167848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 161267848146SThinh Nguyen break; 161367848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 161467848146SThinh Nguyen default: 161567848146SThinh Nguyen switch (hwparam_gen) { 161667848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 161767848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 161867848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 161967848146SThinh Nguyen else 162067848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 162167848146SThinh Nguyen break; 162267848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 162367848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 162467848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 162567848146SThinh Nguyen break; 162667848146SThinh Nguyen } 162767848146SThinh Nguyen break; 162867848146SThinh Nguyen } 162967848146SThinh Nguyen } 16307ac51a12SJohn Youn } 16317ac51a12SJohn Youn 1632c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1633c5ac6116SFelipe Balbi { 1634c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 163544feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1636c5ac6116SFelipe Balbi struct dwc3 *dwc; 1637c5ac6116SFelipe Balbi 1638c5ac6116SFelipe Balbi int ret; 1639c5ac6116SFelipe Balbi 1640c5ac6116SFelipe Balbi void __iomem *regs; 1641c5ac6116SFelipe Balbi 1642c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1643c5ac6116SFelipe Balbi if (!dwc) 1644c5ac6116SFelipe Balbi return -ENOMEM; 1645c5ac6116SFelipe Balbi 1646c5ac6116SFelipe Balbi dwc->dev = dev; 1647c5ac6116SFelipe Balbi 1648c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1649c5ac6116SFelipe Balbi if (!res) { 1650c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1651c5ac6116SFelipe Balbi return -ENODEV; 1652c5ac6116SFelipe Balbi } 1653c5ac6116SFelipe Balbi 1654c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1655c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1656c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1657c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1658c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1659c5ac6116SFelipe Balbi 1660c5ac6116SFelipe Balbi /* 1661c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1662c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1663c5ac6116SFelipe Balbi */ 166444feb8e6SMasahiro Yamada dwc_res = *res; 166544feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 166644feb8e6SMasahiro Yamada 166744feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 166844feb8e6SMasahiro Yamada if (IS_ERR(regs)) 166944feb8e6SMasahiro Yamada return PTR_ERR(regs); 1670c5ac6116SFelipe Balbi 1671c5ac6116SFelipe Balbi dwc->regs = regs; 167244feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1673c5ac6116SFelipe Balbi 1674c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1675c5ac6116SFelipe Balbi 167647ce4590SFabio Aiuto if (!dwc->sysdev_is_parent) { 167745d39448SSven Peter ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 167845d39448SSven Peter if (ret) 167945d39448SSven Peter return ret; 168047ce4590SFabio Aiuto } 168145d39448SSven Peter 1682babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1683fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1684fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1685fe8abf33SMasahiro Yamada 168661527777SHans de Goede if (dev->of_node) { 1687fe8abf33SMasahiro Yamada /* 168861527777SHans de Goede * Clocks are optional, but new DT platforms should support all 168961527777SHans de Goede * clocks as required by the DT-binding. 1690fe8abf33SMasahiro Yamada */ 169133fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 169233fb697eSSean Anderson if (IS_ERR(dwc->bus_clk)) 169333fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 169433fb697eSSean Anderson "could not get bus clock\n"); 16950d3a9708SJohn Stultz 169633fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 169733fb697eSSean Anderson if (IS_ERR(dwc->ref_clk)) 169833fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 169933fb697eSSean Anderson "could not get ref clock\n"); 170033fb697eSSean Anderson 170133fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 170233fb697eSSean Anderson if (IS_ERR(dwc->susp_clk)) 170333fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 170433fb697eSSean Anderson "could not get suspend clock\n"); 170561527777SHans de Goede } 1706fe8abf33SMasahiro Yamada 1707fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1708fe8abf33SMasahiro Yamada if (ret) 170903bf32bbSAndrey Smirnov return ret; 1710fe8abf33SMasahiro Yamada 171133fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1712fe8abf33SMasahiro Yamada if (ret) 1713fe8abf33SMasahiro Yamada goto assert_reset; 1714fe8abf33SMasahiro Yamada 1715dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1716dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1717dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1718dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1719dc1b5d9aSEnric Balletbo i Serra } 1720dc1b5d9aSEnric Balletbo i Serra 17216c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 17222917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 17236c89cce0SHeikki Krogerus 172472246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1725f88359e1SYu Chen mutex_init(&dwc->mutex); 172672246da4SFelipe Balbi 1727fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1728fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1729fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1730802ca850SChanho Park pm_runtime_enable(dev); 173132808237SRoger Quadros ret = pm_runtime_get_sync(dev); 173232808237SRoger Quadros if (ret < 0) 173332808237SRoger Quadros goto err1; 173432808237SRoger Quadros 1735802ca850SChanho Park pm_runtime_forbid(dev); 173672246da4SFelipe Balbi 17373921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 17383921426bSFelipe Balbi if (ret) { 17393921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 17403921426bSFelipe Balbi ret = -ENOMEM; 174132808237SRoger Quadros goto err2; 17423921426bSFelipe Balbi } 17433921426bSFelipe Balbi 17449d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 17459d6173e1SThinh Nguyen if (ret) 17469d6173e1SThinh Nguyen goto err3; 174732a4a135SFelipe Balbi 1748c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1749c499ff71SFelipe Balbi if (ret) 175032808237SRoger Quadros goto err3; 1751c499ff71SFelipe Balbi 175272246da4SFelipe Balbi ret = dwc3_core_init(dwc); 175372246da4SFelipe Balbi if (ret) { 17540c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 175532808237SRoger Quadros goto err4; 175672246da4SFelipe Balbi } 175772246da4SFelipe Balbi 17587ac51a12SJohn Youn dwc3_check_params(dwc); 175984524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 17602c7f1bd9SJohn Youn 17615f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 17625f94adfeSFelipe Balbi if (ret) 176332808237SRoger Quadros goto err5; 176472246da4SFelipe Balbi 1765fc8bb91bSFelipe Balbi pm_runtime_put(dev); 176672246da4SFelipe Balbi 176772246da4SFelipe Balbi return 0; 176872246da4SFelipe Balbi 176932808237SRoger Quadros err5: 177084524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1771f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 177203c1fd62SLi Jun 177303c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 177403c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 177503c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 177603c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 177703c1fd62SLi Jun 177803c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 177903c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 178003c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 178103c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 178203c1fd62SLi Jun 178308fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1784f122d33eSFelipe Balbi 178532808237SRoger Quadros err4: 1786c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 178772246da4SFelipe Balbi 178832808237SRoger Quadros err3: 17893921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 17903921426bSFelipe Balbi 179132808237SRoger Quadros err2: 179232808237SRoger Quadros pm_runtime_allow(&pdev->dev); 179332808237SRoger Quadros 179432808237SRoger Quadros err1: 179532808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 179632808237SRoger Quadros pm_runtime_disable(&pdev->dev); 179732808237SRoger Quadros 1798dc1b5d9aSEnric Balletbo i Serra disable_clks: 179933fb697eSSean Anderson dwc3_clk_disable(dwc); 1800fe8abf33SMasahiro Yamada assert_reset: 1801fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1802fe8abf33SMasahiro Yamada 1803b0bf77cdSColin Ian King if (dwc->usb_psy) 18046f0764b5SRay Chi power_supply_put(dwc->usb_psy); 18056f0764b5SRay Chi 180672246da4SFelipe Balbi return ret; 180772246da4SFelipe Balbi } 180872246da4SFelipe Balbi 1809fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 181072246da4SFelipe Balbi { 181172246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 18123da1f6eeSFelipe Balbi 1813fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 181472246da4SFelipe Balbi 1815dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 18162a042767SPeter Chen dwc3_debugfs_exit(dwc); 18178ba007a9SKishon Vijay Abraham I 181872246da4SFelipe Balbi dwc3_core_exit(dwc); 181988bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 182072246da4SFelipe Balbi 1821fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1822266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1823266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1824fc8bb91bSFelipe Balbi 1825c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1826c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1827c499ff71SFelipe Balbi 1828b0bf77cdSColin Ian King if (dwc->usb_psy) 18296f0764b5SRay Chi power_supply_put(dwc->usb_psy); 18306f0764b5SRay Chi 183172246da4SFelipe Balbi return 0; 183272246da4SFelipe Balbi } 183372246da4SFelipe Balbi 1834fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1835fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1836fe8abf33SMasahiro Yamada { 1837fe8abf33SMasahiro Yamada int ret; 1838fe8abf33SMasahiro Yamada 1839fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1840fe8abf33SMasahiro Yamada if (ret) 1841fe8abf33SMasahiro Yamada return ret; 1842fe8abf33SMasahiro Yamada 184333fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1844fe8abf33SMasahiro Yamada if (ret) 1845fe8abf33SMasahiro Yamada goto assert_reset; 1846fe8abf33SMasahiro Yamada 1847fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1848fe8abf33SMasahiro Yamada if (ret) 1849fe8abf33SMasahiro Yamada goto disable_clks; 1850fe8abf33SMasahiro Yamada 1851fe8abf33SMasahiro Yamada return 0; 1852fe8abf33SMasahiro Yamada 1853fe8abf33SMasahiro Yamada disable_clks: 185433fb697eSSean Anderson dwc3_clk_disable(dwc); 1855fe8abf33SMasahiro Yamada assert_reset: 1856fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1857fe8abf33SMasahiro Yamada 1858fe8abf33SMasahiro Yamada return ret; 1859fe8abf33SMasahiro Yamada } 1860fe8abf33SMasahiro Yamada 1861c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 18627415f17cSFelipe Balbi { 1863fc8bb91bSFelipe Balbi unsigned long flags; 1864bcb12877SManu Gautam u32 reg; 18657415f17cSFelipe Balbi 1866689bf72cSManu Gautam switch (dwc->current_dr_role) { 1867689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 18680227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 18690227cc84SLi Jun break; 1870fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 18717415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1872fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 187341a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1874689bf72cSManu Gautam dwc3_core_exit(dwc); 187551f5d49aSFelipe Balbi break; 1876689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1877bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1878c4a5153eSManu Gautam dwc3_core_exit(dwc); 1879c4a5153eSManu Gautam break; 1880bcb12877SManu Gautam } 1881bcb12877SManu Gautam 1882bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1883bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1884bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1885bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1886bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1887bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1888bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1889bcb12877SManu Gautam 1890bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1891bcb12877SManu Gautam usleep_range(5000, 6000); 1892bcb12877SManu Gautam } 1893bcb12877SManu Gautam 1894bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1895bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1896bcb12877SManu Gautam break; 1897f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1898f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1899f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1900f09cc79bSRoger Quadros break; 1901f09cc79bSRoger Quadros 1902f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1903f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1904f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1905f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 190641a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1907f09cc79bSRoger Quadros } 1908f09cc79bSRoger Quadros 1909f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1910f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1911f09cc79bSRoger Quadros break; 19127415f17cSFelipe Balbi default: 191351f5d49aSFelipe Balbi /* do nothing */ 19147415f17cSFelipe Balbi break; 19157415f17cSFelipe Balbi } 19167415f17cSFelipe Balbi 1917fc8bb91bSFelipe Balbi return 0; 1918fc8bb91bSFelipe Balbi } 1919fc8bb91bSFelipe Balbi 1920c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1921fc8bb91bSFelipe Balbi { 1922fc8bb91bSFelipe Balbi unsigned long flags; 1923fc8bb91bSFelipe Balbi int ret; 1924bcb12877SManu Gautam u32 reg; 1925fc8bb91bSFelipe Balbi 1926689bf72cSManu Gautam switch (dwc->current_dr_role) { 1927689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1928fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1929fc8bb91bSFelipe Balbi if (ret) 1930fc8bb91bSFelipe Balbi return ret; 1931fc8bb91bSFelipe Balbi 19327d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1933fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1934fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1935fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1936689bf72cSManu Gautam break; 1937689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1938c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1939fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1940c4a5153eSManu Gautam if (ret) 1941c4a5153eSManu Gautam return ret; 19427d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1943bcb12877SManu Gautam break; 1944c4a5153eSManu Gautam } 1945bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1946bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1947bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1948bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1949bcb12877SManu Gautam 1950bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1951bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1952bcb12877SManu Gautam 1953bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1954bcb12877SManu Gautam 1955bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1956bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1957c4a5153eSManu Gautam break; 1958f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1959f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1960f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1961f09cc79bSRoger Quadros break; 1962f09cc79bSRoger Quadros 19630e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 1964f09cc79bSRoger Quadros if (ret) 1965f09cc79bSRoger Quadros return ret; 1966f09cc79bSRoger Quadros 1967f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1968f09cc79bSRoger Quadros 1969f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1970f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1971f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1972f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1973f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1974f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1975f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1976f09cc79bSRoger Quadros } 1977f09cc79bSRoger Quadros 1978f09cc79bSRoger Quadros break; 1979fc8bb91bSFelipe Balbi default: 1980fc8bb91bSFelipe Balbi /* do nothing */ 1981fc8bb91bSFelipe Balbi break; 1982fc8bb91bSFelipe Balbi } 1983fc8bb91bSFelipe Balbi 1984fc8bb91bSFelipe Balbi return 0; 1985fc8bb91bSFelipe Balbi } 1986fc8bb91bSFelipe Balbi 1987fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1988fc8bb91bSFelipe Balbi { 1989689bf72cSManu Gautam switch (dwc->current_dr_role) { 1990c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1991fc8bb91bSFelipe Balbi if (dwc->connected) 1992fc8bb91bSFelipe Balbi return -EBUSY; 1993fc8bb91bSFelipe Balbi break; 1994c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1995fc8bb91bSFelipe Balbi default: 1996fc8bb91bSFelipe Balbi /* do nothing */ 1997fc8bb91bSFelipe Balbi break; 1998fc8bb91bSFelipe Balbi } 1999fc8bb91bSFelipe Balbi 2000fc8bb91bSFelipe Balbi return 0; 2001fc8bb91bSFelipe Balbi } 2002fc8bb91bSFelipe Balbi 2003fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2004fc8bb91bSFelipe Balbi { 2005fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2006fc8bb91bSFelipe Balbi int ret; 2007fc8bb91bSFelipe Balbi 2008fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2009fc8bb91bSFelipe Balbi return -EBUSY; 2010fc8bb91bSFelipe Balbi 2011c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2012fc8bb91bSFelipe Balbi if (ret) 2013fc8bb91bSFelipe Balbi return ret; 2014fc8bb91bSFelipe Balbi 2015fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 2016fc8bb91bSFelipe Balbi 2017fc8bb91bSFelipe Balbi return 0; 2018fc8bb91bSFelipe Balbi } 2019fc8bb91bSFelipe Balbi 2020fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2021fc8bb91bSFelipe Balbi { 2022fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2023fc8bb91bSFelipe Balbi int ret; 2024fc8bb91bSFelipe Balbi 2025fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 2026fc8bb91bSFelipe Balbi 2027c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2028fc8bb91bSFelipe Balbi if (ret) 2029fc8bb91bSFelipe Balbi return ret; 2030fc8bb91bSFelipe Balbi 2031689bf72cSManu Gautam switch (dwc->current_dr_role) { 2032689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2033fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2034fc8bb91bSFelipe Balbi break; 2035689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2036fc8bb91bSFelipe Balbi default: 2037fc8bb91bSFelipe Balbi /* do nothing */ 2038fc8bb91bSFelipe Balbi break; 2039fc8bb91bSFelipe Balbi } 2040fc8bb91bSFelipe Balbi 2041fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2042fc8bb91bSFelipe Balbi 2043fc8bb91bSFelipe Balbi return 0; 2044fc8bb91bSFelipe Balbi } 2045fc8bb91bSFelipe Balbi 2046fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2047fc8bb91bSFelipe Balbi { 2048fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2049fc8bb91bSFelipe Balbi 2050689bf72cSManu Gautam switch (dwc->current_dr_role) { 2051689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2052fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2053fc8bb91bSFelipe Balbi return -EBUSY; 2054fc8bb91bSFelipe Balbi break; 2055689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2056fc8bb91bSFelipe Balbi default: 2057fc8bb91bSFelipe Balbi /* do nothing */ 2058fc8bb91bSFelipe Balbi break; 2059fc8bb91bSFelipe Balbi } 2060fc8bb91bSFelipe Balbi 2061fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2062fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2063fc8bb91bSFelipe Balbi 2064fc8bb91bSFelipe Balbi return 0; 2065fc8bb91bSFelipe Balbi } 2066fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2067fc8bb91bSFelipe Balbi 2068fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2069fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2070fc8bb91bSFelipe Balbi { 2071fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2072fc8bb91bSFelipe Balbi int ret; 2073fc8bb91bSFelipe Balbi 2074c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2075fc8bb91bSFelipe Balbi if (ret) 2076fc8bb91bSFelipe Balbi return ret; 2077fc8bb91bSFelipe Balbi 20786344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 20796344475fSSekhar Nori 20807415f17cSFelipe Balbi return 0; 20817415f17cSFelipe Balbi } 20827415f17cSFelipe Balbi 20837415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 20847415f17cSFelipe Balbi { 20857415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 208657303488SKishon Vijay Abraham I int ret; 20877415f17cSFelipe Balbi 20886344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 20896344475fSSekhar Nori 2090c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 209151f5d49aSFelipe Balbi if (ret) 20925c4ad318SFelipe Balbi return ret; 20935c4ad318SFelipe Balbi 20947415f17cSFelipe Balbi pm_runtime_disable(dev); 20957415f17cSFelipe Balbi pm_runtime_set_active(dev); 20967415f17cSFelipe Balbi pm_runtime_enable(dev); 20977415f17cSFelipe Balbi 20987415f17cSFelipe Balbi return 0; 20997415f17cSFelipe Balbi } 2100f580170fSYu Chen 2101f580170fSYu Chen static void dwc3_complete(struct device *dev) 2102f580170fSYu Chen { 2103f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2104f580170fSYu Chen u32 reg; 2105f580170fSYu Chen 2106f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2107f580170fSYu Chen dwc->dis_split_quirk) { 2108f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2109f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2110f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2111f580170fSYu Chen } 2112f580170fSYu Chen } 2113f580170fSYu Chen #else 2114f580170fSYu Chen #define dwc3_complete NULL 21157f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 21167415f17cSFelipe Balbi 21177415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 21187415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2119f580170fSYu Chen .complete = dwc3_complete, 2120fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2121fc8bb91bSFelipe Balbi dwc3_runtime_idle) 21227415f17cSFelipe Balbi }; 21237415f17cSFelipe Balbi 21245088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 21255088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 21265088b6f5SKishon Vijay Abraham I { 212722a5aa17SFelipe Balbi .compatible = "snps,dwc3" 212822a5aa17SFelipe Balbi }, 212922a5aa17SFelipe Balbi { 21305088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 21315088b6f5SKishon Vijay Abraham I }, 21325088b6f5SKishon Vijay Abraham I { }, 21335088b6f5SKishon Vijay Abraham I }; 21345088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 21355088b6f5SKishon Vijay Abraham I #endif 21365088b6f5SKishon Vijay Abraham I 2137404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2138404905a6SHeikki Krogerus 2139404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2140404905a6SHeikki Krogerus 2141404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2142404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2143404905a6SHeikki Krogerus { }, 2144404905a6SHeikki Krogerus }; 2145404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2146404905a6SHeikki Krogerus #endif 2147404905a6SHeikki Krogerus 214872246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 214972246da4SFelipe Balbi .probe = dwc3_probe, 21507690417dSBill Pemberton .remove = dwc3_remove, 215172246da4SFelipe Balbi .driver = { 215272246da4SFelipe Balbi .name = "dwc3", 21535088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2154404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 21557f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 215672246da4SFelipe Balbi }, 215772246da4SFelipe Balbi }; 215872246da4SFelipe Balbi 2159b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2160b1116dccSTobias Klauser 21617ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 216272246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 21635945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 216472246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2165