15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32f7e846f0SFelipe Balbi #include <linux/usb/of.h> 33a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3472246da4SFelipe Balbi 3572246da4SFelipe Balbi #include "core.h" 3672246da4SFelipe Balbi #include "gadget.h" 3772246da4SFelipe Balbi #include "io.h" 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #include "debug.h" 4072246da4SFelipe Balbi 41fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 428300dd23SFelipe Balbi 439d6173e1SThinh Nguyen /** 449d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 459d6173e1SThinh Nguyen * @dwc: pointer to our context structure 469d6173e1SThinh Nguyen */ 479d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 489d6173e1SThinh Nguyen { 499d6173e1SThinh Nguyen enum usb_dr_mode mode; 509d6173e1SThinh Nguyen struct device *dev = dwc->dev; 519d6173e1SThinh Nguyen unsigned int hw_mode; 529d6173e1SThinh Nguyen 539d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 549d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 559d6173e1SThinh Nguyen 569d6173e1SThinh Nguyen mode = dwc->dr_mode; 579d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 589d6173e1SThinh Nguyen 599d6173e1SThinh Nguyen switch (hw_mode) { 609d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 619d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 629d6173e1SThinh Nguyen dev_err(dev, 639d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 649d6173e1SThinh Nguyen return -EINVAL; 659d6173e1SThinh Nguyen } 669d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 679d6173e1SThinh Nguyen break; 689d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 699d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 709d6173e1SThinh Nguyen dev_err(dev, 719d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 729d6173e1SThinh Nguyen return -EINVAL; 739d6173e1SThinh Nguyen } 749d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 759d6173e1SThinh Nguyen break; 769d6173e1SThinh Nguyen default: 779d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 789d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 799d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 81a7700468SThinh Nguyen 82a7700468SThinh Nguyen /* 8389a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8489a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8589a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 86a7700468SThinh Nguyen */ 8789a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 888bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 898bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 909af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 91a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 929d6173e1SThinh Nguyen } 939d6173e1SThinh Nguyen 949d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 959d6173e1SThinh Nguyen dev_warn(dev, 969d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 979d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 989d6173e1SThinh Nguyen 999d6173e1SThinh Nguyen dwc->dr_mode = mode; 1009d6173e1SThinh Nguyen } 1019d6173e1SThinh Nguyen 1029d6173e1SThinh Nguyen return 0; 1039d6173e1SThinh Nguyen } 1049d6173e1SThinh Nguyen 105f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1063140e8cbSSebastian Andrzej Siewior { 1073140e8cbSSebastian Andrzej Siewior u32 reg; 1083140e8cbSSebastian Andrzej Siewior 1093140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1103140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1113140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1123140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113c4a5153eSManu Gautam 114c4a5153eSManu Gautam dwc->current_dr_role = mode; 11541ce1456SRoger Quadros } 1166b3261a2SRoger Quadros 11741ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 11841ce1456SRoger Quadros { 11941ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12041ce1456SRoger Quadros unsigned long flags; 12141ce1456SRoger Quadros int ret; 122f580170fSYu Chen u32 reg; 12341ce1456SRoger Quadros 124c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 125c2cd3452SMartin Kepplinger 126f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 127f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 128f09cc79bSRoger Quadros 12941ce1456SRoger Quadros if (!dwc->desired_dr_role) 130c2cd3452SMartin Kepplinger goto out; 13141ce1456SRoger Quadros 13241ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 133c2cd3452SMartin Kepplinger goto out; 13441ce1456SRoger Quadros 135f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 136c2cd3452SMartin Kepplinger goto out; 13741ce1456SRoger Quadros 13841ce1456SRoger Quadros switch (dwc->current_dr_role) { 13941ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14041ce1456SRoger Quadros dwc3_host_exit(dwc); 14141ce1456SRoger Quadros break; 14241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14341ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14441ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14541ce1456SRoger Quadros break; 146f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 147f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 148f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 149f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 150f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 151f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 152f09cc79bSRoger Quadros break; 15341ce1456SRoger Quadros default: 15441ce1456SRoger Quadros break; 15541ce1456SRoger Quadros } 15641ce1456SRoger Quadros 15741ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 15841ce1456SRoger Quadros 15941ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 16041ce1456SRoger Quadros 16141ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 16241ce1456SRoger Quadros 16341ce1456SRoger Quadros switch (dwc->desired_dr_role) { 16441ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 16541ce1456SRoger Quadros ret = dwc3_host_init(dwc); 166958d1a4cSFelipe Balbi if (ret) { 16741ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 168958d1a4cSFelipe Balbi } else { 169958d1a4cSFelipe Balbi if (dwc->usb2_phy) 170958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 171958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 172644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 173f580170fSYu Chen if (dwc->dis_split_quirk) { 174f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 175f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 176f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 177f580170fSYu Chen } 178958d1a4cSFelipe Balbi } 17941ce1456SRoger Quadros break; 18041ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 18141ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 182958d1a4cSFelipe Balbi 183958d1a4cSFelipe Balbi if (dwc->usb2_phy) 184958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 185958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 186644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 187958d1a4cSFelipe Balbi 18841ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 18941ce1456SRoger Quadros if (ret) 19041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 19141ce1456SRoger Quadros break; 192f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 193f09cc79bSRoger Quadros dwc3_otg_init(dwc); 194f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 195f09cc79bSRoger Quadros break; 19641ce1456SRoger Quadros default: 19741ce1456SRoger Quadros break; 19841ce1456SRoger Quadros } 199f09cc79bSRoger Quadros 200c2cd3452SMartin Kepplinger out: 201c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 202c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 20341ce1456SRoger Quadros } 20441ce1456SRoger Quadros 20541ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 20641ce1456SRoger Quadros { 20741ce1456SRoger Quadros unsigned long flags; 20841ce1456SRoger Quadros 209dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 210dc336b19SLi Jun return; 211dc336b19SLi Jun 21241ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 21341ce1456SRoger Quadros dwc->desired_dr_role = mode; 21441ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 21541ce1456SRoger Quadros 216084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2173140e8cbSSebastian Andrzej Siewior } 2188300dd23SFelipe Balbi 219cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 220cf6d867dSFelipe Balbi { 221cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 222cf6d867dSFelipe Balbi u32 reg; 223cf6d867dSFelipe Balbi 224cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 225cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 226cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 227cf6d867dSFelipe Balbi 228cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 229cf6d867dSFelipe Balbi 230cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 231cf6d867dSFelipe Balbi } 232cf6d867dSFelipe Balbi 23372246da4SFelipe Balbi /** 23472246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 23572246da4SFelipe Balbi * @dwc: pointer to our context structure 23672246da4SFelipe Balbi */ 23757303488SKishon Vijay Abraham I static int dwc3_core_soft_reset(struct dwc3 *dwc) 23872246da4SFelipe Balbi { 23972246da4SFelipe Balbi u32 reg; 240f59dcab1SFelipe Balbi int retries = 1000; 24157303488SKishon Vijay Abraham I int ret; 24272246da4SFelipe Balbi 24351e1e7bcSFelipe Balbi usb_phy_init(dwc->usb2_phy); 24451e1e7bcSFelipe Balbi usb_phy_init(dwc->usb3_phy); 24557303488SKishon Vijay Abraham I ret = phy_init(dwc->usb2_generic_phy); 24657303488SKishon Vijay Abraham I if (ret < 0) 24757303488SKishon Vijay Abraham I return ret; 24857303488SKishon Vijay Abraham I 24957303488SKishon Vijay Abraham I ret = phy_init(dwc->usb3_generic_phy); 25057303488SKishon Vijay Abraham I if (ret < 0) { 25157303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 25257303488SKishon Vijay Abraham I return ret; 25357303488SKishon Vijay Abraham I } 25472246da4SFelipe Balbi 255f59dcab1SFelipe Balbi /* 256f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 257f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 258f59dcab1SFelipe Balbi * host-only mode, then we can return early. 259f59dcab1SFelipe Balbi */ 260c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 26157303488SKishon Vijay Abraham I return 0; 262f59dcab1SFelipe Balbi 263f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 264f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 265f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 266f59dcab1SFelipe Balbi 2674749e0e6SThinh Nguyen /* 2684749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2694749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2704749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2714749e0e6SThinh Nguyen * for 10 times instead. 2724749e0e6SThinh Nguyen */ 2739af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2744749e0e6SThinh Nguyen retries = 10; 2754749e0e6SThinh Nguyen 276f59dcab1SFelipe Balbi do { 277f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 278f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 279fab38333SThinh Nguyen goto done; 280f59dcab1SFelipe Balbi 2819af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2824749e0e6SThinh Nguyen msleep(20); 2834749e0e6SThinh Nguyen else 284f59dcab1SFelipe Balbi udelay(1); 285f59dcab1SFelipe Balbi } while (--retries); 286f59dcab1SFelipe Balbi 28700b42170SBrian Norris phy_exit(dwc->usb3_generic_phy); 28800b42170SBrian Norris phy_exit(dwc->usb2_generic_phy); 28900b42170SBrian Norris 290f59dcab1SFelipe Balbi return -ETIMEDOUT; 291fab38333SThinh Nguyen 292fab38333SThinh Nguyen done: 293fab38333SThinh Nguyen /* 2944749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 2954749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 2964749e0e6SThinh Nguyen * domain (synchronization delay). 297fab38333SThinh Nguyen */ 2989af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 299fab38333SThinh Nguyen msleep(50); 300fab38333SThinh Nguyen 301fab38333SThinh Nguyen return 0; 30272246da4SFelipe Balbi } 30372246da4SFelipe Balbi 304db2be4e9SNikhil Badola /* 305db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 306db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 307db2be4e9SNikhil Badola */ 308bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 309db2be4e9SNikhil Badola { 310db2be4e9SNikhil Badola u32 reg; 311db2be4e9SNikhil Badola u32 dft; 312db2be4e9SNikhil Badola 3139af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 314db2be4e9SNikhil Badola return; 315db2be4e9SNikhil Badola 316bcdb3272SFelipe Balbi if (dwc->fladj == 0) 317db2be4e9SNikhil Badola return; 318db2be4e9SNikhil Badola 319db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 320db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 321a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 322db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 323bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 324db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 325db2be4e9SNikhil Badola } 326db2be4e9SNikhil Badola } 327db2be4e9SNikhil Badola 328c5cc74e8SHeikki Krogerus /** 32972246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 33072246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 33172246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 33272246da4SFelipe Balbi */ 33372246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 33472246da4SFelipe Balbi struct dwc3_event_buffer *evt) 33572246da4SFelipe Balbi { 336d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 33772246da4SFelipe Balbi } 33872246da4SFelipe Balbi 33972246da4SFelipe Balbi /** 3401d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 34172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 34272246da4SFelipe Balbi * @length: size of the event buffer 34372246da4SFelipe Balbi * 3441d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 34572246da4SFelipe Balbi * otherwise ERR_PTR(errno). 34672246da4SFelipe Balbi */ 34767d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 34867d0b500SFelipe Balbi unsigned length) 34972246da4SFelipe Balbi { 35072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 35172246da4SFelipe Balbi 352380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 35372246da4SFelipe Balbi if (!evt) 35472246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 35572246da4SFelipe Balbi 35672246da4SFelipe Balbi evt->dwc = dwc; 35772246da4SFelipe Balbi evt->length = length; 358d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 359d9fa4c63SJohn Youn if (!evt->cache) 360d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 361d9fa4c63SJohn Youn 362d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 36372246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 364e32672f0SFelipe Balbi if (!evt->buf) 36572246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 36672246da4SFelipe Balbi 36772246da4SFelipe Balbi return evt; 36872246da4SFelipe Balbi } 36972246da4SFelipe Balbi 37072246da4SFelipe Balbi /** 37172246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 37272246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 37372246da4SFelipe Balbi */ 37472246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 37572246da4SFelipe Balbi { 37672246da4SFelipe Balbi struct dwc3_event_buffer *evt; 37772246da4SFelipe Balbi 378696c8b12SFelipe Balbi evt = dwc->ev_buf; 37964b6c8a7SAnton Tikhomirov if (evt) 38072246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 38172246da4SFelipe Balbi } 38272246da4SFelipe Balbi 38372246da4SFelipe Balbi /** 38472246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 3851d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 38672246da4SFelipe Balbi * @length: size of event buffer 38772246da4SFelipe Balbi * 3881d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 38972246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 39072246da4SFelipe Balbi */ 39141ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 39272246da4SFelipe Balbi { 39372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 39472246da4SFelipe Balbi 39572246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 39672246da4SFelipe Balbi if (IS_ERR(evt)) { 39772246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 39872246da4SFelipe Balbi return PTR_ERR(evt); 39972246da4SFelipe Balbi } 400696c8b12SFelipe Balbi dwc->ev_buf = evt; 40172246da4SFelipe Balbi 40272246da4SFelipe Balbi return 0; 40372246da4SFelipe Balbi } 40472246da4SFelipe Balbi 40572246da4SFelipe Balbi /** 40672246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4071d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 40872246da4SFelipe Balbi * 40972246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 41072246da4SFelipe Balbi */ 411f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 41272246da4SFelipe Balbi { 41372246da4SFelipe Balbi struct dwc3_event_buffer *evt; 41472246da4SFelipe Balbi 415696c8b12SFelipe Balbi evt = dwc->ev_buf; 4167acd85e0SPaul Zimmerman evt->lpos = 0; 417660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 41872246da4SFelipe Balbi lower_32_bits(evt->dma)); 419660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 42072246da4SFelipe Balbi upper_32_bits(evt->dma)); 421660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 42268d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 423660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 42472246da4SFelipe Balbi 42572246da4SFelipe Balbi return 0; 42672246da4SFelipe Balbi } 42772246da4SFelipe Balbi 428f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 42972246da4SFelipe Balbi { 43072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43172246da4SFelipe Balbi 432696c8b12SFelipe Balbi evt = dwc->ev_buf; 4337acd85e0SPaul Zimmerman 4347acd85e0SPaul Zimmerman evt->lpos = 0; 4357acd85e0SPaul Zimmerman 436660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 437660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 438660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 43968d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 440660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 44172246da4SFelipe Balbi } 44272246da4SFelipe Balbi 4430ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 4440ffcaf37SFelipe Balbi { 4450ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4460ffcaf37SFelipe Balbi return 0; 4470ffcaf37SFelipe Balbi 4480ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4490ffcaf37SFelipe Balbi return 0; 4500ffcaf37SFelipe Balbi 4510ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 4520ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 4530ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 4540ffcaf37SFelipe Balbi return -ENOMEM; 4550ffcaf37SFelipe Balbi 4560ffcaf37SFelipe Balbi return 0; 4570ffcaf37SFelipe Balbi } 4580ffcaf37SFelipe Balbi 4590ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 4600ffcaf37SFelipe Balbi { 4610ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 4620ffcaf37SFelipe Balbi u32 param; 4630ffcaf37SFelipe Balbi int ret; 4640ffcaf37SFelipe Balbi 4650ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4660ffcaf37SFelipe Balbi return 0; 4670ffcaf37SFelipe Balbi 4680ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4690ffcaf37SFelipe Balbi return 0; 4700ffcaf37SFelipe Balbi 4710ffcaf37SFelipe Balbi /* should never fall here */ 4720ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 4730ffcaf37SFelipe Balbi return 0; 4740ffcaf37SFelipe Balbi 475d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 4760ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 4770ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 478d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 479d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 4800ffcaf37SFelipe Balbi ret = -EFAULT; 4810ffcaf37SFelipe Balbi goto err0; 4820ffcaf37SFelipe Balbi } 4830ffcaf37SFelipe Balbi 4840ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 4850ffcaf37SFelipe Balbi 4860ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 4870ffcaf37SFelipe Balbi 4880ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4890ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 4900ffcaf37SFelipe Balbi if (ret < 0) 4910ffcaf37SFelipe Balbi goto err1; 4920ffcaf37SFelipe Balbi 4930ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 4940ffcaf37SFelipe Balbi 4950ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4960ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 4970ffcaf37SFelipe Balbi if (ret < 0) 4980ffcaf37SFelipe Balbi goto err1; 4990ffcaf37SFelipe Balbi 5000ffcaf37SFelipe Balbi return 0; 5010ffcaf37SFelipe Balbi 5020ffcaf37SFelipe Balbi err1: 503d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5040ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5050ffcaf37SFelipe Balbi 5060ffcaf37SFelipe Balbi err0: 5070ffcaf37SFelipe Balbi return ret; 5080ffcaf37SFelipe Balbi } 5090ffcaf37SFelipe Balbi 5100ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5110ffcaf37SFelipe Balbi { 5120ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5130ffcaf37SFelipe Balbi return; 5140ffcaf37SFelipe Balbi 5150ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5160ffcaf37SFelipe Balbi return; 5170ffcaf37SFelipe Balbi 5180ffcaf37SFelipe Balbi /* should never fall here */ 5190ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5200ffcaf37SFelipe Balbi return; 5210ffcaf37SFelipe Balbi 522d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5230ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5240ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 5250ffcaf37SFelipe Balbi } 5260ffcaf37SFelipe Balbi 527789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 528789451f6SFelipe Balbi { 529789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 530789451f6SFelipe Balbi 53147d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 532789451f6SFelipe Balbi } 533789451f6SFelipe Balbi 53441ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 53526ceca97SFelipe Balbi { 53626ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 53726ceca97SFelipe Balbi 53826ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 53926ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 54026ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 54126ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 54226ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 54326ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 54426ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 54526ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 54626ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 54726ceca97SFelipe Balbi } 54826ceca97SFelipe Balbi 54998112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 55098112041SRoger Quadros { 55198112041SRoger Quadros int intf; 55298112041SRoger Quadros int ret = 0; 55398112041SRoger Quadros 55498112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 55598112041SRoger Quadros 55698112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 55798112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 55898112041SRoger Quadros dwc->hsphy_interface && 55998112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 56098112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 56198112041SRoger Quadros 56298112041SRoger Quadros return ret; 56398112041SRoger Quadros } 56498112041SRoger Quadros 56572246da4SFelipe Balbi /** 566b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 567b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 56888bc9d19SHeikki Krogerus * 56988bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 57088bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 57188bc9d19SHeikki Krogerus * the core in dwc3_core_init. 572b5a65c40SHuang Rui */ 57388bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 574b5a65c40SHuang Rui { 5759ba3aca8SThinh Nguyen unsigned int hw_mode; 576b5a65c40SHuang Rui u32 reg; 577b5a65c40SHuang Rui 5789ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 5799ba3aca8SThinh Nguyen 580b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 581b5a65c40SHuang Rui 5822164a476SHuang Rui /* 5831966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 5841966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 5851966b865SFelipe Balbi */ 5861966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 5871966b865SFelipe Balbi 5881966b865SFelipe Balbi /* 5892164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 5902164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 5912164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 5922164a476SHuang Rui * to '1' after the core initialization is completed. 5932164a476SHuang Rui */ 5949af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 5952164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 5962164a476SHuang Rui 5979ba3aca8SThinh Nguyen /* 5989ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 5999ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6009ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6019ba3aca8SThinh Nguyen */ 6029ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6039ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6049ba3aca8SThinh Nguyen 605b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 606b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 607b5a65c40SHuang Rui 608e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 609e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 610e58dd357SRajesh Bhagat 611df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 612df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 613df31f5b3SHuang Rui 614a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 615a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 616a2a1d0f5SHuang Rui 61741c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 61841c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 61941c06ffdSHuang Rui 620fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 621fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 622fb67afcaSHuang Rui 62314f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 62414f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 62514f4ac53SHuang Rui 6266b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 6276b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 6286b6a0c9aSHuang Rui 629cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 63059acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 63159acfa20SHuang Rui 63200fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 63300fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 63400fe081dSWilliam Wu 635b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 636b5a65c40SHuang Rui 6372164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 6382164a476SHuang Rui 6393e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 6403e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 6413e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 64243cacb03SFelipe Balbi if (dwc->hsphy_interface && 64343cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 6443e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 64588bc9d19SHeikki Krogerus break; 64643cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 64743cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 6483e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 64988bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 6503e10a2ceSHeikki Krogerus } else { 65188bc9d19SHeikki Krogerus /* Relying on default value. */ 65288bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 6533e10a2ceSHeikki Krogerus break; 6543e10a2ceSHeikki Krogerus } 655df561f66SGustavo A. R. Silva fallthrough; 65688bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 6573e10a2ceSHeikki Krogerus default: 6583e10a2ceSHeikki Krogerus break; 6593e10a2ceSHeikki Krogerus } 6603e10a2ceSHeikki Krogerus 66132f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 66232f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 66332f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 66432f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66532f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 66632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 66732f2ed86SWilliam Wu break; 66832f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 66932f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 67032f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 67132f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 67232f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 67332f2ed86SWilliam Wu break; 67432f2ed86SWilliam Wu default: 67532f2ed86SWilliam Wu break; 67632f2ed86SWilliam Wu } 67732f2ed86SWilliam Wu 6782164a476SHuang Rui /* 6792164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 6802164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 6812164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 6822164a476SHuang Rui * '1' after the core initialization is completed. 6832164a476SHuang Rui */ 6849af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6852164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 6862164a476SHuang Rui 6879ba3aca8SThinh Nguyen /* 6889ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 6899ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6909ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6919ba3aca8SThinh Nguyen */ 6929ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6939ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6949ba3aca8SThinh Nguyen 695cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 6960effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6970effe0a3SHuang Rui 698ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 699ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 700eafeacf1SThinh Nguyen else 701eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 702ec791d14SJohn Youn 70316199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 70416199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 70516199f33SWilliam Wu 7062164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 70788bc9d19SHeikki Krogerus 70888bc9d19SHeikki Krogerus return 0; 709b5a65c40SHuang Rui } 710b5a65c40SHuang Rui 711c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 712c499ff71SFelipe Balbi { 713c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 714c499ff71SFelipe Balbi 715c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 716c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 717c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 718c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 719c499ff71SFelipe Balbi 720c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 721c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 722c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 723c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 724240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 725fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 726c499ff71SFelipe Balbi } 727c499ff71SFelipe Balbi 7280759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 72972246da4SFelipe Balbi { 73072246da4SFelipe Balbi u32 reg; 73172246da4SFelipe Balbi 7327650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 7339af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 7340759956fSFelipe Balbi 7357650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 7369af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 737690fb371SJohn Youn dwc->revision = reg; 7389af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 739690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 740475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 741690fb371SJohn Youn } else { 7420759956fSFelipe Balbi return false; 7437650bd74SSebastian Andrzej Siewior } 7447650bd74SSebastian Andrzej Siewior 7450759956fSFelipe Balbi return true; 7460e1e5c47SPaul Zimmerman } 7470e1e5c47SPaul Zimmerman 748941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 74972246da4SFelipe Balbi { 75072246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 75172246da4SFelipe Balbi u32 reg; 752c499ff71SFelipe Balbi 7534878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 7543e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 7554878a028SSebastian Andrzej Siewior 756164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 7574878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 75832a4a135SFelipe Balbi /** 75932a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 76032a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 76132a4a135SFelipe Balbi * 76232a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 76332a4a135SFelipe Balbi * configurations. 76432a4a135SFelipe Balbi * 76532a4a135SFelipe Balbi * Refers to: 76632a4a135SFelipe Balbi * 76732a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 76832a4a135SFelipe Balbi * SOF/ITP Mode Used 76932a4a135SFelipe Balbi */ 77032a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 77132a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 7729af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 77332a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 77432a4a135SFelipe Balbi else 7754878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 7764878a028SSebastian Andrzej Siewior break; 7770ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 7780ffcaf37SFelipe Balbi /* enable hibernation here */ 7790ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 7802eac3992SHuang Rui 7812eac3992SHuang Rui /* 7822eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 7832eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 7842eac3992SHuang Rui */ 7852eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 7860ffcaf37SFelipe Balbi break; 7874878a028SSebastian Andrzej Siewior default: 7885eb30cedSFelipe Balbi /* nothing */ 7895eb30cedSFelipe Balbi break; 7904878a028SSebastian Andrzej Siewior } 7914878a028SSebastian Andrzej Siewior 792946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 793946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 7946af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 795946bd579SHuang Rui dwc->is_fpga = true; 796946bd579SHuang Rui } 797946bd579SHuang Rui 7983b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 7993b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 8003b81221aSHuang Rui 8013b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 8023b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 8033b81221aSHuang Rui else 8043b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 8053b81221aSHuang Rui 8069a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 8079a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 8089a5b2f31SHuang Rui 8094878a028SSebastian Andrzej Siewior /* 8104878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 8111d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 8124878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 8131d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 8144878a028SSebastian Andrzej Siewior */ 8159af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 8164878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 8174878a028SSebastian Andrzej Siewior 8184878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 819941f918eSFelipe Balbi } 8204878a028SSebastian Andrzej Siewior 821f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 82298112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 823f54edb53SFelipe Balbi 824d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 825d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 826d9612c2fSPengbo Mu { 827d9612c2fSPengbo Mu struct device *dev = dwc->dev; 828d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 829d9612c2fSPengbo Mu bool incrx_mode; 830d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 831d9612c2fSPengbo Mu u32 incrx_size; 832d9612c2fSPengbo Mu u32 *vals; 833d9612c2fSPengbo Mu u32 cfg; 834d9612c2fSPengbo Mu int ntype; 835d9612c2fSPengbo Mu int ret; 836d9612c2fSPengbo Mu int i; 837d9612c2fSPengbo Mu 838d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 839d9612c2fSPengbo Mu 840d9612c2fSPengbo Mu /* 841d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 842d9612c2fSPengbo Mu * Get the number of value from this property: 843d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 844d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 845d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 846d9612c2fSPengbo Mu */ 847a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 848d9612c2fSPengbo Mu if (ntype <= 0) 849d9612c2fSPengbo Mu return; 850d9612c2fSPengbo Mu 851d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 852d9612c2fSPengbo Mu if (!vals) { 853d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 854d9612c2fSPengbo Mu return; 855d9612c2fSPengbo Mu } 856d9612c2fSPengbo Mu 857d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 858d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 859d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 860d9612c2fSPengbo Mu if (ret) { 86175ecb9ddSAndy Shevchenko kfree(vals); 862d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 863d9612c2fSPengbo Mu return; 864d9612c2fSPengbo Mu } 865d9612c2fSPengbo Mu 866d9612c2fSPengbo Mu incrx_size = *vals; 867d9612c2fSPengbo Mu 868d9612c2fSPengbo Mu if (ntype > 1) { 869d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 870d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 871d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 872d9612c2fSPengbo Mu if (vals[i] > incrx_size) 873d9612c2fSPengbo Mu incrx_size = vals[i]; 874d9612c2fSPengbo Mu } 875d9612c2fSPengbo Mu } else { 876d9612c2fSPengbo Mu /* INCRX burst mode */ 877d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 878d9612c2fSPengbo Mu } 879d9612c2fSPengbo Mu 88075ecb9ddSAndy Shevchenko kfree(vals); 88175ecb9ddSAndy Shevchenko 882d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 883d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 884d9612c2fSPengbo Mu if (incrx_mode) 885d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 886d9612c2fSPengbo Mu switch (incrx_size) { 887d9612c2fSPengbo Mu case 256: 888d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 889d9612c2fSPengbo Mu break; 890d9612c2fSPengbo Mu case 128: 891d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 892d9612c2fSPengbo Mu break; 893d9612c2fSPengbo Mu case 64: 894d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 895d9612c2fSPengbo Mu break; 896d9612c2fSPengbo Mu case 32: 897d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 898d9612c2fSPengbo Mu break; 899d9612c2fSPengbo Mu case 16: 900d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 901d9612c2fSPengbo Mu break; 902d9612c2fSPengbo Mu case 8: 903d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 904d9612c2fSPengbo Mu break; 905d9612c2fSPengbo Mu case 4: 906d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 907d9612c2fSPengbo Mu break; 908d9612c2fSPengbo Mu case 1: 909d9612c2fSPengbo Mu break; 910d9612c2fSPengbo Mu default: 911d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 912d9612c2fSPengbo Mu break; 913d9612c2fSPengbo Mu } 914d9612c2fSPengbo Mu 915d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 916d9612c2fSPengbo Mu } 917d9612c2fSPengbo Mu 918941f918eSFelipe Balbi /** 919941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 920941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 921941f918eSFelipe Balbi * 922941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 923941f918eSFelipe Balbi */ 924941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 925941f918eSFelipe Balbi { 9269ba3aca8SThinh Nguyen unsigned int hw_mode; 927941f918eSFelipe Balbi u32 reg; 928941f918eSFelipe Balbi int ret; 929941f918eSFelipe Balbi 9309ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 9319ba3aca8SThinh Nguyen 932941f918eSFelipe Balbi /* 933941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 934941f918eSFelipe Balbi * out which kernel version a bug was found. 935941f918eSFelipe Balbi */ 936941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 937941f918eSFelipe Balbi 938941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 939941f918eSFelipe Balbi if (ret) 940941f918eSFelipe Balbi goto err0; 941941f918eSFelipe Balbi 94298112041SRoger Quadros if (!dwc->ulpi_ready) { 94398112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 94498112041SRoger Quadros if (ret) 94598112041SRoger Quadros goto err0; 94698112041SRoger Quadros dwc->ulpi_ready = true; 94798112041SRoger Quadros } 94898112041SRoger Quadros 94998112041SRoger Quadros if (!dwc->phys_ready) { 95098112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 95198112041SRoger Quadros if (ret) 95298112041SRoger Quadros goto err0a; 95398112041SRoger Quadros dwc->phys_ready = true; 95498112041SRoger Quadros } 95598112041SRoger Quadros 95698112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 95798112041SRoger Quadros if (ret) 95898112041SRoger Quadros goto err0a; 95998112041SRoger Quadros 9609ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 9619af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 9629ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 9639ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 9649ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 9659ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 9669ba3aca8SThinh Nguyen } 9679ba3aca8SThinh Nguyen 9689ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 9699ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 9709ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 9719ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 9729ba3aca8SThinh Nguyen } 9739ba3aca8SThinh Nguyen } 9749ba3aca8SThinh Nguyen 975941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 976c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 9770ffcaf37SFelipe Balbi 9780ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 9790ffcaf37SFelipe Balbi if (ret) 980c499ff71SFelipe Balbi goto err1; 981c499ff71SFelipe Balbi 982c499ff71SFelipe Balbi /* Adjust Frame Length */ 983c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 984c499ff71SFelipe Balbi 985d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 986d9612c2fSPengbo Mu 987c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 988c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 989c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 990c499ff71SFelipe Balbi if (ret < 0) 9910ffcaf37SFelipe Balbi goto err2; 9920ffcaf37SFelipe Balbi 993c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 994c499ff71SFelipe Balbi if (ret < 0) 995c499ff71SFelipe Balbi goto err3; 996c499ff71SFelipe Balbi 997c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 998c499ff71SFelipe Balbi if (ret) { 999c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1000c499ff71SFelipe Balbi goto err4; 1001c499ff71SFelipe Balbi } 1002c499ff71SFelipe Balbi 100306281d46SJohn Youn /* 100406281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 100506281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 100606281d46SJohn Youn * DWC_usb31 controller. 100706281d46SJohn Youn */ 10089af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 100906281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 101006281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 101106281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 101206281d46SJohn Youn } 101306281d46SJohn Youn 10149af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 10150bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 101665db7a0cSWilliam Wu 101765db7a0cSWilliam Wu /* 101865db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 101965db7a0cSWilliam Wu * in HS when the device is in the L1 state. 102065db7a0cSWilliam Wu */ 10219af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 10220bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 102365db7a0cSWilliam Wu 102465db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 102565db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 102665db7a0cSWilliam Wu 10277ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 10287ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 10297ba6b09fSNeil Armstrong 10300bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 10310bb39ca1SJohn Youn } 10320bb39ca1SJohn Youn 1033b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1034b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1035b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1036b138e23dSAnurag Kumar Vulisha 1037b138e23dSAnurag Kumar Vulisha /* 1038b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1039b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1040b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1041b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1042b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1043b138e23dSAnurag Kumar Vulisha */ 1044b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1045b138e23dSAnurag Kumar Vulisha 1046b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1047b138e23dSAnurag Kumar Vulisha } 1048b138e23dSAnurag Kumar Vulisha 1049938a5ad1SThinh Nguyen /* 1050938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1051938a5ad1SThinh Nguyen * RX and/or TX threshold. 1052938a5ad1SThinh Nguyen */ 10539af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1054938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1055938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1056938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1057938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1058938a5ad1SThinh Nguyen 1059938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1060938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1061938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1062938a5ad1SThinh Nguyen 1063938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1064938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1065938a5ad1SThinh Nguyen 1066938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1067938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1068938a5ad1SThinh Nguyen 1069938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1070938a5ad1SThinh Nguyen } 1071938a5ad1SThinh Nguyen 1072938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1073938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1074938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1075938a5ad1SThinh Nguyen 1076938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1077938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1078938a5ad1SThinh Nguyen 1079938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1080938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1081938a5ad1SThinh Nguyen 1082938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1083938a5ad1SThinh Nguyen } 1084938a5ad1SThinh Nguyen } 1085938a5ad1SThinh Nguyen 108672246da4SFelipe Balbi return 0; 108772246da4SFelipe Balbi 1088c499ff71SFelipe Balbi err4: 10899b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1090c499ff71SFelipe Balbi 1091c499ff71SFelipe Balbi err3: 10929b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1093c499ff71SFelipe Balbi 10940ffcaf37SFelipe Balbi err2: 1095c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1096c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 10970ffcaf37SFelipe Balbi 10980ffcaf37SFelipe Balbi err1: 10990ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 11000ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 110157303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 110257303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 11030ffcaf37SFelipe Balbi 110498112041SRoger Quadros err0a: 110598112041SRoger Quadros dwc3_ulpi_exit(dwc); 110698112041SRoger Quadros 110772246da4SFelipe Balbi err0: 110872246da4SFelipe Balbi return ret; 110972246da4SFelipe Balbi } 111072246da4SFelipe Balbi 11113c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 111272246da4SFelipe Balbi { 11133c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1114941ea361SFelipe Balbi struct device_node *node = dev->of_node; 11153c9f94acSFelipe Balbi int ret; 111672246da4SFelipe Balbi 11175088b6f5SKishon Vijay Abraham I if (node) { 11185088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 11195088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1120bb674907SFelipe Balbi } else { 1121bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1122bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 11235088b6f5SKishon Vijay Abraham I } 11245088b6f5SKishon Vijay Abraham I 1125d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1126d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1127122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1128122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1129122f06e6SKishon Vijay Abraham I } else { 11300c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1131122f06e6SKishon Vijay Abraham I } 113251e1e7bcSFelipe Balbi } 113351e1e7bcSFelipe Balbi 1134d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1135315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1136122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1137122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1138122f06e6SKishon Vijay Abraham I } else { 11390c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1140122f06e6SKishon Vijay Abraham I } 114151e1e7bcSFelipe Balbi } 114251e1e7bcSFelipe Balbi 114357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 114457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 114557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 114657303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 114757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 114857303488SKishon Vijay Abraham I } else { 11490c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 115057303488SKishon Vijay Abraham I } 115157303488SKishon Vijay Abraham I } 115257303488SKishon Vijay Abraham I 115357303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 115457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 115557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 115657303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 115757303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 115857303488SKishon Vijay Abraham I } else { 11590c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 116057303488SKishon Vijay Abraham I } 116157303488SKishon Vijay Abraham I } 116257303488SKishon Vijay Abraham I 11633c9f94acSFelipe Balbi return 0; 11643c9f94acSFelipe Balbi } 11653c9f94acSFelipe Balbi 11665f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 11675f94adfeSFelipe Balbi { 11685f94adfeSFelipe Balbi struct device *dev = dwc->dev; 11695f94adfeSFelipe Balbi int ret; 11705f94adfeSFelipe Balbi 11715f94adfeSFelipe Balbi switch (dwc->dr_mode) { 11725f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 117341ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1174958d1a4cSFelipe Balbi 1175958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1176958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1177958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1178644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1179958d1a4cSFelipe Balbi 11805f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 11810c0a20f6SAndy Shevchenko if (ret) 11820c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 11835f94adfeSFelipe Balbi break; 11845f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 118541ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1186958d1a4cSFelipe Balbi 1187958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1188958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1189958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1190644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1191958d1a4cSFelipe Balbi 11925f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 11930c0a20f6SAndy Shevchenko if (ret) 11940c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 11955f94adfeSFelipe Balbi break; 11965f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 119741ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 11989840354fSRoger Quadros ret = dwc3_drd_init(dwc); 11990c0a20f6SAndy Shevchenko if (ret) 12000c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 12015f94adfeSFelipe Balbi break; 12025f94adfeSFelipe Balbi default: 12035f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 12045f94adfeSFelipe Balbi return -EINVAL; 12055f94adfeSFelipe Balbi } 12065f94adfeSFelipe Balbi 12075f94adfeSFelipe Balbi return 0; 12085f94adfeSFelipe Balbi } 12095f94adfeSFelipe Balbi 12105f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 12115f94adfeSFelipe Balbi { 12125f94adfeSFelipe Balbi switch (dwc->dr_mode) { 12135f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 12145f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 12155f94adfeSFelipe Balbi break; 12165f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 12175f94adfeSFelipe Balbi dwc3_host_exit(dwc); 12185f94adfeSFelipe Balbi break; 12195f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 12209840354fSRoger Quadros dwc3_drd_exit(dwc); 12215f94adfeSFelipe Balbi break; 12225f94adfeSFelipe Balbi default: 12235f94adfeSFelipe Balbi /* do nothing */ 12245f94adfeSFelipe Balbi break; 12255f94adfeSFelipe Balbi } 122609ed259fSBin Liu 122709ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 122809ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 12295f94adfeSFelipe Balbi } 12305f94adfeSFelipe Balbi 1231c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 12323c9f94acSFelipe Balbi { 1233c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 123480caf7d2SHuang Rui u8 lpm_nyet_threshold; 12356b6a0c9aSHuang Rui u8 tx_de_emphasis; 1236460d098cSHuang Rui u8 hird_threshold; 1237938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1238938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1239938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1240938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 12416f0764b5SRay Chi const char *usb_psy_name; 12426f0764b5SRay Chi int ret; 12433c9f94acSFelipe Balbi 124480caf7d2SHuang Rui /* default to highest possible threshold */ 12458d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 124680caf7d2SHuang Rui 12476b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 12486b6a0c9aSHuang Rui tx_de_emphasis = 1; 12496b6a0c9aSHuang Rui 1250460d098cSHuang Rui /* 1251460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1252460d098cSHuang Rui * threshold value of 0b1100 1253460d098cSHuang Rui */ 1254460d098cSHuang Rui hird_threshold = 12; 1255460d098cSHuang Rui 125663863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 125767848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 125806e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 125932f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 126063863b98SHeikki Krogerus 1261d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1262d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1263d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1264d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1265d64ff406SArnd Bergmann else 1266d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1267d64ff406SArnd Bergmann 12686f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 12696f0764b5SRay Chi if (ret >= 0) { 12706f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 12716f0764b5SRay Chi if (!dwc->usb_psy) 12726f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 12736f0764b5SRay Chi } 12746f0764b5SRay Chi 12753d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 127680caf7d2SHuang Rui "snps,has-lpm-erratum"); 12773d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 127880caf7d2SHuang Rui &lpm_nyet_threshold); 12793d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1280460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 12813d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1282460d098cSHuang Rui &hird_threshold); 1283d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1284d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 12853d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1286eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1287022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1288022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1289938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1290938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1291938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1292938a5ad1SThinh Nguyen &rx_max_burst_prd); 1293938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1294938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1295938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1296938a5ad1SThinh Nguyen &tx_max_burst_prd); 12973c9f94acSFelipe Balbi 12983d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 12993b81221aSHuang Rui "snps,disable_scramble_quirk"); 13003d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 13019a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 13023d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1303b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 13043d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1305df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 13063d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1307a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 13083d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 130941c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 13103d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1311fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 13123d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 131314f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 13143d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 131559acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 13163d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 13170effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1318ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1319ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1320729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1321729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1322729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1323729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1324e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1325e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 132616199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 132716199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 132800fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 132900fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 133065db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 133165db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 13327ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 13337ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 13346b6a0c9aSHuang Rui 13353d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 13366b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 13373d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 13386b6a0c9aSHuang Rui &tx_de_emphasis); 13393d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 13403e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 13413d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1342bcdb3272SFelipe Balbi &dwc->fladj); 13433d128919SHeikki Krogerus 134442bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 134542bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 134642bf02ecSRoger Quadros 1347f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1348f580170fSYu Chen "snps,dis-split-quirk"); 1349f580170fSYu Chen 135080caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 13516b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 135280caf7d2SHuang Rui 135316fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1354460d098cSHuang Rui 1355938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1356938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1357938a5ad1SThinh Nguyen 1358938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1359938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1360938a5ad1SThinh Nguyen 1361cf40b86bSJohn Youn dwc->imod_interval = 0; 1362cf40b86bSJohn Youn } 1363cf40b86bSJohn Youn 1364cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1365cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1366cf40b86bSJohn Youn { 13679af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 13689af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 13699af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1370c5ac6116SFelipe Balbi } 1371c5ac6116SFelipe Balbi 13727ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 13737ac51a12SJohn Youn { 13747ac51a12SJohn Youn struct device *dev = dwc->dev; 1375b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1376b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 13777ac51a12SJohn Youn 1378cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1379cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1380cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1381cf40b86bSJohn Youn dwc->imod_interval = 0; 1382cf40b86bSJohn Youn } 1383cf40b86bSJohn Youn 138428632b44SJohn Youn /* 138528632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 138628632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 138728632b44SJohn Youn * interrupt from being masked while handling events. IMOD 138828632b44SJohn Youn * allows us to work around this issue. Enable it for the 138928632b44SJohn Youn * affected version. 139028632b44SJohn Youn */ 139128632b44SJohn Youn if (!dwc->imod_interval && 13929af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 139328632b44SJohn Youn dwc->imod_interval = 1; 139428632b44SJohn Youn 13957ac51a12SJohn Youn /* Check the maximum_speed parameter */ 13967ac51a12SJohn Youn switch (dwc->maximum_speed) { 13977ac51a12SJohn Youn case USB_SPEED_FULL: 13987ac51a12SJohn Youn case USB_SPEED_HIGH: 1399e518bdd9SThinh Nguyen break; 14007ac51a12SJohn Youn case USB_SPEED_SUPER: 1401e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1402e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1403e518bdd9SThinh Nguyen break; 14047ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1405e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1406e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1407e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1408e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1409e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 14107ac51a12SJohn Youn break; 14117ac51a12SJohn Youn default: 14127ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 14137ac51a12SJohn Youn dwc->maximum_speed); 1414df561f66SGustavo A. R. Silva fallthrough; 14157ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1416b574ce3eSThinh Nguyen switch (hwparam_gen) { 1417b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 14187ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1419b574ce3eSThinh Nguyen break; 1420b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1421b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1422b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1423b574ce3eSThinh Nguyen else 1424b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1425b574ce3eSThinh Nguyen break; 1426b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1427b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1428b574ce3eSThinh Nguyen break; 1429b574ce3eSThinh Nguyen default: 1430b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1431b574ce3eSThinh Nguyen break; 1432b574ce3eSThinh Nguyen } 14337ac51a12SJohn Youn break; 14347ac51a12SJohn Youn } 143567848146SThinh Nguyen 143667848146SThinh Nguyen /* 143767848146SThinh Nguyen * Currently the controller does not have visibility into the HW 143867848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 143967848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 144067848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 144167848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 144267848146SThinh Nguyen */ 144367848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 144467848146SThinh Nguyen switch (dwc->max_ssp_rate) { 144567848146SThinh Nguyen case USB_SSP_GEN_2x1: 144667848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 144767848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 144867848146SThinh Nguyen break; 144967848146SThinh Nguyen case USB_SSP_GEN_1x2: 145067848146SThinh Nguyen case USB_SSP_GEN_2x2: 145167848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 145267848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 145367848146SThinh Nguyen break; 145467848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 145567848146SThinh Nguyen default: 145667848146SThinh Nguyen switch (hwparam_gen) { 145767848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 145867848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 145967848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 146067848146SThinh Nguyen else 146167848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 146267848146SThinh Nguyen break; 146367848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 146467848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 146567848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 146667848146SThinh Nguyen break; 146767848146SThinh Nguyen } 146867848146SThinh Nguyen break; 146967848146SThinh Nguyen } 147067848146SThinh Nguyen } 14717ac51a12SJohn Youn } 14727ac51a12SJohn Youn 1473c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1474c5ac6116SFelipe Balbi { 1475c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 147644feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1477c5ac6116SFelipe Balbi struct dwc3 *dwc; 1478c5ac6116SFelipe Balbi 1479c5ac6116SFelipe Balbi int ret; 1480c5ac6116SFelipe Balbi 1481c5ac6116SFelipe Balbi void __iomem *regs; 1482c5ac6116SFelipe Balbi 1483c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1484c5ac6116SFelipe Balbi if (!dwc) 1485c5ac6116SFelipe Balbi return -ENOMEM; 1486c5ac6116SFelipe Balbi 1487c5ac6116SFelipe Balbi dwc->dev = dev; 1488c5ac6116SFelipe Balbi 1489c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1490c5ac6116SFelipe Balbi if (!res) { 1491c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1492c5ac6116SFelipe Balbi return -ENODEV; 1493c5ac6116SFelipe Balbi } 1494c5ac6116SFelipe Balbi 1495c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1496c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1497c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1498c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1499c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1500c5ac6116SFelipe Balbi 1501c5ac6116SFelipe Balbi /* 1502c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1503c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1504c5ac6116SFelipe Balbi */ 150544feb8e6SMasahiro Yamada dwc_res = *res; 150644feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 150744feb8e6SMasahiro Yamada 150844feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 150944feb8e6SMasahiro Yamada if (IS_ERR(regs)) 151044feb8e6SMasahiro Yamada return PTR_ERR(regs); 1511c5ac6116SFelipe Balbi 1512c5ac6116SFelipe Balbi dwc->regs = regs; 151344feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1514c5ac6116SFelipe Balbi 1515c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1516c5ac6116SFelipe Balbi 1517babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1518fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1519fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1520fe8abf33SMasahiro Yamada 152161527777SHans de Goede if (dev->of_node) { 15220d3a9708SJohn Stultz ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1523fe8abf33SMasahiro Yamada if (ret == -EPROBE_DEFER) 1524fe8abf33SMasahiro Yamada return ret; 1525fe8abf33SMasahiro Yamada /* 152661527777SHans de Goede * Clocks are optional, but new DT platforms should support all 152761527777SHans de Goede * clocks as required by the DT-binding. 1528fe8abf33SMasahiro Yamada */ 15290d3a9708SJohn Stultz if (ret < 0) 1530fe8abf33SMasahiro Yamada dwc->num_clks = 0; 15310d3a9708SJohn Stultz else 15320d3a9708SJohn Stultz dwc->num_clks = ret; 15330d3a9708SJohn Stultz 153461527777SHans de Goede } 1535fe8abf33SMasahiro Yamada 1536fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1537fe8abf33SMasahiro Yamada if (ret) 153803bf32bbSAndrey Smirnov return ret; 1539fe8abf33SMasahiro Yamada 1540240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1541fe8abf33SMasahiro Yamada if (ret) 1542fe8abf33SMasahiro Yamada goto assert_reset; 1543fe8abf33SMasahiro Yamada 1544dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1545dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1546dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1547dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1548dc1b5d9aSEnric Balletbo i Serra } 1549dc1b5d9aSEnric Balletbo i Serra 15506c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 15512917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 15526c89cce0SHeikki Krogerus 155372246da4SFelipe Balbi spin_lock_init(&dwc->lock); 155472246da4SFelipe Balbi 1555fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1556fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1557fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1558802ca850SChanho Park pm_runtime_enable(dev); 155932808237SRoger Quadros ret = pm_runtime_get_sync(dev); 156032808237SRoger Quadros if (ret < 0) 156132808237SRoger Quadros goto err1; 156232808237SRoger Quadros 1563802ca850SChanho Park pm_runtime_forbid(dev); 156472246da4SFelipe Balbi 15653921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 15663921426bSFelipe Balbi if (ret) { 15673921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 15683921426bSFelipe Balbi ret = -ENOMEM; 156932808237SRoger Quadros goto err2; 15703921426bSFelipe Balbi } 15713921426bSFelipe Balbi 15729d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 15739d6173e1SThinh Nguyen if (ret) 15749d6173e1SThinh Nguyen goto err3; 157532a4a135SFelipe Balbi 1576c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1577c499ff71SFelipe Balbi if (ret) 157832808237SRoger Quadros goto err3; 1579c499ff71SFelipe Balbi 158072246da4SFelipe Balbi ret = dwc3_core_init(dwc); 158172246da4SFelipe Balbi if (ret) { 15820c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 158332808237SRoger Quadros goto err4; 158472246da4SFelipe Balbi } 158572246da4SFelipe Balbi 15867ac51a12SJohn Youn dwc3_check_params(dwc); 15872c7f1bd9SJohn Youn 15885f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 15895f94adfeSFelipe Balbi if (ret) 159032808237SRoger Quadros goto err5; 159172246da4SFelipe Balbi 15924e9f3118SDu, Changbin dwc3_debugfs_init(dwc); 1593fc8bb91bSFelipe Balbi pm_runtime_put(dev); 159472246da4SFelipe Balbi 159572246da4SFelipe Balbi return 0; 159672246da4SFelipe Balbi 159732808237SRoger Quadros err5: 1598f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 159903c1fd62SLi Jun 160003c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 160103c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 160203c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 160303c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 160403c1fd62SLi Jun 160503c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 160603c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 160703c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 160803c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 160903c1fd62SLi Jun 161008fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1611f122d33eSFelipe Balbi 161232808237SRoger Quadros err4: 1613c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 161472246da4SFelipe Balbi 161532808237SRoger Quadros err3: 16163921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 16173921426bSFelipe Balbi 161832808237SRoger Quadros err2: 161932808237SRoger Quadros pm_runtime_allow(&pdev->dev); 162032808237SRoger Quadros 162132808237SRoger Quadros err1: 162232808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 162332808237SRoger Quadros pm_runtime_disable(&pdev->dev); 162432808237SRoger Quadros 1625dc1b5d9aSEnric Balletbo i Serra disable_clks: 1626240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1627fe8abf33SMasahiro Yamada assert_reset: 1628fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1629fe8abf33SMasahiro Yamada 1630b0bf77cdSColin Ian King if (dwc->usb_psy) 16316f0764b5SRay Chi power_supply_put(dwc->usb_psy); 16326f0764b5SRay Chi 163372246da4SFelipe Balbi return ret; 163472246da4SFelipe Balbi } 163572246da4SFelipe Balbi 1636fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 163772246da4SFelipe Balbi { 163872246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 16393da1f6eeSFelipe Balbi 1640fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 164172246da4SFelipe Balbi 1642dc99f16fSFelipe Balbi dwc3_debugfs_exit(dwc); 1643dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 16448ba007a9SKishon Vijay Abraham I 164572246da4SFelipe Balbi dwc3_core_exit(dwc); 164688bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 164772246da4SFelipe Balbi 1648fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1649266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1650266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1651fc8bb91bSFelipe Balbi 1652c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1653c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1654c499ff71SFelipe Balbi 1655b0bf77cdSColin Ian King if (dwc->usb_psy) 16566f0764b5SRay Chi power_supply_put(dwc->usb_psy); 16576f0764b5SRay Chi 165872246da4SFelipe Balbi return 0; 165972246da4SFelipe Balbi } 166072246da4SFelipe Balbi 1661*568262bfSSandeep Maheswaram static void dwc3_shutdown(struct platform_device *pdev) 1662*568262bfSSandeep Maheswaram { 1663*568262bfSSandeep Maheswaram dwc3_remove(pdev); 1664*568262bfSSandeep Maheswaram } 1665*568262bfSSandeep Maheswaram 1666fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1667fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1668fe8abf33SMasahiro Yamada { 1669fe8abf33SMasahiro Yamada int ret; 1670fe8abf33SMasahiro Yamada 1671fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1672fe8abf33SMasahiro Yamada if (ret) 1673fe8abf33SMasahiro Yamada return ret; 1674fe8abf33SMasahiro Yamada 1675240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1676fe8abf33SMasahiro Yamada if (ret) 1677fe8abf33SMasahiro Yamada goto assert_reset; 1678fe8abf33SMasahiro Yamada 1679fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1680fe8abf33SMasahiro Yamada if (ret) 1681fe8abf33SMasahiro Yamada goto disable_clks; 1682fe8abf33SMasahiro Yamada 1683fe8abf33SMasahiro Yamada return 0; 1684fe8abf33SMasahiro Yamada 1685fe8abf33SMasahiro Yamada disable_clks: 1686240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1687fe8abf33SMasahiro Yamada assert_reset: 1688fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1689fe8abf33SMasahiro Yamada 1690fe8abf33SMasahiro Yamada return ret; 1691fe8abf33SMasahiro Yamada } 1692fe8abf33SMasahiro Yamada 1693c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 16947415f17cSFelipe Balbi { 1695fc8bb91bSFelipe Balbi unsigned long flags; 1696bcb12877SManu Gautam u32 reg; 16977415f17cSFelipe Balbi 1698689bf72cSManu Gautam switch (dwc->current_dr_role) { 1699689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 17000227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 17010227cc84SLi Jun break; 1702fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 17037415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1704fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 170541a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1706689bf72cSManu Gautam dwc3_core_exit(dwc); 170751f5d49aSFelipe Balbi break; 1708689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1709bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1710c4a5153eSManu Gautam dwc3_core_exit(dwc); 1711c4a5153eSManu Gautam break; 1712bcb12877SManu Gautam } 1713bcb12877SManu Gautam 1714bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1715bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1716bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1717bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1718bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1719bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1720bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1721bcb12877SManu Gautam 1722bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1723bcb12877SManu Gautam usleep_range(5000, 6000); 1724bcb12877SManu Gautam } 1725bcb12877SManu Gautam 1726bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1727bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1728bcb12877SManu Gautam break; 1729f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1730f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1731f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1732f09cc79bSRoger Quadros break; 1733f09cc79bSRoger Quadros 1734f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1735f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1736f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1737f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 173841a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1739f09cc79bSRoger Quadros } 1740f09cc79bSRoger Quadros 1741f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1742f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1743f09cc79bSRoger Quadros break; 17447415f17cSFelipe Balbi default: 174551f5d49aSFelipe Balbi /* do nothing */ 17467415f17cSFelipe Balbi break; 17477415f17cSFelipe Balbi } 17487415f17cSFelipe Balbi 1749fc8bb91bSFelipe Balbi return 0; 1750fc8bb91bSFelipe Balbi } 1751fc8bb91bSFelipe Balbi 1752c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1753fc8bb91bSFelipe Balbi { 1754fc8bb91bSFelipe Balbi unsigned long flags; 1755fc8bb91bSFelipe Balbi int ret; 1756bcb12877SManu Gautam u32 reg; 1757fc8bb91bSFelipe Balbi 1758689bf72cSManu Gautam switch (dwc->current_dr_role) { 1759689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1760fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1761fc8bb91bSFelipe Balbi if (ret) 1762fc8bb91bSFelipe Balbi return ret; 1763fc8bb91bSFelipe Balbi 17647d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1765fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1766fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1767fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1768689bf72cSManu Gautam break; 1769689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1770c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1771fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1772c4a5153eSManu Gautam if (ret) 1773c4a5153eSManu Gautam return ret; 17747d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1775bcb12877SManu Gautam break; 1776c4a5153eSManu Gautam } 1777bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1778bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1779bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1780bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1781bcb12877SManu Gautam 1782bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1783bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1784bcb12877SManu Gautam 1785bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1786bcb12877SManu Gautam 1787bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1788bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1789c4a5153eSManu Gautam break; 1790f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1791f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1792f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1793f09cc79bSRoger Quadros break; 1794f09cc79bSRoger Quadros 17950e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 1796f09cc79bSRoger Quadros if (ret) 1797f09cc79bSRoger Quadros return ret; 1798f09cc79bSRoger Quadros 1799f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1800f09cc79bSRoger Quadros 1801f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1802f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1803f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1804f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1805f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1806f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1807f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1808f09cc79bSRoger Quadros } 1809f09cc79bSRoger Quadros 1810f09cc79bSRoger Quadros break; 1811fc8bb91bSFelipe Balbi default: 1812fc8bb91bSFelipe Balbi /* do nothing */ 1813fc8bb91bSFelipe Balbi break; 1814fc8bb91bSFelipe Balbi } 1815fc8bb91bSFelipe Balbi 1816fc8bb91bSFelipe Balbi return 0; 1817fc8bb91bSFelipe Balbi } 1818fc8bb91bSFelipe Balbi 1819fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1820fc8bb91bSFelipe Balbi { 1821689bf72cSManu Gautam switch (dwc->current_dr_role) { 1822c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1823fc8bb91bSFelipe Balbi if (dwc->connected) 1824fc8bb91bSFelipe Balbi return -EBUSY; 1825fc8bb91bSFelipe Balbi break; 1826c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1827fc8bb91bSFelipe Balbi default: 1828fc8bb91bSFelipe Balbi /* do nothing */ 1829fc8bb91bSFelipe Balbi break; 1830fc8bb91bSFelipe Balbi } 1831fc8bb91bSFelipe Balbi 1832fc8bb91bSFelipe Balbi return 0; 1833fc8bb91bSFelipe Balbi } 1834fc8bb91bSFelipe Balbi 1835fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 1836fc8bb91bSFelipe Balbi { 1837fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1838fc8bb91bSFelipe Balbi int ret; 1839fc8bb91bSFelipe Balbi 1840fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1841fc8bb91bSFelipe Balbi return -EBUSY; 1842fc8bb91bSFelipe Balbi 1843c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1844fc8bb91bSFelipe Balbi if (ret) 1845fc8bb91bSFelipe Balbi return ret; 1846fc8bb91bSFelipe Balbi 1847fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 1848fc8bb91bSFelipe Balbi 1849fc8bb91bSFelipe Balbi return 0; 1850fc8bb91bSFelipe Balbi } 1851fc8bb91bSFelipe Balbi 1852fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 1853fc8bb91bSFelipe Balbi { 1854fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1855fc8bb91bSFelipe Balbi int ret; 1856fc8bb91bSFelipe Balbi 1857fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 1858fc8bb91bSFelipe Balbi 1859c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1860fc8bb91bSFelipe Balbi if (ret) 1861fc8bb91bSFelipe Balbi return ret; 1862fc8bb91bSFelipe Balbi 1863689bf72cSManu Gautam switch (dwc->current_dr_role) { 1864689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1865fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 1866fc8bb91bSFelipe Balbi break; 1867689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1868fc8bb91bSFelipe Balbi default: 1869fc8bb91bSFelipe Balbi /* do nothing */ 1870fc8bb91bSFelipe Balbi break; 1871fc8bb91bSFelipe Balbi } 1872fc8bb91bSFelipe Balbi 1873fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1874fc8bb91bSFelipe Balbi 1875fc8bb91bSFelipe Balbi return 0; 1876fc8bb91bSFelipe Balbi } 1877fc8bb91bSFelipe Balbi 1878fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 1879fc8bb91bSFelipe Balbi { 1880fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1881fc8bb91bSFelipe Balbi 1882689bf72cSManu Gautam switch (dwc->current_dr_role) { 1883689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1884fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1885fc8bb91bSFelipe Balbi return -EBUSY; 1886fc8bb91bSFelipe Balbi break; 1887689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1888fc8bb91bSFelipe Balbi default: 1889fc8bb91bSFelipe Balbi /* do nothing */ 1890fc8bb91bSFelipe Balbi break; 1891fc8bb91bSFelipe Balbi } 1892fc8bb91bSFelipe Balbi 1893fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1894fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 1895fc8bb91bSFelipe Balbi 1896fc8bb91bSFelipe Balbi return 0; 1897fc8bb91bSFelipe Balbi } 1898fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 1899fc8bb91bSFelipe Balbi 1900fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 1901fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 1902fc8bb91bSFelipe Balbi { 1903fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1904fc8bb91bSFelipe Balbi int ret; 1905fc8bb91bSFelipe Balbi 1906c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1907fc8bb91bSFelipe Balbi if (ret) 1908fc8bb91bSFelipe Balbi return ret; 1909fc8bb91bSFelipe Balbi 19106344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 19116344475fSSekhar Nori 19127415f17cSFelipe Balbi return 0; 19137415f17cSFelipe Balbi } 19147415f17cSFelipe Balbi 19157415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 19167415f17cSFelipe Balbi { 19177415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 191857303488SKishon Vijay Abraham I int ret; 19197415f17cSFelipe Balbi 19206344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 19216344475fSSekhar Nori 1922c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 192351f5d49aSFelipe Balbi if (ret) 19245c4ad318SFelipe Balbi return ret; 19255c4ad318SFelipe Balbi 19267415f17cSFelipe Balbi pm_runtime_disable(dev); 19277415f17cSFelipe Balbi pm_runtime_set_active(dev); 19287415f17cSFelipe Balbi pm_runtime_enable(dev); 19297415f17cSFelipe Balbi 19307415f17cSFelipe Balbi return 0; 19317415f17cSFelipe Balbi } 1932f580170fSYu Chen 1933f580170fSYu Chen static void dwc3_complete(struct device *dev) 1934f580170fSYu Chen { 1935f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 1936f580170fSYu Chen u32 reg; 1937f580170fSYu Chen 1938f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 1939f580170fSYu Chen dwc->dis_split_quirk) { 1940f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 1941f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 1942f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 1943f580170fSYu Chen } 1944f580170fSYu Chen } 1945f580170fSYu Chen #else 1946f580170fSYu Chen #define dwc3_complete NULL 19477f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 19487415f17cSFelipe Balbi 19497415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 19507415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1951f580170fSYu Chen .complete = dwc3_complete, 1952fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1953fc8bb91bSFelipe Balbi dwc3_runtime_idle) 19547415f17cSFelipe Balbi }; 19557415f17cSFelipe Balbi 19565088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 19575088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 19585088b6f5SKishon Vijay Abraham I { 195922a5aa17SFelipe Balbi .compatible = "snps,dwc3" 196022a5aa17SFelipe Balbi }, 196122a5aa17SFelipe Balbi { 19625088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 19635088b6f5SKishon Vijay Abraham I }, 19645088b6f5SKishon Vijay Abraham I { }, 19655088b6f5SKishon Vijay Abraham I }; 19665088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 19675088b6f5SKishon Vijay Abraham I #endif 19685088b6f5SKishon Vijay Abraham I 1969404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 1970404905a6SHeikki Krogerus 1971404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 1972404905a6SHeikki Krogerus 1973404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 1974404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 1975404905a6SHeikki Krogerus { }, 1976404905a6SHeikki Krogerus }; 1977404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1978404905a6SHeikki Krogerus #endif 1979404905a6SHeikki Krogerus 198072246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 198172246da4SFelipe Balbi .probe = dwc3_probe, 19827690417dSBill Pemberton .remove = dwc3_remove, 1983*568262bfSSandeep Maheswaram .shutdown = dwc3_shutdown, 198472246da4SFelipe Balbi .driver = { 198572246da4SFelipe Balbi .name = "dwc3", 19865088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 1987404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 19887f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 198972246da4SFelipe Balbi }, 199072246da4SFelipe Balbi }; 199172246da4SFelipe Balbi 1992b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 1993b1116dccSTobias Klauser 19947ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 199572246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 19965945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 199772246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1998