15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 260f010171SAndrey Smirnov #include <linux/of_graph.h> 27404905a6SHeikki Krogerus #include <linux/acpi.h> 286344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 29fe8abf33SMasahiro Yamada #include <linux/reset.h> 307bee3188SBalaji Prakash J #include <linux/bitfield.h> 3172246da4SFelipe Balbi 3272246da4SFelipe Balbi #include <linux/usb/ch9.h> 3372246da4SFelipe Balbi #include <linux/usb/gadget.h> 34f7e846f0SFelipe Balbi #include <linux/usb/of.h> 35a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3672246da4SFelipe Balbi 3772246da4SFelipe Balbi #include "core.h" 3872246da4SFelipe Balbi #include "gadget.h" 3972246da4SFelipe Balbi #include "io.h" 4072246da4SFelipe Balbi 4172246da4SFelipe Balbi #include "debug.h" 4272246da4SFelipe Balbi 43fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 448300dd23SFelipe Balbi 459d6173e1SThinh Nguyen /** 469d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 479d6173e1SThinh Nguyen * @dwc: pointer to our context structure 489d6173e1SThinh Nguyen */ 499d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 509d6173e1SThinh Nguyen { 519d6173e1SThinh Nguyen enum usb_dr_mode mode; 529d6173e1SThinh Nguyen struct device *dev = dwc->dev; 539d6173e1SThinh Nguyen unsigned int hw_mode; 549d6173e1SThinh Nguyen 559d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 569d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 579d6173e1SThinh Nguyen 589d6173e1SThinh Nguyen mode = dwc->dr_mode; 599d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 609d6173e1SThinh Nguyen 619d6173e1SThinh Nguyen switch (hw_mode) { 629d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 639d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 649d6173e1SThinh Nguyen dev_err(dev, 659d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 669d6173e1SThinh Nguyen return -EINVAL; 679d6173e1SThinh Nguyen } 689d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 699d6173e1SThinh Nguyen break; 709d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 719d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 729d6173e1SThinh Nguyen dev_err(dev, 739d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 749d6173e1SThinh Nguyen return -EINVAL; 759d6173e1SThinh Nguyen } 769d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 779d6173e1SThinh Nguyen break; 789d6173e1SThinh Nguyen default: 799d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 819d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 829d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 83a7700468SThinh Nguyen 84a7700468SThinh Nguyen /* 8589a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8689a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8789a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 88a7700468SThinh Nguyen */ 890f010171SAndrey Smirnov if (mode == USB_DR_MODE_OTG && !dwc->edev && 908bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 918bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 929af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 93a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 949d6173e1SThinh Nguyen } 959d6173e1SThinh Nguyen 969d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 979d6173e1SThinh Nguyen dev_warn(dev, 989d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 999d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 1009d6173e1SThinh Nguyen 1019d6173e1SThinh Nguyen dwc->dr_mode = mode; 1029d6173e1SThinh Nguyen } 1039d6173e1SThinh Nguyen 1049d6173e1SThinh Nguyen return 0; 1059d6173e1SThinh Nguyen } 1069d6173e1SThinh Nguyen 107f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1083140e8cbSSebastian Andrzej Siewior { 1093140e8cbSSebastian Andrzej Siewior u32 reg; 1103140e8cbSSebastian Andrzej Siewior 1113140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1123140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1133140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1143140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 115c4a5153eSManu Gautam 116c4a5153eSManu Gautam dwc->current_dr_role = mode; 11741ce1456SRoger Quadros } 1186b3261a2SRoger Quadros 11941ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 12041ce1456SRoger Quadros { 12141ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12241ce1456SRoger Quadros unsigned long flags; 12341ce1456SRoger Quadros int ret; 124f580170fSYu Chen u32 reg; 12541ce1456SRoger Quadros 126f88359e1SYu Chen mutex_lock(&dwc->mutex); 127f88359e1SYu Chen 128c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 129c2cd3452SMartin Kepplinger 130f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 131f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 132f09cc79bSRoger Quadros 13341ce1456SRoger Quadros if (!dwc->desired_dr_role) 134c2cd3452SMartin Kepplinger goto out; 13541ce1456SRoger Quadros 13641ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 137c2cd3452SMartin Kepplinger goto out; 13841ce1456SRoger Quadros 139f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 140c2cd3452SMartin Kepplinger goto out; 14141ce1456SRoger Quadros 14241ce1456SRoger Quadros switch (dwc->current_dr_role) { 14341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14441ce1456SRoger Quadros dwc3_host_exit(dwc); 14541ce1456SRoger Quadros break; 14641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14741ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14841ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14941ce1456SRoger Quadros break; 150f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 151f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 152f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 153f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 154f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 155f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 156f09cc79bSRoger Quadros break; 15741ce1456SRoger Quadros default: 15841ce1456SRoger Quadros break; 15941ce1456SRoger Quadros } 16041ce1456SRoger Quadros 161*07903626SRohith Kollalsi /* 162*07903626SRohith Kollalsi * When current_dr_role is not set, there's no role switching. 163*07903626SRohith Kollalsi * Only perform GCTL.CoreSoftReset when there's DRD role switching. 164*07903626SRohith Kollalsi */ 165*07903626SRohith Kollalsi if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || 166*07903626SRohith Kollalsi DWC3_VER_IS_PRIOR(DWC31, 190A)) && 167*07903626SRohith Kollalsi dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) { 168f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 169f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 170f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 171f88359e1SYu Chen 172f88359e1SYu Chen /* 173f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 174f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 175f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 176f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 177f88359e1SYu Chen */ 178f88359e1SYu Chen msleep(100); 179f88359e1SYu Chen 180f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 181f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 182f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 183f88359e1SYu Chen } 184f88359e1SYu Chen 18541ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18641ce1456SRoger Quadros 18741ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18841ce1456SRoger Quadros 18941ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 19041ce1456SRoger Quadros 19141ce1456SRoger Quadros switch (dwc->desired_dr_role) { 19241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 19341ce1456SRoger Quadros ret = dwc3_host_init(dwc); 194958d1a4cSFelipe Balbi if (ret) { 19541ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 196958d1a4cSFelipe Balbi } else { 197958d1a4cSFelipe Balbi if (dwc->usb2_phy) 198958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 199958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 200644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 201f580170fSYu Chen if (dwc->dis_split_quirk) { 202f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 203f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 204f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 205f580170fSYu Chen } 206958d1a4cSFelipe Balbi } 20741ce1456SRoger Quadros break; 20841ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 209f88359e1SYu Chen dwc3_core_soft_reset(dwc); 210f88359e1SYu Chen 21141ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 212958d1a4cSFelipe Balbi 213958d1a4cSFelipe Balbi if (dwc->usb2_phy) 214958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 215958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 216644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 217958d1a4cSFelipe Balbi 21841ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21941ce1456SRoger Quadros if (ret) 22041ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 22141ce1456SRoger Quadros break; 222f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 223f09cc79bSRoger Quadros dwc3_otg_init(dwc); 224f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 225f09cc79bSRoger Quadros break; 22641ce1456SRoger Quadros default: 22741ce1456SRoger Quadros break; 22841ce1456SRoger Quadros } 229f09cc79bSRoger Quadros 230c2cd3452SMartin Kepplinger out: 231c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 232c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 233f88359e1SYu Chen mutex_unlock(&dwc->mutex); 23441ce1456SRoger Quadros } 23541ce1456SRoger Quadros 23641ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23741ce1456SRoger Quadros { 23841ce1456SRoger Quadros unsigned long flags; 23941ce1456SRoger Quadros 240dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 241dc336b19SLi Jun return; 242dc336b19SLi Jun 24341ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 24441ce1456SRoger Quadros dwc->desired_dr_role = mode; 24541ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24641ce1456SRoger Quadros 247084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2483140e8cbSSebastian Andrzej Siewior } 2498300dd23SFelipe Balbi 250cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 251cf6d867dSFelipe Balbi { 252cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 253cf6d867dSFelipe Balbi u32 reg; 254cf6d867dSFelipe Balbi 255cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 256cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 257cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 258cf6d867dSFelipe Balbi 259cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 260cf6d867dSFelipe Balbi 261cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 262cf6d867dSFelipe Balbi } 263cf6d867dSFelipe Balbi 26472246da4SFelipe Balbi /** 26572246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26672246da4SFelipe Balbi * @dwc: pointer to our context structure 26772246da4SFelipe Balbi */ 2680066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 26972246da4SFelipe Balbi { 27072246da4SFelipe Balbi u32 reg; 271f59dcab1SFelipe Balbi int retries = 1000; 27272246da4SFelipe Balbi 273f59dcab1SFelipe Balbi /* 274f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 275f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 276f59dcab1SFelipe Balbi * host-only mode, then we can return early. 277f59dcab1SFelipe Balbi */ 278c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27957303488SKishon Vijay Abraham I return 0; 280f59dcab1SFelipe Balbi 281f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 282f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 283f4fd84aeSThinh Nguyen reg &= ~DWC3_DCTL_RUN_STOP; 284f4fd84aeSThinh Nguyen dwc3_gadget_dctl_write_safe(dwc, reg); 285f59dcab1SFelipe Balbi 2864749e0e6SThinh Nguyen /* 2874749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2884749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2894749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2904749e0e6SThinh Nguyen * for 10 times instead. 2914749e0e6SThinh Nguyen */ 2929af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2934749e0e6SThinh Nguyen retries = 10; 2944749e0e6SThinh Nguyen 295f59dcab1SFelipe Balbi do { 296f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 297f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 298fab38333SThinh Nguyen goto done; 299f59dcab1SFelipe Balbi 3009af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 3014749e0e6SThinh Nguyen msleep(20); 3024749e0e6SThinh Nguyen else 303f59dcab1SFelipe Balbi udelay(1); 304f59dcab1SFelipe Balbi } while (--retries); 305f59dcab1SFelipe Balbi 306859bdc35SMayank Rana dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n"); 307f59dcab1SFelipe Balbi return -ETIMEDOUT; 308fab38333SThinh Nguyen 309fab38333SThinh Nguyen done: 310fab38333SThinh Nguyen /* 3114749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3124749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3134749e0e6SThinh Nguyen * domain (synchronization delay). 314fab38333SThinh Nguyen */ 3159af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 316fab38333SThinh Nguyen msleep(50); 317fab38333SThinh Nguyen 318fab38333SThinh Nguyen return 0; 31972246da4SFelipe Balbi } 32072246da4SFelipe Balbi 321db2be4e9SNikhil Badola /* 322db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 323db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 324db2be4e9SNikhil Badola */ 325bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 326db2be4e9SNikhil Badola { 327db2be4e9SNikhil Badola u32 reg; 328db2be4e9SNikhil Badola u32 dft; 329db2be4e9SNikhil Badola 3309af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 331db2be4e9SNikhil Badola return; 332db2be4e9SNikhil Badola 333bcdb3272SFelipe Balbi if (dwc->fladj == 0) 334db2be4e9SNikhil Badola return; 335db2be4e9SNikhil Badola 336db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 337db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 338a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 339db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 340bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 341db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 342db2be4e9SNikhil Badola } 343db2be4e9SNikhil Badola } 344db2be4e9SNikhil Badola 345c5cc74e8SHeikki Krogerus /** 3467bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3477bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3487bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3497bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3507bee3188SBalaji Prakash J * register. 3517bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3527bee3188SBalaji Prakash J */ 3537bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3547bee3188SBalaji Prakash J { 3555114c3eeSSean Anderson unsigned long period; 356596c8785SSean Anderson unsigned long fladj; 357596c8785SSean Anderson unsigned long decr; 3585114c3eeSSean Anderson unsigned long rate; 3597bee3188SBalaji Prakash J u32 reg; 3607bee3188SBalaji Prakash J 3615114c3eeSSean Anderson if (dwc->ref_clk) { 3625114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3635114c3eeSSean Anderson if (!rate) 3647bee3188SBalaji Prakash J return; 3655114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3665114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3675114c3eeSSean Anderson period = dwc->ref_clk_per; 368596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3695114c3eeSSean Anderson } else { 3705114c3eeSSean Anderson return; 3715114c3eeSSean Anderson } 3727bee3188SBalaji Prakash J 3737bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3747bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3755114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3767bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3777bee3188SBalaji Prakash J 378596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 379596c8785SSean Anderson return; 380596c8785SSean Anderson 381596c8785SSean Anderson /* 382596c8785SSean Anderson * The calculation below is 383596c8785SSean Anderson * 384596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 385596c8785SSean Anderson * 386596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 387596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 388596c8785SSean Anderson * neither does rate * period). 389596c8785SSean Anderson * 390596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 391596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 392596c8785SSean Anderson * the division when calculating rate or period (whichever one was 393596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 394596c8785SSean Anderson * scale it to units of 8 ppm. 395596c8785SSean Anderson */ 396596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 397596c8785SSean Anderson fladj -= 125000; 398596c8785SSean Anderson 399596c8785SSean Anderson /* 400596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 401596c8785SSean Anderson */ 402596c8785SSean Anderson decr = 480000000 / rate; 403596c8785SSean Anderson 404596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 405596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 406596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 407596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 408596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 409596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 410596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 411596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 412596c8785SSean Anderson } 4137bee3188SBalaji Prakash J 4147bee3188SBalaji Prakash J /** 41572246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 41672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 41772246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 41872246da4SFelipe Balbi */ 41972246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 42072246da4SFelipe Balbi struct dwc3_event_buffer *evt) 42172246da4SFelipe Balbi { 422d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 42372246da4SFelipe Balbi } 42472246da4SFelipe Balbi 42572246da4SFelipe Balbi /** 4261d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 42772246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42872246da4SFelipe Balbi * @length: size of the event buffer 42972246da4SFelipe Balbi * 4301d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 43172246da4SFelipe Balbi * otherwise ERR_PTR(errno). 43272246da4SFelipe Balbi */ 43367d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 434ca80ca61SKushagra Verma unsigned int length) 43572246da4SFelipe Balbi { 43672246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43772246da4SFelipe Balbi 438380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 43972246da4SFelipe Balbi if (!evt) 44072246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44172246da4SFelipe Balbi 44272246da4SFelipe Balbi evt->dwc = dwc; 44372246da4SFelipe Balbi evt->length = length; 444d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 445d9fa4c63SJohn Youn if (!evt->cache) 446d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 447d9fa4c63SJohn Youn 448d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 44972246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 450e32672f0SFelipe Balbi if (!evt->buf) 45172246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 45272246da4SFelipe Balbi 45372246da4SFelipe Balbi return evt; 45472246da4SFelipe Balbi } 45572246da4SFelipe Balbi 45672246da4SFelipe Balbi /** 45772246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 45872246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 45972246da4SFelipe Balbi */ 46072246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 46172246da4SFelipe Balbi { 46272246da4SFelipe Balbi struct dwc3_event_buffer *evt; 46372246da4SFelipe Balbi 464696c8b12SFelipe Balbi evt = dwc->ev_buf; 46564b6c8a7SAnton Tikhomirov if (evt) 46672246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 46772246da4SFelipe Balbi } 46872246da4SFelipe Balbi 46972246da4SFelipe Balbi /** 47072246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4711d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 47272246da4SFelipe Balbi * @length: size of event buffer 47372246da4SFelipe Balbi * 4741d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 47572246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 47672246da4SFelipe Balbi */ 477ca80ca61SKushagra Verma static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) 47872246da4SFelipe Balbi { 47972246da4SFelipe Balbi struct dwc3_event_buffer *evt; 48072246da4SFelipe Balbi 48172246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 48272246da4SFelipe Balbi if (IS_ERR(evt)) { 48372246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 48472246da4SFelipe Balbi return PTR_ERR(evt); 48572246da4SFelipe Balbi } 486696c8b12SFelipe Balbi dwc->ev_buf = evt; 48772246da4SFelipe Balbi 48872246da4SFelipe Balbi return 0; 48972246da4SFelipe Balbi } 49072246da4SFelipe Balbi 49172246da4SFelipe Balbi /** 49272246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4931d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 49472246da4SFelipe Balbi * 49572246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 49672246da4SFelipe Balbi */ 497f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 49872246da4SFelipe Balbi { 49972246da4SFelipe Balbi struct dwc3_event_buffer *evt; 50072246da4SFelipe Balbi 501696c8b12SFelipe Balbi evt = dwc->ev_buf; 5027acd85e0SPaul Zimmerman evt->lpos = 0; 503660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 50472246da4SFelipe Balbi lower_32_bits(evt->dma)); 505660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 50672246da4SFelipe Balbi upper_32_bits(evt->dma)); 507660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 50868d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 509660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 51072246da4SFelipe Balbi 51172246da4SFelipe Balbi return 0; 51272246da4SFelipe Balbi } 51372246da4SFelipe Balbi 514f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 51572246da4SFelipe Balbi { 51672246da4SFelipe Balbi struct dwc3_event_buffer *evt; 51772246da4SFelipe Balbi 518696c8b12SFelipe Balbi evt = dwc->ev_buf; 5197acd85e0SPaul Zimmerman 5207acd85e0SPaul Zimmerman evt->lpos = 0; 5217acd85e0SPaul Zimmerman 522660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 523660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 524660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 52568d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 526660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 52772246da4SFelipe Balbi } 52872246da4SFelipe Balbi 5290ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5300ffcaf37SFelipe Balbi { 5310ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5320ffcaf37SFelipe Balbi return 0; 5330ffcaf37SFelipe Balbi 5340ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5350ffcaf37SFelipe Balbi return 0; 5360ffcaf37SFelipe Balbi 5370ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5380ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5390ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5400ffcaf37SFelipe Balbi return -ENOMEM; 5410ffcaf37SFelipe Balbi 5420ffcaf37SFelipe Balbi return 0; 5430ffcaf37SFelipe Balbi } 5440ffcaf37SFelipe Balbi 5450ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5460ffcaf37SFelipe Balbi { 5470ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5480ffcaf37SFelipe Balbi u32 param; 5490ffcaf37SFelipe Balbi int ret; 5500ffcaf37SFelipe Balbi 5510ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5520ffcaf37SFelipe Balbi return 0; 5530ffcaf37SFelipe Balbi 5540ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5550ffcaf37SFelipe Balbi return 0; 5560ffcaf37SFelipe Balbi 5570ffcaf37SFelipe Balbi /* should never fall here */ 5580ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5590ffcaf37SFelipe Balbi return 0; 5600ffcaf37SFelipe Balbi 561d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5620ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5630ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 564d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 565d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5660ffcaf37SFelipe Balbi ret = -EFAULT; 5670ffcaf37SFelipe Balbi goto err0; 5680ffcaf37SFelipe Balbi } 5690ffcaf37SFelipe Balbi 5700ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5710ffcaf37SFelipe Balbi 5720ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5730ffcaf37SFelipe Balbi 5740ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5750ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5760ffcaf37SFelipe Balbi if (ret < 0) 5770ffcaf37SFelipe Balbi goto err1; 5780ffcaf37SFelipe Balbi 5790ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5800ffcaf37SFelipe Balbi 5810ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5820ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5830ffcaf37SFelipe Balbi if (ret < 0) 5840ffcaf37SFelipe Balbi goto err1; 5850ffcaf37SFelipe Balbi 5860ffcaf37SFelipe Balbi return 0; 5870ffcaf37SFelipe Balbi 5880ffcaf37SFelipe Balbi err1: 589d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5900ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5910ffcaf37SFelipe Balbi 5920ffcaf37SFelipe Balbi err0: 5930ffcaf37SFelipe Balbi return ret; 5940ffcaf37SFelipe Balbi } 5950ffcaf37SFelipe Balbi 5960ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5970ffcaf37SFelipe Balbi { 5980ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5990ffcaf37SFelipe Balbi return; 6000ffcaf37SFelipe Balbi 6010ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 6020ffcaf37SFelipe Balbi return; 6030ffcaf37SFelipe Balbi 6040ffcaf37SFelipe Balbi /* should never fall here */ 6050ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 6060ffcaf37SFelipe Balbi return; 6070ffcaf37SFelipe Balbi 608d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6090ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6100ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6110ffcaf37SFelipe Balbi } 6120ffcaf37SFelipe Balbi 613789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 614789451f6SFelipe Balbi { 615789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 616789451f6SFelipe Balbi 61747d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 618789451f6SFelipe Balbi } 619789451f6SFelipe Balbi 62041ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 62126ceca97SFelipe Balbi { 62226ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 62326ceca97SFelipe Balbi 62426ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 62526ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 62626ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 62726ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 62826ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 62926ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 63026ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 63126ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 63226ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 63316710380SThinh Nguyen 63416710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 63516710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 63626ceca97SFelipe Balbi } 63726ceca97SFelipe Balbi 63898112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 63998112041SRoger Quadros { 64098112041SRoger Quadros int intf; 64198112041SRoger Quadros int ret = 0; 64298112041SRoger Quadros 64398112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 64498112041SRoger Quadros 64598112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 64698112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 64798112041SRoger Quadros dwc->hsphy_interface && 64898112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 64998112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 65098112041SRoger Quadros 65198112041SRoger Quadros return ret; 65298112041SRoger Quadros } 65398112041SRoger Quadros 65472246da4SFelipe Balbi /** 655b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 656b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 65788bc9d19SHeikki Krogerus * 65888bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 65988bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 66088bc9d19SHeikki Krogerus * the core in dwc3_core_init. 661b5a65c40SHuang Rui */ 66288bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 663b5a65c40SHuang Rui { 6649ba3aca8SThinh Nguyen unsigned int hw_mode; 665b5a65c40SHuang Rui u32 reg; 666b5a65c40SHuang Rui 6679ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6689ba3aca8SThinh Nguyen 669b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 670b5a65c40SHuang Rui 6712164a476SHuang Rui /* 6721966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6731966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6741966b865SFelipe Balbi */ 6751966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6761966b865SFelipe Balbi 6771966b865SFelipe Balbi /* 6782164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6792164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6802164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6812164a476SHuang Rui * to '1' after the core initialization is completed. 6822164a476SHuang Rui */ 6839af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6842164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6852164a476SHuang Rui 6869ba3aca8SThinh Nguyen /* 6879ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6889ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6899ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6909ba3aca8SThinh Nguyen */ 6919ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6929ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6939ba3aca8SThinh Nguyen 694b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 695b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 696b5a65c40SHuang Rui 697e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 698e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 699e58dd357SRajesh Bhagat 700df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 701df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 702df31f5b3SHuang Rui 703a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 704a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 705a2a1d0f5SHuang Rui 70641c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 70741c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 70841c06ffdSHuang Rui 709fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 710fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 711fb67afcaSHuang Rui 71214f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 71314f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 71414f4ac53SHuang Rui 7156b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7166b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7176b6a0c9aSHuang Rui 718cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 71959acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 72059acfa20SHuang Rui 72100fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 72200fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 72300fe081dSWilliam Wu 724b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 725b5a65c40SHuang Rui 7262164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7272164a476SHuang Rui 7283e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7293e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7303e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 73143cacb03SFelipe Balbi if (dwc->hsphy_interface && 73243cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7333e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 73488bc9d19SHeikki Krogerus break; 73543cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 73643cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7373e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 73888bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7393e10a2ceSHeikki Krogerus } else { 74088bc9d19SHeikki Krogerus /* Relying on default value. */ 74188bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7423e10a2ceSHeikki Krogerus break; 7433e10a2ceSHeikki Krogerus } 744df561f66SGustavo A. R. Silva fallthrough; 74588bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7463e10a2ceSHeikki Krogerus default: 7473e10a2ceSHeikki Krogerus break; 7483e10a2ceSHeikki Krogerus } 7493e10a2ceSHeikki Krogerus 75032f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 75132f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 75232f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75332f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75432f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 75532f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 75632f2ed86SWilliam Wu break; 75732f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 75832f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75932f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 76032f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 76132f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 76232f2ed86SWilliam Wu break; 76332f2ed86SWilliam Wu default: 76432f2ed86SWilliam Wu break; 76532f2ed86SWilliam Wu } 76632f2ed86SWilliam Wu 7672164a476SHuang Rui /* 7682164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7692164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7702164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7712164a476SHuang Rui * '1' after the core initialization is completed. 7722164a476SHuang Rui */ 7739af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7742164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7752164a476SHuang Rui 7769ba3aca8SThinh Nguyen /* 7779ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7789ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7799ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7809ba3aca8SThinh Nguyen */ 7819ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7829ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7839ba3aca8SThinh Nguyen 784cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7850effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7860effe0a3SHuang Rui 787ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 788ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 789eafeacf1SThinh Nguyen else 790eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 791ec791d14SJohn Youn 79216199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 79316199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 79416199f33SWilliam Wu 7952164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 79688bc9d19SHeikki Krogerus 79788bc9d19SHeikki Krogerus return 0; 798b5a65c40SHuang Rui } 799b5a65c40SHuang Rui 80033fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 80133fb697eSSean Anderson { 80233fb697eSSean Anderson int ret; 80333fb697eSSean Anderson 80433fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 80533fb697eSSean Anderson if (ret) 80633fb697eSSean Anderson return ret; 80733fb697eSSean Anderson 80833fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 80933fb697eSSean Anderson if (ret) 81033fb697eSSean Anderson goto disable_bus_clk; 81133fb697eSSean Anderson 81233fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 81333fb697eSSean Anderson if (ret) 81433fb697eSSean Anderson goto disable_ref_clk; 81533fb697eSSean Anderson 81633fb697eSSean Anderson return 0; 81733fb697eSSean Anderson 81833fb697eSSean Anderson disable_ref_clk: 81933fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82033fb697eSSean Anderson disable_bus_clk: 82133fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82233fb697eSSean Anderson return ret; 82333fb697eSSean Anderson } 82433fb697eSSean Anderson 82533fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 82633fb697eSSean Anderson { 82733fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 82833fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82933fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 83033fb697eSSean Anderson } 83133fb697eSSean Anderson 832c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 833c499ff71SFelipe Balbi { 834c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 835c499ff71SFelipe Balbi 836c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 837c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 838c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 839c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 840c499ff71SFelipe Balbi 841c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 842c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 843c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 844c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 84533fb697eSSean Anderson dwc3_clk_disable(dwc); 846fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 847c499ff71SFelipe Balbi } 848c499ff71SFelipe Balbi 8490759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 85072246da4SFelipe Balbi { 85172246da4SFelipe Balbi u32 reg; 85272246da4SFelipe Balbi 8537650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8549af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8550759956fSFelipe Balbi 8567650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8579af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 858690fb371SJohn Youn dwc->revision = reg; 8599af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 860690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 861475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 862690fb371SJohn Youn } else { 8630759956fSFelipe Balbi return false; 8647650bd74SSebastian Andrzej Siewior } 8657650bd74SSebastian Andrzej Siewior 8660759956fSFelipe Balbi return true; 8670e1e5c47SPaul Zimmerman } 8680e1e5c47SPaul Zimmerman 869941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 87072246da4SFelipe Balbi { 87172246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 87272246da4SFelipe Balbi u32 reg; 873c499ff71SFelipe Balbi 8744878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8753e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8764878a028SSebastian Andrzej Siewior 877164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8784878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87932a4a135SFelipe Balbi /** 88032a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 88132a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 88232a4a135SFelipe Balbi * 88332a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 88432a4a135SFelipe Balbi * configurations. 88532a4a135SFelipe Balbi * 88632a4a135SFelipe Balbi * Refers to: 88732a4a135SFelipe Balbi * 88832a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 88932a4a135SFelipe Balbi * SOF/ITP Mode Used 89032a4a135SFelipe Balbi */ 89132a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 89232a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8939af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 89432a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 89532a4a135SFelipe Balbi else 8964878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 8974878a028SSebastian Andrzej Siewior break; 8980ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 8990ffcaf37SFelipe Balbi /* enable hibernation here */ 9000ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 9012eac3992SHuang Rui 9022eac3992SHuang Rui /* 9032eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 9042eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 9052eac3992SHuang Rui */ 9062eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9070ffcaf37SFelipe Balbi break; 9084878a028SSebastian Andrzej Siewior default: 9095eb30cedSFelipe Balbi /* nothing */ 9105eb30cedSFelipe Balbi break; 9114878a028SSebastian Andrzej Siewior } 9124878a028SSebastian Andrzej Siewior 913946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 914946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9156af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 916946bd579SHuang Rui dwc->is_fpga = true; 917946bd579SHuang Rui } 918946bd579SHuang Rui 9193b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9203b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9213b81221aSHuang Rui 9223b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9233b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9243b81221aSHuang Rui else 9253b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9263b81221aSHuang Rui 9279a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9289a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9299a5b2f31SHuang Rui 9304878a028SSebastian Andrzej Siewior /* 9314878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9321d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9334878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9341d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9354878a028SSebastian Andrzej Siewior */ 9369af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9374878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9384878a028SSebastian Andrzej Siewior 9394878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 940941f918eSFelipe Balbi } 9414878a028SSebastian Andrzej Siewior 942f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 94398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 944f54edb53SFelipe Balbi 945d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 946d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 947d9612c2fSPengbo Mu { 948d9612c2fSPengbo Mu struct device *dev = dwc->dev; 949d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 950d9612c2fSPengbo Mu bool incrx_mode; 951d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 952d9612c2fSPengbo Mu u32 incrx_size; 953d9612c2fSPengbo Mu u32 *vals; 954d9612c2fSPengbo Mu u32 cfg; 955d9612c2fSPengbo Mu int ntype; 956d9612c2fSPengbo Mu int ret; 957d9612c2fSPengbo Mu int i; 958d9612c2fSPengbo Mu 959d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 960d9612c2fSPengbo Mu 961d9612c2fSPengbo Mu /* 962d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 963d9612c2fSPengbo Mu * Get the number of value from this property: 964d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 965d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 966d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 967d9612c2fSPengbo Mu */ 968a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 969d9612c2fSPengbo Mu if (ntype <= 0) 970d9612c2fSPengbo Mu return; 971d9612c2fSPengbo Mu 972d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 9734ea15088SKushagra Verma if (!vals) 974d9612c2fSPengbo Mu return; 975d9612c2fSPengbo Mu 976d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 977d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 978d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 979d9612c2fSPengbo Mu if (ret) { 98075ecb9ddSAndy Shevchenko kfree(vals); 981d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 982d9612c2fSPengbo Mu return; 983d9612c2fSPengbo Mu } 984d9612c2fSPengbo Mu 985d9612c2fSPengbo Mu incrx_size = *vals; 986d9612c2fSPengbo Mu 987d9612c2fSPengbo Mu if (ntype > 1) { 988d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 989d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 990d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 991d9612c2fSPengbo Mu if (vals[i] > incrx_size) 992d9612c2fSPengbo Mu incrx_size = vals[i]; 993d9612c2fSPengbo Mu } 994d9612c2fSPengbo Mu } else { 995d9612c2fSPengbo Mu /* INCRX burst mode */ 996d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 997d9612c2fSPengbo Mu } 998d9612c2fSPengbo Mu 99975ecb9ddSAndy Shevchenko kfree(vals); 100075ecb9ddSAndy Shevchenko 1001d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 1002d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 1003d9612c2fSPengbo Mu if (incrx_mode) 1004d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1005d9612c2fSPengbo Mu switch (incrx_size) { 1006d9612c2fSPengbo Mu case 256: 1007d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1008d9612c2fSPengbo Mu break; 1009d9612c2fSPengbo Mu case 128: 1010d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1011d9612c2fSPengbo Mu break; 1012d9612c2fSPengbo Mu case 64: 1013d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1014d9612c2fSPengbo Mu break; 1015d9612c2fSPengbo Mu case 32: 1016d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1017d9612c2fSPengbo Mu break; 1018d9612c2fSPengbo Mu case 16: 1019d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1020d9612c2fSPengbo Mu break; 1021d9612c2fSPengbo Mu case 8: 1022d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1023d9612c2fSPengbo Mu break; 1024d9612c2fSPengbo Mu case 4: 1025d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1026d9612c2fSPengbo Mu break; 1027d9612c2fSPengbo Mu case 1: 1028d9612c2fSPengbo Mu break; 1029d9612c2fSPengbo Mu default: 1030d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1031d9612c2fSPengbo Mu break; 1032d9612c2fSPengbo Mu } 1033d9612c2fSPengbo Mu 1034d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1035d9612c2fSPengbo Mu } 1036d9612c2fSPengbo Mu 10373497b9a5SLi Jun static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) 10383497b9a5SLi Jun { 10393497b9a5SLi Jun u32 scale; 10403497b9a5SLi Jun u32 reg; 10413497b9a5SLi Jun 10423497b9a5SLi Jun if (!dwc->susp_clk) 10433497b9a5SLi Jun return; 10443497b9a5SLi Jun 10453497b9a5SLi Jun /* 10463497b9a5SLi Jun * The power down scale field specifies how many suspend_clk 10473497b9a5SLi Jun * periods fit into a 16KHz clock period. When performing 10483497b9a5SLi Jun * the division, round up the remainder. 10493497b9a5SLi Jun * 10503497b9a5SLi Jun * The power down scale value is calculated using the fastest 10513497b9a5SLi Jun * frequency of the suspend_clk. If it isn't fixed (but within 10523497b9a5SLi Jun * the accuracy requirement), the driver may not know the max 10533497b9a5SLi Jun * rate of the suspend_clk, so only update the power down scale 10543497b9a5SLi Jun * if the default is less than the calculated value from 10553497b9a5SLi Jun * clk_get_rate() or if the default is questionably high 10563497b9a5SLi Jun * (3x or more) to be within the requirement. 10573497b9a5SLi Jun */ 10583497b9a5SLi Jun scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); 10593497b9a5SLi Jun reg = dwc3_readl(dwc->regs, DWC3_GCTL); 10603497b9a5SLi Jun if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || 10613497b9a5SLi Jun (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { 10623497b9a5SLi Jun reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); 10633497b9a5SLi Jun reg |= DWC3_GCTL_PWRDNSCALE(scale); 10643497b9a5SLi Jun dwc3_writel(dwc->regs, DWC3_GCTL, reg); 10653497b9a5SLi Jun } 10663497b9a5SLi Jun } 10673497b9a5SLi Jun 1068941f918eSFelipe Balbi /** 1069941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1070941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1071941f918eSFelipe Balbi * 1072941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1073941f918eSFelipe Balbi */ 1074941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1075941f918eSFelipe Balbi { 10769ba3aca8SThinh Nguyen unsigned int hw_mode; 1077941f918eSFelipe Balbi u32 reg; 1078941f918eSFelipe Balbi int ret; 1079941f918eSFelipe Balbi 10809ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10819ba3aca8SThinh Nguyen 1082941f918eSFelipe Balbi /* 1083941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1084941f918eSFelipe Balbi * out which kernel version a bug was found. 1085941f918eSFelipe Balbi */ 1086941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1087941f918eSFelipe Balbi 1088941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1089941f918eSFelipe Balbi if (ret) 1090941f918eSFelipe Balbi goto err0; 1091941f918eSFelipe Balbi 109298112041SRoger Quadros if (!dwc->ulpi_ready) { 109398112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 109498112041SRoger Quadros if (ret) 109598112041SRoger Quadros goto err0; 109698112041SRoger Quadros dwc->ulpi_ready = true; 109798112041SRoger Quadros } 109898112041SRoger Quadros 109998112041SRoger Quadros if (!dwc->phys_ready) { 110098112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 110198112041SRoger Quadros if (ret) 110298112041SRoger Quadros goto err0a; 110398112041SRoger Quadros dwc->phys_ready = true; 110498112041SRoger Quadros } 110598112041SRoger Quadros 11068cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 11078cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 11088cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 11098cfac9a6SLi Jun if (ret < 0) 11108cfac9a6SLi Jun goto err0a; 11118cfac9a6SLi Jun 11128cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 11138cfac9a6SLi Jun if (ret < 0) { 11148cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 11158cfac9a6SLi Jun goto err0a; 11168cfac9a6SLi Jun } 11178cfac9a6SLi Jun 111898112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 111998112041SRoger Quadros if (ret) 11208cfac9a6SLi Jun goto err1; 112198112041SRoger Quadros 11229ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 11239af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 11249ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 11259ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 11269ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 11279ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 11289ba3aca8SThinh Nguyen } 11299ba3aca8SThinh Nguyen 11309ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 11319ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 11329ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 11339ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 11349ba3aca8SThinh Nguyen } 11359ba3aca8SThinh Nguyen } 11369ba3aca8SThinh Nguyen 1137941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1138c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11390ffcaf37SFelipe Balbi 11400ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11410ffcaf37SFelipe Balbi if (ret) 1142c499ff71SFelipe Balbi goto err1; 1143c499ff71SFelipe Balbi 11443497b9a5SLi Jun /* Set power down scale of suspend_clk */ 11453497b9a5SLi Jun dwc3_set_power_down_clk_scale(dwc); 11463497b9a5SLi Jun 1147c499ff71SFelipe Balbi /* Adjust Frame Length */ 1148c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1149c499ff71SFelipe Balbi 11507bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11517bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11527bee3188SBalaji Prakash J 1153d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1154d9612c2fSPengbo Mu 1155c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1156c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1157c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1158c499ff71SFelipe Balbi if (ret < 0) 11590ffcaf37SFelipe Balbi goto err2; 11600ffcaf37SFelipe Balbi 1161c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1162c499ff71SFelipe Balbi if (ret < 0) 1163c499ff71SFelipe Balbi goto err3; 1164c499ff71SFelipe Balbi 1165c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1166c499ff71SFelipe Balbi if (ret) { 1167c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1168c499ff71SFelipe Balbi goto err4; 1169c499ff71SFelipe Balbi } 1170c499ff71SFelipe Balbi 117106281d46SJohn Youn /* 117206281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 117306281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 117406281d46SJohn Youn * DWC_usb31 controller. 117506281d46SJohn Youn */ 11769af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 117706281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 117806281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 117906281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 118006281d46SJohn Youn } 118106281d46SJohn Youn 11829af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 11830bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 118465db7a0cSWilliam Wu 118565db7a0cSWilliam Wu /* 118665db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 118765db7a0cSWilliam Wu * in HS when the device is in the L1 state. 118865db7a0cSWilliam Wu */ 11899af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 11900bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 119165db7a0cSWilliam Wu 1192843714bbSJack Pham /* 1193843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1194843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1195843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1196843714bbSJack Pham * from interrupting the driver. 1197843714bbSJack Pham */ 1198843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1199843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1200843714bbSJack Pham 120165db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 120265db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 120365db7a0cSWilliam Wu 12047ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 12057ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 12067ba6b09fSNeil Armstrong 120762b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 120862b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 120962b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 121062b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 121162b20e6eSBin Yang 12120bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 12130bb39ca1SJohn Youn } 12140bb39ca1SJohn Youn 1215b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1216b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1217b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1218b138e23dSAnurag Kumar Vulisha 1219b138e23dSAnurag Kumar Vulisha /* 1220b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1221b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1222b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1223b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1224b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1225b138e23dSAnurag Kumar Vulisha */ 1226b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1227b138e23dSAnurag Kumar Vulisha 1228b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1229b138e23dSAnurag Kumar Vulisha } 1230b138e23dSAnurag Kumar Vulisha 1231938a5ad1SThinh Nguyen /* 1232938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1233938a5ad1SThinh Nguyen * RX and/or TX threshold. 1234938a5ad1SThinh Nguyen */ 12359af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1236938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1237938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1238938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1239938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1240938a5ad1SThinh Nguyen 1241938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1242938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1243938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1244938a5ad1SThinh Nguyen 1245938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1246938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1247938a5ad1SThinh Nguyen 1248938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1249938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1250938a5ad1SThinh Nguyen 1251938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1252938a5ad1SThinh Nguyen } 1253938a5ad1SThinh Nguyen 1254938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1255938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1256938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1257938a5ad1SThinh Nguyen 1258938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1259938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1260938a5ad1SThinh Nguyen 1261938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1262938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1263938a5ad1SThinh Nguyen 1264938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1265938a5ad1SThinh Nguyen } 1266938a5ad1SThinh Nguyen } 1267938a5ad1SThinh Nguyen 126872246da4SFelipe Balbi return 0; 126972246da4SFelipe Balbi 1270c499ff71SFelipe Balbi err4: 12719b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1272c499ff71SFelipe Balbi 1273c499ff71SFelipe Balbi err3: 12749b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1275c499ff71SFelipe Balbi 12760ffcaf37SFelipe Balbi err2: 1277c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1278c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12790ffcaf37SFelipe Balbi 12800ffcaf37SFelipe Balbi err1: 12810ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 12820ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 128357303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 128457303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 12850ffcaf37SFelipe Balbi 128698112041SRoger Quadros err0a: 128798112041SRoger Quadros dwc3_ulpi_exit(dwc); 128898112041SRoger Quadros 128972246da4SFelipe Balbi err0: 129072246da4SFelipe Balbi return ret; 129172246da4SFelipe Balbi } 129272246da4SFelipe Balbi 12933c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 129472246da4SFelipe Balbi { 12953c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1296941ea361SFelipe Balbi struct device_node *node = dev->of_node; 12973c9f94acSFelipe Balbi int ret; 129872246da4SFelipe Balbi 12995088b6f5SKishon Vijay Abraham I if (node) { 13005088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 13015088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1302bb674907SFelipe Balbi } else { 1303bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1304bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 13055088b6f5SKishon Vijay Abraham I } 13065088b6f5SKishon Vijay Abraham I 1307d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1308d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1309d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1310122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1311d090c7a2SKushagra Verma else 13120c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1313122f06e6SKishon Vijay Abraham I } 131451e1e7bcSFelipe Balbi 1315d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1316315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1317d090c7a2SKushagra Verma if (ret == -ENXIO || ret == -ENODEV) 1318122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1319d090c7a2SKushagra Verma else 13200c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1321122f06e6SKishon Vijay Abraham I } 132251e1e7bcSFelipe Balbi 132357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 132457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 132557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 1326fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 132757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 1328d090c7a2SKushagra Verma else 13290c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 133057303488SKishon Vijay Abraham I } 133157303488SKishon Vijay Abraham I 133257303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 133357303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 133457303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 1335fb119dcbSThinh Nguyen if (ret == -ENOSYS || ret == -ENODEV) 133657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 1337d090c7a2SKushagra Verma else 13380c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 133957303488SKishon Vijay Abraham I } 134057303488SKishon Vijay Abraham I 13413c9f94acSFelipe Balbi return 0; 13423c9f94acSFelipe Balbi } 13433c9f94acSFelipe Balbi 13445f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13455f94adfeSFelipe Balbi { 13465f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13475f94adfeSFelipe Balbi int ret; 13485f94adfeSFelipe Balbi 13495f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13505f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 135141ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1352958d1a4cSFelipe Balbi 1353958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1354958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1355958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1356644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1357958d1a4cSFelipe Balbi 13585f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13590c0a20f6SAndy Shevchenko if (ret) 13600c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13615f94adfeSFelipe Balbi break; 13625f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 136341ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1364958d1a4cSFelipe Balbi 1365958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1366958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1367958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1368644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1369958d1a4cSFelipe Balbi 13705f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13710c0a20f6SAndy Shevchenko if (ret) 13720c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13735f94adfeSFelipe Balbi break; 13745f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 137541ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13769840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13770c0a20f6SAndy Shevchenko if (ret) 13780c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13795f94adfeSFelipe Balbi break; 13805f94adfeSFelipe Balbi default: 13815f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 13825f94adfeSFelipe Balbi return -EINVAL; 13835f94adfeSFelipe Balbi } 13845f94adfeSFelipe Balbi 13855f94adfeSFelipe Balbi return 0; 13865f94adfeSFelipe Balbi } 13875f94adfeSFelipe Balbi 13885f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 13895f94adfeSFelipe Balbi { 13905f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13915f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 13925f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 13935f94adfeSFelipe Balbi break; 13945f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 13955f94adfeSFelipe Balbi dwc3_host_exit(dwc); 13965f94adfeSFelipe Balbi break; 13975f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 13989840354fSRoger Quadros dwc3_drd_exit(dwc); 13995f94adfeSFelipe Balbi break; 14005f94adfeSFelipe Balbi default: 14015f94adfeSFelipe Balbi /* do nothing */ 14025f94adfeSFelipe Balbi break; 14035f94adfeSFelipe Balbi } 140409ed259fSBin Liu 140509ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 140609ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 14075f94adfeSFelipe Balbi } 14085f94adfeSFelipe Balbi 1409c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 14103c9f94acSFelipe Balbi { 1411c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 141280caf7d2SHuang Rui u8 lpm_nyet_threshold; 14136b6a0c9aSHuang Rui u8 tx_de_emphasis; 1414460d098cSHuang Rui u8 hird_threshold; 1415f28ad906SThinh Nguyen u8 rx_thr_num_pkt_prd = 0; 1416f28ad906SThinh Nguyen u8 rx_max_burst_prd = 0; 1417f28ad906SThinh Nguyen u8 tx_thr_num_pkt_prd = 0; 1418f28ad906SThinh Nguyen u8 tx_max_burst_prd = 0; 14199f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 14206f0764b5SRay Chi const char *usb_psy_name; 14216f0764b5SRay Chi int ret; 14223c9f94acSFelipe Balbi 142380caf7d2SHuang Rui /* default to highest possible threshold */ 14248d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 142580caf7d2SHuang Rui 14266b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 14276b6a0c9aSHuang Rui tx_de_emphasis = 1; 14286b6a0c9aSHuang Rui 1429460d098cSHuang Rui /* 1430460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1431460d098cSHuang Rui * threshold value of 0b1100 1432460d098cSHuang Rui */ 1433460d098cSHuang Rui hird_threshold = 12; 1434460d098cSHuang Rui 14359f607a30SWesley Cheng /* 14369f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 14379f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14389f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14399f607a30SWesley Cheng */ 14409f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14419f607a30SWesley Cheng 144263863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 144367848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 144406e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 144532f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 144663863b98SHeikki Krogerus 1447d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1448d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1449d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1450d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1451d64ff406SArnd Bergmann else 1452d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1453d64ff406SArnd Bergmann 14546f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14556f0764b5SRay Chi if (ret >= 0) { 14566f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14576f0764b5SRay Chi if (!dwc->usb_psy) 14586f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14596f0764b5SRay Chi } 14606f0764b5SRay Chi 14613d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 146280caf7d2SHuang Rui "snps,has-lpm-erratum"); 14633d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 146480caf7d2SHuang Rui &lpm_nyet_threshold); 14653d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1466460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14673d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1468460d098cSHuang Rui &hird_threshold); 1469d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1470d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14713d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1472eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1473022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1474022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1475475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1476475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1477938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1478938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1479938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1480938a5ad1SThinh Nguyen &rx_max_burst_prd); 1481938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1482938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1483938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1484938a5ad1SThinh Nguyen &tx_max_burst_prd); 14859f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 14869f607a30SWesley Cheng "tx-fifo-resize"); 14879f607a30SWesley Cheng if (dwc->do_fifo_resize) 14889f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 14899f607a30SWesley Cheng &tx_fifo_resize_max_num); 14903c9f94acSFelipe Balbi 14913d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 14923b81221aSHuang Rui "snps,disable_scramble_quirk"); 14933d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 14949a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 14953d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1496b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 14973d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1498df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 14993d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1500a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 15013d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 150241c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 15033d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1504fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 15053d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 150614f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 15073d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 150859acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 15093d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 15100effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1511ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1512ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1513729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1514729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1515729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1516729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1517e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1518e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 151916199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 152016199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 152100fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 152200fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 152365db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 152465db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 15257ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 15267ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 15276b6a0c9aSHuang Rui 15283d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 15296b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 15303d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 15316b6a0c9aSHuang Rui &tx_de_emphasis); 15323d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 15333e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 15343d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1535bcdb3272SFelipe Balbi &dwc->fladj); 15367bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 15377bee3188SBalaji Prakash J &dwc->ref_clk_per); 15383d128919SHeikki Krogerus 153942bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 154042bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 154142bf02ecSRoger Quadros 1542f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1543f580170fSYu Chen "snps,dis-split-quirk"); 1544f580170fSYu Chen 154580caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15466b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 154780caf7d2SHuang Rui 154816fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1549460d098cSHuang Rui 1550938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1551938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1552938a5ad1SThinh Nguyen 1553938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1554938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1555938a5ad1SThinh Nguyen 1556cf40b86bSJohn Youn dwc->imod_interval = 0; 15579f607a30SWesley Cheng 15589f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1559cf40b86bSJohn Youn } 1560cf40b86bSJohn Youn 1561cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1562cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1563cf40b86bSJohn Youn { 15649af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15659af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15669af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1567c5ac6116SFelipe Balbi } 1568c5ac6116SFelipe Balbi 15697ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15707ac51a12SJohn Youn { 15717ac51a12SJohn Youn struct device *dev = dwc->dev; 1572b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1573b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15747ac51a12SJohn Youn 1575cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1576cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1577cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1578cf40b86bSJohn Youn dwc->imod_interval = 0; 1579cf40b86bSJohn Youn } 1580cf40b86bSJohn Youn 158128632b44SJohn Youn /* 158228632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 158328632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 158428632b44SJohn Youn * interrupt from being masked while handling events. IMOD 158528632b44SJohn Youn * allows us to work around this issue. Enable it for the 158628632b44SJohn Youn * affected version. 158728632b44SJohn Youn */ 158828632b44SJohn Youn if (!dwc->imod_interval && 15899af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 159028632b44SJohn Youn dwc->imod_interval = 1; 159128632b44SJohn Youn 15927ac51a12SJohn Youn /* Check the maximum_speed parameter */ 15937ac51a12SJohn Youn switch (dwc->maximum_speed) { 15947ac51a12SJohn Youn case USB_SPEED_FULL: 15957ac51a12SJohn Youn case USB_SPEED_HIGH: 1596e518bdd9SThinh Nguyen break; 15977ac51a12SJohn Youn case USB_SPEED_SUPER: 1598e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1599e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1600e518bdd9SThinh Nguyen break; 16017ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1602e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1603e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1604e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1605e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1606e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 16077ac51a12SJohn Youn break; 16087ac51a12SJohn Youn default: 16097ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 16107ac51a12SJohn Youn dwc->maximum_speed); 1611df561f66SGustavo A. R. Silva fallthrough; 16127ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1613b574ce3eSThinh Nguyen switch (hwparam_gen) { 1614b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 16157ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1616b574ce3eSThinh Nguyen break; 1617b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1618b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1619b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1620b574ce3eSThinh Nguyen else 1621b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1622b574ce3eSThinh Nguyen break; 1623b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1624b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1625b574ce3eSThinh Nguyen break; 1626b574ce3eSThinh Nguyen default: 1627b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1628b574ce3eSThinh Nguyen break; 1629b574ce3eSThinh Nguyen } 16307ac51a12SJohn Youn break; 16317ac51a12SJohn Youn } 163267848146SThinh Nguyen 163367848146SThinh Nguyen /* 163467848146SThinh Nguyen * Currently the controller does not have visibility into the HW 163567848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 163667848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 163767848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 163867848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 163967848146SThinh Nguyen */ 164067848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 164167848146SThinh Nguyen switch (dwc->max_ssp_rate) { 164267848146SThinh Nguyen case USB_SSP_GEN_2x1: 164367848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 164467848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 164567848146SThinh Nguyen break; 164667848146SThinh Nguyen case USB_SSP_GEN_1x2: 164767848146SThinh Nguyen case USB_SSP_GEN_2x2: 164867848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 164967848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 165067848146SThinh Nguyen break; 165167848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 165267848146SThinh Nguyen default: 165367848146SThinh Nguyen switch (hwparam_gen) { 165467848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 165567848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 165667848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 165767848146SThinh Nguyen else 165867848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 165967848146SThinh Nguyen break; 166067848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 166167848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 166267848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 166367848146SThinh Nguyen break; 166467848146SThinh Nguyen } 166567848146SThinh Nguyen break; 166667848146SThinh Nguyen } 166767848146SThinh Nguyen } 16687ac51a12SJohn Youn } 16697ac51a12SJohn Youn 16700f010171SAndrey Smirnov static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc) 16710f010171SAndrey Smirnov { 16720f010171SAndrey Smirnov struct device *dev = dwc->dev; 16730f010171SAndrey Smirnov struct device_node *np_phy; 16740f010171SAndrey Smirnov struct extcon_dev *edev = NULL; 16750f010171SAndrey Smirnov const char *name; 16760f010171SAndrey Smirnov 16770f010171SAndrey Smirnov if (device_property_read_bool(dev, "extcon")) 16780f010171SAndrey Smirnov return extcon_get_edev_by_phandle(dev, 0); 16790f010171SAndrey Smirnov 16800f010171SAndrey Smirnov /* 16810f010171SAndrey Smirnov * Device tree platforms should get extcon via phandle. 16820f010171SAndrey Smirnov * On ACPI platforms, we get the name from a device property. 16830f010171SAndrey Smirnov * This device property is for kernel internal use only and 16840f010171SAndrey Smirnov * is expected to be set by the glue code. 16850f010171SAndrey Smirnov */ 16868bd6b8c4SStephen Rothwell if (device_property_read_string(dev, "linux,extcon-name", &name) == 0) 16878bd6b8c4SStephen Rothwell return extcon_get_extcon_dev(name); 16880f010171SAndrey Smirnov 16890f010171SAndrey Smirnov /* 16900f010171SAndrey Smirnov * Try to get an extcon device from the USB PHY controller's "port" 16910f010171SAndrey Smirnov * node. Check if it has the "port" node first, to avoid printing the 16920f010171SAndrey Smirnov * error message from underlying code, as it's a valid case: extcon 16930f010171SAndrey Smirnov * device (and "port" node) may be missing in case of "usb-role-switch" 16940f010171SAndrey Smirnov * or OTG mode. 16950f010171SAndrey Smirnov */ 16960f010171SAndrey Smirnov np_phy = of_parse_phandle(dev->of_node, "phys", 0); 16970f010171SAndrey Smirnov if (of_graph_is_present(np_phy)) { 16980f010171SAndrey Smirnov struct device_node *np_conn; 16990f010171SAndrey Smirnov 17000f010171SAndrey Smirnov np_conn = of_graph_get_remote_node(np_phy, -1, -1); 17010f010171SAndrey Smirnov if (np_conn) 17020f010171SAndrey Smirnov edev = extcon_find_edev_by_node(np_conn); 17030f010171SAndrey Smirnov of_node_put(np_conn); 17040f010171SAndrey Smirnov } 17050f010171SAndrey Smirnov of_node_put(np_phy); 17060f010171SAndrey Smirnov 17070f010171SAndrey Smirnov return edev; 17080f010171SAndrey Smirnov } 17090f010171SAndrey Smirnov 1710c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1711c5ac6116SFelipe Balbi { 1712c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 171344feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1714c5ac6116SFelipe Balbi struct dwc3 *dwc; 1715c5ac6116SFelipe Balbi 1716c5ac6116SFelipe Balbi int ret; 1717c5ac6116SFelipe Balbi 1718c5ac6116SFelipe Balbi void __iomem *regs; 1719c5ac6116SFelipe Balbi 1720c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1721c5ac6116SFelipe Balbi if (!dwc) 1722c5ac6116SFelipe Balbi return -ENOMEM; 1723c5ac6116SFelipe Balbi 1724c5ac6116SFelipe Balbi dwc->dev = dev; 1725c5ac6116SFelipe Balbi 1726c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1727c5ac6116SFelipe Balbi if (!res) { 1728c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1729c5ac6116SFelipe Balbi return -ENODEV; 1730c5ac6116SFelipe Balbi } 1731c5ac6116SFelipe Balbi 1732c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1733c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1734c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1735c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1736c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1737c5ac6116SFelipe Balbi 1738c5ac6116SFelipe Balbi /* 1739c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1740c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1741c5ac6116SFelipe Balbi */ 174244feb8e6SMasahiro Yamada dwc_res = *res; 174344feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 174444feb8e6SMasahiro Yamada 174544feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 174644feb8e6SMasahiro Yamada if (IS_ERR(regs)) 174744feb8e6SMasahiro Yamada return PTR_ERR(regs); 1748c5ac6116SFelipe Balbi 1749c5ac6116SFelipe Balbi dwc->regs = regs; 175044feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1751c5ac6116SFelipe Balbi 1752c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1753c5ac6116SFelipe Balbi 175447ce4590SFabio Aiuto if (!dwc->sysdev_is_parent) { 175545d39448SSven Peter ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 175645d39448SSven Peter if (ret) 175745d39448SSven Peter return ret; 175847ce4590SFabio Aiuto } 175945d39448SSven Peter 1760babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1761fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1762fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1763fe8abf33SMasahiro Yamada 176461527777SHans de Goede if (dev->of_node) { 1765fe8abf33SMasahiro Yamada /* 176661527777SHans de Goede * Clocks are optional, but new DT platforms should support all 176761527777SHans de Goede * clocks as required by the DT-binding. 17684e64cd77SPeter Geis * Some devices have different clock names in legacy device trees, 17694e64cd77SPeter Geis * check for them to retain backwards compatibility. 1770fe8abf33SMasahiro Yamada */ 177133fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 177233fb697eSSean Anderson if (IS_ERR(dwc->bus_clk)) 177333fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 177433fb697eSSean Anderson "could not get bus clock\n"); 17750d3a9708SJohn Stultz 17764e64cd77SPeter Geis if (dwc->bus_clk == NULL) { 17774e64cd77SPeter Geis dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk"); 17784e64cd77SPeter Geis if (IS_ERR(dwc->bus_clk)) 17794e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 17804e64cd77SPeter Geis "could not get bus clock\n"); 17814e64cd77SPeter Geis } 17824e64cd77SPeter Geis 178333fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 178433fb697eSSean Anderson if (IS_ERR(dwc->ref_clk)) 178533fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 178633fb697eSSean Anderson "could not get ref clock\n"); 178733fb697eSSean Anderson 17884e64cd77SPeter Geis if (dwc->ref_clk == NULL) { 17894e64cd77SPeter Geis dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk"); 17904e64cd77SPeter Geis if (IS_ERR(dwc->ref_clk)) 17914e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 17924e64cd77SPeter Geis "could not get ref clock\n"); 17934e64cd77SPeter Geis } 17944e64cd77SPeter Geis 179533fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 179633fb697eSSean Anderson if (IS_ERR(dwc->susp_clk)) 179733fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 179833fb697eSSean Anderson "could not get suspend clock\n"); 17994e64cd77SPeter Geis 18004e64cd77SPeter Geis if (dwc->susp_clk == NULL) { 18014e64cd77SPeter Geis dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk"); 18024e64cd77SPeter Geis if (IS_ERR(dwc->susp_clk)) 18034e64cd77SPeter Geis return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 18044e64cd77SPeter Geis "could not get suspend clock\n"); 18054e64cd77SPeter Geis } 180661527777SHans de Goede } 1807fe8abf33SMasahiro Yamada 1808fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1809fe8abf33SMasahiro Yamada if (ret) 181003bf32bbSAndrey Smirnov return ret; 1811fe8abf33SMasahiro Yamada 181233fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1813fe8abf33SMasahiro Yamada if (ret) 1814fe8abf33SMasahiro Yamada goto assert_reset; 1815fe8abf33SMasahiro Yamada 1816dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1817dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1818dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1819dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1820dc1b5d9aSEnric Balletbo i Serra } 1821dc1b5d9aSEnric Balletbo i Serra 18226c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 18232917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 1824649f5c84SSandeep Maheswaram device_init_wakeup(&pdev->dev, of_property_read_bool(dev->of_node, "wakeup-source")); 18256c89cce0SHeikki Krogerus 182672246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1827f88359e1SYu Chen mutex_init(&dwc->mutex); 182872246da4SFelipe Balbi 1829fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1830fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1831fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1832802ca850SChanho Park pm_runtime_enable(dev); 183332808237SRoger Quadros ret = pm_runtime_get_sync(dev); 183432808237SRoger Quadros if (ret < 0) 183532808237SRoger Quadros goto err1; 183632808237SRoger Quadros 1837802ca850SChanho Park pm_runtime_forbid(dev); 183872246da4SFelipe Balbi 18393921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 18403921426bSFelipe Balbi if (ret) { 18413921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 18423921426bSFelipe Balbi ret = -ENOMEM; 184332808237SRoger Quadros goto err2; 18443921426bSFelipe Balbi } 18453921426bSFelipe Balbi 18460f010171SAndrey Smirnov dwc->edev = dwc3_get_extcon(dwc); 18470f010171SAndrey Smirnov if (IS_ERR(dwc->edev)) { 18480f010171SAndrey Smirnov ret = PTR_ERR(dwc->edev); 18490f010171SAndrey Smirnov dev_err_probe(dwc->dev, ret, "failed to get extcon\n"); 18500f010171SAndrey Smirnov goto err3; 18510f010171SAndrey Smirnov } 18520f010171SAndrey Smirnov 18539d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 18549d6173e1SThinh Nguyen if (ret) 18559d6173e1SThinh Nguyen goto err3; 185632a4a135SFelipe Balbi 1857c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1858c499ff71SFelipe Balbi if (ret) 185932808237SRoger Quadros goto err3; 1860c499ff71SFelipe Balbi 186172246da4SFelipe Balbi ret = dwc3_core_init(dwc); 186272246da4SFelipe Balbi if (ret) { 18630c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 186432808237SRoger Quadros goto err4; 186572246da4SFelipe Balbi } 186672246da4SFelipe Balbi 18677ac51a12SJohn Youn dwc3_check_params(dwc); 186884524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 18692c7f1bd9SJohn Youn 18705f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 18715f94adfeSFelipe Balbi if (ret) 187232808237SRoger Quadros goto err5; 187372246da4SFelipe Balbi 1874fc8bb91bSFelipe Balbi pm_runtime_put(dev); 187572246da4SFelipe Balbi 187672246da4SFelipe Balbi return 0; 187772246da4SFelipe Balbi 187832808237SRoger Quadros err5: 187984524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1880f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 188103c1fd62SLi Jun 188203c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 188303c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 188403c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 188503c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 188603c1fd62SLi Jun 188703c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 188803c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 188903c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 189003c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 189103c1fd62SLi Jun 189208fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1893f122d33eSFelipe Balbi 189432808237SRoger Quadros err4: 1895c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 189672246da4SFelipe Balbi 189732808237SRoger Quadros err3: 18983921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 18993921426bSFelipe Balbi 190032808237SRoger Quadros err2: 190132808237SRoger Quadros pm_runtime_allow(&pdev->dev); 190232808237SRoger Quadros 190332808237SRoger Quadros err1: 190432808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 190532808237SRoger Quadros pm_runtime_disable(&pdev->dev); 190632808237SRoger Quadros 1907dc1b5d9aSEnric Balletbo i Serra disable_clks: 190833fb697eSSean Anderson dwc3_clk_disable(dwc); 1909fe8abf33SMasahiro Yamada assert_reset: 1910fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1911fe8abf33SMasahiro Yamada 1912b0bf77cdSColin Ian King if (dwc->usb_psy) 19136f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19146f0764b5SRay Chi 191572246da4SFelipe Balbi return ret; 191672246da4SFelipe Balbi } 191772246da4SFelipe Balbi 1918fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 191972246da4SFelipe Balbi { 192072246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 19213da1f6eeSFelipe Balbi 1922fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 192372246da4SFelipe Balbi 1924dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 19252a042767SPeter Chen dwc3_debugfs_exit(dwc); 19268ba007a9SKishon Vijay Abraham I 192772246da4SFelipe Balbi dwc3_core_exit(dwc); 192888bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 192972246da4SFelipe Balbi 1930fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1931266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1932266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1933fc8bb91bSFelipe Balbi 1934c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1935c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1936c499ff71SFelipe Balbi 1937b0bf77cdSColin Ian King if (dwc->usb_psy) 19386f0764b5SRay Chi power_supply_put(dwc->usb_psy); 19396f0764b5SRay Chi 194072246da4SFelipe Balbi return 0; 194172246da4SFelipe Balbi } 194272246da4SFelipe Balbi 1943fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1944fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1945fe8abf33SMasahiro Yamada { 1946fe8abf33SMasahiro Yamada int ret; 1947fe8abf33SMasahiro Yamada 1948fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1949fe8abf33SMasahiro Yamada if (ret) 1950fe8abf33SMasahiro Yamada return ret; 1951fe8abf33SMasahiro Yamada 195233fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1953fe8abf33SMasahiro Yamada if (ret) 1954fe8abf33SMasahiro Yamada goto assert_reset; 1955fe8abf33SMasahiro Yamada 1956fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1957fe8abf33SMasahiro Yamada if (ret) 1958fe8abf33SMasahiro Yamada goto disable_clks; 1959fe8abf33SMasahiro Yamada 1960fe8abf33SMasahiro Yamada return 0; 1961fe8abf33SMasahiro Yamada 1962fe8abf33SMasahiro Yamada disable_clks: 196333fb697eSSean Anderson dwc3_clk_disable(dwc); 1964fe8abf33SMasahiro Yamada assert_reset: 1965fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1966fe8abf33SMasahiro Yamada 1967fe8abf33SMasahiro Yamada return ret; 1968fe8abf33SMasahiro Yamada } 1969fe8abf33SMasahiro Yamada 1970c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 19717415f17cSFelipe Balbi { 1972fc8bb91bSFelipe Balbi unsigned long flags; 1973bcb12877SManu Gautam u32 reg; 19747415f17cSFelipe Balbi 1975689bf72cSManu Gautam switch (dwc->current_dr_role) { 1976689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 19770227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 19780227cc84SLi Jun break; 1979fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 19807415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1981fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 198241a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1983689bf72cSManu Gautam dwc3_core_exit(dwc); 198451f5d49aSFelipe Balbi break; 1985689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1986649f5c84SSandeep Maheswaram if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) { 1987c4a5153eSManu Gautam dwc3_core_exit(dwc); 1988c4a5153eSManu Gautam break; 1989bcb12877SManu Gautam } 1990bcb12877SManu Gautam 1991bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1992bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1993bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1994bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1995bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1996bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1997bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1998bcb12877SManu Gautam 1999bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 2000bcb12877SManu Gautam usleep_range(5000, 6000); 2001bcb12877SManu Gautam } 2002bcb12877SManu Gautam 2003bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 2004bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 2005bcb12877SManu Gautam break; 2006f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2007f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 2008f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2009f09cc79bSRoger Quadros break; 2010f09cc79bSRoger Quadros 2011f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2012f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2013f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 2014f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 201541a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 2016f09cc79bSRoger Quadros } 2017f09cc79bSRoger Quadros 2018f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 2019f09cc79bSRoger Quadros dwc3_core_exit(dwc); 2020f09cc79bSRoger Quadros break; 20217415f17cSFelipe Balbi default: 202251f5d49aSFelipe Balbi /* do nothing */ 20237415f17cSFelipe Balbi break; 20247415f17cSFelipe Balbi } 20257415f17cSFelipe Balbi 2026fc8bb91bSFelipe Balbi return 0; 2027fc8bb91bSFelipe Balbi } 2028fc8bb91bSFelipe Balbi 2029c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 2030fc8bb91bSFelipe Balbi { 2031fc8bb91bSFelipe Balbi unsigned long flags; 2032fc8bb91bSFelipe Balbi int ret; 2033bcb12877SManu Gautam u32 reg; 2034fc8bb91bSFelipe Balbi 2035689bf72cSManu Gautam switch (dwc->current_dr_role) { 2036689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2037fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2038fc8bb91bSFelipe Balbi if (ret) 2039fc8bb91bSFelipe Balbi return ret; 2040fc8bb91bSFelipe Balbi 20417d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 2042fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 2043fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 2044fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 2045689bf72cSManu Gautam break; 2046689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2047649f5c84SSandeep Maheswaram if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) { 2048fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 2049c4a5153eSManu Gautam if (ret) 2050c4a5153eSManu Gautam return ret; 20517d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 2052bcb12877SManu Gautam break; 2053c4a5153eSManu Gautam } 2054bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 2055bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 2056bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 2057bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 2058bcb12877SManu Gautam 2059bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 2060bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 2061bcb12877SManu Gautam 2062bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 2063bcb12877SManu Gautam 2064bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 2065bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 2066c4a5153eSManu Gautam break; 2067f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 2068f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 2069f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 2070f09cc79bSRoger Quadros break; 2071f09cc79bSRoger Quadros 20720e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 2073f09cc79bSRoger Quadros if (ret) 2074f09cc79bSRoger Quadros return ret; 2075f09cc79bSRoger Quadros 2076f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 2077f09cc79bSRoger Quadros 2078f09cc79bSRoger Quadros dwc3_otg_init(dwc); 2079f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 2080f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 2081f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 2082f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 2083f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 2084f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 2085f09cc79bSRoger Quadros } 2086f09cc79bSRoger Quadros 2087f09cc79bSRoger Quadros break; 2088fc8bb91bSFelipe Balbi default: 2089fc8bb91bSFelipe Balbi /* do nothing */ 2090fc8bb91bSFelipe Balbi break; 2091fc8bb91bSFelipe Balbi } 2092fc8bb91bSFelipe Balbi 2093fc8bb91bSFelipe Balbi return 0; 2094fc8bb91bSFelipe Balbi } 2095fc8bb91bSFelipe Balbi 2096fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 2097fc8bb91bSFelipe Balbi { 2098689bf72cSManu Gautam switch (dwc->current_dr_role) { 2099c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2100fc8bb91bSFelipe Balbi if (dwc->connected) 2101fc8bb91bSFelipe Balbi return -EBUSY; 2102fc8bb91bSFelipe Balbi break; 2103c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2104fc8bb91bSFelipe Balbi default: 2105fc8bb91bSFelipe Balbi /* do nothing */ 2106fc8bb91bSFelipe Balbi break; 2107fc8bb91bSFelipe Balbi } 2108fc8bb91bSFelipe Balbi 2109fc8bb91bSFelipe Balbi return 0; 2110fc8bb91bSFelipe Balbi } 2111fc8bb91bSFelipe Balbi 2112fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2113fc8bb91bSFelipe Balbi { 2114fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2115fc8bb91bSFelipe Balbi int ret; 2116fc8bb91bSFelipe Balbi 2117fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2118fc8bb91bSFelipe Balbi return -EBUSY; 2119fc8bb91bSFelipe Balbi 2120c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2121fc8bb91bSFelipe Balbi if (ret) 2122fc8bb91bSFelipe Balbi return ret; 2123fc8bb91bSFelipe Balbi 2124fc8bb91bSFelipe Balbi return 0; 2125fc8bb91bSFelipe Balbi } 2126fc8bb91bSFelipe Balbi 2127fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2128fc8bb91bSFelipe Balbi { 2129fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2130fc8bb91bSFelipe Balbi int ret; 2131fc8bb91bSFelipe Balbi 2132c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2133fc8bb91bSFelipe Balbi if (ret) 2134fc8bb91bSFelipe Balbi return ret; 2135fc8bb91bSFelipe Balbi 2136689bf72cSManu Gautam switch (dwc->current_dr_role) { 2137689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2138fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2139fc8bb91bSFelipe Balbi break; 2140689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2141fc8bb91bSFelipe Balbi default: 2142fc8bb91bSFelipe Balbi /* do nothing */ 2143fc8bb91bSFelipe Balbi break; 2144fc8bb91bSFelipe Balbi } 2145fc8bb91bSFelipe Balbi 2146fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2147fc8bb91bSFelipe Balbi 2148fc8bb91bSFelipe Balbi return 0; 2149fc8bb91bSFelipe Balbi } 2150fc8bb91bSFelipe Balbi 2151fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2152fc8bb91bSFelipe Balbi { 2153fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2154fc8bb91bSFelipe Balbi 2155689bf72cSManu Gautam switch (dwc->current_dr_role) { 2156689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2157fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2158fc8bb91bSFelipe Balbi return -EBUSY; 2159fc8bb91bSFelipe Balbi break; 2160689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2161fc8bb91bSFelipe Balbi default: 2162fc8bb91bSFelipe Balbi /* do nothing */ 2163fc8bb91bSFelipe Balbi break; 2164fc8bb91bSFelipe Balbi } 2165fc8bb91bSFelipe Balbi 2166fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2167fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2168fc8bb91bSFelipe Balbi 2169fc8bb91bSFelipe Balbi return 0; 2170fc8bb91bSFelipe Balbi } 2171fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2172fc8bb91bSFelipe Balbi 2173fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2174fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2175fc8bb91bSFelipe Balbi { 2176fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2177fc8bb91bSFelipe Balbi int ret; 2178fc8bb91bSFelipe Balbi 2179c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2180fc8bb91bSFelipe Balbi if (ret) 2181fc8bb91bSFelipe Balbi return ret; 2182fc8bb91bSFelipe Balbi 21836344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 21846344475fSSekhar Nori 21857415f17cSFelipe Balbi return 0; 21867415f17cSFelipe Balbi } 21877415f17cSFelipe Balbi 21887415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 21897415f17cSFelipe Balbi { 21907415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 219157303488SKishon Vijay Abraham I int ret; 21927415f17cSFelipe Balbi 21936344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 21946344475fSSekhar Nori 2195c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 219651f5d49aSFelipe Balbi if (ret) 21975c4ad318SFelipe Balbi return ret; 21985c4ad318SFelipe Balbi 21997415f17cSFelipe Balbi pm_runtime_disable(dev); 22007415f17cSFelipe Balbi pm_runtime_set_active(dev); 22017415f17cSFelipe Balbi pm_runtime_enable(dev); 22027415f17cSFelipe Balbi 22037415f17cSFelipe Balbi return 0; 22047415f17cSFelipe Balbi } 2205f580170fSYu Chen 2206f580170fSYu Chen static void dwc3_complete(struct device *dev) 2207f580170fSYu Chen { 2208f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2209f580170fSYu Chen u32 reg; 2210f580170fSYu Chen 2211f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2212f580170fSYu Chen dwc->dis_split_quirk) { 2213f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2214f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2215f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2216f580170fSYu Chen } 2217f580170fSYu Chen } 2218f580170fSYu Chen #else 2219f580170fSYu Chen #define dwc3_complete NULL 22207f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 22217415f17cSFelipe Balbi 22227415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 22237415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2224f580170fSYu Chen .complete = dwc3_complete, 2225fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2226fc8bb91bSFelipe Balbi dwc3_runtime_idle) 22277415f17cSFelipe Balbi }; 22287415f17cSFelipe Balbi 22295088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 22305088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 22315088b6f5SKishon Vijay Abraham I { 223222a5aa17SFelipe Balbi .compatible = "snps,dwc3" 223322a5aa17SFelipe Balbi }, 223422a5aa17SFelipe Balbi { 22355088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 22365088b6f5SKishon Vijay Abraham I }, 22375088b6f5SKishon Vijay Abraham I { }, 22385088b6f5SKishon Vijay Abraham I }; 22395088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 22405088b6f5SKishon Vijay Abraham I #endif 22415088b6f5SKishon Vijay Abraham I 2242404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2243404905a6SHeikki Krogerus 2244404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2245404905a6SHeikki Krogerus 2246404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2247404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2248404905a6SHeikki Krogerus { }, 2249404905a6SHeikki Krogerus }; 2250404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2251404905a6SHeikki Krogerus #endif 2252404905a6SHeikki Krogerus 225372246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 225472246da4SFelipe Balbi .probe = dwc3_probe, 22557690417dSBill Pemberton .remove = dwc3_remove, 225672246da4SFelipe Balbi .driver = { 225772246da4SFelipe Balbi .name = "dwc3", 22585088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2259404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 22607f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 226172246da4SFelipe Balbi }, 226272246da4SFelipe Balbi }; 226372246da4SFelipe Balbi 2264b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2265b1116dccSTobias Klauser 22667ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 226772246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 22685945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 226972246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 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