15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 272246da4SFelipe Balbi /** 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 2972246da4SFelipe Balbi 3072246da4SFelipe Balbi #include <linux/usb/ch9.h> 3172246da4SFelipe Balbi #include <linux/usb/gadget.h> 32f7e846f0SFelipe Balbi #include <linux/usb/of.h> 33a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3472246da4SFelipe Balbi 3572246da4SFelipe Balbi #include "core.h" 3672246da4SFelipe Balbi #include "gadget.h" 3772246da4SFelipe Balbi #include "io.h" 3872246da4SFelipe Balbi 3972246da4SFelipe Balbi #include "debug.h" 4072246da4SFelipe Balbi 41fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 428300dd23SFelipe Balbi 439d6173e1SThinh Nguyen /** 449d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 459d6173e1SThinh Nguyen * @dwc: pointer to our context structure 469d6173e1SThinh Nguyen */ 479d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 489d6173e1SThinh Nguyen { 499d6173e1SThinh Nguyen enum usb_dr_mode mode; 509d6173e1SThinh Nguyen struct device *dev = dwc->dev; 519d6173e1SThinh Nguyen unsigned int hw_mode; 529d6173e1SThinh Nguyen 539d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 549d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 559d6173e1SThinh Nguyen 569d6173e1SThinh Nguyen mode = dwc->dr_mode; 579d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 589d6173e1SThinh Nguyen 599d6173e1SThinh Nguyen switch (hw_mode) { 609d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 619d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 629d6173e1SThinh Nguyen dev_err(dev, 639d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 649d6173e1SThinh Nguyen return -EINVAL; 659d6173e1SThinh Nguyen } 669d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 679d6173e1SThinh Nguyen break; 689d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 699d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 709d6173e1SThinh Nguyen dev_err(dev, 719d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 729d6173e1SThinh Nguyen return -EINVAL; 739d6173e1SThinh Nguyen } 749d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 759d6173e1SThinh Nguyen break; 769d6173e1SThinh Nguyen default: 779d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 789d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 799d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 809d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 81a7700468SThinh Nguyen 82a7700468SThinh Nguyen /* 8389a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8489a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8589a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 86a7700468SThinh Nguyen */ 8789a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 888bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 898bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 909af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 91a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 929d6173e1SThinh Nguyen } 939d6173e1SThinh Nguyen 949d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 959d6173e1SThinh Nguyen dev_warn(dev, 969d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 979d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 989d6173e1SThinh Nguyen 999d6173e1SThinh Nguyen dwc->dr_mode = mode; 1009d6173e1SThinh Nguyen } 1019d6173e1SThinh Nguyen 1029d6173e1SThinh Nguyen return 0; 1039d6173e1SThinh Nguyen } 1049d6173e1SThinh Nguyen 105f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1063140e8cbSSebastian Andrzej Siewior { 1073140e8cbSSebastian Andrzej Siewior u32 reg; 1083140e8cbSSebastian Andrzej Siewior 1093140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1103140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1113140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1123140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 113c4a5153eSManu Gautam 114c4a5153eSManu Gautam dwc->current_dr_role = mode; 11541ce1456SRoger Quadros } 1166b3261a2SRoger Quadros 11741ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 11841ce1456SRoger Quadros { 11941ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12041ce1456SRoger Quadros unsigned long flags; 12141ce1456SRoger Quadros int ret; 12241ce1456SRoger Quadros 123c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 124c2cd3452SMartin Kepplinger 125f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 126f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 127f09cc79bSRoger Quadros 12841ce1456SRoger Quadros if (!dwc->desired_dr_role) 129c2cd3452SMartin Kepplinger goto out; 13041ce1456SRoger Quadros 13141ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 132c2cd3452SMartin Kepplinger goto out; 13341ce1456SRoger Quadros 134f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 135c2cd3452SMartin Kepplinger goto out; 13641ce1456SRoger Quadros 13741ce1456SRoger Quadros switch (dwc->current_dr_role) { 13841ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 13941ce1456SRoger Quadros dwc3_host_exit(dwc); 14041ce1456SRoger Quadros break; 14141ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14241ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14341ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14441ce1456SRoger Quadros break; 145f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 146f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 147f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 148f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 149f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 150f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 151f09cc79bSRoger Quadros break; 15241ce1456SRoger Quadros default: 15341ce1456SRoger Quadros break; 15441ce1456SRoger Quadros } 15541ce1456SRoger Quadros 15641ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 15741ce1456SRoger Quadros 15841ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 15941ce1456SRoger Quadros 16041ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 16141ce1456SRoger Quadros 16241ce1456SRoger Quadros switch (dwc->desired_dr_role) { 16341ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 16441ce1456SRoger Quadros ret = dwc3_host_init(dwc); 165958d1a4cSFelipe Balbi if (ret) { 16641ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 167958d1a4cSFelipe Balbi } else { 168958d1a4cSFelipe Balbi if (dwc->usb2_phy) 169958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 170958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 171644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 172958d1a4cSFelipe Balbi } 17341ce1456SRoger Quadros break; 17441ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 17541ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 176958d1a4cSFelipe Balbi 177958d1a4cSFelipe Balbi if (dwc->usb2_phy) 178958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 179958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 180644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 181958d1a4cSFelipe Balbi 18241ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 18341ce1456SRoger Quadros if (ret) 18441ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 18541ce1456SRoger Quadros break; 186f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 187f09cc79bSRoger Quadros dwc3_otg_init(dwc); 188f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 189f09cc79bSRoger Quadros break; 19041ce1456SRoger Quadros default: 19141ce1456SRoger Quadros break; 19241ce1456SRoger Quadros } 193f09cc79bSRoger Quadros 194c2cd3452SMartin Kepplinger out: 195c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 196c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 19741ce1456SRoger Quadros } 19841ce1456SRoger Quadros 19941ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 20041ce1456SRoger Quadros { 20141ce1456SRoger Quadros unsigned long flags; 20241ce1456SRoger Quadros 203dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 204dc336b19SLi Jun return; 205dc336b19SLi Jun 20641ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 20741ce1456SRoger Quadros dwc->desired_dr_role = mode; 20841ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 20941ce1456SRoger Quadros 210084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2113140e8cbSSebastian Andrzej Siewior } 2128300dd23SFelipe Balbi 213cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 214cf6d867dSFelipe Balbi { 215cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 216cf6d867dSFelipe Balbi u32 reg; 217cf6d867dSFelipe Balbi 218cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 219cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 220cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 221cf6d867dSFelipe Balbi 222cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 223cf6d867dSFelipe Balbi 224cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 225cf6d867dSFelipe Balbi } 226cf6d867dSFelipe Balbi 22772246da4SFelipe Balbi /** 22872246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 22972246da4SFelipe Balbi * @dwc: pointer to our context structure 23072246da4SFelipe Balbi */ 23157303488SKishon Vijay Abraham I static int dwc3_core_soft_reset(struct dwc3 *dwc) 23272246da4SFelipe Balbi { 23372246da4SFelipe Balbi u32 reg; 234f59dcab1SFelipe Balbi int retries = 1000; 23557303488SKishon Vijay Abraham I int ret; 23672246da4SFelipe Balbi 23751e1e7bcSFelipe Balbi usb_phy_init(dwc->usb2_phy); 23851e1e7bcSFelipe Balbi usb_phy_init(dwc->usb3_phy); 23957303488SKishon Vijay Abraham I ret = phy_init(dwc->usb2_generic_phy); 24057303488SKishon Vijay Abraham I if (ret < 0) 24157303488SKishon Vijay Abraham I return ret; 24257303488SKishon Vijay Abraham I 24357303488SKishon Vijay Abraham I ret = phy_init(dwc->usb3_generic_phy); 24457303488SKishon Vijay Abraham I if (ret < 0) { 24557303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 24657303488SKishon Vijay Abraham I return ret; 24757303488SKishon Vijay Abraham I } 24872246da4SFelipe Balbi 249f59dcab1SFelipe Balbi /* 250f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 251f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 252f59dcab1SFelipe Balbi * host-only mode, then we can return early. 253f59dcab1SFelipe Balbi */ 254c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 25557303488SKishon Vijay Abraham I return 0; 256f59dcab1SFelipe Balbi 257f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 258f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 259f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 260f59dcab1SFelipe Balbi 2614749e0e6SThinh Nguyen /* 2624749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2634749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2644749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2654749e0e6SThinh Nguyen * for 10 times instead. 2664749e0e6SThinh Nguyen */ 2679af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2684749e0e6SThinh Nguyen retries = 10; 2694749e0e6SThinh Nguyen 270f59dcab1SFelipe Balbi do { 271f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 272f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 273fab38333SThinh Nguyen goto done; 274f59dcab1SFelipe Balbi 2759af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2764749e0e6SThinh Nguyen msleep(20); 2774749e0e6SThinh Nguyen else 278f59dcab1SFelipe Balbi udelay(1); 279f59dcab1SFelipe Balbi } while (--retries); 280f59dcab1SFelipe Balbi 28100b42170SBrian Norris phy_exit(dwc->usb3_generic_phy); 28200b42170SBrian Norris phy_exit(dwc->usb2_generic_phy); 28300b42170SBrian Norris 284f59dcab1SFelipe Balbi return -ETIMEDOUT; 285fab38333SThinh Nguyen 286fab38333SThinh Nguyen done: 287fab38333SThinh Nguyen /* 2884749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 2894749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 2904749e0e6SThinh Nguyen * domain (synchronization delay). 291fab38333SThinh Nguyen */ 2929af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 293fab38333SThinh Nguyen msleep(50); 294fab38333SThinh Nguyen 295fab38333SThinh Nguyen return 0; 29672246da4SFelipe Balbi } 29772246da4SFelipe Balbi 298db2be4e9SNikhil Badola /* 299db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 300db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 301db2be4e9SNikhil Badola */ 302bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 303db2be4e9SNikhil Badola { 304db2be4e9SNikhil Badola u32 reg; 305db2be4e9SNikhil Badola u32 dft; 306db2be4e9SNikhil Badola 3079af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 308db2be4e9SNikhil Badola return; 309db2be4e9SNikhil Badola 310bcdb3272SFelipe Balbi if (dwc->fladj == 0) 311db2be4e9SNikhil Badola return; 312db2be4e9SNikhil Badola 313db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 314db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 315a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 316db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 317bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 318db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 319db2be4e9SNikhil Badola } 320db2be4e9SNikhil Badola } 321db2be4e9SNikhil Badola 322c5cc74e8SHeikki Krogerus /** 32372246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 32472246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 32572246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 32672246da4SFelipe Balbi */ 32772246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 32872246da4SFelipe Balbi struct dwc3_event_buffer *evt) 32972246da4SFelipe Balbi { 330d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 33172246da4SFelipe Balbi } 33272246da4SFelipe Balbi 33372246da4SFelipe Balbi /** 3341d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 33572246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 33672246da4SFelipe Balbi * @length: size of the event buffer 33772246da4SFelipe Balbi * 3381d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 33972246da4SFelipe Balbi * otherwise ERR_PTR(errno). 34072246da4SFelipe Balbi */ 34167d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 34267d0b500SFelipe Balbi unsigned length) 34372246da4SFelipe Balbi { 34472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 34572246da4SFelipe Balbi 346380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 34772246da4SFelipe Balbi if (!evt) 34872246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 34972246da4SFelipe Balbi 35072246da4SFelipe Balbi evt->dwc = dwc; 35172246da4SFelipe Balbi evt->length = length; 352d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 353d9fa4c63SJohn Youn if (!evt->cache) 354d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 355d9fa4c63SJohn Youn 356d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 35772246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 358e32672f0SFelipe Balbi if (!evt->buf) 35972246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 36072246da4SFelipe Balbi 36172246da4SFelipe Balbi return evt; 36272246da4SFelipe Balbi } 36372246da4SFelipe Balbi 36472246da4SFelipe Balbi /** 36572246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 36672246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 36772246da4SFelipe Balbi */ 36872246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 36972246da4SFelipe Balbi { 37072246da4SFelipe Balbi struct dwc3_event_buffer *evt; 37172246da4SFelipe Balbi 372696c8b12SFelipe Balbi evt = dwc->ev_buf; 37364b6c8a7SAnton Tikhomirov if (evt) 37472246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 37572246da4SFelipe Balbi } 37672246da4SFelipe Balbi 37772246da4SFelipe Balbi /** 37872246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 3791d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 38072246da4SFelipe Balbi * @length: size of event buffer 38172246da4SFelipe Balbi * 3821d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 38372246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 38472246da4SFelipe Balbi */ 38541ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 38672246da4SFelipe Balbi { 38772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 38872246da4SFelipe Balbi 38972246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 39072246da4SFelipe Balbi if (IS_ERR(evt)) { 39172246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 39272246da4SFelipe Balbi return PTR_ERR(evt); 39372246da4SFelipe Balbi } 394696c8b12SFelipe Balbi dwc->ev_buf = evt; 39572246da4SFelipe Balbi 39672246da4SFelipe Balbi return 0; 39772246da4SFelipe Balbi } 39872246da4SFelipe Balbi 39972246da4SFelipe Balbi /** 40072246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4011d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 40272246da4SFelipe Balbi * 40372246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 40472246da4SFelipe Balbi */ 405f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 40672246da4SFelipe Balbi { 40772246da4SFelipe Balbi struct dwc3_event_buffer *evt; 40872246da4SFelipe Balbi 409696c8b12SFelipe Balbi evt = dwc->ev_buf; 4107acd85e0SPaul Zimmerman evt->lpos = 0; 411660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 41272246da4SFelipe Balbi lower_32_bits(evt->dma)); 413660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 41472246da4SFelipe Balbi upper_32_bits(evt->dma)); 415660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 41668d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 417660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 41872246da4SFelipe Balbi 41972246da4SFelipe Balbi return 0; 42072246da4SFelipe Balbi } 42172246da4SFelipe Balbi 422f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 42372246da4SFelipe Balbi { 42472246da4SFelipe Balbi struct dwc3_event_buffer *evt; 42572246da4SFelipe Balbi 426696c8b12SFelipe Balbi evt = dwc->ev_buf; 4277acd85e0SPaul Zimmerman 4287acd85e0SPaul Zimmerman evt->lpos = 0; 4297acd85e0SPaul Zimmerman 430660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 431660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 432660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 43368d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 434660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 43572246da4SFelipe Balbi } 43672246da4SFelipe Balbi 4370ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 4380ffcaf37SFelipe Balbi { 4390ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4400ffcaf37SFelipe Balbi return 0; 4410ffcaf37SFelipe Balbi 4420ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4430ffcaf37SFelipe Balbi return 0; 4440ffcaf37SFelipe Balbi 4450ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 4460ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 4470ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 4480ffcaf37SFelipe Balbi return -ENOMEM; 4490ffcaf37SFelipe Balbi 4500ffcaf37SFelipe Balbi return 0; 4510ffcaf37SFelipe Balbi } 4520ffcaf37SFelipe Balbi 4530ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 4540ffcaf37SFelipe Balbi { 4550ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 4560ffcaf37SFelipe Balbi u32 param; 4570ffcaf37SFelipe Balbi int ret; 4580ffcaf37SFelipe Balbi 4590ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 4600ffcaf37SFelipe Balbi return 0; 4610ffcaf37SFelipe Balbi 4620ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 4630ffcaf37SFelipe Balbi return 0; 4640ffcaf37SFelipe Balbi 4650ffcaf37SFelipe Balbi /* should never fall here */ 4660ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 4670ffcaf37SFelipe Balbi return 0; 4680ffcaf37SFelipe Balbi 469d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 4700ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 4710ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 472d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 473d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 4740ffcaf37SFelipe Balbi ret = -EFAULT; 4750ffcaf37SFelipe Balbi goto err0; 4760ffcaf37SFelipe Balbi } 4770ffcaf37SFelipe Balbi 4780ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 4790ffcaf37SFelipe Balbi 4800ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 4810ffcaf37SFelipe Balbi 4820ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4830ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 4840ffcaf37SFelipe Balbi if (ret < 0) 4850ffcaf37SFelipe Balbi goto err1; 4860ffcaf37SFelipe Balbi 4870ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 4880ffcaf37SFelipe Balbi 4890ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 4900ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 4910ffcaf37SFelipe Balbi if (ret < 0) 4920ffcaf37SFelipe Balbi goto err1; 4930ffcaf37SFelipe Balbi 4940ffcaf37SFelipe Balbi return 0; 4950ffcaf37SFelipe Balbi 4960ffcaf37SFelipe Balbi err1: 497d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 4980ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 4990ffcaf37SFelipe Balbi 5000ffcaf37SFelipe Balbi err0: 5010ffcaf37SFelipe Balbi return ret; 5020ffcaf37SFelipe Balbi } 5030ffcaf37SFelipe Balbi 5040ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5050ffcaf37SFelipe Balbi { 5060ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5070ffcaf37SFelipe Balbi return; 5080ffcaf37SFelipe Balbi 5090ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5100ffcaf37SFelipe Balbi return; 5110ffcaf37SFelipe Balbi 5120ffcaf37SFelipe Balbi /* should never fall here */ 5130ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5140ffcaf37SFelipe Balbi return; 5150ffcaf37SFelipe Balbi 516d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5170ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5180ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 5190ffcaf37SFelipe Balbi } 5200ffcaf37SFelipe Balbi 521789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 522789451f6SFelipe Balbi { 523789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 524789451f6SFelipe Balbi 52547d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 526789451f6SFelipe Balbi } 527789451f6SFelipe Balbi 52841ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 52926ceca97SFelipe Balbi { 53026ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 53126ceca97SFelipe Balbi 53226ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 53326ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 53426ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 53526ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 53626ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 53726ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 53826ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 53926ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 54026ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 54126ceca97SFelipe Balbi } 54226ceca97SFelipe Balbi 54398112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 54498112041SRoger Quadros { 54598112041SRoger Quadros int intf; 54698112041SRoger Quadros int ret = 0; 54798112041SRoger Quadros 54898112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 54998112041SRoger Quadros 55098112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 55198112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 55298112041SRoger Quadros dwc->hsphy_interface && 55398112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 55498112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 55598112041SRoger Quadros 55698112041SRoger Quadros return ret; 55798112041SRoger Quadros } 55898112041SRoger Quadros 55972246da4SFelipe Balbi /** 560b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 561b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 56288bc9d19SHeikki Krogerus * 56388bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 56488bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 56588bc9d19SHeikki Krogerus * the core in dwc3_core_init. 566b5a65c40SHuang Rui */ 56788bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 568b5a65c40SHuang Rui { 5699ba3aca8SThinh Nguyen unsigned int hw_mode; 570b5a65c40SHuang Rui u32 reg; 571b5a65c40SHuang Rui 5729ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 5739ba3aca8SThinh Nguyen 574b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 575b5a65c40SHuang Rui 5762164a476SHuang Rui /* 5771966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 5781966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 5791966b865SFelipe Balbi */ 5801966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 5811966b865SFelipe Balbi 5821966b865SFelipe Balbi /* 5832164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 5842164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 5852164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 5862164a476SHuang Rui * to '1' after the core initialization is completed. 5872164a476SHuang Rui */ 5889af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 5892164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 5902164a476SHuang Rui 5919ba3aca8SThinh Nguyen /* 5929ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 5939ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 5949ba3aca8SThinh Nguyen * after device soft-reset during initialization. 5959ba3aca8SThinh Nguyen */ 5969ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 5979ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 5989ba3aca8SThinh Nguyen 599b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 600b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 601b5a65c40SHuang Rui 602e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 603e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 604e58dd357SRajesh Bhagat 605df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 606df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 607df31f5b3SHuang Rui 608a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 609a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 610a2a1d0f5SHuang Rui 61141c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 61241c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 61341c06ffdSHuang Rui 614fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 615fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 616fb67afcaSHuang Rui 61714f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 61814f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 61914f4ac53SHuang Rui 6206b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 6216b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 6226b6a0c9aSHuang Rui 623cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 62459acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 62559acfa20SHuang Rui 62600fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 62700fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 62800fe081dSWilliam Wu 629b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 630b5a65c40SHuang Rui 6312164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 6322164a476SHuang Rui 6333e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 6343e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 6353e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 63643cacb03SFelipe Balbi if (dwc->hsphy_interface && 63743cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 6383e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 63988bc9d19SHeikki Krogerus break; 64043cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 64143cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 6423e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 64388bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 6443e10a2ceSHeikki Krogerus } else { 64588bc9d19SHeikki Krogerus /* Relying on default value. */ 64688bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 6473e10a2ceSHeikki Krogerus break; 6483e10a2ceSHeikki Krogerus } 649df561f66SGustavo A. R. Silva fallthrough; 65088bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 6513e10a2ceSHeikki Krogerus default: 6523e10a2ceSHeikki Krogerus break; 6533e10a2ceSHeikki Krogerus } 6543e10a2ceSHeikki Krogerus 65532f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 65632f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 65732f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 65832f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 65932f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 66032f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 66132f2ed86SWilliam Wu break; 66232f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 66332f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 66432f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 66532f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 66632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 66732f2ed86SWilliam Wu break; 66832f2ed86SWilliam Wu default: 66932f2ed86SWilliam Wu break; 67032f2ed86SWilliam Wu } 67132f2ed86SWilliam Wu 6722164a476SHuang Rui /* 6732164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 6742164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 6752164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 6762164a476SHuang Rui * '1' after the core initialization is completed. 6772164a476SHuang Rui */ 6789af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6792164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 6802164a476SHuang Rui 6819ba3aca8SThinh Nguyen /* 6829ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 6839ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6849ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6859ba3aca8SThinh Nguyen */ 6869ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6879ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6889ba3aca8SThinh Nguyen 689cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 6900effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 6910effe0a3SHuang Rui 692ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 693ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 694eafeacf1SThinh Nguyen else 695eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 696ec791d14SJohn Youn 69716199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 69816199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 69916199f33SWilliam Wu 7002164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 70188bc9d19SHeikki Krogerus 70288bc9d19SHeikki Krogerus return 0; 703b5a65c40SHuang Rui } 704b5a65c40SHuang Rui 705c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 706c499ff71SFelipe Balbi { 707c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 708c499ff71SFelipe Balbi 709c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 710c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 711c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 712c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 713c499ff71SFelipe Balbi 714c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 715c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 716c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 717c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 718240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 719fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 720c499ff71SFelipe Balbi } 721c499ff71SFelipe Balbi 7220759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 72372246da4SFelipe Balbi { 72472246da4SFelipe Balbi u32 reg; 72572246da4SFelipe Balbi 7267650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 7279af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 7280759956fSFelipe Balbi 7297650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 7309af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 731690fb371SJohn Youn dwc->revision = reg; 7329af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 733690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 734475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 735690fb371SJohn Youn } else { 7360759956fSFelipe Balbi return false; 7377650bd74SSebastian Andrzej Siewior } 7387650bd74SSebastian Andrzej Siewior 7390759956fSFelipe Balbi return true; 7400e1e5c47SPaul Zimmerman } 7410e1e5c47SPaul Zimmerman 742941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 74372246da4SFelipe Balbi { 74472246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 74572246da4SFelipe Balbi u32 reg; 746c499ff71SFelipe Balbi 7474878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 7483e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 7494878a028SSebastian Andrzej Siewior 750164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 7514878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 75232a4a135SFelipe Balbi /** 75332a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 75432a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 75532a4a135SFelipe Balbi * 75632a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 75732a4a135SFelipe Balbi * configurations. 75832a4a135SFelipe Balbi * 75932a4a135SFelipe Balbi * Refers to: 76032a4a135SFelipe Balbi * 76132a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 76232a4a135SFelipe Balbi * SOF/ITP Mode Used 76332a4a135SFelipe Balbi */ 76432a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 76532a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 7669af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 76732a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 76832a4a135SFelipe Balbi else 7694878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 7704878a028SSebastian Andrzej Siewior break; 7710ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 7720ffcaf37SFelipe Balbi /* enable hibernation here */ 7730ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 7742eac3992SHuang Rui 7752eac3992SHuang Rui /* 7762eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 7772eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 7782eac3992SHuang Rui */ 7792eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 7800ffcaf37SFelipe Balbi break; 7814878a028SSebastian Andrzej Siewior default: 7825eb30cedSFelipe Balbi /* nothing */ 7835eb30cedSFelipe Balbi break; 7844878a028SSebastian Andrzej Siewior } 7854878a028SSebastian Andrzej Siewior 786946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 787946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 7886af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 789946bd579SHuang Rui dwc->is_fpga = true; 790946bd579SHuang Rui } 791946bd579SHuang Rui 7923b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 7933b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 7943b81221aSHuang Rui 7953b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 7963b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 7973b81221aSHuang Rui else 7983b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 7993b81221aSHuang Rui 8009a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 8019a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 8029a5b2f31SHuang Rui 8034878a028SSebastian Andrzej Siewior /* 8044878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 8051d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 8064878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 8071d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 8084878a028SSebastian Andrzej Siewior */ 8099af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 8104878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 8114878a028SSebastian Andrzej Siewior 8124878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 813941f918eSFelipe Balbi } 8144878a028SSebastian Andrzej Siewior 815f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 81698112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 817f54edb53SFelipe Balbi 818d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 819d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 820d9612c2fSPengbo Mu { 821d9612c2fSPengbo Mu struct device *dev = dwc->dev; 822d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 823d9612c2fSPengbo Mu bool incrx_mode; 824d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 825d9612c2fSPengbo Mu u32 incrx_size; 826d9612c2fSPengbo Mu u32 *vals; 827d9612c2fSPengbo Mu u32 cfg; 828d9612c2fSPengbo Mu int ntype; 829d9612c2fSPengbo Mu int ret; 830d9612c2fSPengbo Mu int i; 831d9612c2fSPengbo Mu 832d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 833d9612c2fSPengbo Mu 834d9612c2fSPengbo Mu /* 835d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 836d9612c2fSPengbo Mu * Get the number of value from this property: 837d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 838d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 839d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 840d9612c2fSPengbo Mu */ 841a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 842d9612c2fSPengbo Mu if (ntype <= 0) 843d9612c2fSPengbo Mu return; 844d9612c2fSPengbo Mu 845d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 846d9612c2fSPengbo Mu if (!vals) { 847d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 848d9612c2fSPengbo Mu return; 849d9612c2fSPengbo Mu } 850d9612c2fSPengbo Mu 851d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 852d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 853d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 854d9612c2fSPengbo Mu if (ret) { 85575ecb9ddSAndy Shevchenko kfree(vals); 856d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 857d9612c2fSPengbo Mu return; 858d9612c2fSPengbo Mu } 859d9612c2fSPengbo Mu 860d9612c2fSPengbo Mu incrx_size = *vals; 861d9612c2fSPengbo Mu 862d9612c2fSPengbo Mu if (ntype > 1) { 863d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 864d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 865d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 866d9612c2fSPengbo Mu if (vals[i] > incrx_size) 867d9612c2fSPengbo Mu incrx_size = vals[i]; 868d9612c2fSPengbo Mu } 869d9612c2fSPengbo Mu } else { 870d9612c2fSPengbo Mu /* INCRX burst mode */ 871d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 872d9612c2fSPengbo Mu } 873d9612c2fSPengbo Mu 87475ecb9ddSAndy Shevchenko kfree(vals); 87575ecb9ddSAndy Shevchenko 876d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 877d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 878d9612c2fSPengbo Mu if (incrx_mode) 879d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 880d9612c2fSPengbo Mu switch (incrx_size) { 881d9612c2fSPengbo Mu case 256: 882d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 883d9612c2fSPengbo Mu break; 884d9612c2fSPengbo Mu case 128: 885d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 886d9612c2fSPengbo Mu break; 887d9612c2fSPengbo Mu case 64: 888d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 889d9612c2fSPengbo Mu break; 890d9612c2fSPengbo Mu case 32: 891d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 892d9612c2fSPengbo Mu break; 893d9612c2fSPengbo Mu case 16: 894d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 895d9612c2fSPengbo Mu break; 896d9612c2fSPengbo Mu case 8: 897d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 898d9612c2fSPengbo Mu break; 899d9612c2fSPengbo Mu case 4: 900d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 901d9612c2fSPengbo Mu break; 902d9612c2fSPengbo Mu case 1: 903d9612c2fSPengbo Mu break; 904d9612c2fSPengbo Mu default: 905d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 906d9612c2fSPengbo Mu break; 907d9612c2fSPengbo Mu } 908d9612c2fSPengbo Mu 909d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 910d9612c2fSPengbo Mu } 911d9612c2fSPengbo Mu 912941f918eSFelipe Balbi /** 913941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 914941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 915941f918eSFelipe Balbi * 916941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 917941f918eSFelipe Balbi */ 918941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 919941f918eSFelipe Balbi { 9209ba3aca8SThinh Nguyen unsigned int hw_mode; 921941f918eSFelipe Balbi u32 reg; 922941f918eSFelipe Balbi int ret; 923941f918eSFelipe Balbi 9249ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 9259ba3aca8SThinh Nguyen 926941f918eSFelipe Balbi /* 927941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 928941f918eSFelipe Balbi * out which kernel version a bug was found. 929941f918eSFelipe Balbi */ 930941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 931941f918eSFelipe Balbi 932941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 933941f918eSFelipe Balbi if (ret) 934941f918eSFelipe Balbi goto err0; 935941f918eSFelipe Balbi 93698112041SRoger Quadros if (!dwc->ulpi_ready) { 93798112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 93898112041SRoger Quadros if (ret) 93998112041SRoger Quadros goto err0; 94098112041SRoger Quadros dwc->ulpi_ready = true; 94198112041SRoger Quadros } 94298112041SRoger Quadros 94398112041SRoger Quadros if (!dwc->phys_ready) { 94498112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 94598112041SRoger Quadros if (ret) 94698112041SRoger Quadros goto err0a; 94798112041SRoger Quadros dwc->phys_ready = true; 94898112041SRoger Quadros } 94998112041SRoger Quadros 95098112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 95198112041SRoger Quadros if (ret) 95298112041SRoger Quadros goto err0a; 95398112041SRoger Quadros 9549ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 9559af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 9569ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 9579ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 9589ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 9599ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 9609ba3aca8SThinh Nguyen } 9619ba3aca8SThinh Nguyen 9629ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 9639ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 9649ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 9659ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 9669ba3aca8SThinh Nguyen } 9679ba3aca8SThinh Nguyen } 9689ba3aca8SThinh Nguyen 969941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 970c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 9710ffcaf37SFelipe Balbi 9720ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 9730ffcaf37SFelipe Balbi if (ret) 974c499ff71SFelipe Balbi goto err1; 975c499ff71SFelipe Balbi 976c499ff71SFelipe Balbi /* Adjust Frame Length */ 977c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 978c499ff71SFelipe Balbi 979d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 980d9612c2fSPengbo Mu 981c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 982c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 983c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 984c499ff71SFelipe Balbi if (ret < 0) 9850ffcaf37SFelipe Balbi goto err2; 9860ffcaf37SFelipe Balbi 987c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 988c499ff71SFelipe Balbi if (ret < 0) 989c499ff71SFelipe Balbi goto err3; 990c499ff71SFelipe Balbi 991c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 992c499ff71SFelipe Balbi if (ret) { 993c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 994c499ff71SFelipe Balbi goto err4; 995c499ff71SFelipe Balbi } 996c499ff71SFelipe Balbi 99706281d46SJohn Youn /* 99806281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 99906281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 100006281d46SJohn Youn * DWC_usb31 controller. 100106281d46SJohn Youn */ 10029af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 100306281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 100406281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 100506281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 100606281d46SJohn Youn } 100706281d46SJohn Youn 10089af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 10090bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 101065db7a0cSWilliam Wu 101165db7a0cSWilliam Wu /* 101265db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 101365db7a0cSWilliam Wu * in HS when the device is in the L1 state. 101465db7a0cSWilliam Wu */ 10159af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 10160bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 101765db7a0cSWilliam Wu 101865db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 101965db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 102065db7a0cSWilliam Wu 10217ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 10227ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 10237ba6b09fSNeil Armstrong 10240bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 10250bb39ca1SJohn Youn } 10260bb39ca1SJohn Youn 1027b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1028b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1029b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1030b138e23dSAnurag Kumar Vulisha 1031b138e23dSAnurag Kumar Vulisha /* 1032b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1033b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1034b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1035b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1036b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1037b138e23dSAnurag Kumar Vulisha */ 1038b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1039b138e23dSAnurag Kumar Vulisha 1040b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1041b138e23dSAnurag Kumar Vulisha } 1042b138e23dSAnurag Kumar Vulisha 1043938a5ad1SThinh Nguyen /* 1044938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1045938a5ad1SThinh Nguyen * RX and/or TX threshold. 1046938a5ad1SThinh Nguyen */ 10479af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1048938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1049938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1050938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1051938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1052938a5ad1SThinh Nguyen 1053938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1054938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1055938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1056938a5ad1SThinh Nguyen 1057938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1058938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1059938a5ad1SThinh Nguyen 1060938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1061938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1062938a5ad1SThinh Nguyen 1063938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1064938a5ad1SThinh Nguyen } 1065938a5ad1SThinh Nguyen 1066938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1067938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1068938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1069938a5ad1SThinh Nguyen 1070938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1071938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1072938a5ad1SThinh Nguyen 1073938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1074938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1075938a5ad1SThinh Nguyen 1076938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1077938a5ad1SThinh Nguyen } 1078938a5ad1SThinh Nguyen } 1079938a5ad1SThinh Nguyen 108072246da4SFelipe Balbi return 0; 108172246da4SFelipe Balbi 1082c499ff71SFelipe Balbi err4: 10839b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1084c499ff71SFelipe Balbi 1085c499ff71SFelipe Balbi err3: 10869b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1087c499ff71SFelipe Balbi 10880ffcaf37SFelipe Balbi err2: 1089c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1090c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 10910ffcaf37SFelipe Balbi 10920ffcaf37SFelipe Balbi err1: 10930ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 10940ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 109557303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 109657303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 10970ffcaf37SFelipe Balbi 109898112041SRoger Quadros err0a: 109998112041SRoger Quadros dwc3_ulpi_exit(dwc); 110098112041SRoger Quadros 110172246da4SFelipe Balbi err0: 110272246da4SFelipe Balbi return ret; 110372246da4SFelipe Balbi } 110472246da4SFelipe Balbi 11053c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 110672246da4SFelipe Balbi { 11073c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1108941ea361SFelipe Balbi struct device_node *node = dev->of_node; 11093c9f94acSFelipe Balbi int ret; 111072246da4SFelipe Balbi 11115088b6f5SKishon Vijay Abraham I if (node) { 11125088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 11135088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1114bb674907SFelipe Balbi } else { 1115bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1116bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 11175088b6f5SKishon Vijay Abraham I } 11185088b6f5SKishon Vijay Abraham I 1119d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1120d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1121122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1122122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1123122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1124d105e7f8SFelipe Balbi return ret; 1125122f06e6SKishon Vijay Abraham I } else { 112651e1e7bcSFelipe Balbi dev_err(dev, "no usb2 phy configured\n"); 1127122f06e6SKishon Vijay Abraham I return ret; 1128122f06e6SKishon Vijay Abraham I } 112951e1e7bcSFelipe Balbi } 113051e1e7bcSFelipe Balbi 1131d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1132315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1133122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1134122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1135122f06e6SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 1136d105e7f8SFelipe Balbi return ret; 1137122f06e6SKishon Vijay Abraham I } else { 113851e1e7bcSFelipe Balbi dev_err(dev, "no usb3 phy configured\n"); 1139122f06e6SKishon Vijay Abraham I return ret; 1140122f06e6SKishon Vijay Abraham I } 114151e1e7bcSFelipe Balbi } 114251e1e7bcSFelipe Balbi 114357303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 114457303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 114557303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 114657303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 114757303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 114857303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 114957303488SKishon Vijay Abraham I return ret; 115057303488SKishon Vijay Abraham I } else { 115157303488SKishon Vijay Abraham I dev_err(dev, "no usb2 phy configured\n"); 115257303488SKishon Vijay Abraham I return ret; 115357303488SKishon Vijay Abraham I } 115457303488SKishon Vijay Abraham I } 115557303488SKishon Vijay Abraham I 115657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 115757303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 115857303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 115957303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 116057303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 116157303488SKishon Vijay Abraham I } else if (ret == -EPROBE_DEFER) { 116257303488SKishon Vijay Abraham I return ret; 116357303488SKishon Vijay Abraham I } else { 116457303488SKishon Vijay Abraham I dev_err(dev, "no usb3 phy configured\n"); 116557303488SKishon Vijay Abraham I return ret; 116657303488SKishon Vijay Abraham I } 116757303488SKishon Vijay Abraham I } 116857303488SKishon Vijay Abraham I 11693c9f94acSFelipe Balbi return 0; 11703c9f94acSFelipe Balbi } 11713c9f94acSFelipe Balbi 11725f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 11735f94adfeSFelipe Balbi { 11745f94adfeSFelipe Balbi struct device *dev = dwc->dev; 11755f94adfeSFelipe Balbi int ret; 11765f94adfeSFelipe Balbi 11775f94adfeSFelipe Balbi switch (dwc->dr_mode) { 11785f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 117941ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1180958d1a4cSFelipe Balbi 1181958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1182958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1183958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1184644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1185958d1a4cSFelipe Balbi 11865f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 11875f94adfeSFelipe Balbi if (ret) { 11889522def4SRoger Quadros if (ret != -EPROBE_DEFER) 11895f94adfeSFelipe Balbi dev_err(dev, "failed to initialize gadget\n"); 11905f94adfeSFelipe Balbi return ret; 11915f94adfeSFelipe Balbi } 11925f94adfeSFelipe Balbi break; 11935f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 119441ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1195958d1a4cSFelipe Balbi 1196958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1197958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1198958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1199644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1200958d1a4cSFelipe Balbi 12015f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 12025f94adfeSFelipe Balbi if (ret) { 12039522def4SRoger Quadros if (ret != -EPROBE_DEFER) 12045f94adfeSFelipe Balbi dev_err(dev, "failed to initialize host\n"); 12055f94adfeSFelipe Balbi return ret; 12065f94adfeSFelipe Balbi } 12075f94adfeSFelipe Balbi break; 12085f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 120941ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 12109840354fSRoger Quadros ret = dwc3_drd_init(dwc); 12119840354fSRoger Quadros if (ret) { 12129840354fSRoger Quadros if (ret != -EPROBE_DEFER) 12139840354fSRoger Quadros dev_err(dev, "failed to initialize dual-role\n"); 12149840354fSRoger Quadros return ret; 12159840354fSRoger Quadros } 12165f94adfeSFelipe Balbi break; 12175f94adfeSFelipe Balbi default: 12185f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 12195f94adfeSFelipe Balbi return -EINVAL; 12205f94adfeSFelipe Balbi } 12215f94adfeSFelipe Balbi 12225f94adfeSFelipe Balbi return 0; 12235f94adfeSFelipe Balbi } 12245f94adfeSFelipe Balbi 12255f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 12265f94adfeSFelipe Balbi { 12275f94adfeSFelipe Balbi switch (dwc->dr_mode) { 12285f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 12295f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 12305f94adfeSFelipe Balbi break; 12315f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 12325f94adfeSFelipe Balbi dwc3_host_exit(dwc); 12335f94adfeSFelipe Balbi break; 12345f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 12359840354fSRoger Quadros dwc3_drd_exit(dwc); 12365f94adfeSFelipe Balbi break; 12375f94adfeSFelipe Balbi default: 12385f94adfeSFelipe Balbi /* do nothing */ 12395f94adfeSFelipe Balbi break; 12405f94adfeSFelipe Balbi } 124109ed259fSBin Liu 124209ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 124309ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 12445f94adfeSFelipe Balbi } 12455f94adfeSFelipe Balbi 1246c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 12473c9f94acSFelipe Balbi { 1248c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 124980caf7d2SHuang Rui u8 lpm_nyet_threshold; 12506b6a0c9aSHuang Rui u8 tx_de_emphasis; 1251460d098cSHuang Rui u8 hird_threshold; 1252938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1253938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1254938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1255938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 12563c9f94acSFelipe Balbi 125780caf7d2SHuang Rui /* default to highest possible threshold */ 12588d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 125980caf7d2SHuang Rui 12606b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 12616b6a0c9aSHuang Rui tx_de_emphasis = 1; 12626b6a0c9aSHuang Rui 1263460d098cSHuang Rui /* 1264460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1265460d098cSHuang Rui * threshold value of 0b1100 1266460d098cSHuang Rui */ 1267460d098cSHuang Rui hird_threshold = 12; 1268460d098cSHuang Rui 126963863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 127006e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 127132f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 127263863b98SHeikki Krogerus 1273d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1274d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1275d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1276d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1277d64ff406SArnd Bergmann else 1278d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1279d64ff406SArnd Bergmann 12803d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 128180caf7d2SHuang Rui "snps,has-lpm-erratum"); 12823d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 128380caf7d2SHuang Rui &lpm_nyet_threshold); 12843d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1285460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 12863d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1287460d098cSHuang Rui &hird_threshold); 1288d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1289d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 12903d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1291eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1292022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1293022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1294938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1295938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1296938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1297938a5ad1SThinh Nguyen &rx_max_burst_prd); 1298938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1299938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1300938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1301938a5ad1SThinh Nguyen &tx_max_burst_prd); 13023c9f94acSFelipe Balbi 13033d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 13043b81221aSHuang Rui "snps,disable_scramble_quirk"); 13053d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 13069a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 13073d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1308b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 13093d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1310df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 13113d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1312a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 13133d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 131441c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 13153d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1316fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 13173d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 131814f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 13193d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 132059acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 13213d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 13220effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1323ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1324ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1325729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1326729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1327729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1328729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1329e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1330e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 133116199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 133216199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 133300fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 133400fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 133565db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 133665db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 13377ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 13387ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 13396b6a0c9aSHuang Rui 13403d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 13416b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 13423d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 13436b6a0c9aSHuang Rui &tx_de_emphasis); 13443d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 13453e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 13463d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1347bcdb3272SFelipe Balbi &dwc->fladj); 13483d128919SHeikki Krogerus 134942bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 135042bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 135142bf02ecSRoger Quadros 135280caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 13536b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 135480caf7d2SHuang Rui 135516fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1356460d098cSHuang Rui 1357938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1358938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1359938a5ad1SThinh Nguyen 1360938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1361938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1362938a5ad1SThinh Nguyen 1363cf40b86bSJohn Youn dwc->imod_interval = 0; 1364cf40b86bSJohn Youn } 1365cf40b86bSJohn Youn 1366cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1367cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1368cf40b86bSJohn Youn { 13699af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 13709af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 13719af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1372c5ac6116SFelipe Balbi } 1373c5ac6116SFelipe Balbi 13747ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 13757ac51a12SJohn Youn { 13767ac51a12SJohn Youn struct device *dev = dwc->dev; 1377b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1378b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 13797ac51a12SJohn Youn 1380cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1381cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1382cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1383cf40b86bSJohn Youn dwc->imod_interval = 0; 1384cf40b86bSJohn Youn } 1385cf40b86bSJohn Youn 138628632b44SJohn Youn /* 138728632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 138828632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 138928632b44SJohn Youn * interrupt from being masked while handling events. IMOD 139028632b44SJohn Youn * allows us to work around this issue. Enable it for the 139128632b44SJohn Youn * affected version. 139228632b44SJohn Youn */ 139328632b44SJohn Youn if (!dwc->imod_interval && 13949af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 139528632b44SJohn Youn dwc->imod_interval = 1; 139628632b44SJohn Youn 13977ac51a12SJohn Youn /* Check the maximum_speed parameter */ 13987ac51a12SJohn Youn switch (dwc->maximum_speed) { 13997ac51a12SJohn Youn case USB_SPEED_LOW: 14007ac51a12SJohn Youn case USB_SPEED_FULL: 14017ac51a12SJohn Youn case USB_SPEED_HIGH: 1402e518bdd9SThinh Nguyen break; 14037ac51a12SJohn Youn case USB_SPEED_SUPER: 1404e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1405e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1406e518bdd9SThinh Nguyen break; 14077ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1408e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1409e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1410e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1411e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1412e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 14137ac51a12SJohn Youn break; 14147ac51a12SJohn Youn default: 14157ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 14167ac51a12SJohn Youn dwc->maximum_speed); 1417df561f66SGustavo A. R. Silva fallthrough; 14187ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1419b574ce3eSThinh Nguyen switch (hwparam_gen) { 1420b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 14217ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1422b574ce3eSThinh Nguyen break; 1423b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1424b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1425b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1426b574ce3eSThinh Nguyen else 1427b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1428b574ce3eSThinh Nguyen break; 1429b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1430b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1431b574ce3eSThinh Nguyen break; 1432b574ce3eSThinh Nguyen default: 1433b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1434b574ce3eSThinh Nguyen break; 1435b574ce3eSThinh Nguyen } 14367ac51a12SJohn Youn break; 14377ac51a12SJohn Youn } 14387ac51a12SJohn Youn } 14397ac51a12SJohn Youn 1440c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1441c5ac6116SFelipe Balbi { 1442c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 144344feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1444c5ac6116SFelipe Balbi struct dwc3 *dwc; 1445c5ac6116SFelipe Balbi 1446c5ac6116SFelipe Balbi int ret; 1447c5ac6116SFelipe Balbi 1448c5ac6116SFelipe Balbi void __iomem *regs; 1449c5ac6116SFelipe Balbi 1450c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1451c5ac6116SFelipe Balbi if (!dwc) 1452c5ac6116SFelipe Balbi return -ENOMEM; 1453c5ac6116SFelipe Balbi 1454c5ac6116SFelipe Balbi dwc->dev = dev; 1455c5ac6116SFelipe Balbi 1456c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1457c5ac6116SFelipe Balbi if (!res) { 1458c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1459c5ac6116SFelipe Balbi return -ENODEV; 1460c5ac6116SFelipe Balbi } 1461c5ac6116SFelipe Balbi 1462c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1463c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1464c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1465c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1466c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1467c5ac6116SFelipe Balbi 1468c5ac6116SFelipe Balbi /* 1469c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1470c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1471c5ac6116SFelipe Balbi */ 147244feb8e6SMasahiro Yamada dwc_res = *res; 147344feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 147444feb8e6SMasahiro Yamada 147544feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 147644feb8e6SMasahiro Yamada if (IS_ERR(regs)) 147744feb8e6SMasahiro Yamada return PTR_ERR(regs); 1478c5ac6116SFelipe Balbi 1479c5ac6116SFelipe Balbi dwc->regs = regs; 148044feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1481c5ac6116SFelipe Balbi 1482c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1483c5ac6116SFelipe Balbi 14844a1d042aSJohn Stultz dwc->reset = devm_reset_control_array_get(dev, true, true); 1485fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1486fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1487fe8abf33SMasahiro Yamada 148861527777SHans de Goede if (dev->of_node) { 14890d3a9708SJohn Stultz ret = devm_clk_bulk_get_all(dev, &dwc->clks); 1490fe8abf33SMasahiro Yamada if (ret == -EPROBE_DEFER) 1491fe8abf33SMasahiro Yamada return ret; 1492fe8abf33SMasahiro Yamada /* 149361527777SHans de Goede * Clocks are optional, but new DT platforms should support all 149461527777SHans de Goede * clocks as required by the DT-binding. 1495fe8abf33SMasahiro Yamada */ 14960d3a9708SJohn Stultz if (ret < 0) 1497fe8abf33SMasahiro Yamada dwc->num_clks = 0; 14980d3a9708SJohn Stultz else 14990d3a9708SJohn Stultz dwc->num_clks = ret; 15000d3a9708SJohn Stultz 150161527777SHans de Goede } 1502fe8abf33SMasahiro Yamada 1503fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1504fe8abf33SMasahiro Yamada if (ret) 150503bf32bbSAndrey Smirnov return ret; 1506fe8abf33SMasahiro Yamada 1507240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1508fe8abf33SMasahiro Yamada if (ret) 1509fe8abf33SMasahiro Yamada goto assert_reset; 1510fe8abf33SMasahiro Yamada 1511dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1512dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1513dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1514dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1515dc1b5d9aSEnric Balletbo i Serra } 1516dc1b5d9aSEnric Balletbo i Serra 15176c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 15182917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 15196c89cce0SHeikki Krogerus 152072246da4SFelipe Balbi spin_lock_init(&dwc->lock); 152172246da4SFelipe Balbi 1522fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1523fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1524fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1525802ca850SChanho Park pm_runtime_enable(dev); 152632808237SRoger Quadros ret = pm_runtime_get_sync(dev); 152732808237SRoger Quadros if (ret < 0) 152832808237SRoger Quadros goto err1; 152932808237SRoger Quadros 1530802ca850SChanho Park pm_runtime_forbid(dev); 153172246da4SFelipe Balbi 15323921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 15333921426bSFelipe Balbi if (ret) { 15343921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 15353921426bSFelipe Balbi ret = -ENOMEM; 153632808237SRoger Quadros goto err2; 15373921426bSFelipe Balbi } 15383921426bSFelipe Balbi 15399d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 15409d6173e1SThinh Nguyen if (ret) 15419d6173e1SThinh Nguyen goto err3; 154232a4a135SFelipe Balbi 1543c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1544c499ff71SFelipe Balbi if (ret) 154532808237SRoger Quadros goto err3; 1546c499ff71SFelipe Balbi 154772246da4SFelipe Balbi ret = dwc3_core_init(dwc); 154872246da4SFelipe Balbi if (ret) { 1549408d3ba0SBrian Norris if (ret != -EPROBE_DEFER) 1550408d3ba0SBrian Norris dev_err(dev, "failed to initialize core: %d\n", ret); 155132808237SRoger Quadros goto err4; 155272246da4SFelipe Balbi } 155372246da4SFelipe Balbi 15547ac51a12SJohn Youn dwc3_check_params(dwc); 15552c7f1bd9SJohn Youn 15565f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 15575f94adfeSFelipe Balbi if (ret) 155832808237SRoger Quadros goto err5; 155972246da4SFelipe Balbi 15604e9f3118SDu, Changbin dwc3_debugfs_init(dwc); 1561fc8bb91bSFelipe Balbi pm_runtime_put(dev); 156272246da4SFelipe Balbi 156372246da4SFelipe Balbi return 0; 156472246da4SFelipe Balbi 156532808237SRoger Quadros err5: 1566f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 156703c1fd62SLi Jun 156803c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 156903c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 157003c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 157103c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 157203c1fd62SLi Jun 157303c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 157403c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 157503c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 157603c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 157703c1fd62SLi Jun 157808fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1579f122d33eSFelipe Balbi 158032808237SRoger Quadros err4: 1581c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 158272246da4SFelipe Balbi 158332808237SRoger Quadros err3: 15843921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 15853921426bSFelipe Balbi 158632808237SRoger Quadros err2: 158732808237SRoger Quadros pm_runtime_allow(&pdev->dev); 158832808237SRoger Quadros 158932808237SRoger Quadros err1: 159032808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 159132808237SRoger Quadros pm_runtime_disable(&pdev->dev); 159232808237SRoger Quadros 1593dc1b5d9aSEnric Balletbo i Serra disable_clks: 1594240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1595fe8abf33SMasahiro Yamada assert_reset: 1596fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1597fe8abf33SMasahiro Yamada 159872246da4SFelipe Balbi return ret; 159972246da4SFelipe Balbi } 160072246da4SFelipe Balbi 1601fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 160272246da4SFelipe Balbi { 160372246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 16043da1f6eeSFelipe Balbi 1605fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 160672246da4SFelipe Balbi 1607dc99f16fSFelipe Balbi dwc3_debugfs_exit(dwc); 1608dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 16098ba007a9SKishon Vijay Abraham I 161072246da4SFelipe Balbi dwc3_core_exit(dwc); 161188bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 161272246da4SFelipe Balbi 1613fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1614266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1615266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1616fc8bb91bSFelipe Balbi 1617c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1618c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1619c499ff71SFelipe Balbi 162072246da4SFelipe Balbi return 0; 162172246da4SFelipe Balbi } 162272246da4SFelipe Balbi 1623fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1624fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1625fe8abf33SMasahiro Yamada { 1626fe8abf33SMasahiro Yamada int ret; 1627fe8abf33SMasahiro Yamada 1628fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1629fe8abf33SMasahiro Yamada if (ret) 1630fe8abf33SMasahiro Yamada return ret; 1631fe8abf33SMasahiro Yamada 1632240b65dcSAndrey Smirnov ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks); 1633fe8abf33SMasahiro Yamada if (ret) 1634fe8abf33SMasahiro Yamada goto assert_reset; 1635fe8abf33SMasahiro Yamada 1636fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1637fe8abf33SMasahiro Yamada if (ret) 1638fe8abf33SMasahiro Yamada goto disable_clks; 1639fe8abf33SMasahiro Yamada 1640fe8abf33SMasahiro Yamada return 0; 1641fe8abf33SMasahiro Yamada 1642fe8abf33SMasahiro Yamada disable_clks: 1643240b65dcSAndrey Smirnov clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks); 1644fe8abf33SMasahiro Yamada assert_reset: 1645fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1646fe8abf33SMasahiro Yamada 1647fe8abf33SMasahiro Yamada return ret; 1648fe8abf33SMasahiro Yamada } 1649fe8abf33SMasahiro Yamada 1650c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 16517415f17cSFelipe Balbi { 1652fc8bb91bSFelipe Balbi unsigned long flags; 1653bcb12877SManu Gautam u32 reg; 16547415f17cSFelipe Balbi 1655689bf72cSManu Gautam switch (dwc->current_dr_role) { 1656689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 16570227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 16580227cc84SLi Jun break; 1659fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 16607415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1661fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 166241a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1663689bf72cSManu Gautam dwc3_core_exit(dwc); 166451f5d49aSFelipe Balbi break; 1665689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1666bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1667c4a5153eSManu Gautam dwc3_core_exit(dwc); 1668c4a5153eSManu Gautam break; 1669bcb12877SManu Gautam } 1670bcb12877SManu Gautam 1671bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1672bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1673bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1674bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1675bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1676bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1677bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1678bcb12877SManu Gautam 1679bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1680bcb12877SManu Gautam usleep_range(5000, 6000); 1681bcb12877SManu Gautam } 1682bcb12877SManu Gautam 1683bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1684bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1685bcb12877SManu Gautam break; 1686f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1687f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1688f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1689f09cc79bSRoger Quadros break; 1690f09cc79bSRoger Quadros 1691f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1692f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1693f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1694f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 169541a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1696f09cc79bSRoger Quadros } 1697f09cc79bSRoger Quadros 1698f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1699f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1700f09cc79bSRoger Quadros break; 17017415f17cSFelipe Balbi default: 170251f5d49aSFelipe Balbi /* do nothing */ 17037415f17cSFelipe Balbi break; 17047415f17cSFelipe Balbi } 17057415f17cSFelipe Balbi 1706fc8bb91bSFelipe Balbi return 0; 1707fc8bb91bSFelipe Balbi } 1708fc8bb91bSFelipe Balbi 1709c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1710fc8bb91bSFelipe Balbi { 1711fc8bb91bSFelipe Balbi unsigned long flags; 1712fc8bb91bSFelipe Balbi int ret; 1713bcb12877SManu Gautam u32 reg; 1714fc8bb91bSFelipe Balbi 1715689bf72cSManu Gautam switch (dwc->current_dr_role) { 1716689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1717fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1718fc8bb91bSFelipe Balbi if (ret) 1719fc8bb91bSFelipe Balbi return ret; 1720fc8bb91bSFelipe Balbi 17217d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1722fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1723fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1724fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1725689bf72cSManu Gautam break; 1726689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1727c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1728fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1729c4a5153eSManu Gautam if (ret) 1730c4a5153eSManu Gautam return ret; 17317d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1732bcb12877SManu Gautam break; 1733c4a5153eSManu Gautam } 1734bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1735bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1736bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1737bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1738bcb12877SManu Gautam 1739bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1740bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1741bcb12877SManu Gautam 1742bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1743bcb12877SManu Gautam 1744bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1745bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1746c4a5153eSManu Gautam break; 1747f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1748f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1749f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1750f09cc79bSRoger Quadros break; 1751f09cc79bSRoger Quadros 1752f09cc79bSRoger Quadros ret = dwc3_core_init(dwc); 1753f09cc79bSRoger Quadros if (ret) 1754f09cc79bSRoger Quadros return ret; 1755f09cc79bSRoger Quadros 1756f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1757f09cc79bSRoger Quadros 1758f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1759f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1760f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1761f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1762f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1763f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1764f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1765f09cc79bSRoger Quadros } 1766f09cc79bSRoger Quadros 1767f09cc79bSRoger Quadros break; 1768fc8bb91bSFelipe Balbi default: 1769fc8bb91bSFelipe Balbi /* do nothing */ 1770fc8bb91bSFelipe Balbi break; 1771fc8bb91bSFelipe Balbi } 1772fc8bb91bSFelipe Balbi 1773fc8bb91bSFelipe Balbi return 0; 1774fc8bb91bSFelipe Balbi } 1775fc8bb91bSFelipe Balbi 1776fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1777fc8bb91bSFelipe Balbi { 1778689bf72cSManu Gautam switch (dwc->current_dr_role) { 1779c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1780fc8bb91bSFelipe Balbi if (dwc->connected) 1781fc8bb91bSFelipe Balbi return -EBUSY; 1782fc8bb91bSFelipe Balbi break; 1783c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1784fc8bb91bSFelipe Balbi default: 1785fc8bb91bSFelipe Balbi /* do nothing */ 1786fc8bb91bSFelipe Balbi break; 1787fc8bb91bSFelipe Balbi } 1788fc8bb91bSFelipe Balbi 1789fc8bb91bSFelipe Balbi return 0; 1790fc8bb91bSFelipe Balbi } 1791fc8bb91bSFelipe Balbi 1792fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 1793fc8bb91bSFelipe Balbi { 1794fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1795fc8bb91bSFelipe Balbi int ret; 1796fc8bb91bSFelipe Balbi 1797fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1798fc8bb91bSFelipe Balbi return -EBUSY; 1799fc8bb91bSFelipe Balbi 1800c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 1801fc8bb91bSFelipe Balbi if (ret) 1802fc8bb91bSFelipe Balbi return ret; 1803fc8bb91bSFelipe Balbi 1804fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 1805fc8bb91bSFelipe Balbi 1806fc8bb91bSFelipe Balbi return 0; 1807fc8bb91bSFelipe Balbi } 1808fc8bb91bSFelipe Balbi 1809fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 1810fc8bb91bSFelipe Balbi { 1811fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1812fc8bb91bSFelipe Balbi int ret; 1813fc8bb91bSFelipe Balbi 1814fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 1815fc8bb91bSFelipe Balbi 1816c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 1817fc8bb91bSFelipe Balbi if (ret) 1818fc8bb91bSFelipe Balbi return ret; 1819fc8bb91bSFelipe Balbi 1820689bf72cSManu Gautam switch (dwc->current_dr_role) { 1821689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1822fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 1823fc8bb91bSFelipe Balbi break; 1824689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1825fc8bb91bSFelipe Balbi default: 1826fc8bb91bSFelipe Balbi /* do nothing */ 1827fc8bb91bSFelipe Balbi break; 1828fc8bb91bSFelipe Balbi } 1829fc8bb91bSFelipe Balbi 1830fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1831fc8bb91bSFelipe Balbi 1832fc8bb91bSFelipe Balbi return 0; 1833fc8bb91bSFelipe Balbi } 1834fc8bb91bSFelipe Balbi 1835fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 1836fc8bb91bSFelipe Balbi { 1837fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1838fc8bb91bSFelipe Balbi 1839689bf72cSManu Gautam switch (dwc->current_dr_role) { 1840689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1841fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 1842fc8bb91bSFelipe Balbi return -EBUSY; 1843fc8bb91bSFelipe Balbi break; 1844689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1845fc8bb91bSFelipe Balbi default: 1846fc8bb91bSFelipe Balbi /* do nothing */ 1847fc8bb91bSFelipe Balbi break; 1848fc8bb91bSFelipe Balbi } 1849fc8bb91bSFelipe Balbi 1850fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 1851fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 1852fc8bb91bSFelipe Balbi 1853fc8bb91bSFelipe Balbi return 0; 1854fc8bb91bSFelipe Balbi } 1855fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 1856fc8bb91bSFelipe Balbi 1857fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 1858fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 1859fc8bb91bSFelipe Balbi { 1860fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 1861fc8bb91bSFelipe Balbi int ret; 1862fc8bb91bSFelipe Balbi 1863c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 1864fc8bb91bSFelipe Balbi if (ret) 1865fc8bb91bSFelipe Balbi return ret; 1866fc8bb91bSFelipe Balbi 18676344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 18686344475fSSekhar Nori 18697415f17cSFelipe Balbi return 0; 18707415f17cSFelipe Balbi } 18717415f17cSFelipe Balbi 18727415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 18737415f17cSFelipe Balbi { 18747415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 187557303488SKishon Vijay Abraham I int ret; 18767415f17cSFelipe Balbi 18776344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 18786344475fSSekhar Nori 1879c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 188051f5d49aSFelipe Balbi if (ret) 18815c4ad318SFelipe Balbi return ret; 18825c4ad318SFelipe Balbi 18837415f17cSFelipe Balbi pm_runtime_disable(dev); 18847415f17cSFelipe Balbi pm_runtime_set_active(dev); 18857415f17cSFelipe Balbi pm_runtime_enable(dev); 18867415f17cSFelipe Balbi 18877415f17cSFelipe Balbi return 0; 18887415f17cSFelipe Balbi } 18897f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 18907415f17cSFelipe Balbi 18917415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 18927415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 1893fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 1894fc8bb91bSFelipe Balbi dwc3_runtime_idle) 18957415f17cSFelipe Balbi }; 18967415f17cSFelipe Balbi 18975088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 18985088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 18995088b6f5SKishon Vijay Abraham I { 190022a5aa17SFelipe Balbi .compatible = "snps,dwc3" 190122a5aa17SFelipe Balbi }, 190222a5aa17SFelipe Balbi { 19035088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 19045088b6f5SKishon Vijay Abraham I }, 19055088b6f5SKishon Vijay Abraham I { }, 19065088b6f5SKishon Vijay Abraham I }; 19075088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 19085088b6f5SKishon Vijay Abraham I #endif 19095088b6f5SKishon Vijay Abraham I 1910404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 1911404905a6SHeikki Krogerus 1912404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 1913404905a6SHeikki Krogerus 1914404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 1915404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 1916404905a6SHeikki Krogerus { }, 1917404905a6SHeikki Krogerus }; 1918404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 1919404905a6SHeikki Krogerus #endif 1920404905a6SHeikki Krogerus 192172246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 192272246da4SFelipe Balbi .probe = dwc3_probe, 19237690417dSBill Pemberton .remove = dwc3_remove, 192472246da4SFelipe Balbi .driver = { 192572246da4SFelipe Balbi .name = "dwc3", 19265088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 1927404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 19287f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 192972246da4SFelipe Balbi }, 193072246da4SFelipe Balbi }; 193172246da4SFelipe Balbi 1932b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 1933b1116dccSTobias Klauser 19347ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 193572246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 19365945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 193772246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 1938