15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 2cbdc0f54SMauro Carvalho Chehab /* 372246da4SFelipe Balbi * core.c - DesignWare USB3 DRD Controller Core file 472246da4SFelipe Balbi * 510623b87SAlexander A. Klimov * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 672246da4SFelipe Balbi * 772246da4SFelipe Balbi * Authors: Felipe Balbi <balbi@ti.com>, 872246da4SFelipe Balbi * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 972246da4SFelipe Balbi */ 1072246da4SFelipe Balbi 11fe8abf33SMasahiro Yamada #include <linux/clk.h> 12fa0ea13eSFelipe Balbi #include <linux/version.h> 13a72e658bSFelipe Balbi #include <linux/module.h> 1472246da4SFelipe Balbi #include <linux/kernel.h> 1572246da4SFelipe Balbi #include <linux/slab.h> 1672246da4SFelipe Balbi #include <linux/spinlock.h> 1772246da4SFelipe Balbi #include <linux/platform_device.h> 1872246da4SFelipe Balbi #include <linux/pm_runtime.h> 1972246da4SFelipe Balbi #include <linux/interrupt.h> 2072246da4SFelipe Balbi #include <linux/ioport.h> 2172246da4SFelipe Balbi #include <linux/io.h> 2272246da4SFelipe Balbi #include <linux/list.h> 2372246da4SFelipe Balbi #include <linux/delay.h> 2472246da4SFelipe Balbi #include <linux/dma-mapping.h> 25457e84b6SFelipe Balbi #include <linux/of.h> 26404905a6SHeikki Krogerus #include <linux/acpi.h> 276344475fSSekhar Nori #include <linux/pinctrl/consumer.h> 28fe8abf33SMasahiro Yamada #include <linux/reset.h> 297bee3188SBalaji Prakash J #include <linux/bitfield.h> 3072246da4SFelipe Balbi 3172246da4SFelipe Balbi #include <linux/usb/ch9.h> 3272246da4SFelipe Balbi #include <linux/usb/gadget.h> 33f7e846f0SFelipe Balbi #include <linux/usb/of.h> 34a45c82b8SRuchika Kharwar #include <linux/usb/otg.h> 3572246da4SFelipe Balbi 3672246da4SFelipe Balbi #include "core.h" 3772246da4SFelipe Balbi #include "gadget.h" 3872246da4SFelipe Balbi #include "io.h" 3972246da4SFelipe Balbi 4072246da4SFelipe Balbi #include "debug.h" 4172246da4SFelipe Balbi 42fc8bb91bSFelipe Balbi #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ 438300dd23SFelipe Balbi 449d6173e1SThinh Nguyen /** 459d6173e1SThinh Nguyen * dwc3_get_dr_mode - Validates and sets dr_mode 469d6173e1SThinh Nguyen * @dwc: pointer to our context structure 479d6173e1SThinh Nguyen */ 489d6173e1SThinh Nguyen static int dwc3_get_dr_mode(struct dwc3 *dwc) 499d6173e1SThinh Nguyen { 509d6173e1SThinh Nguyen enum usb_dr_mode mode; 519d6173e1SThinh Nguyen struct device *dev = dwc->dev; 529d6173e1SThinh Nguyen unsigned int hw_mode; 539d6173e1SThinh Nguyen 549d6173e1SThinh Nguyen if (dwc->dr_mode == USB_DR_MODE_UNKNOWN) 559d6173e1SThinh Nguyen dwc->dr_mode = USB_DR_MODE_OTG; 569d6173e1SThinh Nguyen 579d6173e1SThinh Nguyen mode = dwc->dr_mode; 589d6173e1SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 599d6173e1SThinh Nguyen 609d6173e1SThinh Nguyen switch (hw_mode) { 619d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_GADGET: 629d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) { 639d6173e1SThinh Nguyen dev_err(dev, 649d6173e1SThinh Nguyen "Controller does not support host mode.\n"); 659d6173e1SThinh Nguyen return -EINVAL; 669d6173e1SThinh Nguyen } 679d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 689d6173e1SThinh Nguyen break; 699d6173e1SThinh Nguyen case DWC3_GHWPARAMS0_MODE_HOST: 709d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) { 719d6173e1SThinh Nguyen dev_err(dev, 729d6173e1SThinh Nguyen "Controller does not support device mode.\n"); 739d6173e1SThinh Nguyen return -EINVAL; 749d6173e1SThinh Nguyen } 759d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 769d6173e1SThinh Nguyen break; 779d6173e1SThinh Nguyen default: 789d6173e1SThinh Nguyen if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) 799d6173e1SThinh Nguyen mode = USB_DR_MODE_HOST; 809d6173e1SThinh Nguyen else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) 819d6173e1SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 82a7700468SThinh Nguyen 83a7700468SThinh Nguyen /* 8489a9cc47SThinh Nguyen * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG 8589a9cc47SThinh Nguyen * mode. If the controller supports DRD but the dr_mode is not 8689a9cc47SThinh Nguyen * specified or set to OTG, then set the mode to peripheral. 87a7700468SThinh Nguyen */ 8889a9cc47SThinh Nguyen if (mode == USB_DR_MODE_OTG && 898bb14308SThinh Nguyen (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || 908bb14308SThinh Nguyen !device_property_read_bool(dwc->dev, "usb-role-switch")) && 919af21dd6SThinh Nguyen !DWC3_VER_IS_PRIOR(DWC3, 330A)) 92a7700468SThinh Nguyen mode = USB_DR_MODE_PERIPHERAL; 939d6173e1SThinh Nguyen } 949d6173e1SThinh Nguyen 959d6173e1SThinh Nguyen if (mode != dwc->dr_mode) { 969d6173e1SThinh Nguyen dev_warn(dev, 979d6173e1SThinh Nguyen "Configuration mismatch. dr_mode forced to %s\n", 989d6173e1SThinh Nguyen mode == USB_DR_MODE_HOST ? "host" : "gadget"); 999d6173e1SThinh Nguyen 1009d6173e1SThinh Nguyen dwc->dr_mode = mode; 1019d6173e1SThinh Nguyen } 1029d6173e1SThinh Nguyen 1039d6173e1SThinh Nguyen return 0; 1049d6173e1SThinh Nguyen } 1059d6173e1SThinh Nguyen 106f09cc79bSRoger Quadros void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) 1073140e8cbSSebastian Andrzej Siewior { 1083140e8cbSSebastian Andrzej Siewior u32 reg; 1093140e8cbSSebastian Andrzej Siewior 1103140e8cbSSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 1113140e8cbSSebastian Andrzej Siewior reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); 1123140e8cbSSebastian Andrzej Siewior reg |= DWC3_GCTL_PRTCAPDIR(mode); 1133140e8cbSSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 114c4a5153eSManu Gautam 115c4a5153eSManu Gautam dwc->current_dr_role = mode; 11641ce1456SRoger Quadros } 1176b3261a2SRoger Quadros 11841ce1456SRoger Quadros static void __dwc3_set_mode(struct work_struct *work) 11941ce1456SRoger Quadros { 12041ce1456SRoger Quadros struct dwc3 *dwc = work_to_dwc(work); 12141ce1456SRoger Quadros unsigned long flags; 12241ce1456SRoger Quadros int ret; 123f580170fSYu Chen u32 reg; 12441ce1456SRoger Quadros 125f88359e1SYu Chen mutex_lock(&dwc->mutex); 126f88359e1SYu Chen 127c2cd3452SMartin Kepplinger pm_runtime_get_sync(dwc->dev); 128c2cd3452SMartin Kepplinger 129f09cc79bSRoger Quadros if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG) 130f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 131f09cc79bSRoger Quadros 13241ce1456SRoger Quadros if (!dwc->desired_dr_role) 133c2cd3452SMartin Kepplinger goto out; 13441ce1456SRoger Quadros 13541ce1456SRoger Quadros if (dwc->desired_dr_role == dwc->current_dr_role) 136c2cd3452SMartin Kepplinger goto out; 13741ce1456SRoger Quadros 138f09cc79bSRoger Quadros if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev) 139c2cd3452SMartin Kepplinger goto out; 14041ce1456SRoger Quadros 14141ce1456SRoger Quadros switch (dwc->current_dr_role) { 14241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 14341ce1456SRoger Quadros dwc3_host_exit(dwc); 14441ce1456SRoger Quadros break; 14541ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 14641ce1456SRoger Quadros dwc3_gadget_exit(dwc); 14741ce1456SRoger Quadros dwc3_event_buffers_cleanup(dwc); 14841ce1456SRoger Quadros break; 149f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 150f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 151f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 152f09cc79bSRoger Quadros dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE; 153f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 154f09cc79bSRoger Quadros dwc3_otg_update(dwc, 1); 155f09cc79bSRoger Quadros break; 15641ce1456SRoger Quadros default: 15741ce1456SRoger Quadros break; 15841ce1456SRoger Quadros } 15941ce1456SRoger Quadros 160f88359e1SYu Chen /* For DRD host or device mode only */ 161f88359e1SYu Chen if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) { 162f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 163f88359e1SYu Chen reg |= DWC3_GCTL_CORESOFTRESET; 164f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 165f88359e1SYu Chen 166f88359e1SYu Chen /* 167f88359e1SYu Chen * Wait for internal clocks to synchronized. DWC_usb31 and 168f88359e1SYu Chen * DWC_usb32 may need at least 50ms (less for DWC_usb3). To 169f88359e1SYu Chen * keep it consistent across different IPs, let's wait up to 170f88359e1SYu Chen * 100ms before clearing GCTL.CORESOFTRESET. 171f88359e1SYu Chen */ 172f88359e1SYu Chen msleep(100); 173f88359e1SYu Chen 174f88359e1SYu Chen reg = dwc3_readl(dwc->regs, DWC3_GCTL); 175f88359e1SYu Chen reg &= ~DWC3_GCTL_CORESOFTRESET; 176f88359e1SYu Chen dwc3_writel(dwc->regs, DWC3_GCTL, reg); 177f88359e1SYu Chen } 178f88359e1SYu Chen 17941ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 18041ce1456SRoger Quadros 18141ce1456SRoger Quadros dwc3_set_prtcap(dwc, dwc->desired_dr_role); 18241ce1456SRoger Quadros 18341ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 18441ce1456SRoger Quadros 18541ce1456SRoger Quadros switch (dwc->desired_dr_role) { 18641ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_HOST: 18741ce1456SRoger Quadros ret = dwc3_host_init(dwc); 188958d1a4cSFelipe Balbi if (ret) { 18941ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize host\n"); 190958d1a4cSFelipe Balbi } else { 191958d1a4cSFelipe Balbi if (dwc->usb2_phy) 192958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 193958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 194644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 195f580170fSYu Chen if (dwc->dis_split_quirk) { 196f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 197f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 198f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 199f580170fSYu Chen } 200958d1a4cSFelipe Balbi } 20141ce1456SRoger Quadros break; 20241ce1456SRoger Quadros case DWC3_GCTL_PRTCAP_DEVICE: 203f88359e1SYu Chen dwc3_core_soft_reset(dwc); 204f88359e1SYu Chen 20541ce1456SRoger Quadros dwc3_event_buffers_setup(dwc); 206958d1a4cSFelipe Balbi 207958d1a4cSFelipe Balbi if (dwc->usb2_phy) 208958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 209958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 210644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 211958d1a4cSFelipe Balbi 21241ce1456SRoger Quadros ret = dwc3_gadget_init(dwc); 21341ce1456SRoger Quadros if (ret) 21441ce1456SRoger Quadros dev_err(dwc->dev, "failed to initialize peripheral\n"); 21541ce1456SRoger Quadros break; 216f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 217f09cc79bSRoger Quadros dwc3_otg_init(dwc); 218f09cc79bSRoger Quadros dwc3_otg_update(dwc, 0); 219f09cc79bSRoger Quadros break; 22041ce1456SRoger Quadros default: 22141ce1456SRoger Quadros break; 22241ce1456SRoger Quadros } 223f09cc79bSRoger Quadros 224c2cd3452SMartin Kepplinger out: 225c2cd3452SMartin Kepplinger pm_runtime_mark_last_busy(dwc->dev); 226c2cd3452SMartin Kepplinger pm_runtime_put_autosuspend(dwc->dev); 227f88359e1SYu Chen mutex_unlock(&dwc->mutex); 22841ce1456SRoger Quadros } 22941ce1456SRoger Quadros 23041ce1456SRoger Quadros void dwc3_set_mode(struct dwc3 *dwc, u32 mode) 23141ce1456SRoger Quadros { 23241ce1456SRoger Quadros unsigned long flags; 23341ce1456SRoger Quadros 234dc336b19SLi Jun if (dwc->dr_mode != USB_DR_MODE_OTG) 235dc336b19SLi Jun return; 236dc336b19SLi Jun 23741ce1456SRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 23841ce1456SRoger Quadros dwc->desired_dr_role = mode; 23941ce1456SRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 24041ce1456SRoger Quadros 241084a804eSRoger Quadros queue_work(system_freezable_wq, &dwc->drd_work); 2423140e8cbSSebastian Andrzej Siewior } 2438300dd23SFelipe Balbi 244cf6d867dSFelipe Balbi u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) 245cf6d867dSFelipe Balbi { 246cf6d867dSFelipe Balbi struct dwc3 *dwc = dep->dwc; 247cf6d867dSFelipe Balbi u32 reg; 248cf6d867dSFelipe Balbi 249cf6d867dSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE, 250cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_NUM(dep->number) | 251cf6d867dSFelipe Balbi DWC3_GDBGFIFOSPACE_TYPE(type)); 252cf6d867dSFelipe Balbi 253cf6d867dSFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE); 254cf6d867dSFelipe Balbi 255cf6d867dSFelipe Balbi return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg); 256cf6d867dSFelipe Balbi } 257cf6d867dSFelipe Balbi 25872246da4SFelipe Balbi /** 25972246da4SFelipe Balbi * dwc3_core_soft_reset - Issues core soft reset and PHY reset 26072246da4SFelipe Balbi * @dwc: pointer to our context structure 26172246da4SFelipe Balbi */ 262*0066472dSWesley Cheng int dwc3_core_soft_reset(struct dwc3 *dwc) 26372246da4SFelipe Balbi { 26472246da4SFelipe Balbi u32 reg; 265f59dcab1SFelipe Balbi int retries = 1000; 26672246da4SFelipe Balbi 267f59dcab1SFelipe Balbi /* 268f59dcab1SFelipe Balbi * We're resetting only the device side because, if we're in host mode, 269f59dcab1SFelipe Balbi * XHCI driver will reset the host block. If dwc3 was configured for 270f59dcab1SFelipe Balbi * host-only mode, then we can return early. 271f59dcab1SFelipe Balbi */ 272c4a5153eSManu Gautam if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) 27357303488SKishon Vijay Abraham I return 0; 274f59dcab1SFelipe Balbi 275f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 276f59dcab1SFelipe Balbi reg |= DWC3_DCTL_CSFTRST; 277f59dcab1SFelipe Balbi dwc3_writel(dwc->regs, DWC3_DCTL, reg); 278f59dcab1SFelipe Balbi 2794749e0e6SThinh Nguyen /* 2804749e0e6SThinh Nguyen * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit 2814749e0e6SThinh Nguyen * is cleared only after all the clocks are synchronized. This can 2824749e0e6SThinh Nguyen * take a little more than 50ms. Set the polling rate at 20ms 2834749e0e6SThinh Nguyen * for 10 times instead. 2844749e0e6SThinh Nguyen */ 2859af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2864749e0e6SThinh Nguyen retries = 10; 2874749e0e6SThinh Nguyen 288f59dcab1SFelipe Balbi do { 289f59dcab1SFelipe Balbi reg = dwc3_readl(dwc->regs, DWC3_DCTL); 290f59dcab1SFelipe Balbi if (!(reg & DWC3_DCTL_CSFTRST)) 291fab38333SThinh Nguyen goto done; 292f59dcab1SFelipe Balbi 2939af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32)) 2944749e0e6SThinh Nguyen msleep(20); 2954749e0e6SThinh Nguyen else 296f59dcab1SFelipe Balbi udelay(1); 297f59dcab1SFelipe Balbi } while (--retries); 298f59dcab1SFelipe Balbi 299f59dcab1SFelipe Balbi return -ETIMEDOUT; 300fab38333SThinh Nguyen 301fab38333SThinh Nguyen done: 302fab38333SThinh Nguyen /* 3034749e0e6SThinh Nguyen * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit 3044749e0e6SThinh Nguyen * is cleared, we must wait at least 50ms before accessing the PHY 3054749e0e6SThinh Nguyen * domain (synchronization delay). 306fab38333SThinh Nguyen */ 3079af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A)) 308fab38333SThinh Nguyen msleep(50); 309fab38333SThinh Nguyen 310fab38333SThinh Nguyen return 0; 31172246da4SFelipe Balbi } 31272246da4SFelipe Balbi 313db2be4e9SNikhil Badola /* 314db2be4e9SNikhil Badola * dwc3_frame_length_adjustment - Adjusts frame length if required 315db2be4e9SNikhil Badola * @dwc3: Pointer to our controller context structure 316db2be4e9SNikhil Badola */ 317bcdb3272SFelipe Balbi static void dwc3_frame_length_adjustment(struct dwc3 *dwc) 318db2be4e9SNikhil Badola { 319db2be4e9SNikhil Badola u32 reg; 320db2be4e9SNikhil Badola u32 dft; 321db2be4e9SNikhil Badola 3229af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 323db2be4e9SNikhil Badola return; 324db2be4e9SNikhil Badola 325bcdb3272SFelipe Balbi if (dwc->fladj == 0) 326db2be4e9SNikhil Badola return; 327db2be4e9SNikhil Badola 328db2be4e9SNikhil Badola reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 329db2be4e9SNikhil Badola dft = reg & DWC3_GFLADJ_30MHZ_MASK; 330a7d9874cSYinbo Zhu if (dft != dwc->fladj) { 331db2be4e9SNikhil Badola reg &= ~DWC3_GFLADJ_30MHZ_MASK; 332bcdb3272SFelipe Balbi reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj; 333db2be4e9SNikhil Badola dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 334db2be4e9SNikhil Badola } 335db2be4e9SNikhil Badola } 336db2be4e9SNikhil Badola 337c5cc74e8SHeikki Krogerus /** 3387bee3188SBalaji Prakash J * dwc3_ref_clk_period - Reference clock period configuration 3397bee3188SBalaji Prakash J * Default reference clock period depends on hardware 3407bee3188SBalaji Prakash J * configuration. For systems with reference clock that differs 3417bee3188SBalaji Prakash J * from the default, this will set clock period in DWC3_GUCTL 3427bee3188SBalaji Prakash J * register. 3437bee3188SBalaji Prakash J * @dwc: Pointer to our controller context structure 3447bee3188SBalaji Prakash J * @ref_clk_per: reference clock period in ns 3457bee3188SBalaji Prakash J */ 3467bee3188SBalaji Prakash J static void dwc3_ref_clk_period(struct dwc3 *dwc) 3477bee3188SBalaji Prakash J { 3485114c3eeSSean Anderson unsigned long period; 349596c8785SSean Anderson unsigned long fladj; 350596c8785SSean Anderson unsigned long decr; 3515114c3eeSSean Anderson unsigned long rate; 3527bee3188SBalaji Prakash J u32 reg; 3537bee3188SBalaji Prakash J 3545114c3eeSSean Anderson if (dwc->ref_clk) { 3555114c3eeSSean Anderson rate = clk_get_rate(dwc->ref_clk); 3565114c3eeSSean Anderson if (!rate) 3577bee3188SBalaji Prakash J return; 3585114c3eeSSean Anderson period = NSEC_PER_SEC / rate; 3595114c3eeSSean Anderson } else if (dwc->ref_clk_per) { 3605114c3eeSSean Anderson period = dwc->ref_clk_per; 361596c8785SSean Anderson rate = NSEC_PER_SEC / period; 3625114c3eeSSean Anderson } else { 3635114c3eeSSean Anderson return; 3645114c3eeSSean Anderson } 3657bee3188SBalaji Prakash J 3667bee3188SBalaji Prakash J reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 3677bee3188SBalaji Prakash J reg &= ~DWC3_GUCTL_REFCLKPER_MASK; 3685114c3eeSSean Anderson reg |= FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period); 3697bee3188SBalaji Prakash J dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 3707bee3188SBalaji Prakash J 371596c8785SSean Anderson if (DWC3_VER_IS_PRIOR(DWC3, 250A)) 372596c8785SSean Anderson return; 373596c8785SSean Anderson 374596c8785SSean Anderson /* 375596c8785SSean Anderson * The calculation below is 376596c8785SSean Anderson * 377596c8785SSean Anderson * 125000 * (NSEC_PER_SEC / (rate * period) - 1) 378596c8785SSean Anderson * 379596c8785SSean Anderson * but rearranged for fixed-point arithmetic. The division must be 380596c8785SSean Anderson * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and 381596c8785SSean Anderson * neither does rate * period). 382596c8785SSean Anderson * 383596c8785SSean Anderson * Note that rate * period ~= NSEC_PER_SECOND, minus the number of 384596c8785SSean Anderson * nanoseconds of error caused by the truncation which happened during 385596c8785SSean Anderson * the division when calculating rate or period (whichever one was 386596c8785SSean Anderson * derived from the other). We first calculate the relative error, then 387596c8785SSean Anderson * scale it to units of 8 ppm. 388596c8785SSean Anderson */ 389596c8785SSean Anderson fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period); 390596c8785SSean Anderson fladj -= 125000; 391596c8785SSean Anderson 392596c8785SSean Anderson /* 393596c8785SSean Anderson * The documented 240MHz constant is scaled by 2 to get PLS1 as well. 394596c8785SSean Anderson */ 395596c8785SSean Anderson decr = 480000000 / rate; 396596c8785SSean Anderson 397596c8785SSean Anderson reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); 398596c8785SSean Anderson reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK 399596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR 400596c8785SSean Anderson & ~DWC3_GFLADJ_240MHZDECR_PLS1; 401596c8785SSean Anderson reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj) 402596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1) 403596c8785SSean Anderson | FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1); 404596c8785SSean Anderson dwc3_writel(dwc->regs, DWC3_GFLADJ, reg); 405596c8785SSean Anderson } 4067bee3188SBalaji Prakash J 4077bee3188SBalaji Prakash J /** 40872246da4SFelipe Balbi * dwc3_free_one_event_buffer - Frees one event buffer 40972246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 41072246da4SFelipe Balbi * @evt: Pointer to event buffer to be freed 41172246da4SFelipe Balbi */ 41272246da4SFelipe Balbi static void dwc3_free_one_event_buffer(struct dwc3 *dwc, 41372246da4SFelipe Balbi struct dwc3_event_buffer *evt) 41472246da4SFelipe Balbi { 415d64ff406SArnd Bergmann dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); 41672246da4SFelipe Balbi } 41772246da4SFelipe Balbi 41872246da4SFelipe Balbi /** 4191d046793SPaul Zimmerman * dwc3_alloc_one_event_buffer - Allocates one event buffer structure 42072246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 42172246da4SFelipe Balbi * @length: size of the event buffer 42272246da4SFelipe Balbi * 4231d046793SPaul Zimmerman * Returns a pointer to the allocated event buffer structure on success 42472246da4SFelipe Balbi * otherwise ERR_PTR(errno). 42572246da4SFelipe Balbi */ 42667d0b500SFelipe Balbi static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, 42767d0b500SFelipe Balbi unsigned length) 42872246da4SFelipe Balbi { 42972246da4SFelipe Balbi struct dwc3_event_buffer *evt; 43072246da4SFelipe Balbi 431380f0d28SFelipe Balbi evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); 43272246da4SFelipe Balbi if (!evt) 43372246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 43472246da4SFelipe Balbi 43572246da4SFelipe Balbi evt->dwc = dwc; 43672246da4SFelipe Balbi evt->length = length; 437d9fa4c63SJohn Youn evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL); 438d9fa4c63SJohn Youn if (!evt->cache) 439d9fa4c63SJohn Youn return ERR_PTR(-ENOMEM); 440d9fa4c63SJohn Youn 441d64ff406SArnd Bergmann evt->buf = dma_alloc_coherent(dwc->sysdev, length, 44272246da4SFelipe Balbi &evt->dma, GFP_KERNEL); 443e32672f0SFelipe Balbi if (!evt->buf) 44472246da4SFelipe Balbi return ERR_PTR(-ENOMEM); 44572246da4SFelipe Balbi 44672246da4SFelipe Balbi return evt; 44772246da4SFelipe Balbi } 44872246da4SFelipe Balbi 44972246da4SFelipe Balbi /** 45072246da4SFelipe Balbi * dwc3_free_event_buffers - frees all allocated event buffers 45172246da4SFelipe Balbi * @dwc: Pointer to our controller context structure 45272246da4SFelipe Balbi */ 45372246da4SFelipe Balbi static void dwc3_free_event_buffers(struct dwc3 *dwc) 45472246da4SFelipe Balbi { 45572246da4SFelipe Balbi struct dwc3_event_buffer *evt; 45672246da4SFelipe Balbi 457696c8b12SFelipe Balbi evt = dwc->ev_buf; 45864b6c8a7SAnton Tikhomirov if (evt) 45972246da4SFelipe Balbi dwc3_free_one_event_buffer(dwc, evt); 46072246da4SFelipe Balbi } 46172246da4SFelipe Balbi 46272246da4SFelipe Balbi /** 46372246da4SFelipe Balbi * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length 4641d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 46572246da4SFelipe Balbi * @length: size of event buffer 46672246da4SFelipe Balbi * 4671d046793SPaul Zimmerman * Returns 0 on success otherwise negative errno. In the error case, dwc 46872246da4SFelipe Balbi * may contain some buffers allocated but not all which were requested. 46972246da4SFelipe Balbi */ 47041ac7b3aSBill Pemberton static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) 47172246da4SFelipe Balbi { 47272246da4SFelipe Balbi struct dwc3_event_buffer *evt; 47372246da4SFelipe Balbi 47472246da4SFelipe Balbi evt = dwc3_alloc_one_event_buffer(dwc, length); 47572246da4SFelipe Balbi if (IS_ERR(evt)) { 47672246da4SFelipe Balbi dev_err(dwc->dev, "can't allocate event buffer\n"); 47772246da4SFelipe Balbi return PTR_ERR(evt); 47872246da4SFelipe Balbi } 479696c8b12SFelipe Balbi dwc->ev_buf = evt; 48072246da4SFelipe Balbi 48172246da4SFelipe Balbi return 0; 48272246da4SFelipe Balbi } 48372246da4SFelipe Balbi 48472246da4SFelipe Balbi /** 48572246da4SFelipe Balbi * dwc3_event_buffers_setup - setup our allocated event buffers 4861d046793SPaul Zimmerman * @dwc: pointer to our controller context structure 48772246da4SFelipe Balbi * 48872246da4SFelipe Balbi * Returns 0 on success otherwise negative errno. 48972246da4SFelipe Balbi */ 490f09cc79bSRoger Quadros int dwc3_event_buffers_setup(struct dwc3 *dwc) 49172246da4SFelipe Balbi { 49272246da4SFelipe Balbi struct dwc3_event_buffer *evt; 49372246da4SFelipe Balbi 494696c8b12SFelipe Balbi evt = dwc->ev_buf; 4957acd85e0SPaul Zimmerman evt->lpos = 0; 496660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 49772246da4SFelipe Balbi lower_32_bits(evt->dma)); 498660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 49972246da4SFelipe Balbi upper_32_bits(evt->dma)); 500660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), 50168d6a01bSFelipe Balbi DWC3_GEVNTSIZ_SIZE(evt->length)); 502660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 50372246da4SFelipe Balbi 50472246da4SFelipe Balbi return 0; 50572246da4SFelipe Balbi } 50672246da4SFelipe Balbi 507f09cc79bSRoger Quadros void dwc3_event_buffers_cleanup(struct dwc3 *dwc) 50872246da4SFelipe Balbi { 50972246da4SFelipe Balbi struct dwc3_event_buffer *evt; 51072246da4SFelipe Balbi 511696c8b12SFelipe Balbi evt = dwc->ev_buf; 5127acd85e0SPaul Zimmerman 5137acd85e0SPaul Zimmerman evt->lpos = 0; 5147acd85e0SPaul Zimmerman 515660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0); 516660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0); 517660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK 51868d6a01bSFelipe Balbi | DWC3_GEVNTSIZ_SIZE(0)); 519660e9bdeSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0); 52072246da4SFelipe Balbi } 52172246da4SFelipe Balbi 5220ffcaf37SFelipe Balbi static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc) 5230ffcaf37SFelipe Balbi { 5240ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5250ffcaf37SFelipe Balbi return 0; 5260ffcaf37SFelipe Balbi 5270ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5280ffcaf37SFelipe Balbi return 0; 5290ffcaf37SFelipe Balbi 5300ffcaf37SFelipe Balbi dwc->scratchbuf = kmalloc_array(dwc->nr_scratch, 5310ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, GFP_KERNEL); 5320ffcaf37SFelipe Balbi if (!dwc->scratchbuf) 5330ffcaf37SFelipe Balbi return -ENOMEM; 5340ffcaf37SFelipe Balbi 5350ffcaf37SFelipe Balbi return 0; 5360ffcaf37SFelipe Balbi } 5370ffcaf37SFelipe Balbi 5380ffcaf37SFelipe Balbi static int dwc3_setup_scratch_buffers(struct dwc3 *dwc) 5390ffcaf37SFelipe Balbi { 5400ffcaf37SFelipe Balbi dma_addr_t scratch_addr; 5410ffcaf37SFelipe Balbi u32 param; 5420ffcaf37SFelipe Balbi int ret; 5430ffcaf37SFelipe Balbi 5440ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5450ffcaf37SFelipe Balbi return 0; 5460ffcaf37SFelipe Balbi 5470ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5480ffcaf37SFelipe Balbi return 0; 5490ffcaf37SFelipe Balbi 5500ffcaf37SFelipe Balbi /* should never fall here */ 5510ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5520ffcaf37SFelipe Balbi return 0; 5530ffcaf37SFelipe Balbi 554d64ff406SArnd Bergmann scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf, 5550ffcaf37SFelipe Balbi dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE, 5560ffcaf37SFelipe Balbi DMA_BIDIRECTIONAL); 557d64ff406SArnd Bergmann if (dma_mapping_error(dwc->sysdev, scratch_addr)) { 558d64ff406SArnd Bergmann dev_err(dwc->sysdev, "failed to map scratch buffer\n"); 5590ffcaf37SFelipe Balbi ret = -EFAULT; 5600ffcaf37SFelipe Balbi goto err0; 5610ffcaf37SFelipe Balbi } 5620ffcaf37SFelipe Balbi 5630ffcaf37SFelipe Balbi dwc->scratch_addr = scratch_addr; 5640ffcaf37SFelipe Balbi 5650ffcaf37SFelipe Balbi param = lower_32_bits(scratch_addr); 5660ffcaf37SFelipe Balbi 5670ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5680ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param); 5690ffcaf37SFelipe Balbi if (ret < 0) 5700ffcaf37SFelipe Balbi goto err1; 5710ffcaf37SFelipe Balbi 5720ffcaf37SFelipe Balbi param = upper_32_bits(scratch_addr); 5730ffcaf37SFelipe Balbi 5740ffcaf37SFelipe Balbi ret = dwc3_send_gadget_generic_command(dwc, 5750ffcaf37SFelipe Balbi DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param); 5760ffcaf37SFelipe Balbi if (ret < 0) 5770ffcaf37SFelipe Balbi goto err1; 5780ffcaf37SFelipe Balbi 5790ffcaf37SFelipe Balbi return 0; 5800ffcaf37SFelipe Balbi 5810ffcaf37SFelipe Balbi err1: 582d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 5830ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 5840ffcaf37SFelipe Balbi 5850ffcaf37SFelipe Balbi err0: 5860ffcaf37SFelipe Balbi return ret; 5870ffcaf37SFelipe Balbi } 5880ffcaf37SFelipe Balbi 5890ffcaf37SFelipe Balbi static void dwc3_free_scratch_buffers(struct dwc3 *dwc) 5900ffcaf37SFelipe Balbi { 5910ffcaf37SFelipe Balbi if (!dwc->has_hibernation) 5920ffcaf37SFelipe Balbi return; 5930ffcaf37SFelipe Balbi 5940ffcaf37SFelipe Balbi if (!dwc->nr_scratch) 5950ffcaf37SFelipe Balbi return; 5960ffcaf37SFelipe Balbi 5970ffcaf37SFelipe Balbi /* should never fall here */ 5980ffcaf37SFelipe Balbi if (!WARN_ON(dwc->scratchbuf)) 5990ffcaf37SFelipe Balbi return; 6000ffcaf37SFelipe Balbi 601d64ff406SArnd Bergmann dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch * 6020ffcaf37SFelipe Balbi DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL); 6030ffcaf37SFelipe Balbi kfree(dwc->scratchbuf); 6040ffcaf37SFelipe Balbi } 6050ffcaf37SFelipe Balbi 606789451f6SFelipe Balbi static void dwc3_core_num_eps(struct dwc3 *dwc) 607789451f6SFelipe Balbi { 608789451f6SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 609789451f6SFelipe Balbi 61047d3946eSBryan O'Donoghue dwc->num_eps = DWC3_NUM_EPS(parms); 611789451f6SFelipe Balbi } 612789451f6SFelipe Balbi 61341ac7b3aSBill Pemberton static void dwc3_cache_hwparams(struct dwc3 *dwc) 61426ceca97SFelipe Balbi { 61526ceca97SFelipe Balbi struct dwc3_hwparams *parms = &dwc->hwparams; 61626ceca97SFelipe Balbi 61726ceca97SFelipe Balbi parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); 61826ceca97SFelipe Balbi parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); 61926ceca97SFelipe Balbi parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); 62026ceca97SFelipe Balbi parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); 62126ceca97SFelipe Balbi parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); 62226ceca97SFelipe Balbi parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); 62326ceca97SFelipe Balbi parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); 62426ceca97SFelipe Balbi parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); 62526ceca97SFelipe Balbi parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); 62616710380SThinh Nguyen 62716710380SThinh Nguyen if (DWC3_IP_IS(DWC32)) 62816710380SThinh Nguyen parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9); 62926ceca97SFelipe Balbi } 63026ceca97SFelipe Balbi 63198112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc) 63298112041SRoger Quadros { 63398112041SRoger Quadros int intf; 63498112041SRoger Quadros int ret = 0; 63598112041SRoger Quadros 63698112041SRoger Quadros intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3); 63798112041SRoger Quadros 63898112041SRoger Quadros if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI || 63998112041SRoger Quadros (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI && 64098112041SRoger Quadros dwc->hsphy_interface && 64198112041SRoger Quadros !strncmp(dwc->hsphy_interface, "ulpi", 4))) 64298112041SRoger Quadros ret = dwc3_ulpi_init(dwc); 64398112041SRoger Quadros 64498112041SRoger Quadros return ret; 64598112041SRoger Quadros } 64698112041SRoger Quadros 64772246da4SFelipe Balbi /** 648b5a65c40SHuang Rui * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core 649b5a65c40SHuang Rui * @dwc: Pointer to our controller context structure 65088bc9d19SHeikki Krogerus * 65188bc9d19SHeikki Krogerus * Returns 0 on success. The USB PHY interfaces are configured but not 65288bc9d19SHeikki Krogerus * initialized. The PHY interfaces and the PHYs get initialized together with 65388bc9d19SHeikki Krogerus * the core in dwc3_core_init. 654b5a65c40SHuang Rui */ 65588bc9d19SHeikki Krogerus static int dwc3_phy_setup(struct dwc3 *dwc) 656b5a65c40SHuang Rui { 6579ba3aca8SThinh Nguyen unsigned int hw_mode; 658b5a65c40SHuang Rui u32 reg; 659b5a65c40SHuang Rui 6609ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 6619ba3aca8SThinh Nguyen 662b5a65c40SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 663b5a65c40SHuang Rui 6642164a476SHuang Rui /* 6651966b865SFelipe Balbi * Make sure UX_EXIT_PX is cleared as that causes issues with some 6661966b865SFelipe Balbi * PHYs. Also, this bit is not supposed to be used in normal operation. 6671966b865SFelipe Balbi */ 6681966b865SFelipe Balbi reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX; 6691966b865SFelipe Balbi 6701966b865SFelipe Balbi /* 6712164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY 6722164a476SHuang Rui * to '0' during coreConsultant configuration. So default value 6732164a476SHuang Rui * will be '0' when the core is reset. Application needs to set it 6742164a476SHuang Rui * to '1' after the core initialization is completed. 6752164a476SHuang Rui */ 6769af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 6772164a476SHuang Rui reg |= DWC3_GUSB3PIPECTL_SUSPHY; 6782164a476SHuang Rui 6799ba3aca8SThinh Nguyen /* 6809ba3aca8SThinh Nguyen * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after 6819ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 6829ba3aca8SThinh Nguyen * after device soft-reset during initialization. 6839ba3aca8SThinh Nguyen */ 6849ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 6859ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 6869ba3aca8SThinh Nguyen 687b5a65c40SHuang Rui if (dwc->u2ss_inp3_quirk) 688b5a65c40SHuang Rui reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; 689b5a65c40SHuang Rui 690e58dd357SRajesh Bhagat if (dwc->dis_rxdet_inp3_quirk) 691e58dd357SRajesh Bhagat reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3; 692e58dd357SRajesh Bhagat 693df31f5b3SHuang Rui if (dwc->req_p1p2p3_quirk) 694df31f5b3SHuang Rui reg |= DWC3_GUSB3PIPECTL_REQP1P2P3; 695df31f5b3SHuang Rui 696a2a1d0f5SHuang Rui if (dwc->del_p1p2p3_quirk) 697a2a1d0f5SHuang Rui reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN; 698a2a1d0f5SHuang Rui 69941c06ffdSHuang Rui if (dwc->del_phy_power_chg_quirk) 70041c06ffdSHuang Rui reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE; 70141c06ffdSHuang Rui 702fb67afcaSHuang Rui if (dwc->lfps_filter_quirk) 703fb67afcaSHuang Rui reg |= DWC3_GUSB3PIPECTL_LFPSFILT; 704fb67afcaSHuang Rui 70514f4ac53SHuang Rui if (dwc->rx_detect_poll_quirk) 70614f4ac53SHuang Rui reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL; 70714f4ac53SHuang Rui 7086b6a0c9aSHuang Rui if (dwc->tx_de_emphasis_quirk) 7096b6a0c9aSHuang Rui reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis); 7106b6a0c9aSHuang Rui 711cd72f890SFelipe Balbi if (dwc->dis_u3_susphy_quirk) 71259acfa20SHuang Rui reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; 71359acfa20SHuang Rui 71400fe081dSWilliam Wu if (dwc->dis_del_phy_power_chg_quirk) 71500fe081dSWilliam Wu reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE; 71600fe081dSWilliam Wu 717b5a65c40SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 718b5a65c40SHuang Rui 7192164a476SHuang Rui reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 7202164a476SHuang Rui 7213e10a2ceSHeikki Krogerus /* Select the HS PHY interface */ 7223e10a2ceSHeikki Krogerus switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) { 7233e10a2ceSHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI: 72443cacb03SFelipe Balbi if (dwc->hsphy_interface && 72543cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "utmi", 4)) { 7263e10a2ceSHeikki Krogerus reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI; 72788bc9d19SHeikki Krogerus break; 72843cacb03SFelipe Balbi } else if (dwc->hsphy_interface && 72943cacb03SFelipe Balbi !strncmp(dwc->hsphy_interface, "ulpi", 4)) { 7303e10a2ceSHeikki Krogerus reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI; 73188bc9d19SHeikki Krogerus dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 7323e10a2ceSHeikki Krogerus } else { 73388bc9d19SHeikki Krogerus /* Relying on default value. */ 73488bc9d19SHeikki Krogerus if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI)) 7353e10a2ceSHeikki Krogerus break; 7363e10a2ceSHeikki Krogerus } 737df561f66SGustavo A. R. Silva fallthrough; 73888bc9d19SHeikki Krogerus case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI: 7393e10a2ceSHeikki Krogerus default: 7403e10a2ceSHeikki Krogerus break; 7413e10a2ceSHeikki Krogerus } 7423e10a2ceSHeikki Krogerus 74332f2ed86SWilliam Wu switch (dwc->hsphy_mode) { 74432f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMI: 74532f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 74632f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 74732f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | 74832f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT); 74932f2ed86SWilliam Wu break; 75032f2ed86SWilliam Wu case USBPHY_INTERFACE_MODE_UTMIW: 75132f2ed86SWilliam Wu reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK | 75232f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM_MASK); 75332f2ed86SWilliam Wu reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) | 75432f2ed86SWilliam Wu DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT); 75532f2ed86SWilliam Wu break; 75632f2ed86SWilliam Wu default: 75732f2ed86SWilliam Wu break; 75832f2ed86SWilliam Wu } 75932f2ed86SWilliam Wu 7602164a476SHuang Rui /* 7612164a476SHuang Rui * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to 7622164a476SHuang Rui * '0' during coreConsultant configuration. So default value will 7632164a476SHuang Rui * be '0' when the core is reset. Application needs to set it to 7642164a476SHuang Rui * '1' after the core initialization is completed. 7652164a476SHuang Rui */ 7669af21dd6SThinh Nguyen if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) 7672164a476SHuang Rui reg |= DWC3_GUSB2PHYCFG_SUSPHY; 7682164a476SHuang Rui 7699ba3aca8SThinh Nguyen /* 7709ba3aca8SThinh Nguyen * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after 7719ba3aca8SThinh Nguyen * power-on reset, and it can be set after core initialization, which is 7729ba3aca8SThinh Nguyen * after device soft-reset during initialization. 7739ba3aca8SThinh Nguyen */ 7749ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD) 7759ba3aca8SThinh Nguyen reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7769ba3aca8SThinh Nguyen 777cd72f890SFelipe Balbi if (dwc->dis_u2_susphy_quirk) 7780effe0a3SHuang Rui reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 7790effe0a3SHuang Rui 780ec791d14SJohn Youn if (dwc->dis_enblslpm_quirk) 781ec791d14SJohn Youn reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 782eafeacf1SThinh Nguyen else 783eafeacf1SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_ENBLSLPM; 784ec791d14SJohn Youn 78516199f33SWilliam Wu if (dwc->dis_u2_freeclk_exists_quirk) 78616199f33SWilliam Wu reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS; 78716199f33SWilliam Wu 7882164a476SHuang Rui dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 78988bc9d19SHeikki Krogerus 79088bc9d19SHeikki Krogerus return 0; 791b5a65c40SHuang Rui } 792b5a65c40SHuang Rui 79333fb697eSSean Anderson static int dwc3_clk_enable(struct dwc3 *dwc) 79433fb697eSSean Anderson { 79533fb697eSSean Anderson int ret; 79633fb697eSSean Anderson 79733fb697eSSean Anderson ret = clk_prepare_enable(dwc->bus_clk); 79833fb697eSSean Anderson if (ret) 79933fb697eSSean Anderson return ret; 80033fb697eSSean Anderson 80133fb697eSSean Anderson ret = clk_prepare_enable(dwc->ref_clk); 80233fb697eSSean Anderson if (ret) 80333fb697eSSean Anderson goto disable_bus_clk; 80433fb697eSSean Anderson 80533fb697eSSean Anderson ret = clk_prepare_enable(dwc->susp_clk); 80633fb697eSSean Anderson if (ret) 80733fb697eSSean Anderson goto disable_ref_clk; 80833fb697eSSean Anderson 80933fb697eSSean Anderson return 0; 81033fb697eSSean Anderson 81133fb697eSSean Anderson disable_ref_clk: 81233fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 81333fb697eSSean Anderson disable_bus_clk: 81433fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 81533fb697eSSean Anderson return ret; 81633fb697eSSean Anderson } 81733fb697eSSean Anderson 81833fb697eSSean Anderson static void dwc3_clk_disable(struct dwc3 *dwc) 81933fb697eSSean Anderson { 82033fb697eSSean Anderson clk_disable_unprepare(dwc->susp_clk); 82133fb697eSSean Anderson clk_disable_unprepare(dwc->ref_clk); 82233fb697eSSean Anderson clk_disable_unprepare(dwc->bus_clk); 82333fb697eSSean Anderson } 82433fb697eSSean Anderson 825c499ff71SFelipe Balbi static void dwc3_core_exit(struct dwc3 *dwc) 826c499ff71SFelipe Balbi { 827c499ff71SFelipe Balbi dwc3_event_buffers_cleanup(dwc); 828c499ff71SFelipe Balbi 829c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 830c499ff71SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 831c499ff71SFelipe Balbi phy_exit(dwc->usb2_generic_phy); 832c499ff71SFelipe Balbi phy_exit(dwc->usb3_generic_phy); 833c499ff71SFelipe Balbi 834c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 835c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 836c499ff71SFelipe Balbi phy_power_off(dwc->usb2_generic_phy); 837c499ff71SFelipe Balbi phy_power_off(dwc->usb3_generic_phy); 83833fb697eSSean Anderson dwc3_clk_disable(dwc); 839fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 840c499ff71SFelipe Balbi } 841c499ff71SFelipe Balbi 8420759956fSFelipe Balbi static bool dwc3_core_is_valid(struct dwc3 *dwc) 84372246da4SFelipe Balbi { 84472246da4SFelipe Balbi u32 reg; 84572246da4SFelipe Balbi 8467650bd74SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); 8479af21dd6SThinh Nguyen dwc->ip = DWC3_GSNPS_ID(reg); 8480759956fSFelipe Balbi 8497650bd74SSebastian Andrzej Siewior /* This should read as U3 followed by revision number */ 8509af21dd6SThinh Nguyen if (DWC3_IP_IS(DWC3)) { 851690fb371SJohn Youn dwc->revision = reg; 8529af21dd6SThinh Nguyen } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) { 853690fb371SJohn Youn dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER); 854475d8e01SThinh Nguyen dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE); 855690fb371SJohn Youn } else { 8560759956fSFelipe Balbi return false; 8577650bd74SSebastian Andrzej Siewior } 8587650bd74SSebastian Andrzej Siewior 8590759956fSFelipe Balbi return true; 8600e1e5c47SPaul Zimmerman } 8610e1e5c47SPaul Zimmerman 862941f918eSFelipe Balbi static void dwc3_core_setup_global_control(struct dwc3 *dwc) 86372246da4SFelipe Balbi { 86472246da4SFelipe Balbi u32 hwparams4 = dwc->hwparams.hwparams4; 86572246da4SFelipe Balbi u32 reg; 866c499ff71SFelipe Balbi 8674878a028SSebastian Andrzej Siewior reg = dwc3_readl(dwc->regs, DWC3_GCTL); 8683e87c42aSPaul Zimmerman reg &= ~DWC3_GCTL_SCALEDOWN_MASK; 8694878a028SSebastian Andrzej Siewior 870164d7731SSebastian Andrzej Siewior switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { 8714878a028SSebastian Andrzej Siewior case DWC3_GHWPARAMS1_EN_PWROPT_CLK: 87232a4a135SFelipe Balbi /** 87332a4a135SFelipe Balbi * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an 87432a4a135SFelipe Balbi * issue which would cause xHCI compliance tests to fail. 87532a4a135SFelipe Balbi * 87632a4a135SFelipe Balbi * Because of that we cannot enable clock gating on such 87732a4a135SFelipe Balbi * configurations. 87832a4a135SFelipe Balbi * 87932a4a135SFelipe Balbi * Refers to: 88032a4a135SFelipe Balbi * 88132a4a135SFelipe Balbi * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based 88232a4a135SFelipe Balbi * SOF/ITP Mode Used 88332a4a135SFelipe Balbi */ 88432a4a135SFelipe Balbi if ((dwc->dr_mode == USB_DR_MODE_HOST || 88532a4a135SFelipe Balbi dwc->dr_mode == USB_DR_MODE_OTG) && 8869af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC3, 210A, 250A)) 88732a4a135SFelipe Balbi reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC; 88832a4a135SFelipe Balbi else 8894878a028SSebastian Andrzej Siewior reg &= ~DWC3_GCTL_DSBLCLKGTNG; 8904878a028SSebastian Andrzej Siewior break; 8910ffcaf37SFelipe Balbi case DWC3_GHWPARAMS1_EN_PWROPT_HIB: 8920ffcaf37SFelipe Balbi /* enable hibernation here */ 8930ffcaf37SFelipe Balbi dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4); 8942eac3992SHuang Rui 8952eac3992SHuang Rui /* 8962eac3992SHuang Rui * REVISIT Enabling this bit so that host-mode hibernation 8972eac3992SHuang Rui * will work. Device-mode hibernation is not yet implemented. 8982eac3992SHuang Rui */ 8992eac3992SHuang Rui reg |= DWC3_GCTL_GBLHIBERNATIONEN; 9000ffcaf37SFelipe Balbi break; 9014878a028SSebastian Andrzej Siewior default: 9025eb30cedSFelipe Balbi /* nothing */ 9035eb30cedSFelipe Balbi break; 9044878a028SSebastian Andrzej Siewior } 9054878a028SSebastian Andrzej Siewior 906946bd579SHuang Rui /* check if current dwc3 is on simulation board */ 907946bd579SHuang Rui if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) { 9086af19fd1SFaisal Mehmood dev_info(dwc->dev, "Running with FPGA optimizations\n"); 909946bd579SHuang Rui dwc->is_fpga = true; 910946bd579SHuang Rui } 911946bd579SHuang Rui 9123b81221aSHuang Rui WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga, 9133b81221aSHuang Rui "disable_scramble cannot be used on non-FPGA builds\n"); 9143b81221aSHuang Rui 9153b81221aSHuang Rui if (dwc->disable_scramble_quirk && dwc->is_fpga) 9163b81221aSHuang Rui reg |= DWC3_GCTL_DISSCRAMBLE; 9173b81221aSHuang Rui else 9183b81221aSHuang Rui reg &= ~DWC3_GCTL_DISSCRAMBLE; 9193b81221aSHuang Rui 9209a5b2f31SHuang Rui if (dwc->u2exit_lfps_quirk) 9219a5b2f31SHuang Rui reg |= DWC3_GCTL_U2EXIT_LFPS; 9229a5b2f31SHuang Rui 9234878a028SSebastian Andrzej Siewior /* 9244878a028SSebastian Andrzej Siewior * WORKAROUND: DWC3 revisions <1.90a have a bug 9251d046793SPaul Zimmerman * where the device can fail to connect at SuperSpeed 9264878a028SSebastian Andrzej Siewior * and falls back to high-speed mode which causes 9271d046793SPaul Zimmerman * the device to enter a Connect/Disconnect loop 9284878a028SSebastian Andrzej Siewior */ 9299af21dd6SThinh Nguyen if (DWC3_VER_IS_PRIOR(DWC3, 190A)) 9304878a028SSebastian Andrzej Siewior reg |= DWC3_GCTL_U2RSTECN; 9314878a028SSebastian Andrzej Siewior 9324878a028SSebastian Andrzej Siewior dwc3_writel(dwc->regs, DWC3_GCTL, reg); 933941f918eSFelipe Balbi } 9344878a028SSebastian Andrzej Siewior 935f54edb53SFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc); 93698112041SRoger Quadros static int dwc3_core_ulpi_init(struct dwc3 *dwc); 937f54edb53SFelipe Balbi 938d9612c2fSPengbo Mu /* set global incr burst type configuration registers */ 939d9612c2fSPengbo Mu static void dwc3_set_incr_burst_type(struct dwc3 *dwc) 940d9612c2fSPengbo Mu { 941d9612c2fSPengbo Mu struct device *dev = dwc->dev; 942d9612c2fSPengbo Mu /* incrx_mode : for INCR burst type. */ 943d9612c2fSPengbo Mu bool incrx_mode; 944d9612c2fSPengbo Mu /* incrx_size : for size of INCRX burst. */ 945d9612c2fSPengbo Mu u32 incrx_size; 946d9612c2fSPengbo Mu u32 *vals; 947d9612c2fSPengbo Mu u32 cfg; 948d9612c2fSPengbo Mu int ntype; 949d9612c2fSPengbo Mu int ret; 950d9612c2fSPengbo Mu int i; 951d9612c2fSPengbo Mu 952d9612c2fSPengbo Mu cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); 953d9612c2fSPengbo Mu 954d9612c2fSPengbo Mu /* 955d9612c2fSPengbo Mu * Handle property "snps,incr-burst-type-adjustment". 956d9612c2fSPengbo Mu * Get the number of value from this property: 957d9612c2fSPengbo Mu * result <= 0, means this property is not supported. 958d9612c2fSPengbo Mu * result = 1, means INCRx burst mode supported. 959d9612c2fSPengbo Mu * result > 1, means undefined length burst mode supported. 960d9612c2fSPengbo Mu */ 961a6e5e679SAndy Shevchenko ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment"); 962d9612c2fSPengbo Mu if (ntype <= 0) 963d9612c2fSPengbo Mu return; 964d9612c2fSPengbo Mu 965d9612c2fSPengbo Mu vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); 966d9612c2fSPengbo Mu if (!vals) { 967d9612c2fSPengbo Mu dev_err(dev, "Error to get memory\n"); 968d9612c2fSPengbo Mu return; 969d9612c2fSPengbo Mu } 970d9612c2fSPengbo Mu 971d9612c2fSPengbo Mu /* Get INCR burst type, and parse it */ 972d9612c2fSPengbo Mu ret = device_property_read_u32_array(dev, 973d9612c2fSPengbo Mu "snps,incr-burst-type-adjustment", vals, ntype); 974d9612c2fSPengbo Mu if (ret) { 97575ecb9ddSAndy Shevchenko kfree(vals); 976d9612c2fSPengbo Mu dev_err(dev, "Error to get property\n"); 977d9612c2fSPengbo Mu return; 978d9612c2fSPengbo Mu } 979d9612c2fSPengbo Mu 980d9612c2fSPengbo Mu incrx_size = *vals; 981d9612c2fSPengbo Mu 982d9612c2fSPengbo Mu if (ntype > 1) { 983d9612c2fSPengbo Mu /* INCRX (undefined length) burst mode */ 984d9612c2fSPengbo Mu incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; 985d9612c2fSPengbo Mu for (i = 1; i < ntype; i++) { 986d9612c2fSPengbo Mu if (vals[i] > incrx_size) 987d9612c2fSPengbo Mu incrx_size = vals[i]; 988d9612c2fSPengbo Mu } 989d9612c2fSPengbo Mu } else { 990d9612c2fSPengbo Mu /* INCRX burst mode */ 991d9612c2fSPengbo Mu incrx_mode = INCRX_BURST_MODE; 992d9612c2fSPengbo Mu } 993d9612c2fSPengbo Mu 99475ecb9ddSAndy Shevchenko kfree(vals); 99575ecb9ddSAndy Shevchenko 996d9612c2fSPengbo Mu /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ 997d9612c2fSPengbo Mu cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; 998d9612c2fSPengbo Mu if (incrx_mode) 999d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; 1000d9612c2fSPengbo Mu switch (incrx_size) { 1001d9612c2fSPengbo Mu case 256: 1002d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; 1003d9612c2fSPengbo Mu break; 1004d9612c2fSPengbo Mu case 128: 1005d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; 1006d9612c2fSPengbo Mu break; 1007d9612c2fSPengbo Mu case 64: 1008d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; 1009d9612c2fSPengbo Mu break; 1010d9612c2fSPengbo Mu case 32: 1011d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; 1012d9612c2fSPengbo Mu break; 1013d9612c2fSPengbo Mu case 16: 1014d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; 1015d9612c2fSPengbo Mu break; 1016d9612c2fSPengbo Mu case 8: 1017d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; 1018d9612c2fSPengbo Mu break; 1019d9612c2fSPengbo Mu case 4: 1020d9612c2fSPengbo Mu cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; 1021d9612c2fSPengbo Mu break; 1022d9612c2fSPengbo Mu case 1: 1023d9612c2fSPengbo Mu break; 1024d9612c2fSPengbo Mu default: 1025d9612c2fSPengbo Mu dev_err(dev, "Invalid property\n"); 1026d9612c2fSPengbo Mu break; 1027d9612c2fSPengbo Mu } 1028d9612c2fSPengbo Mu 1029d9612c2fSPengbo Mu dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); 1030d9612c2fSPengbo Mu } 1031d9612c2fSPengbo Mu 1032941f918eSFelipe Balbi /** 1033941f918eSFelipe Balbi * dwc3_core_init - Low-level initialization of DWC3 Core 1034941f918eSFelipe Balbi * @dwc: Pointer to our controller context structure 1035941f918eSFelipe Balbi * 1036941f918eSFelipe Balbi * Returns 0 on success otherwise negative errno. 1037941f918eSFelipe Balbi */ 1038941f918eSFelipe Balbi static int dwc3_core_init(struct dwc3 *dwc) 1039941f918eSFelipe Balbi { 10409ba3aca8SThinh Nguyen unsigned int hw_mode; 1041941f918eSFelipe Balbi u32 reg; 1042941f918eSFelipe Balbi int ret; 1043941f918eSFelipe Balbi 10449ba3aca8SThinh Nguyen hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); 10459ba3aca8SThinh Nguyen 1046941f918eSFelipe Balbi /* 1047941f918eSFelipe Balbi * Write Linux Version Code to our GUID register so it's easy to figure 1048941f918eSFelipe Balbi * out which kernel version a bug was found. 1049941f918eSFelipe Balbi */ 1050941f918eSFelipe Balbi dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); 1051941f918eSFelipe Balbi 1052941f918eSFelipe Balbi ret = dwc3_phy_setup(dwc); 1053941f918eSFelipe Balbi if (ret) 1054941f918eSFelipe Balbi goto err0; 1055941f918eSFelipe Balbi 105698112041SRoger Quadros if (!dwc->ulpi_ready) { 105798112041SRoger Quadros ret = dwc3_core_ulpi_init(dwc); 105898112041SRoger Quadros if (ret) 105998112041SRoger Quadros goto err0; 106098112041SRoger Quadros dwc->ulpi_ready = true; 106198112041SRoger Quadros } 106298112041SRoger Quadros 106398112041SRoger Quadros if (!dwc->phys_ready) { 106498112041SRoger Quadros ret = dwc3_core_get_phy(dwc); 106598112041SRoger Quadros if (ret) 106698112041SRoger Quadros goto err0a; 106798112041SRoger Quadros dwc->phys_ready = true; 106898112041SRoger Quadros } 106998112041SRoger Quadros 10708cfac9a6SLi Jun usb_phy_init(dwc->usb2_phy); 10718cfac9a6SLi Jun usb_phy_init(dwc->usb3_phy); 10728cfac9a6SLi Jun ret = phy_init(dwc->usb2_generic_phy); 10738cfac9a6SLi Jun if (ret < 0) 10748cfac9a6SLi Jun goto err0a; 10758cfac9a6SLi Jun 10768cfac9a6SLi Jun ret = phy_init(dwc->usb3_generic_phy); 10778cfac9a6SLi Jun if (ret < 0) { 10788cfac9a6SLi Jun phy_exit(dwc->usb2_generic_phy); 10798cfac9a6SLi Jun goto err0a; 10808cfac9a6SLi Jun } 10818cfac9a6SLi Jun 108298112041SRoger Quadros ret = dwc3_core_soft_reset(dwc); 108398112041SRoger Quadros if (ret) 10848cfac9a6SLi Jun goto err1; 108598112041SRoger Quadros 10869ba3aca8SThinh Nguyen if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD && 10879af21dd6SThinh Nguyen !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) { 10889ba3aca8SThinh Nguyen if (!dwc->dis_u3_susphy_quirk) { 10899ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); 10909ba3aca8SThinh Nguyen reg |= DWC3_GUSB3PIPECTL_SUSPHY; 10919ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); 10929ba3aca8SThinh Nguyen } 10939ba3aca8SThinh Nguyen 10949ba3aca8SThinh Nguyen if (!dwc->dis_u2_susphy_quirk) { 10959ba3aca8SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 10969ba3aca8SThinh Nguyen reg |= DWC3_GUSB2PHYCFG_SUSPHY; 10979ba3aca8SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 10989ba3aca8SThinh Nguyen } 10999ba3aca8SThinh Nguyen } 11009ba3aca8SThinh Nguyen 1101941f918eSFelipe Balbi dwc3_core_setup_global_control(dwc); 1102c499ff71SFelipe Balbi dwc3_core_num_eps(dwc); 11030ffcaf37SFelipe Balbi 11040ffcaf37SFelipe Balbi ret = dwc3_setup_scratch_buffers(dwc); 11050ffcaf37SFelipe Balbi if (ret) 1106c499ff71SFelipe Balbi goto err1; 1107c499ff71SFelipe Balbi 1108c499ff71SFelipe Balbi /* Adjust Frame Length */ 1109c499ff71SFelipe Balbi dwc3_frame_length_adjustment(dwc); 1110c499ff71SFelipe Balbi 11117bee3188SBalaji Prakash J /* Adjust Reference Clock Period */ 11127bee3188SBalaji Prakash J dwc3_ref_clk_period(dwc); 11137bee3188SBalaji Prakash J 1114d9612c2fSPengbo Mu dwc3_set_incr_burst_type(dwc); 1115d9612c2fSPengbo Mu 1116c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 0); 1117c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 0); 1118c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb2_generic_phy); 1119c499ff71SFelipe Balbi if (ret < 0) 11200ffcaf37SFelipe Balbi goto err2; 11210ffcaf37SFelipe Balbi 1122c499ff71SFelipe Balbi ret = phy_power_on(dwc->usb3_generic_phy); 1123c499ff71SFelipe Balbi if (ret < 0) 1124c499ff71SFelipe Balbi goto err3; 1125c499ff71SFelipe Balbi 1126c499ff71SFelipe Balbi ret = dwc3_event_buffers_setup(dwc); 1127c499ff71SFelipe Balbi if (ret) { 1128c499ff71SFelipe Balbi dev_err(dwc->dev, "failed to setup event buffers\n"); 1129c499ff71SFelipe Balbi goto err4; 1130c499ff71SFelipe Balbi } 1131c499ff71SFelipe Balbi 113206281d46SJohn Youn /* 113306281d46SJohn Youn * ENDXFER polling is available on version 3.10a and later of 113406281d46SJohn Youn * the DWC_usb3 controller. It is NOT available in the 113506281d46SJohn Youn * DWC_usb31 controller. 113606281d46SJohn Youn */ 11379af21dd6SThinh Nguyen if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) { 113806281d46SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL2); 113906281d46SJohn Youn reg |= DWC3_GUCTL2_RST_ACTBITLATER; 114006281d46SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); 114106281d46SJohn Youn } 114206281d46SJohn Youn 11439af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { 11440bb39ca1SJohn Youn reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); 114565db7a0cSWilliam Wu 114665db7a0cSWilliam Wu /* 114765db7a0cSWilliam Wu * Enable hardware control of sending remote wakeup 114865db7a0cSWilliam Wu * in HS when the device is in the L1 state. 114965db7a0cSWilliam Wu */ 11509af21dd6SThinh Nguyen if (!DWC3_VER_IS_PRIOR(DWC3, 290A)) 11510bb39ca1SJohn Youn reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW; 115265db7a0cSWilliam Wu 1153843714bbSJack Pham /* 1154843714bbSJack Pham * Decouple USB 2.0 L1 & L2 events which will allow for 1155843714bbSJack Pham * gadget driver to only receive U3/L2 suspend & wakeup 1156843714bbSJack Pham * events and prevent the more frequent L1 LPM transitions 1157843714bbSJack Pham * from interrupting the driver. 1158843714bbSJack Pham */ 1159843714bbSJack Pham if (!DWC3_VER_IS_PRIOR(DWC3, 300A)) 1160843714bbSJack Pham reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT; 1161843714bbSJack Pham 116265db7a0cSWilliam Wu if (dwc->dis_tx_ipgap_linecheck_quirk) 116365db7a0cSWilliam Wu reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; 116465db7a0cSWilliam Wu 11657ba6b09fSNeil Armstrong if (dwc->parkmode_disable_ss_quirk) 11667ba6b09fSNeil Armstrong reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; 11677ba6b09fSNeil Armstrong 116862b20e6eSBin Yang if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) && 116962b20e6eSBin Yang (dwc->maximum_speed == USB_SPEED_HIGH || 117062b20e6eSBin Yang dwc->maximum_speed == USB_SPEED_FULL)) 117162b20e6eSBin Yang reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; 117262b20e6eSBin Yang 11730bb39ca1SJohn Youn dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); 11740bb39ca1SJohn Youn } 11750bb39ca1SJohn Youn 1176b138e23dSAnurag Kumar Vulisha if (dwc->dr_mode == USB_DR_MODE_HOST || 1177b138e23dSAnurag Kumar Vulisha dwc->dr_mode == USB_DR_MODE_OTG) { 1178b138e23dSAnurag Kumar Vulisha reg = dwc3_readl(dwc->regs, DWC3_GUCTL); 1179b138e23dSAnurag Kumar Vulisha 1180b138e23dSAnurag Kumar Vulisha /* 1181b138e23dSAnurag Kumar Vulisha * Enable Auto retry Feature to make the controller operating in 1182b138e23dSAnurag Kumar Vulisha * Host mode on seeing transaction errors(CRC errors or internal 1183b138e23dSAnurag Kumar Vulisha * overrun scenerios) on IN transfers to reply to the device 1184b138e23dSAnurag Kumar Vulisha * with a non-terminating retry ACK (i.e, an ACK transcation 1185b138e23dSAnurag Kumar Vulisha * packet with Retry=1 & Nump != 0) 1186b138e23dSAnurag Kumar Vulisha */ 1187b138e23dSAnurag Kumar Vulisha reg |= DWC3_GUCTL_HSTINAUTORETRY; 1188b138e23dSAnurag Kumar Vulisha 1189b138e23dSAnurag Kumar Vulisha dwc3_writel(dwc->regs, DWC3_GUCTL, reg); 1190b138e23dSAnurag Kumar Vulisha } 1191b138e23dSAnurag Kumar Vulisha 1192938a5ad1SThinh Nguyen /* 1193938a5ad1SThinh Nguyen * Must config both number of packets and max burst settings to enable 1194938a5ad1SThinh Nguyen * RX and/or TX threshold. 1195938a5ad1SThinh Nguyen */ 11969af21dd6SThinh Nguyen if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) { 1197938a5ad1SThinh Nguyen u8 rx_thr_num = dwc->rx_thr_num_pkt_prd; 1198938a5ad1SThinh Nguyen u8 rx_maxburst = dwc->rx_max_burst_prd; 1199938a5ad1SThinh Nguyen u8 tx_thr_num = dwc->tx_thr_num_pkt_prd; 1200938a5ad1SThinh Nguyen u8 tx_maxburst = dwc->tx_max_burst_prd; 1201938a5ad1SThinh Nguyen 1202938a5ad1SThinh Nguyen if (rx_thr_num && rx_maxburst) { 1203938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1204938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKTSEL_PRD; 1205938a5ad1SThinh Nguyen 1206938a5ad1SThinh Nguyen reg &= ~DWC31_RXTHRNUMPKT_PRD(~0); 1207938a5ad1SThinh Nguyen reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num); 1208938a5ad1SThinh Nguyen 1209938a5ad1SThinh Nguyen reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0); 1210938a5ad1SThinh Nguyen reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst); 1211938a5ad1SThinh Nguyen 1212938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1213938a5ad1SThinh Nguyen } 1214938a5ad1SThinh Nguyen 1215938a5ad1SThinh Nguyen if (tx_thr_num && tx_maxburst) { 1216938a5ad1SThinh Nguyen reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG); 1217938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKTSEL_PRD; 1218938a5ad1SThinh Nguyen 1219938a5ad1SThinh Nguyen reg &= ~DWC31_TXTHRNUMPKT_PRD(~0); 1220938a5ad1SThinh Nguyen reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num); 1221938a5ad1SThinh Nguyen 1222938a5ad1SThinh Nguyen reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0); 1223938a5ad1SThinh Nguyen reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst); 1224938a5ad1SThinh Nguyen 1225938a5ad1SThinh Nguyen dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg); 1226938a5ad1SThinh Nguyen } 1227938a5ad1SThinh Nguyen } 1228938a5ad1SThinh Nguyen 122972246da4SFelipe Balbi return 0; 123072246da4SFelipe Balbi 1231c499ff71SFelipe Balbi err4: 12329b9d7cddSVivek Gautam phy_power_off(dwc->usb3_generic_phy); 1233c499ff71SFelipe Balbi 1234c499ff71SFelipe Balbi err3: 12359b9d7cddSVivek Gautam phy_power_off(dwc->usb2_generic_phy); 1236c499ff71SFelipe Balbi 12370ffcaf37SFelipe Balbi err2: 1238c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb2_phy, 1); 1239c499ff71SFelipe Balbi usb_phy_set_suspend(dwc->usb3_phy, 1); 12400ffcaf37SFelipe Balbi 12410ffcaf37SFelipe Balbi err1: 12420ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb2_phy); 12430ffcaf37SFelipe Balbi usb_phy_shutdown(dwc->usb3_phy); 124457303488SKishon Vijay Abraham I phy_exit(dwc->usb2_generic_phy); 124557303488SKishon Vijay Abraham I phy_exit(dwc->usb3_generic_phy); 12460ffcaf37SFelipe Balbi 124798112041SRoger Quadros err0a: 124898112041SRoger Quadros dwc3_ulpi_exit(dwc); 124998112041SRoger Quadros 125072246da4SFelipe Balbi err0: 125172246da4SFelipe Balbi return ret; 125272246da4SFelipe Balbi } 125372246da4SFelipe Balbi 12543c9f94acSFelipe Balbi static int dwc3_core_get_phy(struct dwc3 *dwc) 125572246da4SFelipe Balbi { 12563c9f94acSFelipe Balbi struct device *dev = dwc->dev; 1257941ea361SFelipe Balbi struct device_node *node = dev->of_node; 12583c9f94acSFelipe Balbi int ret; 125972246da4SFelipe Balbi 12605088b6f5SKishon Vijay Abraham I if (node) { 12615088b6f5SKishon Vijay Abraham I dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); 12625088b6f5SKishon Vijay Abraham I dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); 1263bb674907SFelipe Balbi } else { 1264bb674907SFelipe Balbi dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); 1265bb674907SFelipe Balbi dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); 12665088b6f5SKishon Vijay Abraham I } 12675088b6f5SKishon Vijay Abraham I 1268d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb2_phy)) { 1269d105e7f8SFelipe Balbi ret = PTR_ERR(dwc->usb2_phy); 1270122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1271122f06e6SKishon Vijay Abraham I dwc->usb2_phy = NULL; 1272122f06e6SKishon Vijay Abraham I } else { 12730c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 1274122f06e6SKishon Vijay Abraham I } 127551e1e7bcSFelipe Balbi } 127651e1e7bcSFelipe Balbi 1277d105e7f8SFelipe Balbi if (IS_ERR(dwc->usb3_phy)) { 1278315955d7SRuchika Kharwar ret = PTR_ERR(dwc->usb3_phy); 1279122f06e6SKishon Vijay Abraham I if (ret == -ENXIO || ret == -ENODEV) { 1280122f06e6SKishon Vijay Abraham I dwc->usb3_phy = NULL; 1281122f06e6SKishon Vijay Abraham I } else { 12820c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 1283122f06e6SKishon Vijay Abraham I } 128451e1e7bcSFelipe Balbi } 128551e1e7bcSFelipe Balbi 128657303488SKishon Vijay Abraham I dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy"); 128757303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb2_generic_phy)) { 128857303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb2_generic_phy); 128957303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 129057303488SKishon Vijay Abraham I dwc->usb2_generic_phy = NULL; 129157303488SKishon Vijay Abraham I } else { 12920c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb2 phy configured\n"); 129357303488SKishon Vijay Abraham I } 129457303488SKishon Vijay Abraham I } 129557303488SKishon Vijay Abraham I 129657303488SKishon Vijay Abraham I dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy"); 129757303488SKishon Vijay Abraham I if (IS_ERR(dwc->usb3_generic_phy)) { 129857303488SKishon Vijay Abraham I ret = PTR_ERR(dwc->usb3_generic_phy); 129957303488SKishon Vijay Abraham I if (ret == -ENOSYS || ret == -ENODEV) { 130057303488SKishon Vijay Abraham I dwc->usb3_generic_phy = NULL; 130157303488SKishon Vijay Abraham I } else { 13020c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "no usb3 phy configured\n"); 130357303488SKishon Vijay Abraham I } 130457303488SKishon Vijay Abraham I } 130557303488SKishon Vijay Abraham I 13063c9f94acSFelipe Balbi return 0; 13073c9f94acSFelipe Balbi } 13083c9f94acSFelipe Balbi 13095f94adfeSFelipe Balbi static int dwc3_core_init_mode(struct dwc3 *dwc) 13105f94adfeSFelipe Balbi { 13115f94adfeSFelipe Balbi struct device *dev = dwc->dev; 13125f94adfeSFelipe Balbi int ret; 13135f94adfeSFelipe Balbi 13145f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13155f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 131641ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1317958d1a4cSFelipe Balbi 1318958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1319958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, false); 1320958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE); 1321644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE); 1322958d1a4cSFelipe Balbi 13235f94adfeSFelipe Balbi ret = dwc3_gadget_init(dwc); 13240c0a20f6SAndy Shevchenko if (ret) 13250c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize gadget\n"); 13265f94adfeSFelipe Balbi break; 13275f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 132841ce1456SRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1329958d1a4cSFelipe Balbi 1330958d1a4cSFelipe Balbi if (dwc->usb2_phy) 1331958d1a4cSFelipe Balbi otg_set_vbus(dwc->usb2_phy->otg, true); 1332958d1a4cSFelipe Balbi phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST); 1333644cbbc3SManu Gautam phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST); 1334958d1a4cSFelipe Balbi 13355f94adfeSFelipe Balbi ret = dwc3_host_init(dwc); 13360c0a20f6SAndy Shevchenko if (ret) 13370c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize host\n"); 13385f94adfeSFelipe Balbi break; 13395f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 134041ce1456SRoger Quadros INIT_WORK(&dwc->drd_work, __dwc3_set_mode); 13419840354fSRoger Quadros ret = dwc3_drd_init(dwc); 13420c0a20f6SAndy Shevchenko if (ret) 13430c0a20f6SAndy Shevchenko return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); 13445f94adfeSFelipe Balbi break; 13455f94adfeSFelipe Balbi default: 13465f94adfeSFelipe Balbi dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); 13475f94adfeSFelipe Balbi return -EINVAL; 13485f94adfeSFelipe Balbi } 13495f94adfeSFelipe Balbi 13505f94adfeSFelipe Balbi return 0; 13515f94adfeSFelipe Balbi } 13525f94adfeSFelipe Balbi 13535f94adfeSFelipe Balbi static void dwc3_core_exit_mode(struct dwc3 *dwc) 13545f94adfeSFelipe Balbi { 13555f94adfeSFelipe Balbi switch (dwc->dr_mode) { 13565f94adfeSFelipe Balbi case USB_DR_MODE_PERIPHERAL: 13575f94adfeSFelipe Balbi dwc3_gadget_exit(dwc); 13585f94adfeSFelipe Balbi break; 13595f94adfeSFelipe Balbi case USB_DR_MODE_HOST: 13605f94adfeSFelipe Balbi dwc3_host_exit(dwc); 13615f94adfeSFelipe Balbi break; 13625f94adfeSFelipe Balbi case USB_DR_MODE_OTG: 13639840354fSRoger Quadros dwc3_drd_exit(dwc); 13645f94adfeSFelipe Balbi break; 13655f94adfeSFelipe Balbi default: 13665f94adfeSFelipe Balbi /* do nothing */ 13675f94adfeSFelipe Balbi break; 13685f94adfeSFelipe Balbi } 136909ed259fSBin Liu 137009ed259fSBin Liu /* de-assert DRVVBUS for HOST and OTG mode */ 137109ed259fSBin Liu dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 13725f94adfeSFelipe Balbi } 13735f94adfeSFelipe Balbi 1374c5ac6116SFelipe Balbi static void dwc3_get_properties(struct dwc3 *dwc) 13753c9f94acSFelipe Balbi { 1376c5ac6116SFelipe Balbi struct device *dev = dwc->dev; 137780caf7d2SHuang Rui u8 lpm_nyet_threshold; 13786b6a0c9aSHuang Rui u8 tx_de_emphasis; 1379460d098cSHuang Rui u8 hird_threshold; 1380938a5ad1SThinh Nguyen u8 rx_thr_num_pkt_prd; 1381938a5ad1SThinh Nguyen u8 rx_max_burst_prd; 1382938a5ad1SThinh Nguyen u8 tx_thr_num_pkt_prd; 1383938a5ad1SThinh Nguyen u8 tx_max_burst_prd; 13849f607a30SWesley Cheng u8 tx_fifo_resize_max_num; 13856f0764b5SRay Chi const char *usb_psy_name; 13866f0764b5SRay Chi int ret; 13873c9f94acSFelipe Balbi 138880caf7d2SHuang Rui /* default to highest possible threshold */ 13898d791929SThinh Nguyen lpm_nyet_threshold = 0xf; 139080caf7d2SHuang Rui 13916b6a0c9aSHuang Rui /* default to -3.5dB de-emphasis */ 13926b6a0c9aSHuang Rui tx_de_emphasis = 1; 13936b6a0c9aSHuang Rui 1394460d098cSHuang Rui /* 1395460d098cSHuang Rui * default to assert utmi_sleep_n and use maximum allowed HIRD 1396460d098cSHuang Rui * threshold value of 0b1100 1397460d098cSHuang Rui */ 1398460d098cSHuang Rui hird_threshold = 12; 1399460d098cSHuang Rui 14009f607a30SWesley Cheng /* 14019f607a30SWesley Cheng * default to a TXFIFO size large enough to fit 6 max packets. This 14029f607a30SWesley Cheng * allows for systems with larger bus latencies to have some headroom 14039f607a30SWesley Cheng * for endpoints that have a large bMaxBurst value. 14049f607a30SWesley Cheng */ 14059f607a30SWesley Cheng tx_fifo_resize_max_num = 6; 14069f607a30SWesley Cheng 140763863b98SHeikki Krogerus dwc->maximum_speed = usb_get_maximum_speed(dev); 140867848146SThinh Nguyen dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev); 140906e7114fSHeikki Krogerus dwc->dr_mode = usb_get_dr_mode(dev); 141032f2ed86SWilliam Wu dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); 141163863b98SHeikki Krogerus 1412d64ff406SArnd Bergmann dwc->sysdev_is_parent = device_property_read_bool(dev, 1413d64ff406SArnd Bergmann "linux,sysdev_is_parent"); 1414d64ff406SArnd Bergmann if (dwc->sysdev_is_parent) 1415d64ff406SArnd Bergmann dwc->sysdev = dwc->dev->parent; 1416d64ff406SArnd Bergmann else 1417d64ff406SArnd Bergmann dwc->sysdev = dwc->dev; 1418d64ff406SArnd Bergmann 14196f0764b5SRay Chi ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name); 14206f0764b5SRay Chi if (ret >= 0) { 14216f0764b5SRay Chi dwc->usb_psy = power_supply_get_by_name(usb_psy_name); 14226f0764b5SRay Chi if (!dwc->usb_psy) 14236f0764b5SRay Chi dev_err(dev, "couldn't get usb power supply\n"); 14246f0764b5SRay Chi } 14256f0764b5SRay Chi 14263d128919SHeikki Krogerus dwc->has_lpm_erratum = device_property_read_bool(dev, 142780caf7d2SHuang Rui "snps,has-lpm-erratum"); 14283d128919SHeikki Krogerus device_property_read_u8(dev, "snps,lpm-nyet-threshold", 142980caf7d2SHuang Rui &lpm_nyet_threshold); 14303d128919SHeikki Krogerus dwc->is_utmi_l1_suspend = device_property_read_bool(dev, 1431460d098cSHuang Rui "snps,is-utmi-l1-suspend"); 14323d128919SHeikki Krogerus device_property_read_u8(dev, "snps,hird-threshold", 1433460d098cSHuang Rui &hird_threshold); 1434d92021f6SThinh Nguyen dwc->dis_start_transfer_quirk = device_property_read_bool(dev, 1435d92021f6SThinh Nguyen "snps,dis-start-transfer-quirk"); 14363d128919SHeikki Krogerus dwc->usb3_lpm_capable = device_property_read_bool(dev, 1437eac68e8fSRobert Baldyga "snps,usb3_lpm_capable"); 1438022a0208SThinh Nguyen dwc->usb2_lpm_disable = device_property_read_bool(dev, 1439022a0208SThinh Nguyen "snps,usb2-lpm-disable"); 1440475e8be5SThinh Nguyen dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev, 1441475e8be5SThinh Nguyen "snps,usb2-gadget-lpm-disable"); 1442938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd", 1443938a5ad1SThinh Nguyen &rx_thr_num_pkt_prd); 1444938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,rx-max-burst-prd", 1445938a5ad1SThinh Nguyen &rx_max_burst_prd); 1446938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd", 1447938a5ad1SThinh Nguyen &tx_thr_num_pkt_prd); 1448938a5ad1SThinh Nguyen device_property_read_u8(dev, "snps,tx-max-burst-prd", 1449938a5ad1SThinh Nguyen &tx_max_burst_prd); 14509f607a30SWesley Cheng dwc->do_fifo_resize = device_property_read_bool(dev, 14519f607a30SWesley Cheng "tx-fifo-resize"); 14529f607a30SWesley Cheng if (dwc->do_fifo_resize) 14539f607a30SWesley Cheng device_property_read_u8(dev, "tx-fifo-max-num", 14549f607a30SWesley Cheng &tx_fifo_resize_max_num); 14553c9f94acSFelipe Balbi 14563d128919SHeikki Krogerus dwc->disable_scramble_quirk = device_property_read_bool(dev, 14573b81221aSHuang Rui "snps,disable_scramble_quirk"); 14583d128919SHeikki Krogerus dwc->u2exit_lfps_quirk = device_property_read_bool(dev, 14599a5b2f31SHuang Rui "snps,u2exit_lfps_quirk"); 14603d128919SHeikki Krogerus dwc->u2ss_inp3_quirk = device_property_read_bool(dev, 1461b5a65c40SHuang Rui "snps,u2ss_inp3_quirk"); 14623d128919SHeikki Krogerus dwc->req_p1p2p3_quirk = device_property_read_bool(dev, 1463df31f5b3SHuang Rui "snps,req_p1p2p3_quirk"); 14643d128919SHeikki Krogerus dwc->del_p1p2p3_quirk = device_property_read_bool(dev, 1465a2a1d0f5SHuang Rui "snps,del_p1p2p3_quirk"); 14663d128919SHeikki Krogerus dwc->del_phy_power_chg_quirk = device_property_read_bool(dev, 146741c06ffdSHuang Rui "snps,del_phy_power_chg_quirk"); 14683d128919SHeikki Krogerus dwc->lfps_filter_quirk = device_property_read_bool(dev, 1469fb67afcaSHuang Rui "snps,lfps_filter_quirk"); 14703d128919SHeikki Krogerus dwc->rx_detect_poll_quirk = device_property_read_bool(dev, 147114f4ac53SHuang Rui "snps,rx_detect_poll_quirk"); 14723d128919SHeikki Krogerus dwc->dis_u3_susphy_quirk = device_property_read_bool(dev, 147359acfa20SHuang Rui "snps,dis_u3_susphy_quirk"); 14743d128919SHeikki Krogerus dwc->dis_u2_susphy_quirk = device_property_read_bool(dev, 14750effe0a3SHuang Rui "snps,dis_u2_susphy_quirk"); 1476ec791d14SJohn Youn dwc->dis_enblslpm_quirk = device_property_read_bool(dev, 1477ec791d14SJohn Youn "snps,dis_enblslpm_quirk"); 1478729dcffdSAnurag Kumar Vulisha dwc->dis_u1_entry_quirk = device_property_read_bool(dev, 1479729dcffdSAnurag Kumar Vulisha "snps,dis-u1-entry-quirk"); 1480729dcffdSAnurag Kumar Vulisha dwc->dis_u2_entry_quirk = device_property_read_bool(dev, 1481729dcffdSAnurag Kumar Vulisha "snps,dis-u2-entry-quirk"); 1482e58dd357SRajesh Bhagat dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev, 1483e58dd357SRajesh Bhagat "snps,dis_rxdet_inp3_quirk"); 148416199f33SWilliam Wu dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev, 148516199f33SWilliam Wu "snps,dis-u2-freeclk-exists-quirk"); 148600fe081dSWilliam Wu dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev, 148700fe081dSWilliam Wu "snps,dis-del-phy-power-chg-quirk"); 148865db7a0cSWilliam Wu dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, 148965db7a0cSWilliam Wu "snps,dis-tx-ipgap-linecheck-quirk"); 14907ba6b09fSNeil Armstrong dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, 14917ba6b09fSNeil Armstrong "snps,parkmode-disable-ss-quirk"); 14926b6a0c9aSHuang Rui 14933d128919SHeikki Krogerus dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, 14946b6a0c9aSHuang Rui "snps,tx_de_emphasis_quirk"); 14953d128919SHeikki Krogerus device_property_read_u8(dev, "snps,tx_de_emphasis", 14966b6a0c9aSHuang Rui &tx_de_emphasis); 14973d128919SHeikki Krogerus device_property_read_string(dev, "snps,hsphy_interface", 14983e10a2ceSHeikki Krogerus &dwc->hsphy_interface); 14993d128919SHeikki Krogerus device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", 1500bcdb3272SFelipe Balbi &dwc->fladj); 15017bee3188SBalaji Prakash J device_property_read_u32(dev, "snps,ref-clock-period-ns", 15027bee3188SBalaji Prakash J &dwc->ref_clk_per); 15033d128919SHeikki Krogerus 150442bf02ecSRoger Quadros dwc->dis_metastability_quirk = device_property_read_bool(dev, 150542bf02ecSRoger Quadros "snps,dis_metastability_quirk"); 150642bf02ecSRoger Quadros 1507f580170fSYu Chen dwc->dis_split_quirk = device_property_read_bool(dev, 1508f580170fSYu Chen "snps,dis-split-quirk"); 1509f580170fSYu Chen 151080caf7d2SHuang Rui dwc->lpm_nyet_threshold = lpm_nyet_threshold; 15116b6a0c9aSHuang Rui dwc->tx_de_emphasis = tx_de_emphasis; 151280caf7d2SHuang Rui 151316fe4f30SThinh Nguyen dwc->hird_threshold = hird_threshold; 1514460d098cSHuang Rui 1515938a5ad1SThinh Nguyen dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd; 1516938a5ad1SThinh Nguyen dwc->rx_max_burst_prd = rx_max_burst_prd; 1517938a5ad1SThinh Nguyen 1518938a5ad1SThinh Nguyen dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd; 1519938a5ad1SThinh Nguyen dwc->tx_max_burst_prd = tx_max_burst_prd; 1520938a5ad1SThinh Nguyen 1521cf40b86bSJohn Youn dwc->imod_interval = 0; 15229f607a30SWesley Cheng 15239f607a30SWesley Cheng dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num; 1524cf40b86bSJohn Youn } 1525cf40b86bSJohn Youn 1526cf40b86bSJohn Youn /* check whether the core supports IMOD */ 1527cf40b86bSJohn Youn bool dwc3_has_imod(struct dwc3 *dwc) 1528cf40b86bSJohn Youn { 15299af21dd6SThinh Nguyen return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) || 15309af21dd6SThinh Nguyen DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) || 15319af21dd6SThinh Nguyen DWC3_IP_IS(DWC32); 1532c5ac6116SFelipe Balbi } 1533c5ac6116SFelipe Balbi 15347ac51a12SJohn Youn static void dwc3_check_params(struct dwc3 *dwc) 15357ac51a12SJohn Youn { 15367ac51a12SJohn Youn struct device *dev = dwc->dev; 1537b574ce3eSThinh Nguyen unsigned int hwparam_gen = 1538b574ce3eSThinh Nguyen DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3); 15397ac51a12SJohn Youn 1540cf40b86bSJohn Youn /* Check for proper value of imod_interval */ 1541cf40b86bSJohn Youn if (dwc->imod_interval && !dwc3_has_imod(dwc)) { 1542cf40b86bSJohn Youn dev_warn(dwc->dev, "Interrupt moderation not supported\n"); 1543cf40b86bSJohn Youn dwc->imod_interval = 0; 1544cf40b86bSJohn Youn } 1545cf40b86bSJohn Youn 154628632b44SJohn Youn /* 154728632b44SJohn Youn * Workaround for STAR 9000961433 which affects only version 154828632b44SJohn Youn * 3.00a of the DWC_usb3 core. This prevents the controller 154928632b44SJohn Youn * interrupt from being masked while handling events. IMOD 155028632b44SJohn Youn * allows us to work around this issue. Enable it for the 155128632b44SJohn Youn * affected version. 155228632b44SJohn Youn */ 155328632b44SJohn Youn if (!dwc->imod_interval && 15549af21dd6SThinh Nguyen DWC3_VER_IS(DWC3, 300A)) 155528632b44SJohn Youn dwc->imod_interval = 1; 155628632b44SJohn Youn 15577ac51a12SJohn Youn /* Check the maximum_speed parameter */ 15587ac51a12SJohn Youn switch (dwc->maximum_speed) { 15597ac51a12SJohn Youn case USB_SPEED_FULL: 15607ac51a12SJohn Youn case USB_SPEED_HIGH: 1561e518bdd9SThinh Nguyen break; 15627ac51a12SJohn Youn case USB_SPEED_SUPER: 1563e518bdd9SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) 1564e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support Gen 1\n"); 1565e518bdd9SThinh Nguyen break; 15667ac51a12SJohn Youn case USB_SPEED_SUPER_PLUS: 1567e518bdd9SThinh Nguyen if ((DWC3_IP_IS(DWC32) && 1568e518bdd9SThinh Nguyen hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) || 1569e518bdd9SThinh Nguyen (!DWC3_IP_IS(DWC32) && 1570e518bdd9SThinh Nguyen hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2)) 1571e518bdd9SThinh Nguyen dev_warn(dev, "UDC doesn't support SSP\n"); 15727ac51a12SJohn Youn break; 15737ac51a12SJohn Youn default: 15747ac51a12SJohn Youn dev_err(dev, "invalid maximum_speed parameter %d\n", 15757ac51a12SJohn Youn dwc->maximum_speed); 1576df561f66SGustavo A. R. Silva fallthrough; 15777ac51a12SJohn Youn case USB_SPEED_UNKNOWN: 1578b574ce3eSThinh Nguyen switch (hwparam_gen) { 1579b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 15807ac51a12SJohn Youn dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1581b574ce3eSThinh Nguyen break; 1582b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 1583b574ce3eSThinh Nguyen if (DWC3_IP_IS(DWC32)) 1584b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER_PLUS; 1585b574ce3eSThinh Nguyen else 1586b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1587b574ce3eSThinh Nguyen break; 1588b574ce3eSThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_DIS: 1589b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_HIGH; 1590b574ce3eSThinh Nguyen break; 1591b574ce3eSThinh Nguyen default: 1592b574ce3eSThinh Nguyen dwc->maximum_speed = USB_SPEED_SUPER; 1593b574ce3eSThinh Nguyen break; 1594b574ce3eSThinh Nguyen } 15957ac51a12SJohn Youn break; 15967ac51a12SJohn Youn } 159767848146SThinh Nguyen 159867848146SThinh Nguyen /* 159967848146SThinh Nguyen * Currently the controller does not have visibility into the HW 160067848146SThinh Nguyen * parameter to determine the maximum number of lanes the HW supports. 160167848146SThinh Nguyen * If the number of lanes is not specified in the device property, then 160267848146SThinh Nguyen * set the default to support dual-lane for DWC_usb32 and single-lane 160367848146SThinh Nguyen * for DWC_usb31 for super-speed-plus. 160467848146SThinh Nguyen */ 160567848146SThinh Nguyen if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) { 160667848146SThinh Nguyen switch (dwc->max_ssp_rate) { 160767848146SThinh Nguyen case USB_SSP_GEN_2x1: 160867848146SThinh Nguyen if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1) 160967848146SThinh Nguyen dev_warn(dev, "UDC only supports Gen 1\n"); 161067848146SThinh Nguyen break; 161167848146SThinh Nguyen case USB_SSP_GEN_1x2: 161267848146SThinh Nguyen case USB_SSP_GEN_2x2: 161367848146SThinh Nguyen if (DWC3_IP_IS(DWC31)) 161467848146SThinh Nguyen dev_warn(dev, "UDC only supports single lane\n"); 161567848146SThinh Nguyen break; 161667848146SThinh Nguyen case USB_SSP_GEN_UNKNOWN: 161767848146SThinh Nguyen default: 161867848146SThinh Nguyen switch (hwparam_gen) { 161967848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2: 162067848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 162167848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x2; 162267848146SThinh Nguyen else 162367848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_2x1; 162467848146SThinh Nguyen break; 162567848146SThinh Nguyen case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1: 162667848146SThinh Nguyen if (DWC3_IP_IS(DWC32)) 162767848146SThinh Nguyen dwc->max_ssp_rate = USB_SSP_GEN_1x2; 162867848146SThinh Nguyen break; 162967848146SThinh Nguyen } 163067848146SThinh Nguyen break; 163167848146SThinh Nguyen } 163267848146SThinh Nguyen } 16337ac51a12SJohn Youn } 16347ac51a12SJohn Youn 1635c5ac6116SFelipe Balbi static int dwc3_probe(struct platform_device *pdev) 1636c5ac6116SFelipe Balbi { 1637c5ac6116SFelipe Balbi struct device *dev = &pdev->dev; 163844feb8e6SMasahiro Yamada struct resource *res, dwc_res; 1639c5ac6116SFelipe Balbi struct dwc3 *dwc; 1640c5ac6116SFelipe Balbi 1641c5ac6116SFelipe Balbi int ret; 1642c5ac6116SFelipe Balbi 1643c5ac6116SFelipe Balbi void __iomem *regs; 1644c5ac6116SFelipe Balbi 1645c5ac6116SFelipe Balbi dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 1646c5ac6116SFelipe Balbi if (!dwc) 1647c5ac6116SFelipe Balbi return -ENOMEM; 1648c5ac6116SFelipe Balbi 1649c5ac6116SFelipe Balbi dwc->dev = dev; 1650c5ac6116SFelipe Balbi 1651c5ac6116SFelipe Balbi res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1652c5ac6116SFelipe Balbi if (!res) { 1653c5ac6116SFelipe Balbi dev_err(dev, "missing memory resource\n"); 1654c5ac6116SFelipe Balbi return -ENODEV; 1655c5ac6116SFelipe Balbi } 1656c5ac6116SFelipe Balbi 1657c5ac6116SFelipe Balbi dwc->xhci_resources[0].start = res->start; 1658c5ac6116SFelipe Balbi dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + 1659c5ac6116SFelipe Balbi DWC3_XHCI_REGS_END; 1660c5ac6116SFelipe Balbi dwc->xhci_resources[0].flags = res->flags; 1661c5ac6116SFelipe Balbi dwc->xhci_resources[0].name = res->name; 1662c5ac6116SFelipe Balbi 1663c5ac6116SFelipe Balbi /* 1664c5ac6116SFelipe Balbi * Request memory region but exclude xHCI regs, 1665c5ac6116SFelipe Balbi * since it will be requested by the xhci-plat driver. 1666c5ac6116SFelipe Balbi */ 166744feb8e6SMasahiro Yamada dwc_res = *res; 166844feb8e6SMasahiro Yamada dwc_res.start += DWC3_GLOBALS_REGS_START; 166944feb8e6SMasahiro Yamada 167044feb8e6SMasahiro Yamada regs = devm_ioremap_resource(dev, &dwc_res); 167144feb8e6SMasahiro Yamada if (IS_ERR(regs)) 167244feb8e6SMasahiro Yamada return PTR_ERR(regs); 1673c5ac6116SFelipe Balbi 1674c5ac6116SFelipe Balbi dwc->regs = regs; 167544feb8e6SMasahiro Yamada dwc->regs_size = resource_size(&dwc_res); 1676c5ac6116SFelipe Balbi 1677c5ac6116SFelipe Balbi dwc3_get_properties(dwc); 1678c5ac6116SFelipe Balbi 167947ce4590SFabio Aiuto if (!dwc->sysdev_is_parent) { 168045d39448SSven Peter ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64)); 168145d39448SSven Peter if (ret) 168245d39448SSven Peter return ret; 168347ce4590SFabio Aiuto } 168445d39448SSven Peter 1685babbdfc9SYejune Deng dwc->reset = devm_reset_control_array_get_optional_shared(dev); 1686fe8abf33SMasahiro Yamada if (IS_ERR(dwc->reset)) 1687fe8abf33SMasahiro Yamada return PTR_ERR(dwc->reset); 1688fe8abf33SMasahiro Yamada 168961527777SHans de Goede if (dev->of_node) { 1690fe8abf33SMasahiro Yamada /* 169161527777SHans de Goede * Clocks are optional, but new DT platforms should support all 169261527777SHans de Goede * clocks as required by the DT-binding. 1693fe8abf33SMasahiro Yamada */ 169433fb697eSSean Anderson dwc->bus_clk = devm_clk_get_optional(dev, "bus_early"); 169533fb697eSSean Anderson if (IS_ERR(dwc->bus_clk)) 169633fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->bus_clk), 169733fb697eSSean Anderson "could not get bus clock\n"); 16980d3a9708SJohn Stultz 169933fb697eSSean Anderson dwc->ref_clk = devm_clk_get_optional(dev, "ref"); 170033fb697eSSean Anderson if (IS_ERR(dwc->ref_clk)) 170133fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->ref_clk), 170233fb697eSSean Anderson "could not get ref clock\n"); 170333fb697eSSean Anderson 170433fb697eSSean Anderson dwc->susp_clk = devm_clk_get_optional(dev, "suspend"); 170533fb697eSSean Anderson if (IS_ERR(dwc->susp_clk)) 170633fb697eSSean Anderson return dev_err_probe(dev, PTR_ERR(dwc->susp_clk), 170733fb697eSSean Anderson "could not get suspend clock\n"); 170861527777SHans de Goede } 1709fe8abf33SMasahiro Yamada 1710fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1711fe8abf33SMasahiro Yamada if (ret) 171203bf32bbSAndrey Smirnov return ret; 1713fe8abf33SMasahiro Yamada 171433fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1715fe8abf33SMasahiro Yamada if (ret) 1716fe8abf33SMasahiro Yamada goto assert_reset; 1717fe8abf33SMasahiro Yamada 1718dc1b5d9aSEnric Balletbo i Serra if (!dwc3_core_is_valid(dwc)) { 1719dc1b5d9aSEnric Balletbo i Serra dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); 1720dc1b5d9aSEnric Balletbo i Serra ret = -ENODEV; 1721dc1b5d9aSEnric Balletbo i Serra goto disable_clks; 1722dc1b5d9aSEnric Balletbo i Serra } 1723dc1b5d9aSEnric Balletbo i Serra 17246c89cce0SHeikki Krogerus platform_set_drvdata(pdev, dwc); 17252917e718SHeikki Krogerus dwc3_cache_hwparams(dwc); 17266c89cce0SHeikki Krogerus 172772246da4SFelipe Balbi spin_lock_init(&dwc->lock); 1728f88359e1SYu Chen mutex_init(&dwc->mutex); 172972246da4SFelipe Balbi 1730fc8bb91bSFelipe Balbi pm_runtime_set_active(dev); 1731fc8bb91bSFelipe Balbi pm_runtime_use_autosuspend(dev); 1732fc8bb91bSFelipe Balbi pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY); 1733802ca850SChanho Park pm_runtime_enable(dev); 173432808237SRoger Quadros ret = pm_runtime_get_sync(dev); 173532808237SRoger Quadros if (ret < 0) 173632808237SRoger Quadros goto err1; 173732808237SRoger Quadros 1738802ca850SChanho Park pm_runtime_forbid(dev); 173972246da4SFelipe Balbi 17403921426bSFelipe Balbi ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); 17413921426bSFelipe Balbi if (ret) { 17423921426bSFelipe Balbi dev_err(dwc->dev, "failed to allocate event buffers\n"); 17433921426bSFelipe Balbi ret = -ENOMEM; 174432808237SRoger Quadros goto err2; 17453921426bSFelipe Balbi } 17463921426bSFelipe Balbi 17479d6173e1SThinh Nguyen ret = dwc3_get_dr_mode(dwc); 17489d6173e1SThinh Nguyen if (ret) 17499d6173e1SThinh Nguyen goto err3; 175032a4a135SFelipe Balbi 1751c499ff71SFelipe Balbi ret = dwc3_alloc_scratch_buffers(dwc); 1752c499ff71SFelipe Balbi if (ret) 175332808237SRoger Quadros goto err3; 1754c499ff71SFelipe Balbi 175572246da4SFelipe Balbi ret = dwc3_core_init(dwc); 175672246da4SFelipe Balbi if (ret) { 17570c0a20f6SAndy Shevchenko dev_err_probe(dev, ret, "failed to initialize core\n"); 175832808237SRoger Quadros goto err4; 175972246da4SFelipe Balbi } 176072246da4SFelipe Balbi 17617ac51a12SJohn Youn dwc3_check_params(dwc); 176284524d12SMinas Harutyunyan dwc3_debugfs_init(dwc); 17632c7f1bd9SJohn Youn 17645f94adfeSFelipe Balbi ret = dwc3_core_init_mode(dwc); 17655f94adfeSFelipe Balbi if (ret) 176632808237SRoger Quadros goto err5; 176772246da4SFelipe Balbi 1768fc8bb91bSFelipe Balbi pm_runtime_put(dev); 176972246da4SFelipe Balbi 177072246da4SFelipe Balbi return 0; 177172246da4SFelipe Balbi 177232808237SRoger Quadros err5: 177384524d12SMinas Harutyunyan dwc3_debugfs_exit(dwc); 1774f122d33eSFelipe Balbi dwc3_event_buffers_cleanup(dwc); 177503c1fd62SLi Jun 177603c1fd62SLi Jun usb_phy_shutdown(dwc->usb2_phy); 177703c1fd62SLi Jun usb_phy_shutdown(dwc->usb3_phy); 177803c1fd62SLi Jun phy_exit(dwc->usb2_generic_phy); 177903c1fd62SLi Jun phy_exit(dwc->usb3_generic_phy); 178003c1fd62SLi Jun 178103c1fd62SLi Jun usb_phy_set_suspend(dwc->usb2_phy, 1); 178203c1fd62SLi Jun usb_phy_set_suspend(dwc->usb3_phy, 1); 178303c1fd62SLi Jun phy_power_off(dwc->usb2_generic_phy); 178403c1fd62SLi Jun phy_power_off(dwc->usb3_generic_phy); 178503c1fd62SLi Jun 178608fd9a82SAndy Shevchenko dwc3_ulpi_exit(dwc); 1787f122d33eSFelipe Balbi 178832808237SRoger Quadros err4: 1789c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 179072246da4SFelipe Balbi 179132808237SRoger Quadros err3: 17923921426bSFelipe Balbi dwc3_free_event_buffers(dwc); 17933921426bSFelipe Balbi 179432808237SRoger Quadros err2: 179532808237SRoger Quadros pm_runtime_allow(&pdev->dev); 179632808237SRoger Quadros 179732808237SRoger Quadros err1: 179832808237SRoger Quadros pm_runtime_put_sync(&pdev->dev); 179932808237SRoger Quadros pm_runtime_disable(&pdev->dev); 180032808237SRoger Quadros 1801dc1b5d9aSEnric Balletbo i Serra disable_clks: 180233fb697eSSean Anderson dwc3_clk_disable(dwc); 1803fe8abf33SMasahiro Yamada assert_reset: 1804fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1805fe8abf33SMasahiro Yamada 1806b0bf77cdSColin Ian King if (dwc->usb_psy) 18076f0764b5SRay Chi power_supply_put(dwc->usb_psy); 18086f0764b5SRay Chi 180972246da4SFelipe Balbi return ret; 181072246da4SFelipe Balbi } 181172246da4SFelipe Balbi 1812fb4e98abSBill Pemberton static int dwc3_remove(struct platform_device *pdev) 181372246da4SFelipe Balbi { 181472246da4SFelipe Balbi struct dwc3 *dwc = platform_get_drvdata(pdev); 18153da1f6eeSFelipe Balbi 1816fc8bb91bSFelipe Balbi pm_runtime_get_sync(&pdev->dev); 181772246da4SFelipe Balbi 1818dc99f16fSFelipe Balbi dwc3_core_exit_mode(dwc); 18192a042767SPeter Chen dwc3_debugfs_exit(dwc); 18208ba007a9SKishon Vijay Abraham I 182172246da4SFelipe Balbi dwc3_core_exit(dwc); 182288bc9d19SHeikki Krogerus dwc3_ulpi_exit(dwc); 182372246da4SFelipe Balbi 1824fc8bb91bSFelipe Balbi pm_runtime_disable(&pdev->dev); 1825266d0493SLi Jun pm_runtime_put_noidle(&pdev->dev); 1826266d0493SLi Jun pm_runtime_set_suspended(&pdev->dev); 1827fc8bb91bSFelipe Balbi 1828c499ff71SFelipe Balbi dwc3_free_event_buffers(dwc); 1829c499ff71SFelipe Balbi dwc3_free_scratch_buffers(dwc); 1830c499ff71SFelipe Balbi 1831b0bf77cdSColin Ian King if (dwc->usb_psy) 18326f0764b5SRay Chi power_supply_put(dwc->usb_psy); 18336f0764b5SRay Chi 183472246da4SFelipe Balbi return 0; 183572246da4SFelipe Balbi } 183672246da4SFelipe Balbi 1837fc8bb91bSFelipe Balbi #ifdef CONFIG_PM 1838fe8abf33SMasahiro Yamada static int dwc3_core_init_for_resume(struct dwc3 *dwc) 1839fe8abf33SMasahiro Yamada { 1840fe8abf33SMasahiro Yamada int ret; 1841fe8abf33SMasahiro Yamada 1842fe8abf33SMasahiro Yamada ret = reset_control_deassert(dwc->reset); 1843fe8abf33SMasahiro Yamada if (ret) 1844fe8abf33SMasahiro Yamada return ret; 1845fe8abf33SMasahiro Yamada 184633fb697eSSean Anderson ret = dwc3_clk_enable(dwc); 1847fe8abf33SMasahiro Yamada if (ret) 1848fe8abf33SMasahiro Yamada goto assert_reset; 1849fe8abf33SMasahiro Yamada 1850fe8abf33SMasahiro Yamada ret = dwc3_core_init(dwc); 1851fe8abf33SMasahiro Yamada if (ret) 1852fe8abf33SMasahiro Yamada goto disable_clks; 1853fe8abf33SMasahiro Yamada 1854fe8abf33SMasahiro Yamada return 0; 1855fe8abf33SMasahiro Yamada 1856fe8abf33SMasahiro Yamada disable_clks: 185733fb697eSSean Anderson dwc3_clk_disable(dwc); 1858fe8abf33SMasahiro Yamada assert_reset: 1859fe8abf33SMasahiro Yamada reset_control_assert(dwc->reset); 1860fe8abf33SMasahiro Yamada 1861fe8abf33SMasahiro Yamada return ret; 1862fe8abf33SMasahiro Yamada } 1863fe8abf33SMasahiro Yamada 1864c4a5153eSManu Gautam static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) 18657415f17cSFelipe Balbi { 1866fc8bb91bSFelipe Balbi unsigned long flags; 1867bcb12877SManu Gautam u32 reg; 18687415f17cSFelipe Balbi 1869689bf72cSManu Gautam switch (dwc->current_dr_role) { 1870689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 18710227cc84SLi Jun if (pm_runtime_suspended(dwc->dev)) 18720227cc84SLi Jun break; 1873fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 18747415f17cSFelipe Balbi dwc3_gadget_suspend(dwc); 1875fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 187641a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1877689bf72cSManu Gautam dwc3_core_exit(dwc); 187851f5d49aSFelipe Balbi break; 1879689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1880bcb12877SManu Gautam if (!PMSG_IS_AUTO(msg)) { 1881c4a5153eSManu Gautam dwc3_core_exit(dwc); 1882c4a5153eSManu Gautam break; 1883bcb12877SManu Gautam } 1884bcb12877SManu Gautam 1885bcb12877SManu Gautam /* Let controller to suspend HSPHY before PHY driver suspends */ 1886bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk || 1887bcb12877SManu Gautam dwc->dis_enblslpm_quirk) { 1888bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1889bcb12877SManu Gautam reg |= DWC3_GUSB2PHYCFG_ENBLSLPM | 1890bcb12877SManu Gautam DWC3_GUSB2PHYCFG_SUSPHY; 1891bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1892bcb12877SManu Gautam 1893bcb12877SManu Gautam /* Give some time for USB2 PHY to suspend */ 1894bcb12877SManu Gautam usleep_range(5000, 6000); 1895bcb12877SManu Gautam } 1896bcb12877SManu Gautam 1897bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb2_generic_phy); 1898bcb12877SManu Gautam phy_pm_runtime_put_sync(dwc->usb3_generic_phy); 1899bcb12877SManu Gautam break; 1900f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1901f09cc79bSRoger Quadros /* do nothing during runtime_suspend */ 1902f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1903f09cc79bSRoger Quadros break; 1904f09cc79bSRoger Quadros 1905f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1906f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1907f09cc79bSRoger Quadros dwc3_gadget_suspend(dwc); 1908f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 190941a91c60SMarek Szyprowski synchronize_irq(dwc->irq_gadget); 1910f09cc79bSRoger Quadros } 1911f09cc79bSRoger Quadros 1912f09cc79bSRoger Quadros dwc3_otg_exit(dwc); 1913f09cc79bSRoger Quadros dwc3_core_exit(dwc); 1914f09cc79bSRoger Quadros break; 19157415f17cSFelipe Balbi default: 191651f5d49aSFelipe Balbi /* do nothing */ 19177415f17cSFelipe Balbi break; 19187415f17cSFelipe Balbi } 19197415f17cSFelipe Balbi 1920fc8bb91bSFelipe Balbi return 0; 1921fc8bb91bSFelipe Balbi } 1922fc8bb91bSFelipe Balbi 1923c4a5153eSManu Gautam static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg) 1924fc8bb91bSFelipe Balbi { 1925fc8bb91bSFelipe Balbi unsigned long flags; 1926fc8bb91bSFelipe Balbi int ret; 1927bcb12877SManu Gautam u32 reg; 1928fc8bb91bSFelipe Balbi 1929689bf72cSManu Gautam switch (dwc->current_dr_role) { 1930689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1931fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1932fc8bb91bSFelipe Balbi if (ret) 1933fc8bb91bSFelipe Balbi return ret; 1934fc8bb91bSFelipe Balbi 19357d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE); 1936fc8bb91bSFelipe Balbi spin_lock_irqsave(&dwc->lock, flags); 1937fc8bb91bSFelipe Balbi dwc3_gadget_resume(dwc); 1938fc8bb91bSFelipe Balbi spin_unlock_irqrestore(&dwc->lock, flags); 1939689bf72cSManu Gautam break; 1940689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1941c4a5153eSManu Gautam if (!PMSG_IS_AUTO(msg)) { 1942fe8abf33SMasahiro Yamada ret = dwc3_core_init_for_resume(dwc); 1943c4a5153eSManu Gautam if (ret) 1944c4a5153eSManu Gautam return ret; 19457d11c3acSRoger Quadros dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST); 1946bcb12877SManu Gautam break; 1947c4a5153eSManu Gautam } 1948bcb12877SManu Gautam /* Restore GUSB2PHYCFG bits that were modified in suspend */ 1949bcb12877SManu Gautam reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 1950bcb12877SManu Gautam if (dwc->dis_u2_susphy_quirk) 1951bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 1952bcb12877SManu Gautam 1953bcb12877SManu Gautam if (dwc->dis_enblslpm_quirk) 1954bcb12877SManu Gautam reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 1955bcb12877SManu Gautam 1956bcb12877SManu Gautam dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 1957bcb12877SManu Gautam 1958bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb2_generic_phy); 1959bcb12877SManu Gautam phy_pm_runtime_get_sync(dwc->usb3_generic_phy); 1960c4a5153eSManu Gautam break; 1961f09cc79bSRoger Quadros case DWC3_GCTL_PRTCAP_OTG: 1962f09cc79bSRoger Quadros /* nothing to do on runtime_resume */ 1963f09cc79bSRoger Quadros if (PMSG_IS_AUTO(msg)) 1964f09cc79bSRoger Quadros break; 1965f09cc79bSRoger Quadros 19660e5a3c82SGary Bisson ret = dwc3_core_init_for_resume(dwc); 1967f09cc79bSRoger Quadros if (ret) 1968f09cc79bSRoger Quadros return ret; 1969f09cc79bSRoger Quadros 1970f09cc79bSRoger Quadros dwc3_set_prtcap(dwc, dwc->current_dr_role); 1971f09cc79bSRoger Quadros 1972f09cc79bSRoger Quadros dwc3_otg_init(dwc); 1973f09cc79bSRoger Quadros if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) { 1974f09cc79bSRoger Quadros dwc3_otg_host_init(dwc); 1975f09cc79bSRoger Quadros } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) { 1976f09cc79bSRoger Quadros spin_lock_irqsave(&dwc->lock, flags); 1977f09cc79bSRoger Quadros dwc3_gadget_resume(dwc); 1978f09cc79bSRoger Quadros spin_unlock_irqrestore(&dwc->lock, flags); 1979f09cc79bSRoger Quadros } 1980f09cc79bSRoger Quadros 1981f09cc79bSRoger Quadros break; 1982fc8bb91bSFelipe Balbi default: 1983fc8bb91bSFelipe Balbi /* do nothing */ 1984fc8bb91bSFelipe Balbi break; 1985fc8bb91bSFelipe Balbi } 1986fc8bb91bSFelipe Balbi 1987fc8bb91bSFelipe Balbi return 0; 1988fc8bb91bSFelipe Balbi } 1989fc8bb91bSFelipe Balbi 1990fc8bb91bSFelipe Balbi static int dwc3_runtime_checks(struct dwc3 *dwc) 1991fc8bb91bSFelipe Balbi { 1992689bf72cSManu Gautam switch (dwc->current_dr_role) { 1993c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 1994fc8bb91bSFelipe Balbi if (dwc->connected) 1995fc8bb91bSFelipe Balbi return -EBUSY; 1996fc8bb91bSFelipe Balbi break; 1997c4a5153eSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 1998fc8bb91bSFelipe Balbi default: 1999fc8bb91bSFelipe Balbi /* do nothing */ 2000fc8bb91bSFelipe Balbi break; 2001fc8bb91bSFelipe Balbi } 2002fc8bb91bSFelipe Balbi 2003fc8bb91bSFelipe Balbi return 0; 2004fc8bb91bSFelipe Balbi } 2005fc8bb91bSFelipe Balbi 2006fc8bb91bSFelipe Balbi static int dwc3_runtime_suspend(struct device *dev) 2007fc8bb91bSFelipe Balbi { 2008fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2009fc8bb91bSFelipe Balbi int ret; 2010fc8bb91bSFelipe Balbi 2011fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2012fc8bb91bSFelipe Balbi return -EBUSY; 2013fc8bb91bSFelipe Balbi 2014c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND); 2015fc8bb91bSFelipe Balbi if (ret) 2016fc8bb91bSFelipe Balbi return ret; 2017fc8bb91bSFelipe Balbi 2018fc8bb91bSFelipe Balbi device_init_wakeup(dev, true); 2019fc8bb91bSFelipe Balbi 2020fc8bb91bSFelipe Balbi return 0; 2021fc8bb91bSFelipe Balbi } 2022fc8bb91bSFelipe Balbi 2023fc8bb91bSFelipe Balbi static int dwc3_runtime_resume(struct device *dev) 2024fc8bb91bSFelipe Balbi { 2025fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2026fc8bb91bSFelipe Balbi int ret; 2027fc8bb91bSFelipe Balbi 2028fc8bb91bSFelipe Balbi device_init_wakeup(dev, false); 2029fc8bb91bSFelipe Balbi 2030c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME); 2031fc8bb91bSFelipe Balbi if (ret) 2032fc8bb91bSFelipe Balbi return ret; 2033fc8bb91bSFelipe Balbi 2034689bf72cSManu Gautam switch (dwc->current_dr_role) { 2035689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2036fc8bb91bSFelipe Balbi dwc3_gadget_process_pending_events(dwc); 2037fc8bb91bSFelipe Balbi break; 2038689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2039fc8bb91bSFelipe Balbi default: 2040fc8bb91bSFelipe Balbi /* do nothing */ 2041fc8bb91bSFelipe Balbi break; 2042fc8bb91bSFelipe Balbi } 2043fc8bb91bSFelipe Balbi 2044fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2045fc8bb91bSFelipe Balbi 2046fc8bb91bSFelipe Balbi return 0; 2047fc8bb91bSFelipe Balbi } 2048fc8bb91bSFelipe Balbi 2049fc8bb91bSFelipe Balbi static int dwc3_runtime_idle(struct device *dev) 2050fc8bb91bSFelipe Balbi { 2051fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2052fc8bb91bSFelipe Balbi 2053689bf72cSManu Gautam switch (dwc->current_dr_role) { 2054689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_DEVICE: 2055fc8bb91bSFelipe Balbi if (dwc3_runtime_checks(dwc)) 2056fc8bb91bSFelipe Balbi return -EBUSY; 2057fc8bb91bSFelipe Balbi break; 2058689bf72cSManu Gautam case DWC3_GCTL_PRTCAP_HOST: 2059fc8bb91bSFelipe Balbi default: 2060fc8bb91bSFelipe Balbi /* do nothing */ 2061fc8bb91bSFelipe Balbi break; 2062fc8bb91bSFelipe Balbi } 2063fc8bb91bSFelipe Balbi 2064fc8bb91bSFelipe Balbi pm_runtime_mark_last_busy(dev); 2065fc8bb91bSFelipe Balbi pm_runtime_autosuspend(dev); 2066fc8bb91bSFelipe Balbi 2067fc8bb91bSFelipe Balbi return 0; 2068fc8bb91bSFelipe Balbi } 2069fc8bb91bSFelipe Balbi #endif /* CONFIG_PM */ 2070fc8bb91bSFelipe Balbi 2071fc8bb91bSFelipe Balbi #ifdef CONFIG_PM_SLEEP 2072fc8bb91bSFelipe Balbi static int dwc3_suspend(struct device *dev) 2073fc8bb91bSFelipe Balbi { 2074fc8bb91bSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 2075fc8bb91bSFelipe Balbi int ret; 2076fc8bb91bSFelipe Balbi 2077c4a5153eSManu Gautam ret = dwc3_suspend_common(dwc, PMSG_SUSPEND); 2078fc8bb91bSFelipe Balbi if (ret) 2079fc8bb91bSFelipe Balbi return ret; 2080fc8bb91bSFelipe Balbi 20816344475fSSekhar Nori pinctrl_pm_select_sleep_state(dev); 20826344475fSSekhar Nori 20837415f17cSFelipe Balbi return 0; 20847415f17cSFelipe Balbi } 20857415f17cSFelipe Balbi 20867415f17cSFelipe Balbi static int dwc3_resume(struct device *dev) 20877415f17cSFelipe Balbi { 20887415f17cSFelipe Balbi struct dwc3 *dwc = dev_get_drvdata(dev); 208957303488SKishon Vijay Abraham I int ret; 20907415f17cSFelipe Balbi 20916344475fSSekhar Nori pinctrl_pm_select_default_state(dev); 20926344475fSSekhar Nori 2093c4a5153eSManu Gautam ret = dwc3_resume_common(dwc, PMSG_RESUME); 209451f5d49aSFelipe Balbi if (ret) 20955c4ad318SFelipe Balbi return ret; 20965c4ad318SFelipe Balbi 20977415f17cSFelipe Balbi pm_runtime_disable(dev); 20987415f17cSFelipe Balbi pm_runtime_set_active(dev); 20997415f17cSFelipe Balbi pm_runtime_enable(dev); 21007415f17cSFelipe Balbi 21017415f17cSFelipe Balbi return 0; 21027415f17cSFelipe Balbi } 2103f580170fSYu Chen 2104f580170fSYu Chen static void dwc3_complete(struct device *dev) 2105f580170fSYu Chen { 2106f580170fSYu Chen struct dwc3 *dwc = dev_get_drvdata(dev); 2107f580170fSYu Chen u32 reg; 2108f580170fSYu Chen 2109f580170fSYu Chen if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST && 2110f580170fSYu Chen dwc->dis_split_quirk) { 2111f580170fSYu Chen reg = dwc3_readl(dwc->regs, DWC3_GUCTL3); 2112f580170fSYu Chen reg |= DWC3_GUCTL3_SPLITDISABLE; 2113f580170fSYu Chen dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); 2114f580170fSYu Chen } 2115f580170fSYu Chen } 2116f580170fSYu Chen #else 2117f580170fSYu Chen #define dwc3_complete NULL 21187f370ed0SFelipe Balbi #endif /* CONFIG_PM_SLEEP */ 21197415f17cSFelipe Balbi 21207415f17cSFelipe Balbi static const struct dev_pm_ops dwc3_dev_pm_ops = { 21217415f17cSFelipe Balbi SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) 2122f580170fSYu Chen .complete = dwc3_complete, 2123fc8bb91bSFelipe Balbi SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, 2124fc8bb91bSFelipe Balbi dwc3_runtime_idle) 21257415f17cSFelipe Balbi }; 21267415f17cSFelipe Balbi 21275088b6f5SKishon Vijay Abraham I #ifdef CONFIG_OF 21285088b6f5SKishon Vijay Abraham I static const struct of_device_id of_dwc3_match[] = { 21295088b6f5SKishon Vijay Abraham I { 213022a5aa17SFelipe Balbi .compatible = "snps,dwc3" 213122a5aa17SFelipe Balbi }, 213222a5aa17SFelipe Balbi { 21335088b6f5SKishon Vijay Abraham I .compatible = "synopsys,dwc3" 21345088b6f5SKishon Vijay Abraham I }, 21355088b6f5SKishon Vijay Abraham I { }, 21365088b6f5SKishon Vijay Abraham I }; 21375088b6f5SKishon Vijay Abraham I MODULE_DEVICE_TABLE(of, of_dwc3_match); 21385088b6f5SKishon Vijay Abraham I #endif 21395088b6f5SKishon Vijay Abraham I 2140404905a6SHeikki Krogerus #ifdef CONFIG_ACPI 2141404905a6SHeikki Krogerus 2142404905a6SHeikki Krogerus #define ACPI_ID_INTEL_BSW "808622B7" 2143404905a6SHeikki Krogerus 2144404905a6SHeikki Krogerus static const struct acpi_device_id dwc3_acpi_match[] = { 2145404905a6SHeikki Krogerus { ACPI_ID_INTEL_BSW, 0 }, 2146404905a6SHeikki Krogerus { }, 2147404905a6SHeikki Krogerus }; 2148404905a6SHeikki Krogerus MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match); 2149404905a6SHeikki Krogerus #endif 2150404905a6SHeikki Krogerus 215172246da4SFelipe Balbi static struct platform_driver dwc3_driver = { 215272246da4SFelipe Balbi .probe = dwc3_probe, 21537690417dSBill Pemberton .remove = dwc3_remove, 215472246da4SFelipe Balbi .driver = { 215572246da4SFelipe Balbi .name = "dwc3", 21565088b6f5SKishon Vijay Abraham I .of_match_table = of_match_ptr(of_dwc3_match), 2157404905a6SHeikki Krogerus .acpi_match_table = ACPI_PTR(dwc3_acpi_match), 21587f370ed0SFelipe Balbi .pm = &dwc3_dev_pm_ops, 215972246da4SFelipe Balbi }, 216072246da4SFelipe Balbi }; 216172246da4SFelipe Balbi 2162b1116dccSTobias Klauser module_platform_driver(dwc3_driver); 2163b1116dccSTobias Klauser 21647ae4fc4dSSebastian Andrzej Siewior MODULE_ALIAS("platform:dwc3"); 216572246da4SFelipe Balbi MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 21665945f789SFelipe Balbi MODULE_LICENSE("GPL v2"); 216772246da4SFelipe Balbi MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); 2168