1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * platform.c - DesignWare HS OTG Controller platform driver 4 * 5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/of_device.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_data/s3c-hsotg.h> 19 #include <linux/reset.h> 20 21 #include <linux/usb/of.h> 22 23 #include "core.h" 24 #include "hcd.h" 25 #include "debug.h" 26 27 static const char dwc2_driver_name[] = "dwc2"; 28 29 /* 30 * Check the dr_mode against the module configuration and hardware 31 * capabilities. 32 * 33 * The hardware, module, and dr_mode, can each be set to host, device, 34 * or otg. Check that all these values are compatible and adjust the 35 * value of dr_mode if possible. 36 * 37 * actual 38 * HW MOD dr_mode dr_mode 39 * ------------------------------ 40 * HST HST any : HST 41 * HST DEV any : --- 42 * HST OTG any : HST 43 * 44 * DEV HST any : --- 45 * DEV DEV any : DEV 46 * DEV OTG any : DEV 47 * 48 * OTG HST any : HST 49 * OTG DEV any : DEV 50 * OTG OTG any : dr_mode 51 */ 52 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) 53 { 54 enum usb_dr_mode mode; 55 56 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); 57 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) 58 hsotg->dr_mode = USB_DR_MODE_OTG; 59 60 mode = hsotg->dr_mode; 61 62 if (dwc2_hw_is_device(hsotg)) { 63 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { 64 dev_err(hsotg->dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 } else if (dwc2_hw_is_host(hsotg)) { 70 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { 71 dev_err(hsotg->dev, 72 "Controller does not support device mode.\n"); 73 return -EINVAL; 74 } 75 mode = USB_DR_MODE_HOST; 76 } else { 77 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 } 82 83 if (mode != hsotg->dr_mode) { 84 dev_warn(hsotg->dev, 85 "Configuration mismatch. dr_mode forced to %s\n", 86 mode == USB_DR_MODE_HOST ? "host" : "device"); 87 88 hsotg->dr_mode = mode; 89 } 90 91 return 0; 92 } 93 94 static void __dwc2_disable_regulators(void *data) 95 { 96 struct dwc2_hsotg *hsotg = data; 97 98 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); 99 } 100 101 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 102 { 103 struct platform_device *pdev = to_platform_device(hsotg->dev); 104 int ret; 105 106 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), 107 hsotg->supplies); 108 if (ret) 109 return ret; 110 111 ret = devm_add_action_or_reset(&pdev->dev, 112 __dwc2_disable_regulators, hsotg); 113 if (ret) 114 return ret; 115 116 if (hsotg->clk) { 117 ret = clk_prepare_enable(hsotg->clk); 118 if (ret) 119 return ret; 120 } 121 122 if (hsotg->uphy) { 123 ret = usb_phy_init(hsotg->uphy); 124 } else if (hsotg->plat && hsotg->plat->phy_init) { 125 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); 126 } else { 127 ret = phy_init(hsotg->phy); 128 if (ret == 0) 129 ret = phy_power_on(hsotg->phy); 130 } 131 132 return ret; 133 } 134 135 /** 136 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources 137 * @hsotg: The driver state 138 * 139 * A wrapper for platform code responsible for controlling 140 * low-level USB platform resources (phy, clock, regulators) 141 */ 142 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 143 { 144 int ret = __dwc2_lowlevel_hw_enable(hsotg); 145 146 if (ret == 0) 147 hsotg->ll_hw_enabled = true; 148 return ret; 149 } 150 151 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 152 { 153 struct platform_device *pdev = to_platform_device(hsotg->dev); 154 int ret = 0; 155 156 if (hsotg->uphy) { 157 usb_phy_shutdown(hsotg->uphy); 158 } else if (hsotg->plat && hsotg->plat->phy_exit) { 159 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); 160 } else { 161 ret = phy_power_off(hsotg->phy); 162 if (ret == 0) 163 ret = phy_exit(hsotg->phy); 164 } 165 if (ret) 166 return ret; 167 168 if (hsotg->clk) 169 clk_disable_unprepare(hsotg->clk); 170 171 return 0; 172 } 173 174 /** 175 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources 176 * @hsotg: The driver state 177 * 178 * A wrapper for platform code responsible for controlling 179 * low-level USB platform resources (phy, clock, regulators) 180 */ 181 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 182 { 183 int ret = __dwc2_lowlevel_hw_disable(hsotg); 184 185 if (ret == 0) 186 hsotg->ll_hw_enabled = false; 187 return ret; 188 } 189 190 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) 191 { 192 int i, ret; 193 194 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); 195 if (IS_ERR(hsotg->reset)) 196 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset), 197 "error getting reset control\n"); 198 199 reset_control_deassert(hsotg->reset); 200 201 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); 202 if (IS_ERR(hsotg->reset_ecc)) 203 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc), 204 "error getting reset control for ecc\n"); 205 206 reset_control_deassert(hsotg->reset_ecc); 207 208 /* 209 * Attempt to find a generic PHY, then look for an old style 210 * USB PHY and then fall back to pdata 211 */ 212 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); 213 if (IS_ERR(hsotg->phy)) { 214 ret = PTR_ERR(hsotg->phy); 215 switch (ret) { 216 case -ENODEV: 217 case -ENOSYS: 218 hsotg->phy = NULL; 219 break; 220 default: 221 return dev_err_probe(hsotg->dev, ret, "error getting phy\n"); 222 } 223 } 224 225 if (!hsotg->phy) { 226 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); 227 if (IS_ERR(hsotg->uphy)) { 228 ret = PTR_ERR(hsotg->uphy); 229 switch (ret) { 230 case -ENODEV: 231 case -ENXIO: 232 hsotg->uphy = NULL; 233 break; 234 default: 235 return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n"); 236 } 237 } 238 } 239 240 hsotg->plat = dev_get_platdata(hsotg->dev); 241 242 /* Clock */ 243 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); 244 if (IS_ERR(hsotg->clk)) 245 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n"); 246 247 /* Regulators */ 248 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) 249 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; 250 251 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), 252 hsotg->supplies); 253 if (ret) 254 return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n"); 255 256 return 0; 257 } 258 259 /** 260 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the 261 * DWC_otg driver 262 * 263 * @dev: Platform device 264 * 265 * This routine is called, for example, when the rmmod command is executed. The 266 * device may or may not be electrically present. If it is present, the driver 267 * stops device processing. Any resources used on behalf of this device are 268 * freed. 269 */ 270 static int dwc2_driver_remove(struct platform_device *dev) 271 { 272 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 273 struct dwc2_gregs_backup *gr; 274 int ret = 0; 275 276 gr = &hsotg->gr_backup; 277 278 /* Exit Hibernation when driver is removed. */ 279 if (hsotg->hibernated) { 280 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 281 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 282 else 283 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0); 284 285 if (ret) 286 dev_err(hsotg->dev, 287 "exit hibernation failed.\n"); 288 } 289 290 /* Exit Partial Power Down when driver is removed. */ 291 if (hsotg->in_ppd) { 292 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 293 if (ret) 294 dev_err(hsotg->dev, 295 "exit partial_power_down failed\n"); 296 } 297 298 /* Exit clock gating when driver is removed. */ 299 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && 300 hsotg->bus_suspended) { 301 if (dwc2_is_device_mode(hsotg)) 302 dwc2_gadget_exit_clock_gating(hsotg, 0); 303 else 304 dwc2_host_exit_clock_gating(hsotg, 0); 305 } 306 307 dwc2_debugfs_exit(hsotg); 308 if (hsotg->hcd_enabled) 309 dwc2_hcd_remove(hsotg); 310 if (hsotg->gadget_enabled) 311 dwc2_hsotg_remove(hsotg); 312 313 dwc2_drd_exit(hsotg); 314 315 if (hsotg->params.activate_stm_id_vb_detection) 316 regulator_disable(hsotg->usb33d); 317 318 if (hsotg->ll_hw_enabled) 319 dwc2_lowlevel_hw_disable(hsotg); 320 321 reset_control_assert(hsotg->reset); 322 reset_control_assert(hsotg->reset_ecc); 323 324 return ret; 325 } 326 327 /** 328 * dwc2_driver_shutdown() - Called on device shutdown 329 * 330 * @dev: Platform device 331 * 332 * In specific conditions (involving usb hubs) dwc2 devices can create a 333 * lot of interrupts, even to the point of overwhelming devices running 334 * at low frequencies. Some devices need to do special clock handling 335 * at shutdown-time which may bring the system clock below the threshold 336 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs 337 * prevents reboots/poweroffs from getting stuck in such cases. 338 */ 339 static void dwc2_driver_shutdown(struct platform_device *dev) 340 { 341 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 342 343 dwc2_disable_global_interrupts(hsotg); 344 synchronize_irq(hsotg->irq); 345 } 346 347 /** 348 * dwc2_check_core_endianness() - Returns true if core and AHB have 349 * opposite endianness. 350 * @hsotg: Programming view of the DWC_otg controller. 351 */ 352 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) 353 { 354 u32 snpsid; 355 356 snpsid = ioread32(hsotg->regs + GSNPSID); 357 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || 358 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || 359 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) 360 return false; 361 return true; 362 } 363 364 /** 365 * dwc2_check_core_version() - Check core version 366 * 367 * @hsotg: Programming view of the DWC_otg controller 368 * 369 */ 370 int dwc2_check_core_version(struct dwc2_hsotg *hsotg) 371 { 372 struct dwc2_hw_params *hw = &hsotg->hw_params; 373 374 /* 375 * Attempt to ensure this device is really a DWC_otg Controller. 376 * Read and verify the GSNPSID register contents. The value should be 377 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 378 */ 379 380 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 381 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 382 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 383 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 384 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 385 hw->snpsid); 386 return -ENODEV; 387 } 388 389 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 390 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 391 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 392 return 0; 393 } 394 395 /** 396 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 397 * driver 398 * 399 * @dev: Platform device 400 * 401 * This routine creates the driver components required to control the device 402 * (core, HCD, and PCD) and initializes the device. The driver components are 403 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved 404 * in the device private data. This allows the driver to access the dwc2_hsotg 405 * structure on subsequent calls to driver methods for this device. 406 */ 407 static int dwc2_driver_probe(struct platform_device *dev) 408 { 409 struct dwc2_hsotg *hsotg; 410 struct resource *res; 411 int retval; 412 413 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); 414 if (!hsotg) 415 return -ENOMEM; 416 417 hsotg->dev = &dev->dev; 418 419 /* 420 * Use reasonable defaults so platforms don't have to provide these. 421 */ 422 if (!dev->dev.dma_mask) 423 dev->dev.dma_mask = &dev->dev.coherent_dma_mask; 424 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 425 if (retval) { 426 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); 427 return retval; 428 } 429 430 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res); 431 if (IS_ERR(hsotg->regs)) 432 return PTR_ERR(hsotg->regs); 433 434 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 435 (unsigned long)res->start, hsotg->regs); 436 437 retval = dwc2_lowlevel_hw_init(hsotg); 438 if (retval) 439 return retval; 440 441 spin_lock_init(&hsotg->lock); 442 443 hsotg->irq = platform_get_irq(dev, 0); 444 if (hsotg->irq < 0) 445 return hsotg->irq; 446 447 dev_dbg(hsotg->dev, "registering common handler for irq%d\n", 448 hsotg->irq); 449 retval = devm_request_irq(hsotg->dev, hsotg->irq, 450 dwc2_handle_common_intr, IRQF_SHARED, 451 dev_name(hsotg->dev), hsotg); 452 if (retval) 453 return retval; 454 455 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); 456 if (IS_ERR(hsotg->vbus_supply)) { 457 retval = PTR_ERR(hsotg->vbus_supply); 458 hsotg->vbus_supply = NULL; 459 if (retval != -ENODEV) 460 return retval; 461 } 462 463 retval = dwc2_lowlevel_hw_enable(hsotg); 464 if (retval) 465 return retval; 466 467 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); 468 469 retval = dwc2_get_dr_mode(hsotg); 470 if (retval) 471 goto error; 472 473 hsotg->need_phy_for_wake = 474 of_property_read_bool(dev->dev.of_node, 475 "snps,need-phy-for-wake"); 476 477 /* 478 * Before performing any core related operations 479 * check core version. 480 */ 481 retval = dwc2_check_core_version(hsotg); 482 if (retval) 483 goto error; 484 485 /* 486 * Reset before dwc2_get_hwparams() then it could get power-on real 487 * reset value form registers. 488 */ 489 retval = dwc2_core_reset(hsotg, false); 490 if (retval) 491 goto error; 492 493 /* Detect config values from hardware */ 494 retval = dwc2_get_hwparams(hsotg); 495 if (retval) 496 goto error; 497 498 /* 499 * For OTG cores, set the force mode bits to reflect the value 500 * of dr_mode. Force mode bits should not be touched at any 501 * other time after this. 502 */ 503 dwc2_force_dr_mode(hsotg); 504 505 retval = dwc2_init_params(hsotg); 506 if (retval) 507 goto error; 508 509 if (hsotg->params.activate_stm_id_vb_detection) { 510 u32 ggpio; 511 512 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d"); 513 if (IS_ERR(hsotg->usb33d)) { 514 retval = PTR_ERR(hsotg->usb33d); 515 dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n"); 516 goto error; 517 } 518 retval = regulator_enable(hsotg->usb33d); 519 if (retval) { 520 dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n"); 521 goto error; 522 } 523 524 ggpio = dwc2_readl(hsotg, GGPIO); 525 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 526 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 527 dwc2_writel(hsotg, ggpio, GGPIO); 528 529 /* ID/VBUS detection startup time */ 530 usleep_range(5000, 7000); 531 } 532 533 retval = dwc2_drd_init(hsotg); 534 if (retval) { 535 dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n"); 536 goto error_init; 537 } 538 539 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 540 retval = dwc2_gadget_init(hsotg); 541 if (retval) 542 goto error_drd; 543 hsotg->gadget_enabled = 1; 544 } 545 546 /* 547 * If we need PHY for wakeup we must be wakeup capable. 548 * When we have a device that can wake without the PHY we 549 * can adjust this condition. 550 */ 551 if (hsotg->need_phy_for_wake) 552 device_set_wakeup_capable(&dev->dev, true); 553 554 hsotg->reset_phy_on_wake = 555 of_property_read_bool(dev->dev.of_node, 556 "snps,reset-phy-on-wake"); 557 if (hsotg->reset_phy_on_wake && !hsotg->phy) { 558 dev_warn(hsotg->dev, 559 "Quirk reset-phy-on-wake only supports generic PHYs\n"); 560 hsotg->reset_phy_on_wake = false; 561 } 562 563 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 564 retval = dwc2_hcd_init(hsotg); 565 if (retval) { 566 if (hsotg->gadget_enabled) 567 dwc2_hsotg_remove(hsotg); 568 goto error_drd; 569 } 570 hsotg->hcd_enabled = 1; 571 } 572 573 platform_set_drvdata(dev, hsotg); 574 hsotg->hibernated = 0; 575 576 dwc2_debugfs_init(hsotg); 577 578 /* Gadget code manages lowlevel hw on its own */ 579 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 580 dwc2_lowlevel_hw_disable(hsotg); 581 582 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 583 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 584 /* Postponed adding a new gadget to the udc class driver list */ 585 if (hsotg->gadget_enabled) { 586 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget); 587 if (retval) { 588 hsotg->gadget.udc = NULL; 589 dwc2_hsotg_remove(hsotg); 590 goto error_debugfs; 591 } 592 } 593 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 594 return 0; 595 596 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 597 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 598 error_debugfs: 599 dwc2_debugfs_exit(hsotg); 600 if (hsotg->hcd_enabled) 601 dwc2_hcd_remove(hsotg); 602 #endif 603 error_drd: 604 dwc2_drd_exit(hsotg); 605 606 error_init: 607 if (hsotg->params.activate_stm_id_vb_detection) 608 regulator_disable(hsotg->usb33d); 609 error: 610 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) 611 dwc2_lowlevel_hw_disable(hsotg); 612 return retval; 613 } 614 615 static int __maybe_unused dwc2_suspend(struct device *dev) 616 { 617 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 618 bool is_device_mode = dwc2_is_device_mode(dwc2); 619 int ret = 0; 620 621 if (is_device_mode) 622 dwc2_hsotg_suspend(dwc2); 623 624 dwc2_drd_suspend(dwc2); 625 626 if (dwc2->params.activate_stm_id_vb_detection) { 627 unsigned long flags; 628 u32 ggpio, gotgctl; 629 630 /* 631 * Need to force the mode to the current mode to avoid Mode 632 * Mismatch Interrupt when ID detection will be disabled. 633 */ 634 dwc2_force_mode(dwc2, !is_device_mode); 635 636 spin_lock_irqsave(&dwc2->lock, flags); 637 gotgctl = dwc2_readl(dwc2, GOTGCTL); 638 /* bypass debounce filter, enable overrides */ 639 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS; 640 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN; 641 /* Force A / B session if needed */ 642 if (gotgctl & GOTGCTL_ASESVLD) 643 gotgctl |= GOTGCTL_AVALOVAL; 644 if (gotgctl & GOTGCTL_BSESVLD) 645 gotgctl |= GOTGCTL_BVALOVAL; 646 dwc2_writel(dwc2, gotgctl, GOTGCTL); 647 spin_unlock_irqrestore(&dwc2->lock, flags); 648 649 ggpio = dwc2_readl(dwc2, GGPIO); 650 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN; 651 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN; 652 dwc2_writel(dwc2, ggpio, GGPIO); 653 654 regulator_disable(dwc2->usb33d); 655 } 656 657 if (dwc2->ll_hw_enabled && 658 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { 659 ret = __dwc2_lowlevel_hw_disable(dwc2); 660 dwc2->phy_off_for_suspend = true; 661 } 662 663 return ret; 664 } 665 666 static int __maybe_unused dwc2_resume(struct device *dev) 667 { 668 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 669 int ret = 0; 670 671 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { 672 ret = __dwc2_lowlevel_hw_enable(dwc2); 673 if (ret) 674 return ret; 675 } 676 dwc2->phy_off_for_suspend = false; 677 678 if (dwc2->params.activate_stm_id_vb_detection) { 679 unsigned long flags; 680 u32 ggpio, gotgctl; 681 682 ret = regulator_enable(dwc2->usb33d); 683 if (ret) 684 return ret; 685 686 ggpio = dwc2_readl(dwc2, GGPIO); 687 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 688 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 689 dwc2_writel(dwc2, ggpio, GGPIO); 690 691 /* ID/VBUS detection startup time */ 692 usleep_range(5000, 7000); 693 694 spin_lock_irqsave(&dwc2->lock, flags); 695 gotgctl = dwc2_readl(dwc2, GOTGCTL); 696 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS; 697 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | 698 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL); 699 dwc2_writel(dwc2, gotgctl, GOTGCTL); 700 spin_unlock_irqrestore(&dwc2->lock, flags); 701 } 702 703 if (!dwc2->role_sw) { 704 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */ 705 dwc2_force_dr_mode(dwc2); 706 } else { 707 dwc2_drd_resume(dwc2); 708 } 709 710 if (dwc2_is_device_mode(dwc2)) 711 ret = dwc2_hsotg_resume(dwc2); 712 713 return ret; 714 } 715 716 static const struct dev_pm_ops dwc2_dev_pm_ops = { 717 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) 718 }; 719 720 static struct platform_driver dwc2_platform_driver = { 721 .driver = { 722 .name = dwc2_driver_name, 723 .of_match_table = dwc2_of_match_table, 724 .acpi_match_table = ACPI_PTR(dwc2_acpi_match), 725 .pm = &dwc2_dev_pm_ops, 726 }, 727 .probe = dwc2_driver_probe, 728 .remove = dwc2_driver_remove, 729 .shutdown = dwc2_driver_shutdown, 730 }; 731 732 module_platform_driver(dwc2_platform_driver); 733