xref: /openbmc/linux/drivers/usb/dwc2/platform.c (revision 8365a898)
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * platform.c - DesignWare HS OTG Controller platform driver
4  *
5  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The names of the above-listed copyright holders may not be used
17  *    to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * ALTERNATIVELY, this software may be distributed under the terms of the
21  * GNU General Public License ("GPL") as published by the Free Software
22  * Foundation; either version 2 of the License, or (at your option) any
23  * later version.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
41 #include <linux/clk.h>
42 #include <linux/device.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/of_device.h>
45 #include <linux/mutex.h>
46 #include <linux/platform_device.h>
47 #include <linux/phy/phy.h>
48 #include <linux/platform_data/s3c-hsotg.h>
49 #include <linux/reset.h>
50 
51 #include <linux/usb/of.h>
52 
53 #include "core.h"
54 #include "hcd.h"
55 #include "debug.h"
56 
57 static const char dwc2_driver_name[] = "dwc2";
58 
59 /*
60  * Check the dr_mode against the module configuration and hardware
61  * capabilities.
62  *
63  * The hardware, module, and dr_mode, can each be set to host, device,
64  * or otg. Check that all these values are compatible and adjust the
65  * value of dr_mode if possible.
66  *
67  *                      actual
68  *    HW  MOD dr_mode   dr_mode
69  *  ------------------------------
70  *   HST  HST  any    :  HST
71  *   HST  DEV  any    :  ---
72  *   HST  OTG  any    :  HST
73  *
74  *   DEV  HST  any    :  ---
75  *   DEV  DEV  any    :  DEV
76  *   DEV  OTG  any    :  DEV
77  *
78  *   OTG  HST  any    :  HST
79  *   OTG  DEV  any    :  DEV
80  *   OTG  OTG  any    :  dr_mode
81  */
82 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg)
83 {
84 	enum usb_dr_mode mode;
85 
86 	hsotg->dr_mode = usb_get_dr_mode(hsotg->dev);
87 	if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN)
88 		hsotg->dr_mode = USB_DR_MODE_OTG;
89 
90 	mode = hsotg->dr_mode;
91 
92 	if (dwc2_hw_is_device(hsotg)) {
93 		if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) {
94 			dev_err(hsotg->dev,
95 				"Controller does not support host mode.\n");
96 			return -EINVAL;
97 		}
98 		mode = USB_DR_MODE_PERIPHERAL;
99 	} else if (dwc2_hw_is_host(hsotg)) {
100 		if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) {
101 			dev_err(hsotg->dev,
102 				"Controller does not support device mode.\n");
103 			return -EINVAL;
104 		}
105 		mode = USB_DR_MODE_HOST;
106 	} else {
107 		if (IS_ENABLED(CONFIG_USB_DWC2_HOST))
108 			mode = USB_DR_MODE_HOST;
109 		else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL))
110 			mode = USB_DR_MODE_PERIPHERAL;
111 	}
112 
113 	if (mode != hsotg->dr_mode) {
114 		dev_warn(hsotg->dev,
115 			 "Configuration mismatch. dr_mode forced to %s\n",
116 			mode == USB_DR_MODE_HOST ? "host" : "device");
117 
118 		hsotg->dr_mode = mode;
119 	}
120 
121 	return 0;
122 }
123 
124 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
125 {
126 	struct platform_device *pdev = to_platform_device(hsotg->dev);
127 	int ret;
128 
129 	ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
130 				    hsotg->supplies);
131 	if (ret)
132 		return ret;
133 
134 	if (hsotg->clk) {
135 		ret = clk_prepare_enable(hsotg->clk);
136 		if (ret)
137 			return ret;
138 	}
139 
140 	if (hsotg->uphy) {
141 		ret = usb_phy_init(hsotg->uphy);
142 	} else if (hsotg->plat && hsotg->plat->phy_init) {
143 		ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
144 	} else {
145 		ret = phy_power_on(hsotg->phy);
146 		if (ret == 0)
147 			ret = phy_init(hsotg->phy);
148 	}
149 
150 	return ret;
151 }
152 
153 /**
154  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
155  * @hsotg: The driver state
156  *
157  * A wrapper for platform code responsible for controlling
158  * low-level USB platform resources (phy, clock, regulators)
159  */
160 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
161 {
162 	int ret = __dwc2_lowlevel_hw_enable(hsotg);
163 
164 	if (ret == 0)
165 		hsotg->ll_hw_enabled = true;
166 	return ret;
167 }
168 
169 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
170 {
171 	struct platform_device *pdev = to_platform_device(hsotg->dev);
172 	int ret = 0;
173 
174 	if (hsotg->uphy) {
175 		usb_phy_shutdown(hsotg->uphy);
176 	} else if (hsotg->plat && hsotg->plat->phy_exit) {
177 		ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
178 	} else {
179 		ret = phy_exit(hsotg->phy);
180 		if (ret == 0)
181 			ret = phy_power_off(hsotg->phy);
182 	}
183 	if (ret)
184 		return ret;
185 
186 	if (hsotg->clk)
187 		clk_disable_unprepare(hsotg->clk);
188 
189 	ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
190 				     hsotg->supplies);
191 
192 	return ret;
193 }
194 
195 /**
196  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
197  * @hsotg: The driver state
198  *
199  * A wrapper for platform code responsible for controlling
200  * low-level USB platform resources (phy, clock, regulators)
201  */
202 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
203 {
204 	int ret = __dwc2_lowlevel_hw_disable(hsotg);
205 
206 	if (ret == 0)
207 		hsotg->ll_hw_enabled = false;
208 	return ret;
209 }
210 
211 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
212 {
213 	int i, ret;
214 
215 	hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
216 	if (IS_ERR(hsotg->reset)) {
217 		ret = PTR_ERR(hsotg->reset);
218 		dev_err(hsotg->dev, "error getting reset control %d\n", ret);
219 		return ret;
220 	}
221 
222 	reset_control_deassert(hsotg->reset);
223 
224 	hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc");
225 	if (IS_ERR(hsotg->reset_ecc)) {
226 		ret = PTR_ERR(hsotg->reset_ecc);
227 		dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret);
228 		return ret;
229 	}
230 
231 	reset_control_deassert(hsotg->reset_ecc);
232 
233 	/*
234 	 * Attempt to find a generic PHY, then look for an old style
235 	 * USB PHY and then fall back to pdata
236 	 */
237 	hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
238 	if (IS_ERR(hsotg->phy)) {
239 		ret = PTR_ERR(hsotg->phy);
240 		switch (ret) {
241 		case -ENODEV:
242 		case -ENOSYS:
243 			hsotg->phy = NULL;
244 			break;
245 		case -EPROBE_DEFER:
246 			return ret;
247 		default:
248 			dev_err(hsotg->dev, "error getting phy %d\n", ret);
249 			return ret;
250 		}
251 	}
252 
253 	if (!hsotg->phy) {
254 		hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
255 		if (IS_ERR(hsotg->uphy)) {
256 			ret = PTR_ERR(hsotg->uphy);
257 			switch (ret) {
258 			case -ENODEV:
259 			case -ENXIO:
260 				hsotg->uphy = NULL;
261 				break;
262 			case -EPROBE_DEFER:
263 				return ret;
264 			default:
265 				dev_err(hsotg->dev, "error getting usb phy %d\n",
266 					ret);
267 				return ret;
268 			}
269 		}
270 	}
271 
272 	hsotg->plat = dev_get_platdata(hsotg->dev);
273 
274 	/* Clock */
275 	hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg");
276 	if (IS_ERR(hsotg->clk)) {
277 		dev_err(hsotg->dev, "cannot get otg clock\n");
278 		return PTR_ERR(hsotg->clk);
279 	}
280 
281 	/* Regulators */
282 	for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
283 		hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
284 
285 	ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
286 				      hsotg->supplies);
287 	if (ret) {
288 		if (ret != -EPROBE_DEFER)
289 			dev_err(hsotg->dev, "failed to request supplies: %d\n",
290 				ret);
291 		return ret;
292 	}
293 	return 0;
294 }
295 
296 /**
297  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
298  * DWC_otg driver
299  *
300  * @dev: Platform device
301  *
302  * This routine is called, for example, when the rmmod command is executed. The
303  * device may or may not be electrically present. If it is present, the driver
304  * stops device processing. Any resources used on behalf of this device are
305  * freed.
306  */
307 static int dwc2_driver_remove(struct platform_device *dev)
308 {
309 	struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
310 
311 	dwc2_debugfs_exit(hsotg);
312 	if (hsotg->hcd_enabled)
313 		dwc2_hcd_remove(hsotg);
314 	if (hsotg->gadget_enabled)
315 		dwc2_hsotg_remove(hsotg);
316 
317 	if (hsotg->params.activate_stm_id_vb_detection)
318 		regulator_disable(hsotg->usb33d);
319 
320 	if (hsotg->ll_hw_enabled)
321 		dwc2_lowlevel_hw_disable(hsotg);
322 
323 	reset_control_assert(hsotg->reset);
324 	reset_control_assert(hsotg->reset_ecc);
325 
326 	return 0;
327 }
328 
329 /**
330  * dwc2_driver_shutdown() - Called on device shutdown
331  *
332  * @dev: Platform device
333  *
334  * In specific conditions (involving usb hubs) dwc2 devices can create a
335  * lot of interrupts, even to the point of overwhelming devices running
336  * at low frequencies. Some devices need to do special clock handling
337  * at shutdown-time which may bring the system clock below the threshold
338  * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs
339  * prevents reboots/poweroffs from getting stuck in such cases.
340  */
341 static void dwc2_driver_shutdown(struct platform_device *dev)
342 {
343 	struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
344 
345 	disable_irq(hsotg->irq);
346 }
347 
348 /**
349  * dwc2_check_core_endianness() - Returns true if core and AHB have
350  * opposite endianness.
351  * @hsotg:	Programming view of the DWC_otg controller.
352  */
353 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg)
354 {
355 	u32 snpsid;
356 
357 	snpsid = ioread32(hsotg->regs + GSNPSID);
358 	if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID ||
359 	    (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID ||
360 	    (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID)
361 		return false;
362 	return true;
363 }
364 
365 /**
366  * Check core version
367  *
368  * @hsotg: Programming view of the DWC_otg controller
369  *
370  */
371 int dwc2_check_core_version(struct dwc2_hsotg *hsotg)
372 {
373 	struct dwc2_hw_params *hw = &hsotg->hw_params;
374 
375 	/*
376 	 * Attempt to ensure this device is really a DWC_otg Controller.
377 	 * Read and verify the GSNPSID register contents. The value should be
378 	 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
379 	 */
380 
381 	hw->snpsid = dwc2_readl(hsotg, GSNPSID);
382 	if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
383 	    (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
384 	    (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
385 		dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
386 			hw->snpsid);
387 		return -ENODEV;
388 	}
389 
390 	dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
391 		hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
392 		hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
393 	return 0;
394 }
395 
396 /**
397  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
398  * driver
399  *
400  * @dev: Platform device
401  *
402  * This routine creates the driver components required to control the device
403  * (core, HCD, and PCD) and initializes the device. The driver components are
404  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
405  * in the device private data. This allows the driver to access the dwc2_hsotg
406  * structure on subsequent calls to driver methods for this device.
407  */
408 static int dwc2_driver_probe(struct platform_device *dev)
409 {
410 	struct dwc2_hsotg *hsotg;
411 	struct resource *res;
412 	int retval;
413 
414 	hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
415 	if (!hsotg)
416 		return -ENOMEM;
417 
418 	hsotg->dev = &dev->dev;
419 
420 	/*
421 	 * Use reasonable defaults so platforms don't have to provide these.
422 	 */
423 	if (!dev->dev.dma_mask)
424 		dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
425 	retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
426 	if (retval) {
427 		dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval);
428 		return retval;
429 	}
430 
431 	hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res);
432 	if (IS_ERR(hsotg->regs))
433 		return PTR_ERR(hsotg->regs);
434 
435 	dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
436 		(unsigned long)res->start, hsotg->regs);
437 
438 	retval = dwc2_lowlevel_hw_init(hsotg);
439 	if (retval)
440 		return retval;
441 
442 	spin_lock_init(&hsotg->lock);
443 
444 	hsotg->irq = platform_get_irq(dev, 0);
445 	if (hsotg->irq < 0)
446 		return hsotg->irq;
447 
448 	dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
449 		hsotg->irq);
450 	retval = devm_request_irq(hsotg->dev, hsotg->irq,
451 				  dwc2_handle_common_intr, IRQF_SHARED,
452 				  dev_name(hsotg->dev), hsotg);
453 	if (retval)
454 		return retval;
455 
456 	hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
457 	if (IS_ERR(hsotg->vbus_supply)) {
458 		retval = PTR_ERR(hsotg->vbus_supply);
459 		hsotg->vbus_supply = NULL;
460 		if (retval != -ENODEV)
461 			return retval;
462 	}
463 
464 	retval = dwc2_lowlevel_hw_enable(hsotg);
465 	if (retval)
466 		return retval;
467 
468 	hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
469 
470 	retval = dwc2_get_dr_mode(hsotg);
471 	if (retval)
472 		goto error;
473 
474 	hsotg->need_phy_for_wake =
475 		of_property_read_bool(dev->dev.of_node,
476 				      "snps,need-phy-for-wake");
477 
478 	/*
479 	 * Before performing any core related operations
480 	 * check core version.
481 	 */
482 	retval = dwc2_check_core_version(hsotg);
483 	if (retval)
484 		goto error;
485 
486 	/*
487 	 * Reset before dwc2_get_hwparams() then it could get power-on real
488 	 * reset value form registers.
489 	 */
490 	retval = dwc2_core_reset(hsotg, false);
491 	if (retval)
492 		goto error;
493 
494 	/* Detect config values from hardware */
495 	retval = dwc2_get_hwparams(hsotg);
496 	if (retval)
497 		goto error;
498 
499 	/*
500 	 * For OTG cores, set the force mode bits to reflect the value
501 	 * of dr_mode. Force mode bits should not be touched at any
502 	 * other time after this.
503 	 */
504 	dwc2_force_dr_mode(hsotg);
505 
506 	retval = dwc2_init_params(hsotg);
507 	if (retval)
508 		goto error;
509 
510 	if (hsotg->params.activate_stm_id_vb_detection) {
511 		u32 ggpio;
512 
513 		hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d");
514 		if (IS_ERR(hsotg->usb33d)) {
515 			retval = PTR_ERR(hsotg->usb33d);
516 			if (retval != -EPROBE_DEFER)
517 				dev_err(hsotg->dev,
518 					"failed to request usb33d supply: %d\n",
519 					retval);
520 			goto error;
521 		}
522 		retval = regulator_enable(hsotg->usb33d);
523 		if (retval) {
524 			dev_err(hsotg->dev,
525 				"failed to enable usb33d supply: %d\n", retval);
526 			goto error;
527 		}
528 
529 		ggpio = dwc2_readl(hsotg, GGPIO);
530 		ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
531 		ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
532 		dwc2_writel(hsotg, ggpio, GGPIO);
533 	}
534 
535 	if (hsotg->dr_mode != USB_DR_MODE_HOST) {
536 		retval = dwc2_gadget_init(hsotg);
537 		if (retval)
538 			goto error_init;
539 		hsotg->gadget_enabled = 1;
540 	}
541 
542 	/*
543 	 * If we need PHY for wakeup we must be wakeup capable.
544 	 * When we have a device that can wake without the PHY we
545 	 * can adjust this condition.
546 	 */
547 	if (hsotg->need_phy_for_wake)
548 		device_set_wakeup_capable(&dev->dev, true);
549 
550 	hsotg->reset_phy_on_wake =
551 		of_property_read_bool(dev->dev.of_node,
552 				      "snps,reset-phy-on-wake");
553 	if (hsotg->reset_phy_on_wake && !hsotg->phy) {
554 		dev_warn(hsotg->dev,
555 			 "Quirk reset-phy-on-wake only supports generic PHYs\n");
556 		hsotg->reset_phy_on_wake = false;
557 	}
558 
559 	if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
560 		retval = dwc2_hcd_init(hsotg);
561 		if (retval) {
562 			if (hsotg->gadget_enabled)
563 				dwc2_hsotg_remove(hsotg);
564 			goto error_init;
565 		}
566 		hsotg->hcd_enabled = 1;
567 	}
568 
569 	platform_set_drvdata(dev, hsotg);
570 	hsotg->hibernated = 0;
571 
572 	dwc2_debugfs_init(hsotg);
573 
574 	/* Gadget code manages lowlevel hw on its own */
575 	if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
576 		dwc2_lowlevel_hw_disable(hsotg);
577 
578 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
579 	IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
580 	/* Postponed adding a new gadget to the udc class driver list */
581 	if (hsotg->gadget_enabled) {
582 		retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget);
583 		if (retval) {
584 			dwc2_hsotg_remove(hsotg);
585 			goto error_init;
586 		}
587 	}
588 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
589 	return 0;
590 
591 error_init:
592 	if (hsotg->params.activate_stm_id_vb_detection)
593 		regulator_disable(hsotg->usb33d);
594 error:
595 	dwc2_lowlevel_hw_disable(hsotg);
596 	return retval;
597 }
598 
599 static int __maybe_unused dwc2_suspend(struct device *dev)
600 {
601 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
602 	bool is_device_mode = dwc2_is_device_mode(dwc2);
603 	int ret = 0;
604 
605 	if (is_device_mode)
606 		dwc2_hsotg_suspend(dwc2);
607 
608 	if (dwc2->params.activate_stm_id_vb_detection) {
609 		unsigned long flags;
610 		u32 ggpio, gotgctl;
611 
612 		/*
613 		 * Need to force the mode to the current mode to avoid Mode
614 		 * Mismatch Interrupt when ID detection will be disabled.
615 		 */
616 		dwc2_force_mode(dwc2, !is_device_mode);
617 
618 		spin_lock_irqsave(&dwc2->lock, flags);
619 		gotgctl = dwc2_readl(dwc2, GOTGCTL);
620 		/* bypass debounce filter, enable overrides */
621 		gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS;
622 		gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN;
623 		/* Force A / B session if needed */
624 		if (gotgctl & GOTGCTL_ASESVLD)
625 			gotgctl |= GOTGCTL_AVALOVAL;
626 		if (gotgctl & GOTGCTL_BSESVLD)
627 			gotgctl |= GOTGCTL_BVALOVAL;
628 		dwc2_writel(dwc2, gotgctl, GOTGCTL);
629 		spin_unlock_irqrestore(&dwc2->lock, flags);
630 
631 		ggpio = dwc2_readl(dwc2, GGPIO);
632 		ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN;
633 		ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN;
634 		dwc2_writel(dwc2, ggpio, GGPIO);
635 
636 		regulator_disable(dwc2->usb33d);
637 	}
638 
639 	if (dwc2->ll_hw_enabled &&
640 	    (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) {
641 		ret = __dwc2_lowlevel_hw_disable(dwc2);
642 		dwc2->phy_off_for_suspend = true;
643 	}
644 
645 	return ret;
646 }
647 
648 static int __maybe_unused dwc2_resume(struct device *dev)
649 {
650 	struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
651 	int ret = 0;
652 
653 	if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) {
654 		ret = __dwc2_lowlevel_hw_enable(dwc2);
655 		if (ret)
656 			return ret;
657 	}
658 	dwc2->phy_off_for_suspend = false;
659 
660 	if (dwc2->params.activate_stm_id_vb_detection) {
661 		unsigned long flags;
662 		u32 ggpio, gotgctl;
663 
664 		ret = regulator_enable(dwc2->usb33d);
665 		if (ret)
666 			return ret;
667 
668 		ggpio = dwc2_readl(dwc2, GGPIO);
669 		ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN;
670 		ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN;
671 		dwc2_writel(dwc2, ggpio, GGPIO);
672 
673 		/* ID/VBUS detection startup time */
674 		usleep_range(5000, 7000);
675 
676 		spin_lock_irqsave(&dwc2->lock, flags);
677 		gotgctl = dwc2_readl(dwc2, GOTGCTL);
678 		gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS;
679 		gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN |
680 			     GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL);
681 		dwc2_writel(dwc2, gotgctl, GOTGCTL);
682 		spin_unlock_irqrestore(&dwc2->lock, flags);
683 	}
684 
685 	/* Need to restore FORCEDEVMODE/FORCEHOSTMODE */
686 	dwc2_force_dr_mode(dwc2);
687 
688 	if (dwc2_is_device_mode(dwc2))
689 		ret = dwc2_hsotg_resume(dwc2);
690 
691 	return ret;
692 }
693 
694 static const struct dev_pm_ops dwc2_dev_pm_ops = {
695 	SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
696 };
697 
698 static struct platform_driver dwc2_platform_driver = {
699 	.driver = {
700 		.name = dwc2_driver_name,
701 		.of_match_table = dwc2_of_match_table,
702 		.pm = &dwc2_dev_pm_ops,
703 	},
704 	.probe = dwc2_driver_probe,
705 	.remove = dwc2_driver_remove,
706 	.shutdown = dwc2_driver_shutdown,
707 };
708 
709 module_platform_driver(dwc2_platform_driver);
710 
711 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
712 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
713 MODULE_LICENSE("Dual BSD/GPL");
714