1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * platform.c - DesignWare HS OTG Controller platform driver 4 * 5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/slab.h> 41 #include <linux/clk.h> 42 #include <linux/device.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/of_device.h> 45 #include <linux/mutex.h> 46 #include <linux/platform_device.h> 47 #include <linux/phy/phy.h> 48 #include <linux/platform_data/s3c-hsotg.h> 49 #include <linux/reset.h> 50 51 #include <linux/usb/of.h> 52 53 #include "core.h" 54 #include "hcd.h" 55 #include "debug.h" 56 57 static const char dwc2_driver_name[] = "dwc2"; 58 59 /* 60 * Check the dr_mode against the module configuration and hardware 61 * capabilities. 62 * 63 * The hardware, module, and dr_mode, can each be set to host, device, 64 * or otg. Check that all these values are compatible and adjust the 65 * value of dr_mode if possible. 66 * 67 * actual 68 * HW MOD dr_mode dr_mode 69 * ------------------------------ 70 * HST HST any : HST 71 * HST DEV any : --- 72 * HST OTG any : HST 73 * 74 * DEV HST any : --- 75 * DEV DEV any : DEV 76 * DEV OTG any : DEV 77 * 78 * OTG HST any : HST 79 * OTG DEV any : DEV 80 * OTG OTG any : dr_mode 81 */ 82 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) 83 { 84 enum usb_dr_mode mode; 85 86 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); 87 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) 88 hsotg->dr_mode = USB_DR_MODE_OTG; 89 90 mode = hsotg->dr_mode; 91 92 if (dwc2_hw_is_device(hsotg)) { 93 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { 94 dev_err(hsotg->dev, 95 "Controller does not support host mode.\n"); 96 return -EINVAL; 97 } 98 mode = USB_DR_MODE_PERIPHERAL; 99 } else if (dwc2_hw_is_host(hsotg)) { 100 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { 101 dev_err(hsotg->dev, 102 "Controller does not support device mode.\n"); 103 return -EINVAL; 104 } 105 mode = USB_DR_MODE_HOST; 106 } else { 107 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) 108 mode = USB_DR_MODE_HOST; 109 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) 110 mode = USB_DR_MODE_PERIPHERAL; 111 } 112 113 if (mode != hsotg->dr_mode) { 114 dev_warn(hsotg->dev, 115 "Configuration mismatch. dr_mode forced to %s\n", 116 mode == USB_DR_MODE_HOST ? "host" : "device"); 117 118 hsotg->dr_mode = mode; 119 } 120 121 return 0; 122 } 123 124 static void __dwc2_disable_regulators(void *data) 125 { 126 struct dwc2_hsotg *hsotg = data; 127 128 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); 129 } 130 131 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 132 { 133 struct platform_device *pdev = to_platform_device(hsotg->dev); 134 int ret; 135 136 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), 137 hsotg->supplies); 138 if (ret) 139 return ret; 140 141 ret = devm_add_action_or_reset(&pdev->dev, 142 __dwc2_disable_regulators, hsotg); 143 if (ret) 144 return ret; 145 146 if (hsotg->clk) { 147 ret = clk_prepare_enable(hsotg->clk); 148 if (ret) 149 return ret; 150 } 151 152 if (hsotg->uphy) { 153 ret = usb_phy_init(hsotg->uphy); 154 } else if (hsotg->plat && hsotg->plat->phy_init) { 155 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); 156 } else { 157 ret = phy_power_on(hsotg->phy); 158 if (ret == 0) 159 ret = phy_init(hsotg->phy); 160 } 161 162 return ret; 163 } 164 165 /** 166 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources 167 * @hsotg: The driver state 168 * 169 * A wrapper for platform code responsible for controlling 170 * low-level USB platform resources (phy, clock, regulators) 171 */ 172 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 173 { 174 int ret = __dwc2_lowlevel_hw_enable(hsotg); 175 176 if (ret == 0) 177 hsotg->ll_hw_enabled = true; 178 return ret; 179 } 180 181 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 182 { 183 struct platform_device *pdev = to_platform_device(hsotg->dev); 184 int ret = 0; 185 186 if (hsotg->uphy) { 187 usb_phy_shutdown(hsotg->uphy); 188 } else if (hsotg->plat && hsotg->plat->phy_exit) { 189 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); 190 } else { 191 ret = phy_exit(hsotg->phy); 192 if (ret == 0) 193 ret = phy_power_off(hsotg->phy); 194 } 195 if (ret) 196 return ret; 197 198 if (hsotg->clk) 199 clk_disable_unprepare(hsotg->clk); 200 201 return 0; 202 } 203 204 /** 205 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources 206 * @hsotg: The driver state 207 * 208 * A wrapper for platform code responsible for controlling 209 * low-level USB platform resources (phy, clock, regulators) 210 */ 211 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 212 { 213 int ret = __dwc2_lowlevel_hw_disable(hsotg); 214 215 if (ret == 0) 216 hsotg->ll_hw_enabled = false; 217 return ret; 218 } 219 220 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) 221 { 222 int i, ret; 223 224 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); 225 if (IS_ERR(hsotg->reset)) { 226 ret = PTR_ERR(hsotg->reset); 227 dev_err(hsotg->dev, "error getting reset control %d\n", ret); 228 return ret; 229 } 230 231 reset_control_deassert(hsotg->reset); 232 233 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); 234 if (IS_ERR(hsotg->reset_ecc)) { 235 ret = PTR_ERR(hsotg->reset_ecc); 236 dev_err(hsotg->dev, "error getting reset control for ecc %d\n", ret); 237 return ret; 238 } 239 240 reset_control_deassert(hsotg->reset_ecc); 241 242 /* 243 * Attempt to find a generic PHY, then look for an old style 244 * USB PHY and then fall back to pdata 245 */ 246 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); 247 if (IS_ERR(hsotg->phy)) { 248 ret = PTR_ERR(hsotg->phy); 249 switch (ret) { 250 case -ENODEV: 251 case -ENOSYS: 252 hsotg->phy = NULL; 253 break; 254 case -EPROBE_DEFER: 255 return ret; 256 default: 257 dev_err(hsotg->dev, "error getting phy %d\n", ret); 258 return ret; 259 } 260 } 261 262 if (!hsotg->phy) { 263 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); 264 if (IS_ERR(hsotg->uphy)) { 265 ret = PTR_ERR(hsotg->uphy); 266 switch (ret) { 267 case -ENODEV: 268 case -ENXIO: 269 hsotg->uphy = NULL; 270 break; 271 case -EPROBE_DEFER: 272 return ret; 273 default: 274 dev_err(hsotg->dev, "error getting usb phy %d\n", 275 ret); 276 return ret; 277 } 278 } 279 } 280 281 hsotg->plat = dev_get_platdata(hsotg->dev); 282 283 /* Clock */ 284 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); 285 if (IS_ERR(hsotg->clk)) { 286 dev_err(hsotg->dev, "cannot get otg clock\n"); 287 return PTR_ERR(hsotg->clk); 288 } 289 290 /* Regulators */ 291 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) 292 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; 293 294 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), 295 hsotg->supplies); 296 if (ret) { 297 if (ret != -EPROBE_DEFER) 298 dev_err(hsotg->dev, "failed to request supplies: %d\n", 299 ret); 300 return ret; 301 } 302 return 0; 303 } 304 305 /** 306 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the 307 * DWC_otg driver 308 * 309 * @dev: Platform device 310 * 311 * This routine is called, for example, when the rmmod command is executed. The 312 * device may or may not be electrically present. If it is present, the driver 313 * stops device processing. Any resources used on behalf of this device are 314 * freed. 315 */ 316 static int dwc2_driver_remove(struct platform_device *dev) 317 { 318 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 319 struct dwc2_gregs_backup *gr; 320 int ret = 0; 321 322 gr = &hsotg->gr_backup; 323 324 /* Exit Hibernation when driver is removed. */ 325 if (hsotg->hibernated) { 326 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 327 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 328 else 329 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0); 330 331 if (ret) 332 dev_err(hsotg->dev, 333 "exit hibernation failed.\n"); 334 } 335 336 /* Exit Partial Power Down when driver is removed. */ 337 if (hsotg->in_ppd) { 338 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 339 if (ret) 340 dev_err(hsotg->dev, 341 "exit partial_power_down failed\n"); 342 } 343 344 /* Exit clock gating when driver is removed. */ 345 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && 346 hsotg->bus_suspended) { 347 if (dwc2_is_device_mode(hsotg)) 348 dwc2_gadget_exit_clock_gating(hsotg, 0); 349 else 350 dwc2_host_exit_clock_gating(hsotg, 0); 351 } 352 353 dwc2_debugfs_exit(hsotg); 354 if (hsotg->hcd_enabled) 355 dwc2_hcd_remove(hsotg); 356 if (hsotg->gadget_enabled) 357 dwc2_hsotg_remove(hsotg); 358 359 dwc2_drd_exit(hsotg); 360 361 if (hsotg->params.activate_stm_id_vb_detection) 362 regulator_disable(hsotg->usb33d); 363 364 if (hsotg->ll_hw_enabled) 365 dwc2_lowlevel_hw_disable(hsotg); 366 367 reset_control_assert(hsotg->reset); 368 reset_control_assert(hsotg->reset_ecc); 369 370 return ret; 371 } 372 373 /** 374 * dwc2_driver_shutdown() - Called on device shutdown 375 * 376 * @dev: Platform device 377 * 378 * In specific conditions (involving usb hubs) dwc2 devices can create a 379 * lot of interrupts, even to the point of overwhelming devices running 380 * at low frequencies. Some devices need to do special clock handling 381 * at shutdown-time which may bring the system clock below the threshold 382 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs 383 * prevents reboots/poweroffs from getting stuck in such cases. 384 */ 385 static void dwc2_driver_shutdown(struct platform_device *dev) 386 { 387 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 388 389 dwc2_disable_global_interrupts(hsotg); 390 synchronize_irq(hsotg->irq); 391 } 392 393 /** 394 * dwc2_check_core_endianness() - Returns true if core and AHB have 395 * opposite endianness. 396 * @hsotg: Programming view of the DWC_otg controller. 397 */ 398 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) 399 { 400 u32 snpsid; 401 402 snpsid = ioread32(hsotg->regs + GSNPSID); 403 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || 404 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || 405 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) 406 return false; 407 return true; 408 } 409 410 /** 411 * dwc2_check_core_version() - Check core version 412 * 413 * @hsotg: Programming view of the DWC_otg controller 414 * 415 */ 416 int dwc2_check_core_version(struct dwc2_hsotg *hsotg) 417 { 418 struct dwc2_hw_params *hw = &hsotg->hw_params; 419 420 /* 421 * Attempt to ensure this device is really a DWC_otg Controller. 422 * Read and verify the GSNPSID register contents. The value should be 423 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 424 */ 425 426 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 427 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 428 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 429 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 430 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 431 hw->snpsid); 432 return -ENODEV; 433 } 434 435 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 436 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 437 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 438 return 0; 439 } 440 441 /** 442 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 443 * driver 444 * 445 * @dev: Platform device 446 * 447 * This routine creates the driver components required to control the device 448 * (core, HCD, and PCD) and initializes the device. The driver components are 449 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved 450 * in the device private data. This allows the driver to access the dwc2_hsotg 451 * structure on subsequent calls to driver methods for this device. 452 */ 453 static int dwc2_driver_probe(struct platform_device *dev) 454 { 455 struct dwc2_hsotg *hsotg; 456 struct resource *res; 457 int retval; 458 459 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); 460 if (!hsotg) 461 return -ENOMEM; 462 463 hsotg->dev = &dev->dev; 464 465 /* 466 * Use reasonable defaults so platforms don't have to provide these. 467 */ 468 if (!dev->dev.dma_mask) 469 dev->dev.dma_mask = &dev->dev.coherent_dma_mask; 470 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 471 if (retval) { 472 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); 473 return retval; 474 } 475 476 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res); 477 if (IS_ERR(hsotg->regs)) 478 return PTR_ERR(hsotg->regs); 479 480 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 481 (unsigned long)res->start, hsotg->regs); 482 483 retval = dwc2_lowlevel_hw_init(hsotg); 484 if (retval) 485 return retval; 486 487 spin_lock_init(&hsotg->lock); 488 489 hsotg->irq = platform_get_irq(dev, 0); 490 if (hsotg->irq < 0) 491 return hsotg->irq; 492 493 dev_dbg(hsotg->dev, "registering common handler for irq%d\n", 494 hsotg->irq); 495 retval = devm_request_irq(hsotg->dev, hsotg->irq, 496 dwc2_handle_common_intr, IRQF_SHARED, 497 dev_name(hsotg->dev), hsotg); 498 if (retval) 499 return retval; 500 501 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); 502 if (IS_ERR(hsotg->vbus_supply)) { 503 retval = PTR_ERR(hsotg->vbus_supply); 504 hsotg->vbus_supply = NULL; 505 if (retval != -ENODEV) 506 return retval; 507 } 508 509 retval = dwc2_lowlevel_hw_enable(hsotg); 510 if (retval) 511 return retval; 512 513 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); 514 515 retval = dwc2_get_dr_mode(hsotg); 516 if (retval) 517 goto error; 518 519 hsotg->need_phy_for_wake = 520 of_property_read_bool(dev->dev.of_node, 521 "snps,need-phy-for-wake"); 522 523 /* 524 * Before performing any core related operations 525 * check core version. 526 */ 527 retval = dwc2_check_core_version(hsotg); 528 if (retval) 529 goto error; 530 531 /* 532 * Reset before dwc2_get_hwparams() then it could get power-on real 533 * reset value form registers. 534 */ 535 retval = dwc2_core_reset(hsotg, false); 536 if (retval) 537 goto error; 538 539 /* Detect config values from hardware */ 540 retval = dwc2_get_hwparams(hsotg); 541 if (retval) 542 goto error; 543 544 /* 545 * For OTG cores, set the force mode bits to reflect the value 546 * of dr_mode. Force mode bits should not be touched at any 547 * other time after this. 548 */ 549 dwc2_force_dr_mode(hsotg); 550 551 retval = dwc2_init_params(hsotg); 552 if (retval) 553 goto error; 554 555 if (hsotg->params.activate_stm_id_vb_detection) { 556 u32 ggpio; 557 558 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d"); 559 if (IS_ERR(hsotg->usb33d)) { 560 retval = PTR_ERR(hsotg->usb33d); 561 if (retval != -EPROBE_DEFER) 562 dev_err(hsotg->dev, 563 "failed to request usb33d supply: %d\n", 564 retval); 565 goto error; 566 } 567 retval = regulator_enable(hsotg->usb33d); 568 if (retval) { 569 dev_err(hsotg->dev, 570 "failed to enable usb33d supply: %d\n", retval); 571 goto error; 572 } 573 574 ggpio = dwc2_readl(hsotg, GGPIO); 575 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 576 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 577 dwc2_writel(hsotg, ggpio, GGPIO); 578 } 579 580 retval = dwc2_drd_init(hsotg); 581 if (retval) { 582 if (retval != -EPROBE_DEFER) 583 dev_err(hsotg->dev, "failed to initialize dual-role\n"); 584 goto error_init; 585 } 586 587 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 588 retval = dwc2_gadget_init(hsotg); 589 if (retval) 590 goto error_drd; 591 hsotg->gadget_enabled = 1; 592 } 593 594 /* 595 * If we need PHY for wakeup we must be wakeup capable. 596 * When we have a device that can wake without the PHY we 597 * can adjust this condition. 598 */ 599 if (hsotg->need_phy_for_wake) 600 device_set_wakeup_capable(&dev->dev, true); 601 602 hsotg->reset_phy_on_wake = 603 of_property_read_bool(dev->dev.of_node, 604 "snps,reset-phy-on-wake"); 605 if (hsotg->reset_phy_on_wake && !hsotg->phy) { 606 dev_warn(hsotg->dev, 607 "Quirk reset-phy-on-wake only supports generic PHYs\n"); 608 hsotg->reset_phy_on_wake = false; 609 } 610 611 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 612 retval = dwc2_hcd_init(hsotg); 613 if (retval) { 614 if (hsotg->gadget_enabled) 615 dwc2_hsotg_remove(hsotg); 616 goto error_drd; 617 } 618 hsotg->hcd_enabled = 1; 619 } 620 621 platform_set_drvdata(dev, hsotg); 622 hsotg->hibernated = 0; 623 624 dwc2_debugfs_init(hsotg); 625 626 /* Gadget code manages lowlevel hw on its own */ 627 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 628 dwc2_lowlevel_hw_disable(hsotg); 629 630 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 631 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 632 /* Postponed adding a new gadget to the udc class driver list */ 633 if (hsotg->gadget_enabled) { 634 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget); 635 if (retval) { 636 hsotg->gadget.udc = NULL; 637 dwc2_hsotg_remove(hsotg); 638 goto error_debugfs; 639 } 640 } 641 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 642 return 0; 643 644 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 645 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 646 error_debugfs: 647 dwc2_debugfs_exit(hsotg); 648 if (hsotg->hcd_enabled) 649 dwc2_hcd_remove(hsotg); 650 #endif 651 error_drd: 652 dwc2_drd_exit(hsotg); 653 654 error_init: 655 if (hsotg->params.activate_stm_id_vb_detection) 656 regulator_disable(hsotg->usb33d); 657 error: 658 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) 659 dwc2_lowlevel_hw_disable(hsotg); 660 return retval; 661 } 662 663 static int __maybe_unused dwc2_suspend(struct device *dev) 664 { 665 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 666 bool is_device_mode = dwc2_is_device_mode(dwc2); 667 int ret = 0; 668 669 if (is_device_mode) 670 dwc2_hsotg_suspend(dwc2); 671 672 dwc2_drd_suspend(dwc2); 673 674 if (dwc2->params.activate_stm_id_vb_detection) { 675 unsigned long flags; 676 u32 ggpio, gotgctl; 677 678 /* 679 * Need to force the mode to the current mode to avoid Mode 680 * Mismatch Interrupt when ID detection will be disabled. 681 */ 682 dwc2_force_mode(dwc2, !is_device_mode); 683 684 spin_lock_irqsave(&dwc2->lock, flags); 685 gotgctl = dwc2_readl(dwc2, GOTGCTL); 686 /* bypass debounce filter, enable overrides */ 687 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS; 688 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN; 689 /* Force A / B session if needed */ 690 if (gotgctl & GOTGCTL_ASESVLD) 691 gotgctl |= GOTGCTL_AVALOVAL; 692 if (gotgctl & GOTGCTL_BSESVLD) 693 gotgctl |= GOTGCTL_BVALOVAL; 694 dwc2_writel(dwc2, gotgctl, GOTGCTL); 695 spin_unlock_irqrestore(&dwc2->lock, flags); 696 697 ggpio = dwc2_readl(dwc2, GGPIO); 698 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN; 699 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN; 700 dwc2_writel(dwc2, ggpio, GGPIO); 701 702 regulator_disable(dwc2->usb33d); 703 } 704 705 if (dwc2->ll_hw_enabled && 706 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { 707 ret = __dwc2_lowlevel_hw_disable(dwc2); 708 dwc2->phy_off_for_suspend = true; 709 } 710 711 return ret; 712 } 713 714 static int __maybe_unused dwc2_resume(struct device *dev) 715 { 716 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 717 int ret = 0; 718 719 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { 720 ret = __dwc2_lowlevel_hw_enable(dwc2); 721 if (ret) 722 return ret; 723 } 724 dwc2->phy_off_for_suspend = false; 725 726 if (dwc2->params.activate_stm_id_vb_detection) { 727 unsigned long flags; 728 u32 ggpio, gotgctl; 729 730 ret = regulator_enable(dwc2->usb33d); 731 if (ret) 732 return ret; 733 734 ggpio = dwc2_readl(dwc2, GGPIO); 735 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 736 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 737 dwc2_writel(dwc2, ggpio, GGPIO); 738 739 /* ID/VBUS detection startup time */ 740 usleep_range(5000, 7000); 741 742 spin_lock_irqsave(&dwc2->lock, flags); 743 gotgctl = dwc2_readl(dwc2, GOTGCTL); 744 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS; 745 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | 746 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL); 747 dwc2_writel(dwc2, gotgctl, GOTGCTL); 748 spin_unlock_irqrestore(&dwc2->lock, flags); 749 } 750 751 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */ 752 dwc2_force_dr_mode(dwc2); 753 754 dwc2_drd_resume(dwc2); 755 756 if (dwc2_is_device_mode(dwc2)) 757 ret = dwc2_hsotg_resume(dwc2); 758 759 return ret; 760 } 761 762 static const struct dev_pm_ops dwc2_dev_pm_ops = { 763 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) 764 }; 765 766 static struct platform_driver dwc2_platform_driver = { 767 .driver = { 768 .name = dwc2_driver_name, 769 .of_match_table = dwc2_of_match_table, 770 .acpi_match_table = ACPI_PTR(dwc2_acpi_match), 771 .pm = &dwc2_dev_pm_ops, 772 }, 773 .probe = dwc2_driver_probe, 774 .remove = dwc2_driver_remove, 775 .shutdown = dwc2_driver_shutdown, 776 }; 777 778 module_platform_driver(dwc2_platform_driver); 779