1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * platform.c - DesignWare HS OTG Controller platform driver 4 * 5 * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/of_device.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_data/s3c-hsotg.h> 19 #include <linux/reset.h> 20 21 #include <linux/usb/of.h> 22 23 #include "core.h" 24 #include "hcd.h" 25 #include "debug.h" 26 27 static const char dwc2_driver_name[] = "dwc2"; 28 29 /* 30 * Check the dr_mode against the module configuration and hardware 31 * capabilities. 32 * 33 * The hardware, module, and dr_mode, can each be set to host, device, 34 * or otg. Check that all these values are compatible and adjust the 35 * value of dr_mode if possible. 36 * 37 * actual 38 * HW MOD dr_mode dr_mode 39 * ------------------------------ 40 * HST HST any : HST 41 * HST DEV any : --- 42 * HST OTG any : HST 43 * 44 * DEV HST any : --- 45 * DEV DEV any : DEV 46 * DEV OTG any : DEV 47 * 48 * OTG HST any : HST 49 * OTG DEV any : DEV 50 * OTG OTG any : dr_mode 51 */ 52 static int dwc2_get_dr_mode(struct dwc2_hsotg *hsotg) 53 { 54 enum usb_dr_mode mode; 55 56 hsotg->dr_mode = usb_get_dr_mode(hsotg->dev); 57 if (hsotg->dr_mode == USB_DR_MODE_UNKNOWN) 58 hsotg->dr_mode = USB_DR_MODE_OTG; 59 60 mode = hsotg->dr_mode; 61 62 if (dwc2_hw_is_device(hsotg)) { 63 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) { 64 dev_err(hsotg->dev, 65 "Controller does not support host mode.\n"); 66 return -EINVAL; 67 } 68 mode = USB_DR_MODE_PERIPHERAL; 69 } else if (dwc2_hw_is_host(hsotg)) { 70 if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) { 71 dev_err(hsotg->dev, 72 "Controller does not support device mode.\n"); 73 return -EINVAL; 74 } 75 mode = USB_DR_MODE_HOST; 76 } else { 77 if (IS_ENABLED(CONFIG_USB_DWC2_HOST)) 78 mode = USB_DR_MODE_HOST; 79 else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL)) 80 mode = USB_DR_MODE_PERIPHERAL; 81 } 82 83 if (mode != hsotg->dr_mode) { 84 dev_warn(hsotg->dev, 85 "Configuration mismatch. dr_mode forced to %s\n", 86 mode == USB_DR_MODE_HOST ? "host" : "device"); 87 88 hsotg->dr_mode = mode; 89 } 90 91 return 0; 92 } 93 94 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 95 { 96 struct platform_device *pdev = to_platform_device(hsotg->dev); 97 int ret; 98 99 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies), 100 hsotg->supplies); 101 if (ret) 102 return ret; 103 104 if (hsotg->clk) { 105 ret = clk_prepare_enable(hsotg->clk); 106 if (ret) 107 return ret; 108 } 109 110 if (hsotg->uphy) { 111 ret = usb_phy_init(hsotg->uphy); 112 } else if (hsotg->plat && hsotg->plat->phy_init) { 113 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type); 114 } else { 115 ret = phy_init(hsotg->phy); 116 if (ret == 0) 117 ret = phy_power_on(hsotg->phy); 118 } 119 120 return ret; 121 } 122 123 /** 124 * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources 125 * @hsotg: The driver state 126 * 127 * A wrapper for platform code responsible for controlling 128 * low-level USB platform resources (phy, clock, regulators) 129 */ 130 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg) 131 { 132 int ret = __dwc2_lowlevel_hw_enable(hsotg); 133 134 if (ret == 0) 135 hsotg->ll_hw_enabled = true; 136 return ret; 137 } 138 139 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 140 { 141 struct platform_device *pdev = to_platform_device(hsotg->dev); 142 int ret = 0; 143 144 if (hsotg->uphy) { 145 usb_phy_shutdown(hsotg->uphy); 146 } else if (hsotg->plat && hsotg->plat->phy_exit) { 147 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type); 148 } else { 149 ret = phy_power_off(hsotg->phy); 150 if (ret == 0) 151 ret = phy_exit(hsotg->phy); 152 } 153 if (ret) 154 return ret; 155 156 if (hsotg->clk) 157 clk_disable_unprepare(hsotg->clk); 158 159 return regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies); 160 } 161 162 /** 163 * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources 164 * @hsotg: The driver state 165 * 166 * A wrapper for platform code responsible for controlling 167 * low-level USB platform resources (phy, clock, regulators) 168 */ 169 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg) 170 { 171 int ret = __dwc2_lowlevel_hw_disable(hsotg); 172 173 if (ret == 0) 174 hsotg->ll_hw_enabled = false; 175 return ret; 176 } 177 178 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg) 179 { 180 int i, ret; 181 182 hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2"); 183 if (IS_ERR(hsotg->reset)) 184 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset), 185 "error getting reset control\n"); 186 187 reset_control_deassert(hsotg->reset); 188 189 hsotg->reset_ecc = devm_reset_control_get_optional(hsotg->dev, "dwc2-ecc"); 190 if (IS_ERR(hsotg->reset_ecc)) 191 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->reset_ecc), 192 "error getting reset control for ecc\n"); 193 194 reset_control_deassert(hsotg->reset_ecc); 195 196 /* 197 * Attempt to find a generic PHY, then look for an old style 198 * USB PHY and then fall back to pdata 199 */ 200 hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy"); 201 if (IS_ERR(hsotg->phy)) { 202 ret = PTR_ERR(hsotg->phy); 203 switch (ret) { 204 case -ENODEV: 205 case -ENOSYS: 206 hsotg->phy = NULL; 207 break; 208 default: 209 return dev_err_probe(hsotg->dev, ret, "error getting phy\n"); 210 } 211 } 212 213 if (!hsotg->phy) { 214 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2); 215 if (IS_ERR(hsotg->uphy)) { 216 ret = PTR_ERR(hsotg->uphy); 217 switch (ret) { 218 case -ENODEV: 219 case -ENXIO: 220 hsotg->uphy = NULL; 221 break; 222 default: 223 return dev_err_probe(hsotg->dev, ret, "error getting usb phy\n"); 224 } 225 } 226 } 227 228 hsotg->plat = dev_get_platdata(hsotg->dev); 229 230 /* Clock */ 231 hsotg->clk = devm_clk_get_optional(hsotg->dev, "otg"); 232 if (IS_ERR(hsotg->clk)) 233 return dev_err_probe(hsotg->dev, PTR_ERR(hsotg->clk), "cannot get otg clock\n"); 234 235 /* Regulators */ 236 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++) 237 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i]; 238 239 ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies), 240 hsotg->supplies); 241 if (ret) 242 return dev_err_probe(hsotg->dev, ret, "failed to request supplies\n"); 243 244 return 0; 245 } 246 247 /** 248 * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the 249 * DWC_otg driver 250 * 251 * @dev: Platform device 252 * 253 * This routine is called, for example, when the rmmod command is executed. The 254 * device may or may not be electrically present. If it is present, the driver 255 * stops device processing. Any resources used on behalf of this device are 256 * freed. 257 */ 258 static int dwc2_driver_remove(struct platform_device *dev) 259 { 260 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 261 struct dwc2_gregs_backup *gr; 262 int ret = 0; 263 264 gr = &hsotg->gr_backup; 265 266 /* Exit Hibernation when driver is removed. */ 267 if (hsotg->hibernated) { 268 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 269 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 270 else 271 ret = dwc2_exit_hibernation(hsotg, 0, 0, 0); 272 273 if (ret) 274 dev_err(hsotg->dev, 275 "exit hibernation failed.\n"); 276 } 277 278 /* Exit Partial Power Down when driver is removed. */ 279 if (hsotg->in_ppd) { 280 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 281 if (ret) 282 dev_err(hsotg->dev, 283 "exit partial_power_down failed\n"); 284 } 285 286 /* Exit clock gating when driver is removed. */ 287 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && 288 hsotg->bus_suspended) { 289 if (dwc2_is_device_mode(hsotg)) 290 dwc2_gadget_exit_clock_gating(hsotg, 0); 291 else 292 dwc2_host_exit_clock_gating(hsotg, 0); 293 } 294 295 dwc2_debugfs_exit(hsotg); 296 if (hsotg->hcd_enabled) 297 dwc2_hcd_remove(hsotg); 298 if (hsotg->gadget_enabled) 299 dwc2_hsotg_remove(hsotg); 300 301 dwc2_drd_exit(hsotg); 302 303 if (hsotg->params.activate_stm_id_vb_detection) 304 regulator_disable(hsotg->usb33d); 305 306 if (hsotg->ll_hw_enabled) 307 dwc2_lowlevel_hw_disable(hsotg); 308 309 reset_control_assert(hsotg->reset); 310 reset_control_assert(hsotg->reset_ecc); 311 312 return 0; 313 } 314 315 /** 316 * dwc2_driver_shutdown() - Called on device shutdown 317 * 318 * @dev: Platform device 319 * 320 * In specific conditions (involving usb hubs) dwc2 devices can create a 321 * lot of interrupts, even to the point of overwhelming devices running 322 * at low frequencies. Some devices need to do special clock handling 323 * at shutdown-time which may bring the system clock below the threshold 324 * of being able to handle the dwc2 interrupts. Disabling dwc2-irqs 325 * prevents reboots/poweroffs from getting stuck in such cases. 326 */ 327 static void dwc2_driver_shutdown(struct platform_device *dev) 328 { 329 struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); 330 331 dwc2_disable_global_interrupts(hsotg); 332 synchronize_irq(hsotg->irq); 333 } 334 335 /** 336 * dwc2_check_core_endianness() - Returns true if core and AHB have 337 * opposite endianness. 338 * @hsotg: Programming view of the DWC_otg controller. 339 */ 340 static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) 341 { 342 u32 snpsid; 343 344 snpsid = ioread32(hsotg->regs + GSNPSID); 345 if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || 346 (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || 347 (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) 348 return false; 349 return true; 350 } 351 352 /** 353 * dwc2_check_core_version() - Check core version 354 * 355 * @hsotg: Programming view of the DWC_otg controller 356 * 357 */ 358 int dwc2_check_core_version(struct dwc2_hsotg *hsotg) 359 { 360 struct dwc2_hw_params *hw = &hsotg->hw_params; 361 362 /* 363 * Attempt to ensure this device is really a DWC_otg Controller. 364 * Read and verify the GSNPSID register contents. The value should be 365 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 366 */ 367 368 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 369 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 370 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 371 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 372 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 373 hw->snpsid); 374 return -ENODEV; 375 } 376 377 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 378 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 379 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 380 return 0; 381 } 382 383 /** 384 * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg 385 * driver 386 * 387 * @dev: Platform device 388 * 389 * This routine creates the driver components required to control the device 390 * (core, HCD, and PCD) and initializes the device. The driver components are 391 * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved 392 * in the device private data. This allows the driver to access the dwc2_hsotg 393 * structure on subsequent calls to driver methods for this device. 394 */ 395 static int dwc2_driver_probe(struct platform_device *dev) 396 { 397 struct dwc2_hsotg *hsotg; 398 struct resource *res; 399 int retval; 400 401 hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL); 402 if (!hsotg) 403 return -ENOMEM; 404 405 hsotg->dev = &dev->dev; 406 407 /* 408 * Use reasonable defaults so platforms don't have to provide these. 409 */ 410 if (!dev->dev.dma_mask) 411 dev->dev.dma_mask = &dev->dev.coherent_dma_mask; 412 retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32)); 413 if (retval) { 414 dev_err(&dev->dev, "can't set coherent DMA mask: %d\n", retval); 415 return retval; 416 } 417 418 hsotg->regs = devm_platform_get_and_ioremap_resource(dev, 0, &res); 419 if (IS_ERR(hsotg->regs)) 420 return PTR_ERR(hsotg->regs); 421 422 dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", 423 (unsigned long)res->start, hsotg->regs); 424 425 retval = dwc2_lowlevel_hw_init(hsotg); 426 if (retval) 427 return retval; 428 429 spin_lock_init(&hsotg->lock); 430 431 hsotg->irq = platform_get_irq(dev, 0); 432 if (hsotg->irq < 0) 433 return hsotg->irq; 434 435 dev_dbg(hsotg->dev, "registering common handler for irq%d\n", 436 hsotg->irq); 437 retval = devm_request_irq(hsotg->dev, hsotg->irq, 438 dwc2_handle_common_intr, IRQF_SHARED, 439 dev_name(hsotg->dev), hsotg); 440 if (retval) 441 return retval; 442 443 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); 444 if (IS_ERR(hsotg->vbus_supply)) { 445 retval = PTR_ERR(hsotg->vbus_supply); 446 hsotg->vbus_supply = NULL; 447 if (retval != -ENODEV) 448 return retval; 449 } 450 451 retval = dwc2_lowlevel_hw_enable(hsotg); 452 if (retval) 453 return retval; 454 455 hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); 456 457 retval = dwc2_get_dr_mode(hsotg); 458 if (retval) 459 goto error; 460 461 hsotg->need_phy_for_wake = 462 of_property_read_bool(dev->dev.of_node, 463 "snps,need-phy-for-wake"); 464 465 /* 466 * Before performing any core related operations 467 * check core version. 468 */ 469 retval = dwc2_check_core_version(hsotg); 470 if (retval) 471 goto error; 472 473 /* 474 * Reset before dwc2_get_hwparams() then it could get power-on real 475 * reset value form registers. 476 */ 477 retval = dwc2_core_reset(hsotg, false); 478 if (retval) 479 goto error; 480 481 /* Detect config values from hardware */ 482 retval = dwc2_get_hwparams(hsotg); 483 if (retval) 484 goto error; 485 486 /* 487 * For OTG cores, set the force mode bits to reflect the value 488 * of dr_mode. Force mode bits should not be touched at any 489 * other time after this. 490 */ 491 dwc2_force_dr_mode(hsotg); 492 493 retval = dwc2_init_params(hsotg); 494 if (retval) 495 goto error; 496 497 if (hsotg->params.activate_stm_id_vb_detection) { 498 u32 ggpio; 499 500 hsotg->usb33d = devm_regulator_get(hsotg->dev, "usb33d"); 501 if (IS_ERR(hsotg->usb33d)) { 502 retval = PTR_ERR(hsotg->usb33d); 503 dev_err_probe(hsotg->dev, retval, "failed to request usb33d supply\n"); 504 goto error; 505 } 506 retval = regulator_enable(hsotg->usb33d); 507 if (retval) { 508 dev_err_probe(hsotg->dev, retval, "failed to enable usb33d supply\n"); 509 goto error; 510 } 511 512 ggpio = dwc2_readl(hsotg, GGPIO); 513 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 514 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 515 dwc2_writel(hsotg, ggpio, GGPIO); 516 517 /* ID/VBUS detection startup time */ 518 usleep_range(5000, 7000); 519 } 520 521 retval = dwc2_drd_init(hsotg); 522 if (retval) { 523 dev_err_probe(hsotg->dev, retval, "failed to initialize dual-role\n"); 524 goto error_init; 525 } 526 527 if (hsotg->dr_mode != USB_DR_MODE_HOST) { 528 retval = dwc2_gadget_init(hsotg); 529 if (retval) 530 goto error_drd; 531 hsotg->gadget_enabled = 1; 532 } 533 534 /* 535 * If we need PHY for wakeup we must be wakeup capable. 536 * When we have a device that can wake without the PHY we 537 * can adjust this condition. 538 */ 539 if (hsotg->need_phy_for_wake) 540 device_set_wakeup_capable(&dev->dev, true); 541 542 hsotg->reset_phy_on_wake = 543 of_property_read_bool(dev->dev.of_node, 544 "snps,reset-phy-on-wake"); 545 if (hsotg->reset_phy_on_wake && !hsotg->phy) { 546 dev_warn(hsotg->dev, 547 "Quirk reset-phy-on-wake only supports generic PHYs\n"); 548 hsotg->reset_phy_on_wake = false; 549 } 550 551 if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) { 552 retval = dwc2_hcd_init(hsotg); 553 if (retval) { 554 if (hsotg->gadget_enabled) 555 dwc2_hsotg_remove(hsotg); 556 goto error_drd; 557 } 558 hsotg->hcd_enabled = 1; 559 } 560 561 platform_set_drvdata(dev, hsotg); 562 hsotg->hibernated = 0; 563 564 dwc2_debugfs_init(hsotg); 565 566 /* Gadget code manages lowlevel hw on its own */ 567 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 568 dwc2_lowlevel_hw_disable(hsotg); 569 570 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 571 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 572 /* Postponed adding a new gadget to the udc class driver list */ 573 if (hsotg->gadget_enabled) { 574 retval = usb_add_gadget_udc(hsotg->dev, &hsotg->gadget); 575 if (retval) { 576 hsotg->gadget.udc = NULL; 577 dwc2_hsotg_remove(hsotg); 578 goto error_debugfs; 579 } 580 } 581 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ 582 return 0; 583 584 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ 585 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE) 586 error_debugfs: 587 dwc2_debugfs_exit(hsotg); 588 if (hsotg->hcd_enabled) 589 dwc2_hcd_remove(hsotg); 590 #endif 591 error_drd: 592 dwc2_drd_exit(hsotg); 593 594 error_init: 595 if (hsotg->params.activate_stm_id_vb_detection) 596 regulator_disable(hsotg->usb33d); 597 error: 598 if (hsotg->ll_hw_enabled) 599 dwc2_lowlevel_hw_disable(hsotg); 600 return retval; 601 } 602 603 static int __maybe_unused dwc2_suspend(struct device *dev) 604 { 605 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 606 bool is_device_mode = dwc2_is_device_mode(dwc2); 607 int ret = 0; 608 609 if (is_device_mode) 610 dwc2_hsotg_suspend(dwc2); 611 612 dwc2_drd_suspend(dwc2); 613 614 if (dwc2->params.activate_stm_id_vb_detection) { 615 unsigned long flags; 616 u32 ggpio, gotgctl; 617 618 /* 619 * Need to force the mode to the current mode to avoid Mode 620 * Mismatch Interrupt when ID detection will be disabled. 621 */ 622 dwc2_force_mode(dwc2, !is_device_mode); 623 624 spin_lock_irqsave(&dwc2->lock, flags); 625 gotgctl = dwc2_readl(dwc2, GOTGCTL); 626 /* bypass debounce filter, enable overrides */ 627 gotgctl |= GOTGCTL_DBNCE_FLTR_BYPASS; 628 gotgctl |= GOTGCTL_BVALOEN | GOTGCTL_AVALOEN; 629 /* Force A / B session if needed */ 630 if (gotgctl & GOTGCTL_ASESVLD) 631 gotgctl |= GOTGCTL_AVALOVAL; 632 if (gotgctl & GOTGCTL_BSESVLD) 633 gotgctl |= GOTGCTL_BVALOVAL; 634 dwc2_writel(dwc2, gotgctl, GOTGCTL); 635 spin_unlock_irqrestore(&dwc2->lock, flags); 636 637 ggpio = dwc2_readl(dwc2, GGPIO); 638 ggpio &= ~GGPIO_STM32_OTG_GCCFG_IDEN; 639 ggpio &= ~GGPIO_STM32_OTG_GCCFG_VBDEN; 640 dwc2_writel(dwc2, ggpio, GGPIO); 641 642 regulator_disable(dwc2->usb33d); 643 } 644 645 if (dwc2->ll_hw_enabled && 646 (is_device_mode || dwc2_host_can_poweroff_phy(dwc2))) { 647 ret = __dwc2_lowlevel_hw_disable(dwc2); 648 dwc2->phy_off_for_suspend = true; 649 } 650 651 return ret; 652 } 653 654 static int __maybe_unused dwc2_resume(struct device *dev) 655 { 656 struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev); 657 int ret = 0; 658 659 if (dwc2->phy_off_for_suspend && dwc2->ll_hw_enabled) { 660 ret = __dwc2_lowlevel_hw_enable(dwc2); 661 if (ret) 662 return ret; 663 } 664 dwc2->phy_off_for_suspend = false; 665 666 if (dwc2->params.activate_stm_id_vb_detection) { 667 unsigned long flags; 668 u32 ggpio, gotgctl; 669 670 ret = regulator_enable(dwc2->usb33d); 671 if (ret) 672 return ret; 673 674 ggpio = dwc2_readl(dwc2, GGPIO); 675 ggpio |= GGPIO_STM32_OTG_GCCFG_IDEN; 676 ggpio |= GGPIO_STM32_OTG_GCCFG_VBDEN; 677 dwc2_writel(dwc2, ggpio, GGPIO); 678 679 /* ID/VBUS detection startup time */ 680 usleep_range(5000, 7000); 681 682 spin_lock_irqsave(&dwc2->lock, flags); 683 gotgctl = dwc2_readl(dwc2, GOTGCTL); 684 gotgctl &= ~GOTGCTL_DBNCE_FLTR_BYPASS; 685 gotgctl &= ~(GOTGCTL_BVALOEN | GOTGCTL_AVALOEN | 686 GOTGCTL_BVALOVAL | GOTGCTL_AVALOVAL); 687 dwc2_writel(dwc2, gotgctl, GOTGCTL); 688 spin_unlock_irqrestore(&dwc2->lock, flags); 689 } 690 691 if (!dwc2->role_sw) { 692 /* Need to restore FORCEDEVMODE/FORCEHOSTMODE */ 693 dwc2_force_dr_mode(dwc2); 694 } else { 695 dwc2_drd_resume(dwc2); 696 } 697 698 if (dwc2_is_device_mode(dwc2)) 699 ret = dwc2_hsotg_resume(dwc2); 700 701 return ret; 702 } 703 704 static const struct dev_pm_ops dwc2_dev_pm_ops = { 705 SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume) 706 }; 707 708 static struct platform_driver dwc2_platform_driver = { 709 .driver = { 710 .name = dwc2_driver_name, 711 .of_match_table = dwc2_of_match_table, 712 .acpi_match_table = ACPI_PTR(dwc2_acpi_match), 713 .pm = &dwc2_dev_pm_ops, 714 }, 715 .probe = dwc2_driver_probe, 716 .remove = dwc2_driver_remove, 717 .shutdown = dwc2_driver_shutdown, 718 }; 719 720 module_platform_driver(dwc2_platform_driver); 721