1 /* 2 * Copyright (C) 2004-2016 Synopsys, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions, and the following disclaimer, 9 * without modification. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The names of the above-listed copyright holders may not be used 14 * to endorse or promote products derived from this software without 15 * specific prior written permission. 16 * 17 * ALTERNATIVELY, this software may be distributed under the terms of the 18 * GNU General Public License ("GPL") as published by the Free Software 19 * Foundation; either version 2 of the License, or (at your option) any 20 * later version. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_device.h> 38 39 #include "core.h" 40 41 static const struct dwc2_core_params params_hi6220 = { 42 .otg_cap = 2, /* No HNP/SRP capable */ 43 .otg_ver = 0, /* 1.3 */ 44 .dma_desc_enable = 0, 45 .dma_desc_fs_enable = 0, 46 .speed = 0, /* High Speed */ 47 .enable_dynamic_fifo = 1, 48 .en_multiple_tx_fifo = 1, 49 .host_rx_fifo_size = 512, 50 .host_nperio_tx_fifo_size = 512, 51 .host_perio_tx_fifo_size = 512, 52 .max_transfer_size = 65535, 53 .max_packet_count = 511, 54 .host_channels = 16, 55 .phy_type = 1, /* UTMI */ 56 .phy_utmi_width = 8, 57 .phy_ulpi_ddr = 0, /* Single */ 58 .phy_ulpi_ext_vbus = 0, 59 .i2c_enable = 0, 60 .ulpi_fs_ls = 0, 61 .host_support_fs_ls_low_power = 0, 62 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 63 .ts_dline = 0, 64 .reload_ctl = 0, 65 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 66 GAHBCFG_HBSTLEN_SHIFT, 67 .uframe_sched = 0, 68 .external_id_pin_ctl = -1, 69 .hibernation = -1, 70 }; 71 72 static const struct dwc2_core_params params_bcm2835 = { 73 .otg_cap = 0, /* HNP/SRP capable */ 74 .otg_ver = 0, /* 1.3 */ 75 .dma_desc_enable = 0, 76 .dma_desc_fs_enable = 0, 77 .speed = 0, /* High Speed */ 78 .enable_dynamic_fifo = 1, 79 .en_multiple_tx_fifo = 1, 80 .host_rx_fifo_size = 774, /* 774 DWORDs */ 81 .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */ 82 .host_perio_tx_fifo_size = 512, /* 512 DWORDs */ 83 .max_transfer_size = 65535, 84 .max_packet_count = 511, 85 .host_channels = 8, 86 .phy_type = 1, /* UTMI */ 87 .phy_utmi_width = 8, /* 8 bits */ 88 .phy_ulpi_ddr = 0, /* Single */ 89 .phy_ulpi_ext_vbus = 0, 90 .i2c_enable = 0, 91 .ulpi_fs_ls = 0, 92 .host_support_fs_ls_low_power = 0, 93 .host_ls_low_power_phy_clk = 0, /* 48 MHz */ 94 .ts_dline = 0, 95 .reload_ctl = 0, 96 .ahbcfg = 0x10, 97 .uframe_sched = 0, 98 .external_id_pin_ctl = -1, 99 .hibernation = -1, 100 }; 101 102 static const struct dwc2_core_params params_rk3066 = { 103 .otg_cap = 2, /* non-HNP/non-SRP */ 104 .otg_ver = -1, 105 .dma_desc_enable = 0, 106 .dma_desc_fs_enable = 0, 107 .speed = -1, 108 .enable_dynamic_fifo = 1, 109 .en_multiple_tx_fifo = -1, 110 .host_rx_fifo_size = 525, /* 525 DWORDs */ 111 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ 112 .host_perio_tx_fifo_size = 256, /* 256 DWORDs */ 113 .max_transfer_size = -1, 114 .max_packet_count = -1, 115 .host_channels = -1, 116 .phy_type = -1, 117 .phy_utmi_width = -1, 118 .phy_ulpi_ddr = -1, 119 .phy_ulpi_ext_vbus = -1, 120 .i2c_enable = -1, 121 .ulpi_fs_ls = -1, 122 .host_support_fs_ls_low_power = -1, 123 .host_ls_low_power_phy_clk = -1, 124 .ts_dline = -1, 125 .reload_ctl = -1, 126 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 127 GAHBCFG_HBSTLEN_SHIFT, 128 .uframe_sched = -1, 129 .external_id_pin_ctl = -1, 130 .hibernation = -1, 131 }; 132 133 static const struct dwc2_core_params params_ltq = { 134 .otg_cap = 2, /* non-HNP/non-SRP */ 135 .otg_ver = -1, 136 .dma_desc_enable = -1, 137 .dma_desc_fs_enable = -1, 138 .speed = -1, 139 .enable_dynamic_fifo = -1, 140 .en_multiple_tx_fifo = -1, 141 .host_rx_fifo_size = 288, /* 288 DWORDs */ 142 .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */ 143 .host_perio_tx_fifo_size = 96, /* 96 DWORDs */ 144 .max_transfer_size = 65535, 145 .max_packet_count = 511, 146 .host_channels = -1, 147 .phy_type = -1, 148 .phy_utmi_width = -1, 149 .phy_ulpi_ddr = -1, 150 .phy_ulpi_ext_vbus = -1, 151 .i2c_enable = -1, 152 .ulpi_fs_ls = -1, 153 .host_support_fs_ls_low_power = -1, 154 .host_ls_low_power_phy_clk = -1, 155 .ts_dline = -1, 156 .reload_ctl = -1, 157 .ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 158 GAHBCFG_HBSTLEN_SHIFT, 159 .uframe_sched = -1, 160 .external_id_pin_ctl = -1, 161 .hibernation = -1, 162 }; 163 164 static const struct dwc2_core_params params_amlogic = { 165 .otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE, 166 .otg_ver = -1, 167 .dma_desc_enable = 0, 168 .dma_desc_fs_enable = 0, 169 .speed = DWC2_SPEED_PARAM_HIGH, 170 .enable_dynamic_fifo = 1, 171 .en_multiple_tx_fifo = -1, 172 .host_rx_fifo_size = 512, 173 .host_nperio_tx_fifo_size = 500, 174 .host_perio_tx_fifo_size = 500, 175 .max_transfer_size = -1, 176 .max_packet_count = -1, 177 .host_channels = 16, 178 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, 179 .phy_utmi_width = -1, 180 .phy_ulpi_ddr = -1, 181 .phy_ulpi_ext_vbus = -1, 182 .i2c_enable = -1, 183 .ulpi_fs_ls = -1, 184 .host_support_fs_ls_low_power = -1, 185 .host_ls_low_power_phy_clk = -1, 186 .ts_dline = -1, 187 .reload_ctl = 1, 188 .ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 189 GAHBCFG_HBSTLEN_SHIFT, 190 .uframe_sched = 0, 191 .external_id_pin_ctl = -1, 192 .hibernation = -1, 193 }; 194 195 static const struct dwc2_core_params params_default = { 196 .otg_cap = -1, 197 .otg_ver = -1, 198 199 /* 200 * Disable descriptor dma mode by default as the HW can support 201 * it, but does not support it for SPLIT transactions. 202 * Disable it for FS devices as well. 203 */ 204 .dma_desc_enable = 0, 205 .dma_desc_fs_enable = 0, 206 207 .speed = -1, 208 .enable_dynamic_fifo = -1, 209 .en_multiple_tx_fifo = -1, 210 .host_rx_fifo_size = -1, 211 .host_nperio_tx_fifo_size = -1, 212 .host_perio_tx_fifo_size = -1, 213 .max_transfer_size = -1, 214 .max_packet_count = -1, 215 .host_channels = -1, 216 .phy_type = -1, 217 .phy_utmi_width = -1, 218 .phy_ulpi_ddr = -1, 219 .phy_ulpi_ext_vbus = -1, 220 .i2c_enable = -1, 221 .ulpi_fs_ls = -1, 222 .host_support_fs_ls_low_power = -1, 223 .host_ls_low_power_phy_clk = -1, 224 .ts_dline = -1, 225 .reload_ctl = -1, 226 .ahbcfg = -1, 227 .uframe_sched = -1, 228 .external_id_pin_ctl = -1, 229 .hibernation = -1, 230 }; 231 232 const struct of_device_id dwc2_of_match_table[] = { 233 { .compatible = "brcm,bcm2835-usb", .data = ¶ms_bcm2835 }, 234 { .compatible = "hisilicon,hi6220-usb", .data = ¶ms_hi6220 }, 235 { .compatible = "rockchip,rk3066-usb", .data = ¶ms_rk3066 }, 236 { .compatible = "lantiq,arx100-usb", .data = ¶ms_ltq }, 237 { .compatible = "lantiq,xrx200-usb", .data = ¶ms_ltq }, 238 { .compatible = "snps,dwc2", .data = NULL }, 239 { .compatible = "samsung,s3c6400-hsotg", .data = NULL}, 240 { .compatible = "amlogic,meson8b-usb", .data = ¶ms_amlogic }, 241 { .compatible = "amlogic,meson-gxbb-usb", .data = ¶ms_amlogic }, 242 { .compatible = "amcc,dwc-otg", .data = NULL }, 243 {}, 244 }; 245 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 246 247 static void dwc2_get_device_property(struct dwc2_hsotg *hsotg, 248 char *property, u8 size, u64 *value) 249 { 250 u32 val32; 251 252 switch (size) { 253 case 0: 254 *value = device_property_read_bool(hsotg->dev, property); 255 break; 256 case 1: 257 case 2: 258 case 4: 259 if (device_property_read_u32(hsotg->dev, property, &val32)) 260 return; 261 262 *value = val32; 263 break; 264 case 8: 265 if (device_property_read_u64(hsotg->dev, property, value)) 266 return; 267 268 break; 269 default: 270 /* 271 * The size is checked by the only function that calls 272 * this so this should never happen. 273 */ 274 WARN_ON(1); 275 return; 276 } 277 } 278 279 static void dwc2_set_core_param(void *param, u8 size, u64 value) 280 { 281 switch (size) { 282 case 0: 283 *((bool *)param) = !!value; 284 break; 285 case 1: 286 *((u8 *)param) = (u8)value; 287 break; 288 case 2: 289 *((u16 *)param) = (u16)value; 290 break; 291 case 4: 292 *((u32 *)param) = (u32)value; 293 break; 294 case 8: 295 *((u64 *)param) = (u64)value; 296 break; 297 default: 298 /* 299 * The size is checked by the only function that calls 300 * this so this should never happen. 301 */ 302 WARN_ON(1); 303 return; 304 } 305 } 306 307 /** 308 * dwc2_set_param() - Set a core parameter 309 * 310 * @hsotg: Programming view of the DWC_otg controller 311 * @param: Pointer to the parameter to set 312 * @lookup: True if the property should be looked up 313 * @property: The device property to read 314 * @legacy: The param value to set if @property is not available. This 315 * will typically be the legacy value set in the static 316 * params structure. 317 * @def: The default value 318 * @min: The minimum value 319 * @max: The maximum value 320 * @size: The size of the core parameter in bytes, or 0 for bool. 321 * 322 * This function looks up @property and sets the @param to that value. 323 * If the property doesn't exist it uses the passed-in @value. It will 324 * verify that the value falls between @min and @max. If it doesn't, 325 * it will output an error and set the parameter to either @def or, 326 * failing that, to @min. 327 * 328 * The @size is used to write to @param and to query the device 329 * properties so that this same function can be used with different 330 * types of parameters. 331 */ 332 static void dwc2_set_param(struct dwc2_hsotg *hsotg, void *param, 333 bool lookup, char *property, u64 legacy, 334 u64 def, u64 min, u64 max, u8 size) 335 { 336 u64 sizemax; 337 u64 value; 338 339 if (WARN_ON(!hsotg || !param || !property)) 340 return; 341 342 if (WARN((size > 8) || ((size & (size - 1)) != 0), 343 "Invalid size %d for %s\n", size, property)) 344 return; 345 346 dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n", 347 __func__, property, legacy, def, min, max, size); 348 349 sizemax = (1ULL << (size * 8)) - 1; 350 value = legacy; 351 352 /* Override legacy settings. */ 353 if (lookup) 354 dwc2_get_device_property(hsotg, property, size, &value); 355 356 /* 357 * While the value is not valid, try setting it to the default 358 * value, and failing that, set it to the minimum. 359 */ 360 while ((value < min) || (value > max)) { 361 /* Print an error unless the value is set to auto. */ 362 if (value != sizemax) 363 dev_err(hsotg->dev, "Invalid value %llu for param %s\n", 364 value, property); 365 366 /* 367 * If we are already the default, just set it to the 368 * minimum. 369 */ 370 if (value == def) { 371 dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n", 372 __func__, min); 373 value = min; 374 break; 375 } 376 377 /* Try the default value */ 378 dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n", 379 __func__, def); 380 value = def; 381 } 382 383 dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value); 384 dwc2_set_core_param(param, size, value); 385 } 386 387 /** 388 * dwc2_set_param_u32() - Set a u32 parameter 389 * 390 * See dwc2_set_param(). 391 */ 392 static void dwc2_set_param_u32(struct dwc2_hsotg *hsotg, u32 *param, 393 bool lookup, char *property, u16 legacy, 394 u16 def, u16 min, u16 max) 395 { 396 dwc2_set_param(hsotg, param, lookup, property, 397 legacy, def, min, max, 4); 398 } 399 400 /** 401 * dwc2_set_param_bool() - Set a bool parameter 402 * 403 * See dwc2_set_param(). 404 * 405 * Note: there is no 'legacy' argument here because there is no legacy 406 * source of bool params. 407 */ 408 static void dwc2_set_param_bool(struct dwc2_hsotg *hsotg, bool *param, 409 bool lookup, char *property, 410 bool def, bool min, bool max) 411 { 412 dwc2_set_param(hsotg, param, lookup, property, 413 def, def, min, max, 0); 414 } 415 416 #define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) || (a) > (c)) 417 418 /* Parameter access functions */ 419 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val) 420 { 421 int valid = 1; 422 423 switch (val) { 424 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 425 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 426 valid = 0; 427 break; 428 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 429 switch (hsotg->hw_params.op_mode) { 430 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 431 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 432 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 433 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 434 break; 435 default: 436 valid = 0; 437 break; 438 } 439 break; 440 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 441 /* always valid */ 442 break; 443 default: 444 valid = 0; 445 break; 446 } 447 448 if (!valid) { 449 if (val >= 0) 450 dev_err(hsotg->dev, 451 "%d invalid for otg_cap parameter. Check HW configuration.\n", 452 val); 453 switch (hsotg->hw_params.op_mode) { 454 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 455 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 456 break; 457 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 458 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 459 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 460 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 461 break; 462 default: 463 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 464 break; 465 } 466 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val); 467 } 468 469 hsotg->params.otg_cap = val; 470 } 471 472 static void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val) 473 { 474 int valid = 1; 475 476 if (val > 0 && (hsotg->params.host_dma <= 0 || 477 !hsotg->hw_params.dma_desc_enable)) 478 valid = 0; 479 if (val < 0) 480 valid = 0; 481 482 if (!valid) { 483 if (val >= 0) 484 dev_err(hsotg->dev, 485 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n", 486 val); 487 val = (hsotg->params.host_dma > 0 && 488 hsotg->hw_params.dma_desc_enable); 489 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val); 490 } 491 492 hsotg->params.dma_desc_enable = val; 493 } 494 495 static void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val) 496 { 497 int valid = 1; 498 499 if (val > 0 && (hsotg->params.host_dma <= 0 || 500 !hsotg->hw_params.dma_desc_enable)) 501 valid = 0; 502 if (val < 0) 503 valid = 0; 504 505 if (!valid) { 506 if (val >= 0) 507 dev_err(hsotg->dev, 508 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n", 509 val); 510 val = (hsotg->params.host_dma > 0 && 511 hsotg->hw_params.dma_desc_enable); 512 } 513 514 hsotg->params.dma_desc_fs_enable = val; 515 dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val); 516 } 517 518 static void 519 dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg, 520 int val) 521 { 522 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 523 if (val >= 0) { 524 dev_err(hsotg->dev, 525 "Wrong value for host_support_fs_low_power\n"); 526 dev_err(hsotg->dev, 527 "host_support_fs_low_power must be 0 or 1\n"); 528 } 529 val = 0; 530 dev_dbg(hsotg->dev, 531 "Setting host_support_fs_low_power to %d\n", val); 532 } 533 534 hsotg->params.host_support_fs_ls_low_power = val; 535 } 536 537 static void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, 538 int val) 539 { 540 int valid = 1; 541 542 if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo) 543 valid = 0; 544 if (val < 0) 545 valid = 0; 546 547 if (!valid) { 548 if (val >= 0) 549 dev_err(hsotg->dev, 550 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n", 551 val); 552 val = hsotg->hw_params.enable_dynamic_fifo; 553 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val); 554 } 555 556 hsotg->params.enable_dynamic_fifo = val; 557 } 558 559 static void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val) 560 { 561 int valid = 1; 562 563 if (val < 16 || val > hsotg->hw_params.rx_fifo_size) 564 valid = 0; 565 566 if (!valid) { 567 if (val >= 0) 568 dev_err(hsotg->dev, 569 "%d invalid for host_rx_fifo_size. Check HW configuration.\n", 570 val); 571 val = hsotg->hw_params.rx_fifo_size; 572 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val); 573 } 574 575 hsotg->params.host_rx_fifo_size = val; 576 } 577 578 static void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, 579 int val) 580 { 581 int valid = 1; 582 583 if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size) 584 valid = 0; 585 586 if (!valid) { 587 if (val >= 0) 588 dev_err(hsotg->dev, 589 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", 590 val); 591 val = hsotg->hw_params.host_nperio_tx_fifo_size; 592 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n", 593 val); 594 } 595 596 hsotg->params.host_nperio_tx_fifo_size = val; 597 } 598 599 static void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, 600 int val) 601 { 602 int valid = 1; 603 604 if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size) 605 valid = 0; 606 607 if (!valid) { 608 if (val >= 0) 609 dev_err(hsotg->dev, 610 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", 611 val); 612 val = hsotg->hw_params.host_perio_tx_fifo_size; 613 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n", 614 val); 615 } 616 617 hsotg->params.host_perio_tx_fifo_size = val; 618 } 619 620 static void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val) 621 { 622 int valid = 1; 623 624 if (val < 2047 || val > hsotg->hw_params.max_transfer_size) 625 valid = 0; 626 627 if (!valid) { 628 if (val >= 0) 629 dev_err(hsotg->dev, 630 "%d invalid for max_transfer_size. Check HW configuration.\n", 631 val); 632 val = hsotg->hw_params.max_transfer_size; 633 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val); 634 } 635 636 hsotg->params.max_transfer_size = val; 637 } 638 639 static void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val) 640 { 641 int valid = 1; 642 643 if (val < 15 || val > hsotg->hw_params.max_packet_count) 644 valid = 0; 645 646 if (!valid) { 647 if (val >= 0) 648 dev_err(hsotg->dev, 649 "%d invalid for max_packet_count. Check HW configuration.\n", 650 val); 651 val = hsotg->hw_params.max_packet_count; 652 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val); 653 } 654 655 hsotg->params.max_packet_count = val; 656 } 657 658 static void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val) 659 { 660 int valid = 1; 661 662 if (val < 1 || val > hsotg->hw_params.host_channels) 663 valid = 0; 664 665 if (!valid) { 666 if (val >= 0) 667 dev_err(hsotg->dev, 668 "%d invalid for host_channels. Check HW configuration.\n", 669 val); 670 val = hsotg->hw_params.host_channels; 671 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val); 672 } 673 674 hsotg->params.host_channels = val; 675 } 676 677 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val) 678 { 679 int valid = 0; 680 u32 hs_phy_type, fs_phy_type; 681 682 if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS, 683 DWC2_PHY_TYPE_PARAM_ULPI)) { 684 if (val >= 0) { 685 dev_err(hsotg->dev, "Wrong value for phy_type\n"); 686 dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n"); 687 } 688 689 valid = 0; 690 } 691 692 hs_phy_type = hsotg->hw_params.hs_phy_type; 693 fs_phy_type = hsotg->hw_params.fs_phy_type; 694 if (val == DWC2_PHY_TYPE_PARAM_UTMI && 695 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 696 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 697 valid = 1; 698 else if (val == DWC2_PHY_TYPE_PARAM_ULPI && 699 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI || 700 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 701 valid = 1; 702 else if (val == DWC2_PHY_TYPE_PARAM_FS && 703 fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 704 valid = 1; 705 706 if (!valid) { 707 if (val >= 0) 708 dev_err(hsotg->dev, 709 "%d invalid for phy_type. Check HW configuration.\n", 710 val); 711 val = DWC2_PHY_TYPE_PARAM_FS; 712 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 713 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 714 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 715 val = DWC2_PHY_TYPE_PARAM_UTMI; 716 else 717 val = DWC2_PHY_TYPE_PARAM_ULPI; 718 } 719 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val); 720 } 721 722 hsotg->params.phy_type = val; 723 } 724 725 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg) 726 { 727 return hsotg->params.phy_type; 728 } 729 730 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val) 731 { 732 int valid = 1; 733 734 if (DWC2_OUT_OF_BOUNDS(val, 0, 2)) { 735 if (val >= 0) { 736 dev_err(hsotg->dev, "Wrong value for speed parameter\n"); 737 dev_err(hsotg->dev, "max_speed parameter must be 0, 1, or 2\n"); 738 } 739 valid = 0; 740 } 741 742 if (dwc2_is_hs_iot(hsotg) && 743 val == DWC2_SPEED_PARAM_LOW) 744 valid = 0; 745 746 if (val == DWC2_SPEED_PARAM_HIGH && 747 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 748 valid = 0; 749 750 if (!valid) { 751 if (val >= 0) 752 dev_err(hsotg->dev, 753 "%d invalid for speed parameter. Check HW configuration.\n", 754 val); 755 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ? 756 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 757 dev_dbg(hsotg->dev, "Setting speed to %d\n", val); 758 } 759 760 hsotg->params.speed = val; 761 } 762 763 static void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, 764 int val) 765 { 766 int valid = 1; 767 768 if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ, 769 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) { 770 if (val >= 0) { 771 dev_err(hsotg->dev, 772 "Wrong value for host_ls_low_power_phy_clk parameter\n"); 773 dev_err(hsotg->dev, 774 "host_ls_low_power_phy_clk must be 0 or 1\n"); 775 } 776 valid = 0; 777 } 778 779 if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ && 780 dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS) 781 valid = 0; 782 783 if (!valid) { 784 if (val >= 0) 785 dev_err(hsotg->dev, 786 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", 787 val); 788 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS 789 ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 790 : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; 791 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n", 792 val); 793 } 794 795 hsotg->params.host_ls_low_power_phy_clk = val; 796 } 797 798 static void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val) 799 { 800 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 801 if (val >= 0) { 802 dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n"); 803 dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n"); 804 } 805 val = 0; 806 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val); 807 } 808 809 hsotg->params.phy_ulpi_ddr = val; 810 } 811 812 static void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val) 813 { 814 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 815 if (val >= 0) { 816 dev_err(hsotg->dev, 817 "Wrong value for phy_ulpi_ext_vbus\n"); 818 dev_err(hsotg->dev, 819 "phy_ulpi_ext_vbus must be 0 or 1\n"); 820 } 821 val = 0; 822 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val); 823 } 824 825 hsotg->params.phy_ulpi_ext_vbus = val; 826 } 827 828 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val) 829 { 830 int valid = 0; 831 832 switch (hsotg->hw_params.utmi_phy_data_width) { 833 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 834 valid = (val == 8); 835 break; 836 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 837 valid = (val == 16); 838 break; 839 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 840 valid = (val == 8 || val == 16); 841 break; 842 } 843 844 if (!valid) { 845 if (val >= 0) { 846 dev_err(hsotg->dev, 847 "%d invalid for phy_utmi_width. Check HW configuration.\n", 848 val); 849 } 850 val = (hsotg->hw_params.utmi_phy_data_width == 851 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 852 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val); 853 } 854 855 hsotg->params.phy_utmi_width = val; 856 } 857 858 static void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val) 859 { 860 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 861 if (val >= 0) { 862 dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n"); 863 dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n"); 864 } 865 val = 0; 866 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val); 867 } 868 869 hsotg->params.ulpi_fs_ls = val; 870 } 871 872 static void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val) 873 { 874 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 875 if (val >= 0) { 876 dev_err(hsotg->dev, "Wrong value for ts_dline\n"); 877 dev_err(hsotg->dev, "ts_dline must be 0 or 1\n"); 878 } 879 val = 0; 880 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val); 881 } 882 883 hsotg->params.ts_dline = val; 884 } 885 886 static void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val) 887 { 888 int valid = 1; 889 890 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 891 if (val >= 0) { 892 dev_err(hsotg->dev, "Wrong value for i2c_enable\n"); 893 dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n"); 894 } 895 896 valid = 0; 897 } 898 899 if (val == 1 && !(hsotg->hw_params.i2c_enable)) 900 valid = 0; 901 902 if (!valid) { 903 if (val >= 0) 904 dev_err(hsotg->dev, 905 "%d invalid for i2c_enable. Check HW configuration.\n", 906 val); 907 val = hsotg->hw_params.i2c_enable; 908 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val); 909 } 910 911 hsotg->params.i2c_enable = val; 912 } 913 914 static void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, 915 int val) 916 { 917 int valid = 1; 918 919 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 920 if (val >= 0) { 921 dev_err(hsotg->dev, 922 "Wrong value for en_multiple_tx_fifo,\n"); 923 dev_err(hsotg->dev, 924 "en_multiple_tx_fifo must be 0 or 1\n"); 925 } 926 valid = 0; 927 } 928 929 if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo) 930 valid = 0; 931 932 if (!valid) { 933 if (val >= 0) 934 dev_err(hsotg->dev, 935 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", 936 val); 937 val = hsotg->hw_params.en_multiple_tx_fifo; 938 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val); 939 } 940 941 hsotg->params.en_multiple_tx_fifo = val; 942 } 943 944 static void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val) 945 { 946 int valid = 1; 947 948 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 949 if (val >= 0) { 950 dev_err(hsotg->dev, 951 "'%d' invalid for parameter reload_ctl\n", val); 952 dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n"); 953 } 954 valid = 0; 955 } 956 957 if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a) 958 valid = 0; 959 960 if (!valid) { 961 if (val >= 0) 962 dev_err(hsotg->dev, 963 "%d invalid for parameter reload_ctl. Check HW configuration.\n", 964 val); 965 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a; 966 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val); 967 } 968 969 hsotg->params.reload_ctl = val; 970 } 971 972 static void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val) 973 { 974 if (val != -1) 975 hsotg->params.ahbcfg = val; 976 else 977 hsotg->params.ahbcfg = GAHBCFG_HBSTLEN_INCR4 << 978 GAHBCFG_HBSTLEN_SHIFT; 979 } 980 981 static void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val) 982 { 983 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 984 if (val >= 0) { 985 dev_err(hsotg->dev, 986 "'%d' invalid for parameter otg_ver\n", val); 987 dev_err(hsotg->dev, 988 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n"); 989 } 990 val = 0; 991 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val); 992 } 993 994 hsotg->params.otg_ver = val; 995 } 996 997 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val) 998 { 999 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1000 if (val >= 0) { 1001 dev_err(hsotg->dev, 1002 "'%d' invalid for parameter uframe_sched\n", 1003 val); 1004 dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n"); 1005 } 1006 val = 1; 1007 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val); 1008 } 1009 1010 hsotg->params.uframe_sched = val; 1011 } 1012 1013 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg, 1014 int val) 1015 { 1016 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1017 if (val >= 0) { 1018 dev_err(hsotg->dev, 1019 "'%d' invalid for parameter external_id_pin_ctl\n", 1020 val); 1021 dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n"); 1022 } 1023 val = 0; 1024 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val); 1025 } 1026 1027 hsotg->params.external_id_pin_ctl = val; 1028 } 1029 1030 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg, 1031 int val) 1032 { 1033 if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) { 1034 if (val >= 0) { 1035 dev_err(hsotg->dev, 1036 "'%d' invalid for parameter hibernation\n", 1037 val); 1038 dev_err(hsotg->dev, "hibernation must be 0 or 1\n"); 1039 } 1040 val = 0; 1041 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val); 1042 } 1043 1044 hsotg->params.hibernation = val; 1045 } 1046 1047 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 1048 { 1049 int i; 1050 int num; 1051 char *property = "g-tx-fifo-size"; 1052 struct dwc2_core_params *p = &hsotg->params; 1053 1054 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 1055 1056 /* Read tx fifo sizes */ 1057 num = device_property_read_u32_array(hsotg->dev, property, NULL, 0); 1058 1059 if (num > 0) { 1060 device_property_read_u32_array(hsotg->dev, property, 1061 &p->g_tx_fifo_size[1], 1062 num); 1063 } else { 1064 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE; 1065 1066 memcpy(&p->g_tx_fifo_size[1], 1067 p_tx_fifo, 1068 sizeof(p_tx_fifo)); 1069 1070 num = ARRAY_SIZE(p_tx_fifo); 1071 } 1072 1073 for (i = 0; i < num; i++) { 1074 if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size)) 1075 break; 1076 1077 dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n", 1078 property, i + 1, p->g_tx_fifo_size[i + 1]); 1079 } 1080 } 1081 1082 static void dwc2_set_gadget_dma(struct dwc2_hsotg *hsotg) 1083 { 1084 struct dwc2_hw_params *hw = &hsotg->hw_params; 1085 struct dwc2_core_params *p = &hsotg->params; 1086 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 1087 1088 /* Buffer DMA */ 1089 dwc2_set_param_bool(hsotg, &p->g_dma, 1090 false, "gadget-dma", 1091 dma_capable, false, 1092 dma_capable); 1093 1094 /* DMA Descriptor */ 1095 dwc2_set_param_bool(hsotg, &p->g_dma_desc, false, 1096 "gadget-dma-desc", 1097 !!hw->dma_desc_enable, false, 1098 !!hw->dma_desc_enable); 1099 } 1100 1101 /** 1102 * dwc2_set_parameters() - Set all core parameters. 1103 * 1104 * @hsotg: Programming view of the DWC_otg controller 1105 * @params: The parameters to set 1106 */ 1107 static void dwc2_set_parameters(struct dwc2_hsotg *hsotg, 1108 const struct dwc2_core_params *params) 1109 { 1110 struct dwc2_hw_params *hw = &hsotg->hw_params; 1111 struct dwc2_core_params *p = &hsotg->params; 1112 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 1113 1114 dwc2_set_param_otg_cap(hsotg, params->otg_cap); 1115 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 1116 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 1117 dev_dbg(hsotg->dev, "Setting HOST parameters\n"); 1118 1119 dwc2_set_param_bool(hsotg, &p->host_dma, 1120 false, "host-dma", 1121 dma_capable, false, 1122 dma_capable); 1123 dwc2_set_param_host_rx_fifo_size(hsotg, 1124 params->host_rx_fifo_size); 1125 dwc2_set_param_host_nperio_tx_fifo_size(hsotg, 1126 params->host_nperio_tx_fifo_size); 1127 dwc2_set_param_host_perio_tx_fifo_size(hsotg, 1128 params->host_perio_tx_fifo_size); 1129 } 1130 dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable); 1131 dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable); 1132 1133 dwc2_set_param_host_support_fs_ls_low_power(hsotg, 1134 params->host_support_fs_ls_low_power); 1135 dwc2_set_param_enable_dynamic_fifo(hsotg, 1136 params->enable_dynamic_fifo); 1137 dwc2_set_param_max_transfer_size(hsotg, 1138 params->max_transfer_size); 1139 dwc2_set_param_max_packet_count(hsotg, 1140 params->max_packet_count); 1141 dwc2_set_param_host_channels(hsotg, params->host_channels); 1142 dwc2_set_param_phy_type(hsotg, params->phy_type); 1143 dwc2_set_param_speed(hsotg, params->speed); 1144 dwc2_set_param_host_ls_low_power_phy_clk(hsotg, 1145 params->host_ls_low_power_phy_clk); 1146 dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr); 1147 dwc2_set_param_phy_ulpi_ext_vbus(hsotg, 1148 params->phy_ulpi_ext_vbus); 1149 dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width); 1150 dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls); 1151 dwc2_set_param_ts_dline(hsotg, params->ts_dline); 1152 dwc2_set_param_i2c_enable(hsotg, params->i2c_enable); 1153 dwc2_set_param_en_multiple_tx_fifo(hsotg, 1154 params->en_multiple_tx_fifo); 1155 dwc2_set_param_reload_ctl(hsotg, params->reload_ctl); 1156 dwc2_set_param_ahbcfg(hsotg, params->ahbcfg); 1157 dwc2_set_param_otg_ver(hsotg, params->otg_ver); 1158 dwc2_set_param_uframe_sched(hsotg, params->uframe_sched); 1159 dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl); 1160 dwc2_set_param_hibernation(hsotg, params->hibernation); 1161 1162 /* 1163 * Set devicetree-only parameters. These parameters do not 1164 * take any values from @params. 1165 */ 1166 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 1167 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 1168 dev_dbg(hsotg->dev, "Setting peripheral device properties\n"); 1169 1170 dwc2_set_gadget_dma(hsotg); 1171 1172 /* 1173 * The values for g_rx_fifo_size (2048) and 1174 * g_np_tx_fifo_size (1024) come from the legacy s3c 1175 * gadget driver. These defaults have been hard-coded 1176 * for some time so many platforms depend on these 1177 * values. Leave them as defaults for now and only 1178 * auto-detect if the hardware does not support the 1179 * default. 1180 */ 1181 dwc2_set_param_u32(hsotg, &p->g_rx_fifo_size, 1182 true, "g-rx-fifo-size", 2048, 1183 hw->rx_fifo_size, 1184 16, hw->rx_fifo_size); 1185 1186 dwc2_set_param_u32(hsotg, &p->g_np_tx_fifo_size, 1187 true, "g-np-tx-fifo-size", 1024, 1188 hw->dev_nperio_tx_fifo_size, 1189 16, hw->dev_nperio_tx_fifo_size); 1190 1191 dwc2_set_param_tx_fifo_sizes(hsotg); 1192 } 1193 } 1194 1195 /* 1196 * Gets host hardware parameters. Forces host mode if not currently in 1197 * host mode. Should be called immediately after a core soft reset in 1198 * order to get the reset values. 1199 */ 1200 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 1201 { 1202 struct dwc2_hw_params *hw = &hsotg->hw_params; 1203 u32 gnptxfsiz; 1204 u32 hptxfsiz; 1205 bool forced; 1206 1207 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 1208 return; 1209 1210 forced = dwc2_force_mode_if_needed(hsotg, true); 1211 1212 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1213 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 1214 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1215 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); 1216 1217 if (forced) 1218 dwc2_clear_force_mode(hsotg); 1219 1220 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1221 FIFOSIZE_DEPTH_SHIFT; 1222 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1223 FIFOSIZE_DEPTH_SHIFT; 1224 } 1225 1226 /* 1227 * Gets device hardware parameters. Forces device mode if not 1228 * currently in device mode. Should be called immediately after a core 1229 * soft reset in order to get the reset values. 1230 */ 1231 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 1232 { 1233 struct dwc2_hw_params *hw = &hsotg->hw_params; 1234 bool forced; 1235 u32 gnptxfsiz; 1236 1237 if (hsotg->dr_mode == USB_DR_MODE_HOST) 1238 return; 1239 1240 forced = dwc2_force_mode_if_needed(hsotg, false); 1241 1242 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 1243 dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); 1244 1245 if (forced) 1246 dwc2_clear_force_mode(hsotg); 1247 1248 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 1249 FIFOSIZE_DEPTH_SHIFT; 1250 } 1251 1252 /** 1253 * During device initialization, read various hardware configuration 1254 * registers and interpret the contents. 1255 */ 1256 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 1257 { 1258 struct dwc2_hw_params *hw = &hsotg->hw_params; 1259 unsigned int width; 1260 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 1261 u32 grxfsiz; 1262 1263 /* 1264 * Attempt to ensure this device is really a DWC_otg Controller. 1265 * Read and verify the GSNPSID register contents. The value should be 1266 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 1267 * as in "OTG version 2.xx" or "OTG version 3.xx". 1268 */ 1269 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 1270 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 1271 (hw->snpsid & 0xfffff000) != 0x4f543000 && 1272 (hw->snpsid & 0xffff0000) != 0x55310000 && 1273 (hw->snpsid & 0xffff0000) != 0x55320000) { 1274 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 1275 hw->snpsid); 1276 return -ENODEV; 1277 } 1278 1279 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 1280 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 1281 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 1282 1283 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 1284 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 1285 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 1286 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 1287 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 1288 1289 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); 1290 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); 1291 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3); 1292 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4); 1293 dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); 1294 1295 /* 1296 * Host specific hardware parameters. Reading these parameters 1297 * requires the controller to be in host mode. The mode will 1298 * be forced, if necessary, to read these values. 1299 */ 1300 dwc2_get_host_hwparams(hsotg); 1301 dwc2_get_dev_hwparams(hsotg); 1302 1303 /* hwcfg1 */ 1304 hw->dev_ep_dirs = hwcfg1; 1305 1306 /* hwcfg2 */ 1307 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 1308 GHWCFG2_OP_MODE_SHIFT; 1309 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 1310 GHWCFG2_ARCHITECTURE_SHIFT; 1311 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 1312 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 1313 GHWCFG2_NUM_HOST_CHAN_SHIFT); 1314 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 1315 GHWCFG2_HS_PHY_TYPE_SHIFT; 1316 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 1317 GHWCFG2_FS_PHY_TYPE_SHIFT; 1318 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 1319 GHWCFG2_NUM_DEV_EP_SHIFT; 1320 hw->nperio_tx_q_depth = 1321 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 1322 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 1323 hw->host_perio_tx_q_depth = 1324 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 1325 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 1326 hw->dev_token_q_depth = 1327 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 1328 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 1329 1330 /* hwcfg3 */ 1331 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 1332 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 1333 hw->max_transfer_size = (1 << (width + 11)) - 1; 1334 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 1335 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 1336 hw->max_packet_count = (1 << (width + 4)) - 1; 1337 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 1338 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 1339 GHWCFG3_DFIFO_DEPTH_SHIFT; 1340 1341 /* hwcfg4 */ 1342 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 1343 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 1344 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 1345 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 1346 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 1347 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 1348 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 1349 1350 /* fifo sizes */ 1351 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 1352 GRXFSIZ_DEPTH_SHIFT; 1353 1354 dev_dbg(hsotg->dev, "Detected values from hardware:\n"); 1355 dev_dbg(hsotg->dev, " op_mode=%d\n", 1356 hw->op_mode); 1357 dev_dbg(hsotg->dev, " arch=%d\n", 1358 hw->arch); 1359 dev_dbg(hsotg->dev, " dma_desc_enable=%d\n", 1360 hw->dma_desc_enable); 1361 dev_dbg(hsotg->dev, " power_optimized=%d\n", 1362 hw->power_optimized); 1363 dev_dbg(hsotg->dev, " i2c_enable=%d\n", 1364 hw->i2c_enable); 1365 dev_dbg(hsotg->dev, " hs_phy_type=%d\n", 1366 hw->hs_phy_type); 1367 dev_dbg(hsotg->dev, " fs_phy_type=%d\n", 1368 hw->fs_phy_type); 1369 dev_dbg(hsotg->dev, " utmi_phy_data_width=%d\n", 1370 hw->utmi_phy_data_width); 1371 dev_dbg(hsotg->dev, " num_dev_ep=%d\n", 1372 hw->num_dev_ep); 1373 dev_dbg(hsotg->dev, " num_dev_perio_in_ep=%d\n", 1374 hw->num_dev_perio_in_ep); 1375 dev_dbg(hsotg->dev, " host_channels=%d\n", 1376 hw->host_channels); 1377 dev_dbg(hsotg->dev, " max_transfer_size=%d\n", 1378 hw->max_transfer_size); 1379 dev_dbg(hsotg->dev, " max_packet_count=%d\n", 1380 hw->max_packet_count); 1381 dev_dbg(hsotg->dev, " nperio_tx_q_depth=0x%0x\n", 1382 hw->nperio_tx_q_depth); 1383 dev_dbg(hsotg->dev, " host_perio_tx_q_depth=0x%0x\n", 1384 hw->host_perio_tx_q_depth); 1385 dev_dbg(hsotg->dev, " dev_token_q_depth=0x%0x\n", 1386 hw->dev_token_q_depth); 1387 dev_dbg(hsotg->dev, " enable_dynamic_fifo=%d\n", 1388 hw->enable_dynamic_fifo); 1389 dev_dbg(hsotg->dev, " en_multiple_tx_fifo=%d\n", 1390 hw->en_multiple_tx_fifo); 1391 dev_dbg(hsotg->dev, " total_fifo_size=%d\n", 1392 hw->total_fifo_size); 1393 dev_dbg(hsotg->dev, " rx_fifo_size=%d\n", 1394 hw->rx_fifo_size); 1395 dev_dbg(hsotg->dev, " host_nperio_tx_fifo_size=%d\n", 1396 hw->host_nperio_tx_fifo_size); 1397 dev_dbg(hsotg->dev, " host_perio_tx_fifo_size=%d\n", 1398 hw->host_perio_tx_fifo_size); 1399 dev_dbg(hsotg->dev, "\n"); 1400 1401 return 0; 1402 } 1403 1404 int dwc2_init_params(struct dwc2_hsotg *hsotg) 1405 { 1406 const struct of_device_id *match; 1407 struct dwc2_core_params params; 1408 1409 match = of_match_device(dwc2_of_match_table, hsotg->dev); 1410 if (match && match->data) 1411 params = *((struct dwc2_core_params *)match->data); 1412 else 1413 params = params_default; 1414 1415 if (dwc2_is_fs_iot(hsotg)) { 1416 params.speed = DWC2_SPEED_PARAM_FULL; 1417 params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 1418 } 1419 1420 dwc2_set_parameters(hsotg, ¶ms); 1421 1422 return 0; 1423 } 1424