1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 #include <linux/usb/of.h> 40 41 #include "core.h" 42 43 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 44 { 45 struct dwc2_core_params *p = &hsotg->params; 46 47 p->host_rx_fifo_size = 774; 48 p->max_transfer_size = 65535; 49 p->max_packet_count = 511; 50 p->ahbcfg = 0x10; 51 } 52 53 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 54 { 55 struct dwc2_core_params *p = &hsotg->params; 56 57 p->otg_caps.hnp_support = false; 58 p->otg_caps.srp_support = false; 59 p->speed = DWC2_SPEED_PARAM_HIGH; 60 p->host_rx_fifo_size = 512; 61 p->host_nperio_tx_fifo_size = 512; 62 p->host_perio_tx_fifo_size = 512; 63 p->max_transfer_size = 65535; 64 p->max_packet_count = 511; 65 p->host_channels = 16; 66 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 67 p->phy_utmi_width = 8; 68 p->i2c_enable = false; 69 p->reload_ctl = false; 70 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 71 GAHBCFG_HBSTLEN_SHIFT; 72 p->change_speed_quirk = true; 73 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 74 } 75 76 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 77 { 78 struct dwc2_core_params *p = &hsotg->params; 79 80 p->otg_caps.hnp_support = false; 81 p->speed = DWC2_SPEED_PARAM_HIGH; 82 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 83 p->phy_utmi_width = 16; 84 p->activate_ingenic_overcurrent_detection = 85 !device_property_read_bool(hsotg->dev, "disable-over-current"); 86 } 87 88 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 89 { 90 struct dwc2_core_params *p = &hsotg->params; 91 92 p->otg_caps.hnp_support = false; 93 p->speed = DWC2_SPEED_PARAM_HIGH; 94 p->host_channels = 16; 95 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 96 p->phy_utmi_width = 16; 97 p->activate_ingenic_overcurrent_detection = 98 !device_property_read_bool(hsotg->dev, "disable-over-current"); 99 } 100 101 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 102 { 103 struct dwc2_core_params *p = &hsotg->params; 104 105 p->otg_caps.hnp_support = false; 106 p->speed = DWC2_SPEED_PARAM_HIGH; 107 p->host_rx_fifo_size = 1024; 108 p->host_nperio_tx_fifo_size = 1024; 109 p->host_perio_tx_fifo_size = 1024; 110 p->host_channels = 16; 111 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 112 p->phy_utmi_width = 16; 113 p->activate_ingenic_overcurrent_detection = 114 !device_property_read_bool(hsotg->dev, "disable-over-current"); 115 } 116 117 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 118 { 119 struct dwc2_core_params *p = &hsotg->params; 120 121 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 122 p->no_clock_gating = true; 123 p->phy_utmi_width = 8; 124 } 125 126 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 127 { 128 struct dwc2_core_params *p = &hsotg->params; 129 130 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 131 p->no_clock_gating = true; 132 } 133 134 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 135 { 136 struct dwc2_core_params *p = &hsotg->params; 137 138 p->otg_caps.hnp_support = false; 139 p->otg_caps.srp_support = false; 140 p->host_rx_fifo_size = 525; 141 p->host_nperio_tx_fifo_size = 128; 142 p->host_perio_tx_fifo_size = 256; 143 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 144 GAHBCFG_HBSTLEN_SHIFT; 145 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 146 } 147 148 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 149 { 150 struct dwc2_core_params *p = &hsotg->params; 151 152 p->otg_caps.hnp_support = false; 153 p->otg_caps.srp_support = false; 154 p->host_rx_fifo_size = 288; 155 p->host_nperio_tx_fifo_size = 128; 156 p->host_perio_tx_fifo_size = 96; 157 p->max_transfer_size = 65535; 158 p->max_packet_count = 511; 159 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 160 GAHBCFG_HBSTLEN_SHIFT; 161 } 162 163 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 164 { 165 struct dwc2_core_params *p = &hsotg->params; 166 167 p->otg_caps.hnp_support = false; 168 p->otg_caps.srp_support = false; 169 p->speed = DWC2_SPEED_PARAM_HIGH; 170 p->host_rx_fifo_size = 512; 171 p->host_nperio_tx_fifo_size = 500; 172 p->host_perio_tx_fifo_size = 500; 173 p->host_channels = 16; 174 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 175 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 176 GAHBCFG_HBSTLEN_SHIFT; 177 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 178 } 179 180 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 181 { 182 struct dwc2_core_params *p = &hsotg->params; 183 184 p->lpm = false; 185 p->lpm_clock_gating = false; 186 p->besl = false; 187 p->hird_threshold_en = false; 188 } 189 190 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 191 { 192 struct dwc2_core_params *p = &hsotg->params; 193 194 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 195 } 196 197 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 198 { 199 struct dwc2_core_params *p = &hsotg->params; 200 201 p->otg_caps.hnp_support = false; 202 p->otg_caps.srp_support = false; 203 p->speed = DWC2_SPEED_PARAM_FULL; 204 p->host_rx_fifo_size = 128; 205 p->host_nperio_tx_fifo_size = 96; 206 p->host_perio_tx_fifo_size = 96; 207 p->max_packet_count = 256; 208 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 209 p->i2c_enable = false; 210 p->activate_stm_fs_transceiver = true; 211 } 212 213 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 214 { 215 struct dwc2_core_params *p = &hsotg->params; 216 217 p->host_rx_fifo_size = 622; 218 p->host_nperio_tx_fifo_size = 128; 219 p->host_perio_tx_fifo_size = 256; 220 } 221 222 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 223 { 224 struct dwc2_core_params *p = &hsotg->params; 225 226 p->otg_caps.hnp_support = false; 227 p->otg_caps.srp_support = false; 228 p->otg_caps.otg_rev = 0x200; 229 p->speed = DWC2_SPEED_PARAM_FULL; 230 p->host_rx_fifo_size = 128; 231 p->host_nperio_tx_fifo_size = 96; 232 p->host_perio_tx_fifo_size = 96; 233 p->max_packet_count = 256; 234 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 235 p->i2c_enable = false; 236 p->activate_stm_fs_transceiver = true; 237 p->activate_stm_id_vb_detection = true; 238 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 239 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 240 p->host_support_fs_ls_low_power = true; 241 p->host_ls_low_power_phy_clk = true; 242 } 243 244 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 245 { 246 struct dwc2_core_params *p = &hsotg->params; 247 248 p->otg_caps.hnp_support = false; 249 p->otg_caps.srp_support = false; 250 p->otg_caps.otg_rev = 0x200; 251 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 252 p->host_rx_fifo_size = 440; 253 p->host_nperio_tx_fifo_size = 256; 254 p->host_perio_tx_fifo_size = 256; 255 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 256 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 257 p->lpm = false; 258 p->lpm_clock_gating = false; 259 p->besl = false; 260 p->hird_threshold_en = false; 261 } 262 263 const struct of_device_id dwc2_of_match_table[] = { 264 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 265 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 266 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 267 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 268 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 269 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 270 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 271 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 272 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 273 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 274 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 275 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 276 { .compatible = "snps,dwc2" }, 277 { .compatible = "samsung,s3c6400-hsotg", 278 .data = dwc2_set_s3c6400_params }, 279 { .compatible = "amlogic,meson8-usb", 280 .data = dwc2_set_amlogic_params }, 281 { .compatible = "amlogic,meson8b-usb", 282 .data = dwc2_set_amlogic_params }, 283 { .compatible = "amlogic,meson-gxbb-usb", 284 .data = dwc2_set_amlogic_params }, 285 { .compatible = "amlogic,meson-g12a-usb", 286 .data = dwc2_set_amlogic_g12a_params }, 287 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 288 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 289 { .compatible = "st,stm32f4x9-fsotg", 290 .data = dwc2_set_stm32f4x9_fsotg_params }, 291 { .compatible = "st,stm32f4x9-hsotg" }, 292 { .compatible = "st,stm32f7-hsotg", 293 .data = dwc2_set_stm32f7_hsotg_params }, 294 { .compatible = "st,stm32mp15-fsotg", 295 .data = dwc2_set_stm32mp15_fsotg_params }, 296 { .compatible = "st,stm32mp15-hsotg", 297 .data = dwc2_set_stm32mp15_hsotg_params }, 298 { .compatible = "intel,socfpga-agilex-hsotg", 299 .data = dwc2_set_socfpga_agilex_params }, 300 {}, 301 }; 302 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 303 304 const struct acpi_device_id dwc2_acpi_match[] = { 305 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 306 { }, 307 }; 308 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 309 310 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 311 { 312 switch (hsotg->hw_params.op_mode) { 313 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 314 hsotg->params.otg_caps.hnp_support = true; 315 hsotg->params.otg_caps.srp_support = true; 316 break; 317 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 318 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 319 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 320 hsotg->params.otg_caps.hnp_support = false; 321 hsotg->params.otg_caps.srp_support = true; 322 break; 323 default: 324 hsotg->params.otg_caps.hnp_support = false; 325 hsotg->params.otg_caps.srp_support = false; 326 break; 327 } 328 } 329 330 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 331 { 332 int val; 333 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 334 335 val = DWC2_PHY_TYPE_PARAM_FS; 336 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 337 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 338 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 339 val = DWC2_PHY_TYPE_PARAM_UTMI; 340 else 341 val = DWC2_PHY_TYPE_PARAM_ULPI; 342 } 343 344 if (dwc2_is_fs_iot(hsotg)) 345 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 346 347 hsotg->params.phy_type = val; 348 } 349 350 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 351 { 352 int val; 353 354 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 355 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 356 357 if (dwc2_is_fs_iot(hsotg)) 358 val = DWC2_SPEED_PARAM_FULL; 359 360 if (dwc2_is_hs_iot(hsotg)) 361 val = DWC2_SPEED_PARAM_HIGH; 362 363 hsotg->params.speed = val; 364 } 365 366 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 367 { 368 int val; 369 370 val = (hsotg->hw_params.utmi_phy_data_width == 371 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 372 373 if (hsotg->phy) { 374 /* 375 * If using the generic PHY framework, check if the PHY bus 376 * width is 8-bit and set the phyif appropriately. 377 */ 378 if (phy_get_bus_width(hsotg->phy) == 8) 379 val = 8; 380 } 381 382 hsotg->params.phy_utmi_width = val; 383 } 384 385 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 386 { 387 struct dwc2_core_params *p = &hsotg->params; 388 int depth_average; 389 int fifo_count; 390 int i; 391 392 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 393 394 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 395 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 396 for (i = 1; i <= fifo_count; i++) 397 p->g_tx_fifo_size[i] = depth_average; 398 } 399 400 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 401 { 402 int val; 403 404 if (hsotg->hw_params.hibernation) 405 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 406 else if (hsotg->hw_params.power_optimized) 407 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 408 else 409 val = DWC2_POWER_DOWN_PARAM_NONE; 410 411 hsotg->params.power_down = val; 412 } 413 414 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 415 { 416 struct dwc2_core_params *p = &hsotg->params; 417 418 p->lpm = hsotg->hw_params.lpm_mode; 419 if (p->lpm) { 420 p->lpm_clock_gating = true; 421 p->besl = true; 422 p->hird_threshold_en = true; 423 p->hird_threshold = 4; 424 } else { 425 p->lpm_clock_gating = false; 426 p->besl = false; 427 p->hird_threshold_en = false; 428 } 429 } 430 431 /** 432 * dwc2_set_default_params() - Set all core parameters to their 433 * auto-detected default values. 434 * 435 * @hsotg: Programming view of the DWC_otg controller 436 * 437 */ 438 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 439 { 440 struct dwc2_hw_params *hw = &hsotg->hw_params; 441 struct dwc2_core_params *p = &hsotg->params; 442 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 443 444 dwc2_set_param_otg_cap(hsotg); 445 dwc2_set_param_phy_type(hsotg); 446 dwc2_set_param_speed(hsotg); 447 dwc2_set_param_phy_utmi_width(hsotg); 448 dwc2_set_param_power_down(hsotg); 449 dwc2_set_param_lpm(hsotg); 450 p->phy_ulpi_ddr = false; 451 p->phy_ulpi_ext_vbus = false; 452 453 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 454 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 455 p->i2c_enable = hw->i2c_enable; 456 p->acg_enable = hw->acg_enable; 457 p->ulpi_fs_ls = false; 458 p->ts_dline = false; 459 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 460 p->uframe_sched = true; 461 p->external_id_pin_ctl = false; 462 p->ipg_isoc_en = false; 463 p->service_interval = false; 464 p->max_packet_count = hw->max_packet_count; 465 p->max_transfer_size = hw->max_transfer_size; 466 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 467 p->ref_clk_per = 33333; 468 p->sof_cnt_wkup_alert = 100; 469 470 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 471 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 472 p->host_dma = dma_capable; 473 p->dma_desc_enable = false; 474 p->dma_desc_fs_enable = false; 475 p->host_support_fs_ls_low_power = false; 476 p->host_ls_low_power_phy_clk = false; 477 p->host_channels = hw->host_channels; 478 p->host_rx_fifo_size = hw->rx_fifo_size; 479 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 480 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 481 } 482 483 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 484 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 485 p->g_dma = dma_capable; 486 p->g_dma_desc = hw->dma_desc_enable; 487 488 /* 489 * The values for g_rx_fifo_size (2048) and 490 * g_np_tx_fifo_size (1024) come from the legacy s3c 491 * gadget driver. These defaults have been hard-coded 492 * for some time so many platforms depend on these 493 * values. Leave them as defaults for now and only 494 * auto-detect if the hardware does not support the 495 * default. 496 */ 497 p->g_rx_fifo_size = 2048; 498 p->g_np_tx_fifo_size = 1024; 499 dwc2_set_param_tx_fifo_sizes(hsotg); 500 } 501 } 502 503 /** 504 * dwc2_get_device_properties() - Read in device properties. 505 * 506 * @hsotg: Programming view of the DWC_otg controller 507 * 508 * Read in the device properties and adjust core parameters if needed. 509 */ 510 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 511 { 512 struct dwc2_core_params *p = &hsotg->params; 513 int num; 514 515 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 516 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 517 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 518 &p->g_rx_fifo_size); 519 520 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 521 &p->g_np_tx_fifo_size); 522 523 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 524 if (num > 0) { 525 num = min(num, 15); 526 memset(p->g_tx_fifo_size, 0, 527 sizeof(p->g_tx_fifo_size)); 528 device_property_read_u32_array(hsotg->dev, 529 "g-tx-fifo-size", 530 &p->g_tx_fifo_size[1], 531 num); 532 } 533 534 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 535 } 536 537 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 538 p->oc_disable = true; 539 } 540 541 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 542 { 543 int valid = 1; 544 545 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 546 /* check HNP && SRP capable */ 547 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 548 valid = 0; 549 } else if (!hsotg->params.otg_caps.hnp_support) { 550 /* check SRP only capable */ 551 if (hsotg->params.otg_caps.srp_support) { 552 switch (hsotg->hw_params.op_mode) { 553 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 554 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 555 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 556 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 557 break; 558 default: 559 valid = 0; 560 break; 561 } 562 } 563 /* else: NO HNP && NO SRP capable: always valid */ 564 } else { 565 valid = 0; 566 } 567 568 if (!valid) 569 dwc2_set_param_otg_cap(hsotg); 570 } 571 572 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 573 { 574 int valid = 0; 575 u32 hs_phy_type; 576 u32 fs_phy_type; 577 578 hs_phy_type = hsotg->hw_params.hs_phy_type; 579 fs_phy_type = hsotg->hw_params.fs_phy_type; 580 581 switch (hsotg->params.phy_type) { 582 case DWC2_PHY_TYPE_PARAM_FS: 583 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 584 valid = 1; 585 break; 586 case DWC2_PHY_TYPE_PARAM_UTMI: 587 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 588 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 589 valid = 1; 590 break; 591 case DWC2_PHY_TYPE_PARAM_ULPI: 592 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 593 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 594 valid = 1; 595 break; 596 default: 597 break; 598 } 599 600 if (!valid) 601 dwc2_set_param_phy_type(hsotg); 602 } 603 604 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 605 { 606 int valid = 1; 607 int phy_type = hsotg->params.phy_type; 608 int speed = hsotg->params.speed; 609 610 switch (speed) { 611 case DWC2_SPEED_PARAM_HIGH: 612 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 613 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 614 valid = 0; 615 break; 616 case DWC2_SPEED_PARAM_FULL: 617 case DWC2_SPEED_PARAM_LOW: 618 break; 619 default: 620 valid = 0; 621 break; 622 } 623 624 if (!valid) 625 dwc2_set_param_speed(hsotg); 626 } 627 628 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 629 { 630 int valid = 0; 631 int param = hsotg->params.phy_utmi_width; 632 int width = hsotg->hw_params.utmi_phy_data_width; 633 634 switch (width) { 635 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 636 valid = (param == 8); 637 break; 638 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 639 valid = (param == 16); 640 break; 641 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 642 valid = (param == 8 || param == 16); 643 break; 644 } 645 646 if (!valid) 647 dwc2_set_param_phy_utmi_width(hsotg); 648 } 649 650 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 651 { 652 int param = hsotg->params.power_down; 653 654 switch (param) { 655 case DWC2_POWER_DOWN_PARAM_NONE: 656 break; 657 case DWC2_POWER_DOWN_PARAM_PARTIAL: 658 if (hsotg->hw_params.power_optimized) 659 break; 660 dev_dbg(hsotg->dev, 661 "Partial power down isn't supported by HW\n"); 662 param = DWC2_POWER_DOWN_PARAM_NONE; 663 break; 664 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 665 if (hsotg->hw_params.hibernation) 666 break; 667 dev_dbg(hsotg->dev, 668 "Hibernation isn't supported by HW\n"); 669 param = DWC2_POWER_DOWN_PARAM_NONE; 670 break; 671 default: 672 dev_err(hsotg->dev, 673 "%s: Invalid parameter power_down=%d\n", 674 __func__, param); 675 param = DWC2_POWER_DOWN_PARAM_NONE; 676 break; 677 } 678 679 hsotg->params.power_down = param; 680 } 681 682 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 683 { 684 int fifo_count; 685 int fifo; 686 int min; 687 u32 total = 0; 688 u32 dptxfszn; 689 690 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 691 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 692 693 for (fifo = 1; fifo <= fifo_count; fifo++) 694 total += hsotg->params.g_tx_fifo_size[fifo]; 695 696 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 697 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 698 __func__); 699 dwc2_set_param_tx_fifo_sizes(hsotg); 700 } 701 702 for (fifo = 1; fifo <= fifo_count; fifo++) { 703 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 704 705 if (hsotg->params.g_tx_fifo_size[fifo] < min || 706 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 707 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 708 __func__, fifo, 709 hsotg->params.g_tx_fifo_size[fifo]); 710 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 711 } 712 } 713 } 714 715 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 716 if ((int)(hsotg->params._param) < (_min) || \ 717 (hsotg->params._param) > (_max)) { \ 718 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 719 __func__, #_param, hsotg->params._param); \ 720 hsotg->params._param = (_def); \ 721 } \ 722 } while (0) 723 724 #define CHECK_BOOL(_param, _check) do { \ 725 if (hsotg->params._param && !(_check)) { \ 726 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 727 __func__, #_param, hsotg->params._param); \ 728 hsotg->params._param = false; \ 729 } \ 730 } while (0) 731 732 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 733 { 734 struct dwc2_hw_params *hw = &hsotg->hw_params; 735 struct dwc2_core_params *p = &hsotg->params; 736 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 737 738 dwc2_check_param_otg_cap(hsotg); 739 dwc2_check_param_phy_type(hsotg); 740 dwc2_check_param_speed(hsotg); 741 dwc2_check_param_phy_utmi_width(hsotg); 742 dwc2_check_param_power_down(hsotg); 743 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 744 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 745 CHECK_BOOL(i2c_enable, hw->i2c_enable); 746 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 747 CHECK_BOOL(acg_enable, hw->acg_enable); 748 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 749 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 750 CHECK_BOOL(lpm, hw->lpm_mode); 751 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 752 CHECK_BOOL(besl, hsotg->params.lpm); 753 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 754 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 755 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 756 CHECK_BOOL(service_interval, hw->service_interval_mode); 757 CHECK_RANGE(max_packet_count, 758 15, hw->max_packet_count, 759 hw->max_packet_count); 760 CHECK_RANGE(max_transfer_size, 761 2047, hw->max_transfer_size, 762 hw->max_transfer_size); 763 764 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 765 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 766 CHECK_BOOL(host_dma, dma_capable); 767 CHECK_BOOL(dma_desc_enable, p->host_dma); 768 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 769 CHECK_BOOL(host_ls_low_power_phy_clk, 770 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 771 CHECK_RANGE(host_channels, 772 1, hw->host_channels, 773 hw->host_channels); 774 CHECK_RANGE(host_rx_fifo_size, 775 16, hw->rx_fifo_size, 776 hw->rx_fifo_size); 777 CHECK_RANGE(host_nperio_tx_fifo_size, 778 16, hw->host_nperio_tx_fifo_size, 779 hw->host_nperio_tx_fifo_size); 780 CHECK_RANGE(host_perio_tx_fifo_size, 781 16, hw->host_perio_tx_fifo_size, 782 hw->host_perio_tx_fifo_size); 783 } 784 785 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 786 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 787 CHECK_BOOL(g_dma, dma_capable); 788 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 789 CHECK_RANGE(g_rx_fifo_size, 790 16, hw->rx_fifo_size, 791 hw->rx_fifo_size); 792 CHECK_RANGE(g_np_tx_fifo_size, 793 16, hw->dev_nperio_tx_fifo_size, 794 hw->dev_nperio_tx_fifo_size); 795 dwc2_check_param_tx_fifo_sizes(hsotg); 796 } 797 } 798 799 /* 800 * Gets host hardware parameters. Forces host mode if not currently in 801 * host mode. Should be called immediately after a core soft reset in 802 * order to get the reset values. 803 */ 804 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 805 { 806 struct dwc2_hw_params *hw = &hsotg->hw_params; 807 u32 gnptxfsiz; 808 u32 hptxfsiz; 809 810 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 811 return; 812 813 dwc2_force_mode(hsotg, true); 814 815 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 816 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 817 818 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 819 FIFOSIZE_DEPTH_SHIFT; 820 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 821 FIFOSIZE_DEPTH_SHIFT; 822 } 823 824 /* 825 * Gets device hardware parameters. Forces device mode if not 826 * currently in device mode. Should be called immediately after a core 827 * soft reset in order to get the reset values. 828 */ 829 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 830 { 831 struct dwc2_hw_params *hw = &hsotg->hw_params; 832 u32 gnptxfsiz; 833 int fifo, fifo_count; 834 835 if (hsotg->dr_mode == USB_DR_MODE_HOST) 836 return; 837 838 dwc2_force_mode(hsotg, false); 839 840 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 841 842 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 843 844 for (fifo = 1; fifo <= fifo_count; fifo++) { 845 hw->g_tx_fifo_size[fifo] = 846 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 847 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 848 } 849 850 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 851 FIFOSIZE_DEPTH_SHIFT; 852 } 853 854 /** 855 * dwc2_get_hwparams() - During device initialization, read various hardware 856 * configuration registers and interpret the contents. 857 * 858 * @hsotg: Programming view of the DWC_otg controller 859 * 860 */ 861 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 862 { 863 struct dwc2_hw_params *hw = &hsotg->hw_params; 864 unsigned int width; 865 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 866 u32 grxfsiz; 867 868 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 869 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 870 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 871 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 872 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 873 874 /* hwcfg1 */ 875 hw->dev_ep_dirs = hwcfg1; 876 877 /* hwcfg2 */ 878 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 879 GHWCFG2_OP_MODE_SHIFT; 880 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 881 GHWCFG2_ARCHITECTURE_SHIFT; 882 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 883 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 884 GHWCFG2_NUM_HOST_CHAN_SHIFT); 885 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 886 GHWCFG2_HS_PHY_TYPE_SHIFT; 887 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 888 GHWCFG2_FS_PHY_TYPE_SHIFT; 889 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 890 GHWCFG2_NUM_DEV_EP_SHIFT; 891 hw->nperio_tx_q_depth = 892 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 893 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 894 hw->host_perio_tx_q_depth = 895 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 896 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 897 hw->dev_token_q_depth = 898 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 899 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 900 901 /* hwcfg3 */ 902 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 903 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 904 hw->max_transfer_size = (1 << (width + 11)) - 1; 905 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 906 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 907 hw->max_packet_count = (1 << (width + 4)) - 1; 908 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 909 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 910 GHWCFG3_DFIFO_DEPTH_SHIFT; 911 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 912 913 /* hwcfg4 */ 914 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 915 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 916 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 917 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 918 GHWCFG4_NUM_IN_EPS_SHIFT; 919 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 920 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 921 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 922 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 923 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 924 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 925 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 926 hw->service_interval_mode = !!(hwcfg4 & 927 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 928 929 /* fifo sizes */ 930 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 931 GRXFSIZ_DEPTH_SHIFT; 932 /* 933 * Host specific hardware parameters. Reading these parameters 934 * requires the controller to be in host mode. The mode will 935 * be forced, if necessary, to read these values. 936 */ 937 dwc2_get_host_hwparams(hsotg); 938 dwc2_get_dev_hwparams(hsotg); 939 940 return 0; 941 } 942 943 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 944 945 int dwc2_init_params(struct dwc2_hsotg *hsotg) 946 { 947 const struct of_device_id *match; 948 set_params_cb set_params; 949 950 dwc2_set_default_params(hsotg); 951 dwc2_get_device_properties(hsotg); 952 953 match = of_match_device(dwc2_of_match_table, hsotg->dev); 954 if (match && match->data) { 955 set_params = match->data; 956 set_params(hsotg); 957 } else { 958 const struct acpi_device_id *amatch; 959 960 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 961 if (amatch && amatch->driver_data) { 962 set_params = (set_params_cb)amatch->driver_data; 963 set_params(hsotg); 964 } 965 } 966 967 dwc2_check_params(hsotg); 968 969 return 0; 970 } 971