1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 40 #include "core.h" 41 42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 43 { 44 struct dwc2_core_params *p = &hsotg->params; 45 46 p->host_rx_fifo_size = 774; 47 p->max_transfer_size = 65535; 48 p->max_packet_count = 511; 49 p->ahbcfg = 0x10; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->change_speed_quirk = true; 71 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 72 } 73 74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 79 p->phy_utmi_width = 8; 80 } 81 82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 83 { 84 struct dwc2_core_params *p = &hsotg->params; 85 86 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 87 p->host_rx_fifo_size = 525; 88 p->host_nperio_tx_fifo_size = 128; 89 p->host_perio_tx_fifo_size = 256; 90 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 91 GAHBCFG_HBSTLEN_SHIFT; 92 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 93 } 94 95 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 96 { 97 struct dwc2_core_params *p = &hsotg->params; 98 99 p->otg_cap = 2; 100 p->host_rx_fifo_size = 288; 101 p->host_nperio_tx_fifo_size = 128; 102 p->host_perio_tx_fifo_size = 96; 103 p->max_transfer_size = 65535; 104 p->max_packet_count = 511; 105 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 106 GAHBCFG_HBSTLEN_SHIFT; 107 } 108 109 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 110 { 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 114 p->speed = DWC2_SPEED_PARAM_HIGH; 115 p->host_rx_fifo_size = 512; 116 p->host_nperio_tx_fifo_size = 500; 117 p->host_perio_tx_fifo_size = 500; 118 p->host_channels = 16; 119 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 121 GAHBCFG_HBSTLEN_SHIFT; 122 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 123 } 124 125 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 126 { 127 struct dwc2_core_params *p = &hsotg->params; 128 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133 } 134 135 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 136 { 137 struct dwc2_core_params *p = &hsotg->params; 138 139 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 140 } 141 142 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 143 { 144 struct dwc2_core_params *p = &hsotg->params; 145 146 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 147 p->speed = DWC2_SPEED_PARAM_FULL; 148 p->host_rx_fifo_size = 128; 149 p->host_nperio_tx_fifo_size = 96; 150 p->host_perio_tx_fifo_size = 96; 151 p->max_packet_count = 256; 152 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 153 p->i2c_enable = false; 154 p->activate_stm_fs_transceiver = true; 155 } 156 157 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 158 { 159 struct dwc2_core_params *p = &hsotg->params; 160 161 p->host_rx_fifo_size = 622; 162 p->host_nperio_tx_fifo_size = 128; 163 p->host_perio_tx_fifo_size = 256; 164 } 165 166 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 167 { 168 struct dwc2_core_params *p = &hsotg->params; 169 170 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 171 p->speed = DWC2_SPEED_PARAM_FULL; 172 p->host_rx_fifo_size = 128; 173 p->host_nperio_tx_fifo_size = 96; 174 p->host_perio_tx_fifo_size = 96; 175 p->max_packet_count = 256; 176 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 177 p->i2c_enable = false; 178 p->activate_stm_fs_transceiver = true; 179 p->activate_stm_id_vb_detection = true; 180 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 181 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 182 p->host_support_fs_ls_low_power = true; 183 p->host_ls_low_power_phy_clk = true; 184 } 185 186 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 187 { 188 struct dwc2_core_params *p = &hsotg->params; 189 190 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 191 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 192 p->host_rx_fifo_size = 440; 193 p->host_nperio_tx_fifo_size = 256; 194 p->host_perio_tx_fifo_size = 256; 195 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 196 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 197 p->lpm = false; 198 p->lpm_clock_gating = false; 199 p->besl = false; 200 p->hird_threshold_en = false; 201 } 202 203 const struct of_device_id dwc2_of_match_table[] = { 204 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 205 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 206 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 207 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 208 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 209 { .compatible = "snps,dwc2" }, 210 { .compatible = "samsung,s3c6400-hsotg", 211 .data = dwc2_set_s3c6400_params }, 212 { .compatible = "amlogic,meson8-usb", 213 .data = dwc2_set_amlogic_params }, 214 { .compatible = "amlogic,meson8b-usb", 215 .data = dwc2_set_amlogic_params }, 216 { .compatible = "amlogic,meson-gxbb-usb", 217 .data = dwc2_set_amlogic_params }, 218 { .compatible = "amlogic,meson-g12a-usb", 219 .data = dwc2_set_amlogic_g12a_params }, 220 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 221 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 222 { .compatible = "st,stm32f4x9-fsotg", 223 .data = dwc2_set_stm32f4x9_fsotg_params }, 224 { .compatible = "st,stm32f4x9-hsotg" }, 225 { .compatible = "st,stm32f7-hsotg", 226 .data = dwc2_set_stm32f7_hsotg_params }, 227 { .compatible = "st,stm32mp15-fsotg", 228 .data = dwc2_set_stm32mp15_fsotg_params }, 229 { .compatible = "st,stm32mp15-hsotg", 230 .data = dwc2_set_stm32mp15_hsotg_params }, 231 {}, 232 }; 233 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 234 235 const struct acpi_device_id dwc2_acpi_match[] = { 236 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 237 { }, 238 }; 239 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 240 241 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 242 { 243 u8 val; 244 245 switch (hsotg->hw_params.op_mode) { 246 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 247 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 248 break; 249 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 250 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 251 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 252 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 253 break; 254 default: 255 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 256 break; 257 } 258 259 hsotg->params.otg_cap = val; 260 } 261 262 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 263 { 264 int val; 265 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 266 267 val = DWC2_PHY_TYPE_PARAM_FS; 268 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 269 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 270 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 271 val = DWC2_PHY_TYPE_PARAM_UTMI; 272 else 273 val = DWC2_PHY_TYPE_PARAM_ULPI; 274 } 275 276 if (dwc2_is_fs_iot(hsotg)) 277 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 278 279 hsotg->params.phy_type = val; 280 } 281 282 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 283 { 284 int val; 285 286 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 287 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 288 289 if (dwc2_is_fs_iot(hsotg)) 290 val = DWC2_SPEED_PARAM_FULL; 291 292 if (dwc2_is_hs_iot(hsotg)) 293 val = DWC2_SPEED_PARAM_HIGH; 294 295 hsotg->params.speed = val; 296 } 297 298 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 299 { 300 int val; 301 302 val = (hsotg->hw_params.utmi_phy_data_width == 303 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 304 305 if (hsotg->phy) { 306 /* 307 * If using the generic PHY framework, check if the PHY bus 308 * width is 8-bit and set the phyif appropriately. 309 */ 310 if (phy_get_bus_width(hsotg->phy) == 8) 311 val = 8; 312 } 313 314 hsotg->params.phy_utmi_width = val; 315 } 316 317 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 318 { 319 struct dwc2_core_params *p = &hsotg->params; 320 int depth_average; 321 int fifo_count; 322 int i; 323 324 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 325 326 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 327 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 328 for (i = 1; i <= fifo_count; i++) 329 p->g_tx_fifo_size[i] = depth_average; 330 } 331 332 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 333 { 334 int val; 335 336 if (hsotg->hw_params.hibernation) 337 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 338 else if (hsotg->hw_params.power_optimized) 339 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 340 else 341 val = DWC2_POWER_DOWN_PARAM_NONE; 342 343 hsotg->params.power_down = val; 344 } 345 346 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 347 { 348 struct dwc2_core_params *p = &hsotg->params; 349 350 p->lpm = hsotg->hw_params.lpm_mode; 351 if (p->lpm) { 352 p->lpm_clock_gating = true; 353 p->besl = true; 354 p->hird_threshold_en = true; 355 p->hird_threshold = 4; 356 } else { 357 p->lpm_clock_gating = false; 358 p->besl = false; 359 p->hird_threshold_en = false; 360 } 361 } 362 363 /** 364 * dwc2_set_default_params() - Set all core parameters to their 365 * auto-detected default values. 366 * 367 * @hsotg: Programming view of the DWC_otg controller 368 * 369 */ 370 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 371 { 372 struct dwc2_hw_params *hw = &hsotg->hw_params; 373 struct dwc2_core_params *p = &hsotg->params; 374 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 375 376 dwc2_set_param_otg_cap(hsotg); 377 dwc2_set_param_phy_type(hsotg); 378 dwc2_set_param_speed(hsotg); 379 dwc2_set_param_phy_utmi_width(hsotg); 380 dwc2_set_param_power_down(hsotg); 381 dwc2_set_param_lpm(hsotg); 382 p->phy_ulpi_ddr = false; 383 p->phy_ulpi_ext_vbus = false; 384 385 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 386 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 387 p->i2c_enable = hw->i2c_enable; 388 p->acg_enable = hw->acg_enable; 389 p->ulpi_fs_ls = false; 390 p->ts_dline = false; 391 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 392 p->uframe_sched = true; 393 p->external_id_pin_ctl = false; 394 p->ipg_isoc_en = false; 395 p->service_interval = false; 396 p->max_packet_count = hw->max_packet_count; 397 p->max_transfer_size = hw->max_transfer_size; 398 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 399 p->ref_clk_per = 33333; 400 p->sof_cnt_wkup_alert = 100; 401 402 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 403 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 404 p->host_dma = dma_capable; 405 p->dma_desc_enable = false; 406 p->dma_desc_fs_enable = false; 407 p->host_support_fs_ls_low_power = false; 408 p->host_ls_low_power_phy_clk = false; 409 p->host_channels = hw->host_channels; 410 p->host_rx_fifo_size = hw->rx_fifo_size; 411 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 412 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 413 } 414 415 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 416 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 417 p->g_dma = dma_capable; 418 p->g_dma_desc = hw->dma_desc_enable; 419 420 /* 421 * The values for g_rx_fifo_size (2048) and 422 * g_np_tx_fifo_size (1024) come from the legacy s3c 423 * gadget driver. These defaults have been hard-coded 424 * for some time so many platforms depend on these 425 * values. Leave them as defaults for now and only 426 * auto-detect if the hardware does not support the 427 * default. 428 */ 429 p->g_rx_fifo_size = 2048; 430 p->g_np_tx_fifo_size = 1024; 431 dwc2_set_param_tx_fifo_sizes(hsotg); 432 } 433 } 434 435 /** 436 * dwc2_get_device_properties() - Read in device properties. 437 * 438 * @hsotg: Programming view of the DWC_otg controller 439 * 440 * Read in the device properties and adjust core parameters if needed. 441 */ 442 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 443 { 444 struct dwc2_core_params *p = &hsotg->params; 445 int num; 446 447 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 448 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 449 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 450 &p->g_rx_fifo_size); 451 452 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 453 &p->g_np_tx_fifo_size); 454 455 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 456 if (num > 0) { 457 num = min(num, 15); 458 memset(p->g_tx_fifo_size, 0, 459 sizeof(p->g_tx_fifo_size)); 460 device_property_read_u32_array(hsotg->dev, 461 "g-tx-fifo-size", 462 &p->g_tx_fifo_size[1], 463 num); 464 } 465 } 466 467 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 468 p->oc_disable = true; 469 } 470 471 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 472 { 473 int valid = 1; 474 475 switch (hsotg->params.otg_cap) { 476 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 477 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 478 valid = 0; 479 break; 480 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 481 switch (hsotg->hw_params.op_mode) { 482 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 483 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 484 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 485 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 486 break; 487 default: 488 valid = 0; 489 break; 490 } 491 break; 492 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 493 /* always valid */ 494 break; 495 default: 496 valid = 0; 497 break; 498 } 499 500 if (!valid) 501 dwc2_set_param_otg_cap(hsotg); 502 } 503 504 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 505 { 506 int valid = 0; 507 u32 hs_phy_type; 508 u32 fs_phy_type; 509 510 hs_phy_type = hsotg->hw_params.hs_phy_type; 511 fs_phy_type = hsotg->hw_params.fs_phy_type; 512 513 switch (hsotg->params.phy_type) { 514 case DWC2_PHY_TYPE_PARAM_FS: 515 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 516 valid = 1; 517 break; 518 case DWC2_PHY_TYPE_PARAM_UTMI: 519 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 520 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 521 valid = 1; 522 break; 523 case DWC2_PHY_TYPE_PARAM_ULPI: 524 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 525 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 526 valid = 1; 527 break; 528 default: 529 break; 530 } 531 532 if (!valid) 533 dwc2_set_param_phy_type(hsotg); 534 } 535 536 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 537 { 538 int valid = 1; 539 int phy_type = hsotg->params.phy_type; 540 int speed = hsotg->params.speed; 541 542 switch (speed) { 543 case DWC2_SPEED_PARAM_HIGH: 544 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 545 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 546 valid = 0; 547 break; 548 case DWC2_SPEED_PARAM_FULL: 549 case DWC2_SPEED_PARAM_LOW: 550 break; 551 default: 552 valid = 0; 553 break; 554 } 555 556 if (!valid) 557 dwc2_set_param_speed(hsotg); 558 } 559 560 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 561 { 562 int valid = 0; 563 int param = hsotg->params.phy_utmi_width; 564 int width = hsotg->hw_params.utmi_phy_data_width; 565 566 switch (width) { 567 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 568 valid = (param == 8); 569 break; 570 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 571 valid = (param == 16); 572 break; 573 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 574 valid = (param == 8 || param == 16); 575 break; 576 } 577 578 if (!valid) 579 dwc2_set_param_phy_utmi_width(hsotg); 580 } 581 582 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 583 { 584 int param = hsotg->params.power_down; 585 586 switch (param) { 587 case DWC2_POWER_DOWN_PARAM_NONE: 588 break; 589 case DWC2_POWER_DOWN_PARAM_PARTIAL: 590 if (hsotg->hw_params.power_optimized) 591 break; 592 dev_dbg(hsotg->dev, 593 "Partial power down isn't supported by HW\n"); 594 param = DWC2_POWER_DOWN_PARAM_NONE; 595 break; 596 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 597 if (hsotg->hw_params.hibernation) 598 break; 599 dev_dbg(hsotg->dev, 600 "Hibernation isn't supported by HW\n"); 601 param = DWC2_POWER_DOWN_PARAM_NONE; 602 break; 603 default: 604 dev_err(hsotg->dev, 605 "%s: Invalid parameter power_down=%d\n", 606 __func__, param); 607 param = DWC2_POWER_DOWN_PARAM_NONE; 608 break; 609 } 610 611 hsotg->params.power_down = param; 612 } 613 614 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 615 { 616 int fifo_count; 617 int fifo; 618 int min; 619 u32 total = 0; 620 u32 dptxfszn; 621 622 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 623 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 624 625 for (fifo = 1; fifo <= fifo_count; fifo++) 626 total += hsotg->params.g_tx_fifo_size[fifo]; 627 628 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 629 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 630 __func__); 631 dwc2_set_param_tx_fifo_sizes(hsotg); 632 } 633 634 for (fifo = 1; fifo <= fifo_count; fifo++) { 635 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 636 637 if (hsotg->params.g_tx_fifo_size[fifo] < min || 638 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 639 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 640 __func__, fifo, 641 hsotg->params.g_tx_fifo_size[fifo]); 642 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 643 } 644 } 645 } 646 647 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 648 if ((int)(hsotg->params._param) < (_min) || \ 649 (hsotg->params._param) > (_max)) { \ 650 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 651 __func__, #_param, hsotg->params._param); \ 652 hsotg->params._param = (_def); \ 653 } \ 654 } while (0) 655 656 #define CHECK_BOOL(_param, _check) do { \ 657 if (hsotg->params._param && !(_check)) { \ 658 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 659 __func__, #_param, hsotg->params._param); \ 660 hsotg->params._param = false; \ 661 } \ 662 } while (0) 663 664 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 665 { 666 struct dwc2_hw_params *hw = &hsotg->hw_params; 667 struct dwc2_core_params *p = &hsotg->params; 668 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 669 670 dwc2_check_param_otg_cap(hsotg); 671 dwc2_check_param_phy_type(hsotg); 672 dwc2_check_param_speed(hsotg); 673 dwc2_check_param_phy_utmi_width(hsotg); 674 dwc2_check_param_power_down(hsotg); 675 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 676 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 677 CHECK_BOOL(i2c_enable, hw->i2c_enable); 678 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 679 CHECK_BOOL(acg_enable, hw->acg_enable); 680 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 681 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 682 CHECK_BOOL(lpm, hw->lpm_mode); 683 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 684 CHECK_BOOL(besl, hsotg->params.lpm); 685 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 686 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 687 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 688 CHECK_BOOL(service_interval, hw->service_interval_mode); 689 CHECK_RANGE(max_packet_count, 690 15, hw->max_packet_count, 691 hw->max_packet_count); 692 CHECK_RANGE(max_transfer_size, 693 2047, hw->max_transfer_size, 694 hw->max_transfer_size); 695 696 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 697 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 698 CHECK_BOOL(host_dma, dma_capable); 699 CHECK_BOOL(dma_desc_enable, p->host_dma); 700 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 701 CHECK_BOOL(host_ls_low_power_phy_clk, 702 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 703 CHECK_RANGE(host_channels, 704 1, hw->host_channels, 705 hw->host_channels); 706 CHECK_RANGE(host_rx_fifo_size, 707 16, hw->rx_fifo_size, 708 hw->rx_fifo_size); 709 CHECK_RANGE(host_nperio_tx_fifo_size, 710 16, hw->host_nperio_tx_fifo_size, 711 hw->host_nperio_tx_fifo_size); 712 CHECK_RANGE(host_perio_tx_fifo_size, 713 16, hw->host_perio_tx_fifo_size, 714 hw->host_perio_tx_fifo_size); 715 } 716 717 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 718 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 719 CHECK_BOOL(g_dma, dma_capable); 720 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 721 CHECK_RANGE(g_rx_fifo_size, 722 16, hw->rx_fifo_size, 723 hw->rx_fifo_size); 724 CHECK_RANGE(g_np_tx_fifo_size, 725 16, hw->dev_nperio_tx_fifo_size, 726 hw->dev_nperio_tx_fifo_size); 727 dwc2_check_param_tx_fifo_sizes(hsotg); 728 } 729 } 730 731 /* 732 * Gets host hardware parameters. Forces host mode if not currently in 733 * host mode. Should be called immediately after a core soft reset in 734 * order to get the reset values. 735 */ 736 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 737 { 738 struct dwc2_hw_params *hw = &hsotg->hw_params; 739 u32 gnptxfsiz; 740 u32 hptxfsiz; 741 742 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 743 return; 744 745 dwc2_force_mode(hsotg, true); 746 747 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 748 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 749 750 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 751 FIFOSIZE_DEPTH_SHIFT; 752 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 753 FIFOSIZE_DEPTH_SHIFT; 754 } 755 756 /* 757 * Gets device hardware parameters. Forces device mode if not 758 * currently in device mode. Should be called immediately after a core 759 * soft reset in order to get the reset values. 760 */ 761 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 762 { 763 struct dwc2_hw_params *hw = &hsotg->hw_params; 764 u32 gnptxfsiz; 765 int fifo, fifo_count; 766 767 if (hsotg->dr_mode == USB_DR_MODE_HOST) 768 return; 769 770 dwc2_force_mode(hsotg, false); 771 772 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 773 774 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 775 776 for (fifo = 1; fifo <= fifo_count; fifo++) { 777 hw->g_tx_fifo_size[fifo] = 778 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 779 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 780 } 781 782 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 783 FIFOSIZE_DEPTH_SHIFT; 784 } 785 786 /** 787 * dwc2_get_hwparams() - During device initialization, read various hardware 788 * configuration registers and interpret the contents. 789 * 790 * @hsotg: Programming view of the DWC_otg controller 791 * 792 */ 793 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 794 { 795 struct dwc2_hw_params *hw = &hsotg->hw_params; 796 unsigned int width; 797 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 798 u32 grxfsiz; 799 800 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 801 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 802 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 803 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 804 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 805 806 /* hwcfg1 */ 807 hw->dev_ep_dirs = hwcfg1; 808 809 /* hwcfg2 */ 810 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 811 GHWCFG2_OP_MODE_SHIFT; 812 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 813 GHWCFG2_ARCHITECTURE_SHIFT; 814 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 815 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 816 GHWCFG2_NUM_HOST_CHAN_SHIFT); 817 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 818 GHWCFG2_HS_PHY_TYPE_SHIFT; 819 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 820 GHWCFG2_FS_PHY_TYPE_SHIFT; 821 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 822 GHWCFG2_NUM_DEV_EP_SHIFT; 823 hw->nperio_tx_q_depth = 824 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 825 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 826 hw->host_perio_tx_q_depth = 827 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 828 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 829 hw->dev_token_q_depth = 830 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 831 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 832 833 /* hwcfg3 */ 834 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 835 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 836 hw->max_transfer_size = (1 << (width + 11)) - 1; 837 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 838 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 839 hw->max_packet_count = (1 << (width + 4)) - 1; 840 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 841 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 842 GHWCFG3_DFIFO_DEPTH_SHIFT; 843 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 844 845 /* hwcfg4 */ 846 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 847 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 848 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 849 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 850 GHWCFG4_NUM_IN_EPS_SHIFT; 851 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 852 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 853 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 854 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 855 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 856 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 857 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 858 hw->service_interval_mode = !!(hwcfg4 & 859 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 860 861 /* fifo sizes */ 862 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 863 GRXFSIZ_DEPTH_SHIFT; 864 /* 865 * Host specific hardware parameters. Reading these parameters 866 * requires the controller to be in host mode. The mode will 867 * be forced, if necessary, to read these values. 868 */ 869 dwc2_get_host_hwparams(hsotg); 870 dwc2_get_dev_hwparams(hsotg); 871 872 return 0; 873 } 874 875 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 876 877 int dwc2_init_params(struct dwc2_hsotg *hsotg) 878 { 879 const struct of_device_id *match; 880 set_params_cb set_params; 881 882 dwc2_set_default_params(hsotg); 883 dwc2_get_device_properties(hsotg); 884 885 match = of_match_device(dwc2_of_match_table, hsotg->dev); 886 if (match && match->data) { 887 set_params = match->data; 888 set_params(hsotg); 889 } else { 890 const struct acpi_device_id *amatch; 891 892 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 893 if (amatch && amatch->driver_data) { 894 set_params = (set_params_cb)amatch->driver_data; 895 set_params(hsotg); 896 } 897 } 898 899 dwc2_check_params(hsotg); 900 901 return 0; 902 } 903