1 /* 2 * Copyright (C) 2004-2016 Synopsys, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions, and the following disclaimer, 9 * without modification. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The names of the above-listed copyright holders may not be used 14 * to endorse or promote products derived from this software without 15 * specific prior written permission. 16 * 17 * ALTERNATIVELY, this software may be distributed under the terms of the 18 * GNU General Public License ("GPL") as published by the Free Software 19 * Foundation; either version 2 of the License, or (at your option) any 20 * later version. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_device.h> 38 39 #include "core.h" 40 41 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 42 { 43 struct dwc2_core_params *p = &hsotg->params; 44 45 p->host_rx_fifo_size = 774; 46 p->max_transfer_size = 65535; 47 p->max_packet_count = 511; 48 p->ahbcfg = 0x10; 49 p->uframe_sched = false; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->uframe_sched = false; 71 p->change_speed_quirk = true; 72 } 73 74 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 79 p->host_rx_fifo_size = 525; 80 p->host_nperio_tx_fifo_size = 128; 81 p->host_perio_tx_fifo_size = 256; 82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 83 GAHBCFG_HBSTLEN_SHIFT; 84 } 85 86 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 87 { 88 struct dwc2_core_params *p = &hsotg->params; 89 90 p->otg_cap = 2; 91 p->host_rx_fifo_size = 288; 92 p->host_nperio_tx_fifo_size = 128; 93 p->host_perio_tx_fifo_size = 96; 94 p->max_transfer_size = 65535; 95 p->max_packet_count = 511; 96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 97 GAHBCFG_HBSTLEN_SHIFT; 98 } 99 100 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 105 p->speed = DWC2_SPEED_PARAM_HIGH; 106 p->host_rx_fifo_size = 512; 107 p->host_nperio_tx_fifo_size = 500; 108 p->host_perio_tx_fifo_size = 500; 109 p->host_channels = 16; 110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 112 GAHBCFG_HBSTLEN_SHIFT; 113 p->uframe_sched = false; 114 } 115 116 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 117 { 118 struct dwc2_core_params *p = &hsotg->params; 119 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 121 } 122 123 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 124 { 125 struct dwc2_core_params *p = &hsotg->params; 126 127 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 128 p->speed = DWC2_SPEED_PARAM_FULL; 129 p->host_rx_fifo_size = 128; 130 p->host_nperio_tx_fifo_size = 96; 131 p->host_perio_tx_fifo_size = 96; 132 p->max_packet_count = 256; 133 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 134 p->i2c_enable = false; 135 p->uframe_sched = false; 136 p->activate_stm_fs_transceiver = true; 137 } 138 139 const struct of_device_id dwc2_of_match_table[] = { 140 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 141 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 142 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 143 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 144 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 145 { .compatible = "snps,dwc2" }, 146 { .compatible = "samsung,s3c6400-hsotg" }, 147 { .compatible = "amlogic,meson8b-usb", 148 .data = dwc2_set_amlogic_params }, 149 { .compatible = "amlogic,meson-gxbb-usb", 150 .data = dwc2_set_amlogic_params }, 151 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 152 { .compatible = "st,stm32f4x9-fsotg", 153 .data = dwc2_set_stm32f4x9_fsotg_params }, 154 { .compatible = "st,stm32f4x9-hsotg" }, 155 {}, 156 }; 157 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 158 159 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 160 { 161 u8 val; 162 163 switch (hsotg->hw_params.op_mode) { 164 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 165 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 166 break; 167 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 168 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 169 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 170 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 171 break; 172 default: 173 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 174 break; 175 } 176 177 hsotg->params.otg_cap = val; 178 } 179 180 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 181 { 182 int val; 183 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 184 185 val = DWC2_PHY_TYPE_PARAM_FS; 186 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 187 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 188 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 189 val = DWC2_PHY_TYPE_PARAM_UTMI; 190 else 191 val = DWC2_PHY_TYPE_PARAM_ULPI; 192 } 193 194 if (dwc2_is_fs_iot(hsotg)) 195 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 196 197 hsotg->params.phy_type = val; 198 } 199 200 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 201 { 202 int val; 203 204 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 205 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 206 207 if (dwc2_is_fs_iot(hsotg)) 208 val = DWC2_SPEED_PARAM_FULL; 209 210 if (dwc2_is_hs_iot(hsotg)) 211 val = DWC2_SPEED_PARAM_HIGH; 212 213 hsotg->params.speed = val; 214 } 215 216 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 217 { 218 int val; 219 220 val = (hsotg->hw_params.utmi_phy_data_width == 221 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 222 223 hsotg->params.phy_utmi_width = val; 224 } 225 226 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 227 { 228 struct dwc2_core_params *p = &hsotg->params; 229 int depth_average; 230 int fifo_count; 231 int i; 232 233 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 234 235 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 236 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 237 for (i = 1; i <= fifo_count; i++) 238 p->g_tx_fifo_size[i] = depth_average; 239 } 240 241 /** 242 * dwc2_set_default_params() - Set all core parameters to their 243 * auto-detected default values. 244 */ 245 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 246 { 247 struct dwc2_hw_params *hw = &hsotg->hw_params; 248 struct dwc2_core_params *p = &hsotg->params; 249 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 250 251 dwc2_set_param_otg_cap(hsotg); 252 dwc2_set_param_phy_type(hsotg); 253 dwc2_set_param_speed(hsotg); 254 dwc2_set_param_phy_utmi_width(hsotg); 255 p->phy_ulpi_ddr = false; 256 p->phy_ulpi_ext_vbus = false; 257 258 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 259 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 260 p->i2c_enable = hw->i2c_enable; 261 p->ulpi_fs_ls = false; 262 p->ts_dline = false; 263 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 264 p->uframe_sched = true; 265 p->external_id_pin_ctl = false; 266 p->hibernation = false; 267 p->max_packet_count = hw->max_packet_count; 268 p->max_transfer_size = hw->max_transfer_size; 269 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; 270 271 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 272 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 273 p->host_dma = dma_capable; 274 p->dma_desc_enable = false; 275 p->dma_desc_fs_enable = false; 276 p->host_support_fs_ls_low_power = false; 277 p->host_ls_low_power_phy_clk = false; 278 p->host_channels = hw->host_channels; 279 p->host_rx_fifo_size = hw->rx_fifo_size; 280 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 281 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 282 } 283 284 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 285 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 286 p->g_dma = dma_capable; 287 p->g_dma_desc = hw->dma_desc_enable; 288 289 /* 290 * The values for g_rx_fifo_size (2048) and 291 * g_np_tx_fifo_size (1024) come from the legacy s3c 292 * gadget driver. These defaults have been hard-coded 293 * for some time so many platforms depend on these 294 * values. Leave them as defaults for now and only 295 * auto-detect if the hardware does not support the 296 * default. 297 */ 298 p->g_rx_fifo_size = 2048; 299 p->g_np_tx_fifo_size = 1024; 300 dwc2_set_param_tx_fifo_sizes(hsotg); 301 } 302 } 303 304 /** 305 * dwc2_get_device_properties() - Read in device properties. 306 * 307 * Read in the device properties and adjust core parameters if needed. 308 */ 309 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 310 { 311 struct dwc2_core_params *p = &hsotg->params; 312 int num; 313 314 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 315 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 316 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 317 &p->g_rx_fifo_size); 318 319 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 320 &p->g_np_tx_fifo_size); 321 322 num = device_property_read_u32_array(hsotg->dev, 323 "g-tx-fifo-size", 324 NULL, 0); 325 326 if (num > 0) { 327 num = min(num, 15); 328 memset(p->g_tx_fifo_size, 0, 329 sizeof(p->g_tx_fifo_size)); 330 device_property_read_u32_array(hsotg->dev, 331 "g-tx-fifo-size", 332 &p->g_tx_fifo_size[1], 333 num); 334 } 335 } 336 } 337 338 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 339 { 340 int valid = 1; 341 342 switch (hsotg->params.otg_cap) { 343 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 344 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 345 valid = 0; 346 break; 347 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 348 switch (hsotg->hw_params.op_mode) { 349 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 350 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 351 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 352 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 353 break; 354 default: 355 valid = 0; 356 break; 357 } 358 break; 359 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 360 /* always valid */ 361 break; 362 default: 363 valid = 0; 364 break; 365 } 366 367 if (!valid) 368 dwc2_set_param_otg_cap(hsotg); 369 } 370 371 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 372 { 373 int valid = 0; 374 u32 hs_phy_type; 375 u32 fs_phy_type; 376 377 hs_phy_type = hsotg->hw_params.hs_phy_type; 378 fs_phy_type = hsotg->hw_params.fs_phy_type; 379 380 switch (hsotg->params.phy_type) { 381 case DWC2_PHY_TYPE_PARAM_FS: 382 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 383 valid = 1; 384 break; 385 case DWC2_PHY_TYPE_PARAM_UTMI: 386 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 387 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 388 valid = 1; 389 break; 390 case DWC2_PHY_TYPE_PARAM_ULPI: 391 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 392 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 393 valid = 1; 394 break; 395 default: 396 break; 397 } 398 399 if (!valid) 400 dwc2_set_param_phy_type(hsotg); 401 } 402 403 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 404 { 405 int valid = 1; 406 int phy_type = hsotg->params.phy_type; 407 int speed = hsotg->params.speed; 408 409 switch (speed) { 410 case DWC2_SPEED_PARAM_HIGH: 411 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 412 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 413 valid = 0; 414 break; 415 case DWC2_SPEED_PARAM_FULL: 416 case DWC2_SPEED_PARAM_LOW: 417 break; 418 default: 419 valid = 0; 420 break; 421 } 422 423 if (!valid) 424 dwc2_set_param_speed(hsotg); 425 } 426 427 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 428 { 429 int valid = 0; 430 int param = hsotg->params.phy_utmi_width; 431 int width = hsotg->hw_params.utmi_phy_data_width; 432 433 switch (width) { 434 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 435 valid = (param == 8); 436 break; 437 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 438 valid = (param == 16); 439 break; 440 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 441 valid = (param == 8 || param == 16); 442 break; 443 } 444 445 if (!valid) 446 dwc2_set_param_phy_utmi_width(hsotg); 447 } 448 449 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 450 { 451 int fifo_count; 452 int fifo; 453 int min; 454 u32 total = 0; 455 u32 dptxfszn; 456 457 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 458 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 459 460 for (fifo = 1; fifo <= fifo_count; fifo++) 461 total += hsotg->params.g_tx_fifo_size[fifo]; 462 463 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 464 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 465 __func__); 466 dwc2_set_param_tx_fifo_sizes(hsotg); 467 } 468 469 for (fifo = 1; fifo <= fifo_count; fifo++) { 470 dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & 471 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 472 473 if (hsotg->params.g_tx_fifo_size[fifo] < min || 474 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 475 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 476 __func__, fifo, 477 hsotg->params.g_tx_fifo_size[fifo]); 478 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 479 } 480 } 481 } 482 483 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 484 if ((hsotg->params._param) < (_min) || \ 485 (hsotg->params._param) > (_max)) { \ 486 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 487 __func__, #_param, hsotg->params._param); \ 488 hsotg->params._param = (_def); \ 489 } \ 490 } while (0) 491 492 #define CHECK_BOOL(_param, _check) do { \ 493 if (hsotg->params._param && !(_check)) { \ 494 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 495 __func__, #_param, hsotg->params._param); \ 496 hsotg->params._param = false; \ 497 } \ 498 } while (0) 499 500 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 501 { 502 struct dwc2_hw_params *hw = &hsotg->hw_params; 503 struct dwc2_core_params *p = &hsotg->params; 504 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 505 506 dwc2_check_param_otg_cap(hsotg); 507 dwc2_check_param_phy_type(hsotg); 508 dwc2_check_param_speed(hsotg); 509 dwc2_check_param_phy_utmi_width(hsotg); 510 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 511 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 512 CHECK_BOOL(i2c_enable, hw->i2c_enable); 513 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 514 CHECK_RANGE(max_packet_count, 515 15, hw->max_packet_count, 516 hw->max_packet_count); 517 CHECK_RANGE(max_transfer_size, 518 2047, hw->max_transfer_size, 519 hw->max_transfer_size); 520 521 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 522 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 523 CHECK_BOOL(host_dma, dma_capable); 524 CHECK_BOOL(dma_desc_enable, p->host_dma); 525 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 526 CHECK_BOOL(host_ls_low_power_phy_clk, 527 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 528 CHECK_RANGE(host_channels, 529 1, hw->host_channels, 530 hw->host_channels); 531 CHECK_RANGE(host_rx_fifo_size, 532 16, hw->rx_fifo_size, 533 hw->rx_fifo_size); 534 CHECK_RANGE(host_nperio_tx_fifo_size, 535 16, hw->host_nperio_tx_fifo_size, 536 hw->host_nperio_tx_fifo_size); 537 CHECK_RANGE(host_perio_tx_fifo_size, 538 16, hw->host_perio_tx_fifo_size, 539 hw->host_perio_tx_fifo_size); 540 } 541 542 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 543 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 544 CHECK_BOOL(g_dma, dma_capable); 545 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 546 CHECK_RANGE(g_rx_fifo_size, 547 16, hw->rx_fifo_size, 548 hw->rx_fifo_size); 549 CHECK_RANGE(g_np_tx_fifo_size, 550 16, hw->dev_nperio_tx_fifo_size, 551 hw->dev_nperio_tx_fifo_size); 552 dwc2_check_param_tx_fifo_sizes(hsotg); 553 } 554 } 555 556 /* 557 * Gets host hardware parameters. Forces host mode if not currently in 558 * host mode. Should be called immediately after a core soft reset in 559 * order to get the reset values. 560 */ 561 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 562 { 563 struct dwc2_hw_params *hw = &hsotg->hw_params; 564 u32 gnptxfsiz; 565 u32 hptxfsiz; 566 bool forced; 567 568 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 569 return; 570 571 forced = dwc2_force_mode_if_needed(hsotg, true); 572 573 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 574 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 575 576 if (forced) 577 dwc2_clear_force_mode(hsotg); 578 579 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 580 FIFOSIZE_DEPTH_SHIFT; 581 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 582 FIFOSIZE_DEPTH_SHIFT; 583 } 584 585 /* 586 * Gets device hardware parameters. Forces device mode if not 587 * currently in device mode. Should be called immediately after a core 588 * soft reset in order to get the reset values. 589 */ 590 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 591 { 592 struct dwc2_hw_params *hw = &hsotg->hw_params; 593 bool forced; 594 u32 gnptxfsiz; 595 596 if (hsotg->dr_mode == USB_DR_MODE_HOST) 597 return; 598 599 forced = dwc2_force_mode_if_needed(hsotg, false); 600 601 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 602 603 if (forced) 604 dwc2_clear_force_mode(hsotg); 605 606 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 607 FIFOSIZE_DEPTH_SHIFT; 608 } 609 610 /** 611 * During device initialization, read various hardware configuration 612 * registers and interpret the contents. 613 */ 614 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 615 { 616 struct dwc2_hw_params *hw = &hsotg->hw_params; 617 unsigned int width; 618 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 619 u32 grxfsiz; 620 621 /* 622 * Attempt to ensure this device is really a DWC_otg Controller. 623 * Read and verify the GSNPSID register contents. The value should be 624 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 625 * as in "OTG version 2.xx" or "OTG version 3.xx". 626 */ 627 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 628 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 629 (hw->snpsid & 0xfffff000) != 0x4f543000 && 630 (hw->snpsid & 0xffff0000) != 0x55310000 && 631 (hw->snpsid & 0xffff0000) != 0x55320000) { 632 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 633 hw->snpsid); 634 return -ENODEV; 635 } 636 637 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 638 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 639 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 640 641 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 642 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 643 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 644 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 645 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 646 647 /* 648 * Host specific hardware parameters. Reading these parameters 649 * requires the controller to be in host mode. The mode will 650 * be forced, if necessary, to read these values. 651 */ 652 dwc2_get_host_hwparams(hsotg); 653 dwc2_get_dev_hwparams(hsotg); 654 655 /* hwcfg1 */ 656 hw->dev_ep_dirs = hwcfg1; 657 658 /* hwcfg2 */ 659 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 660 GHWCFG2_OP_MODE_SHIFT; 661 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 662 GHWCFG2_ARCHITECTURE_SHIFT; 663 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 664 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 665 GHWCFG2_NUM_HOST_CHAN_SHIFT); 666 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 667 GHWCFG2_HS_PHY_TYPE_SHIFT; 668 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 669 GHWCFG2_FS_PHY_TYPE_SHIFT; 670 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 671 GHWCFG2_NUM_DEV_EP_SHIFT; 672 hw->nperio_tx_q_depth = 673 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 674 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 675 hw->host_perio_tx_q_depth = 676 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 677 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 678 hw->dev_token_q_depth = 679 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 680 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 681 682 /* hwcfg3 */ 683 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 684 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 685 hw->max_transfer_size = (1 << (width + 11)) - 1; 686 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 687 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 688 hw->max_packet_count = (1 << (width + 4)) - 1; 689 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 690 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 691 GHWCFG3_DFIFO_DEPTH_SHIFT; 692 693 /* hwcfg4 */ 694 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 695 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 696 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 697 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 698 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 699 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 700 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 701 702 /* fifo sizes */ 703 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 704 GRXFSIZ_DEPTH_SHIFT; 705 706 return 0; 707 } 708 709 int dwc2_init_params(struct dwc2_hsotg *hsotg) 710 { 711 const struct of_device_id *match; 712 void (*set_params)(void *data); 713 714 dwc2_set_default_params(hsotg); 715 dwc2_get_device_properties(hsotg); 716 717 match = of_match_device(dwc2_of_match_table, hsotg->dev); 718 if (match && match->data) { 719 set_params = match->data; 720 set_params(hsotg); 721 } 722 723 dwc2_check_params(hsotg); 724 725 return 0; 726 } 727