1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/usb/of.h> 10 11 #include "core.h" 12 13 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 14 { 15 struct dwc2_core_params *p = &hsotg->params; 16 17 p->host_rx_fifo_size = 774; 18 p->max_transfer_size = 65535; 19 p->max_packet_count = 511; 20 p->ahbcfg = 0x10; 21 } 22 23 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 24 { 25 struct dwc2_core_params *p = &hsotg->params; 26 27 p->otg_caps.hnp_support = false; 28 p->otg_caps.srp_support = false; 29 p->speed = DWC2_SPEED_PARAM_HIGH; 30 p->host_rx_fifo_size = 512; 31 p->host_nperio_tx_fifo_size = 512; 32 p->host_perio_tx_fifo_size = 512; 33 p->max_transfer_size = 65535; 34 p->max_packet_count = 511; 35 p->host_channels = 16; 36 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 37 p->phy_utmi_width = 8; 38 p->i2c_enable = false; 39 p->reload_ctl = false; 40 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 41 GAHBCFG_HBSTLEN_SHIFT; 42 p->change_speed_quirk = true; 43 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 44 } 45 46 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 47 { 48 struct dwc2_core_params *p = &hsotg->params; 49 50 p->otg_caps.hnp_support = false; 51 p->speed = DWC2_SPEED_PARAM_HIGH; 52 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 53 p->phy_utmi_width = 16; 54 p->activate_ingenic_overcurrent_detection = 55 !device_property_read_bool(hsotg->dev, "disable-over-current"); 56 } 57 58 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 59 { 60 struct dwc2_core_params *p = &hsotg->params; 61 62 p->otg_caps.hnp_support = false; 63 p->speed = DWC2_SPEED_PARAM_HIGH; 64 p->host_channels = 16; 65 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 66 p->phy_utmi_width = 16; 67 p->activate_ingenic_overcurrent_detection = 68 !device_property_read_bool(hsotg->dev, "disable-over-current"); 69 } 70 71 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 72 { 73 struct dwc2_core_params *p = &hsotg->params; 74 75 p->otg_caps.hnp_support = false; 76 p->speed = DWC2_SPEED_PARAM_HIGH; 77 p->host_rx_fifo_size = 1024; 78 p->host_nperio_tx_fifo_size = 1024; 79 p->host_perio_tx_fifo_size = 1024; 80 p->host_channels = 16; 81 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 82 p->phy_utmi_width = 16; 83 p->activate_ingenic_overcurrent_detection = 84 !device_property_read_bool(hsotg->dev, "disable-over-current"); 85 } 86 87 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 88 { 89 struct dwc2_core_params *p = &hsotg->params; 90 91 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 92 p->no_clock_gating = true; 93 p->phy_utmi_width = 8; 94 } 95 96 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 97 { 98 struct dwc2_core_params *p = &hsotg->params; 99 100 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 101 p->no_clock_gating = true; 102 } 103 104 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 105 { 106 struct dwc2_core_params *p = &hsotg->params; 107 108 p->otg_caps.hnp_support = false; 109 p->otg_caps.srp_support = false; 110 p->host_rx_fifo_size = 525; 111 p->host_nperio_tx_fifo_size = 128; 112 p->host_perio_tx_fifo_size = 256; 113 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 114 GAHBCFG_HBSTLEN_SHIFT; 115 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 116 p->lpm = false; 117 p->lpm_clock_gating = false; 118 p->besl = false; 119 p->hird_threshold_en = false; 120 } 121 122 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 123 { 124 struct dwc2_core_params *p = &hsotg->params; 125 126 p->otg_caps.hnp_support = false; 127 p->otg_caps.srp_support = false; 128 p->host_rx_fifo_size = 288; 129 p->host_nperio_tx_fifo_size = 128; 130 p->host_perio_tx_fifo_size = 96; 131 p->max_transfer_size = 65535; 132 p->max_packet_count = 511; 133 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 134 GAHBCFG_HBSTLEN_SHIFT; 135 } 136 137 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 138 { 139 struct dwc2_core_params *p = &hsotg->params; 140 141 p->otg_caps.hnp_support = false; 142 p->otg_caps.srp_support = false; 143 p->speed = DWC2_SPEED_PARAM_HIGH; 144 p->host_rx_fifo_size = 512; 145 p->host_nperio_tx_fifo_size = 500; 146 p->host_perio_tx_fifo_size = 500; 147 p->host_channels = 16; 148 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 149 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 150 GAHBCFG_HBSTLEN_SHIFT; 151 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 152 } 153 154 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 155 { 156 struct dwc2_core_params *p = &hsotg->params; 157 158 p->lpm = false; 159 p->lpm_clock_gating = false; 160 p->besl = false; 161 p->hird_threshold_en = false; 162 } 163 164 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg) 165 { 166 struct dwc2_core_params *p = &hsotg->params; 167 168 p->otg_caps.hnp_support = false; 169 p->otg_caps.srp_support = false; 170 p->speed = DWC2_SPEED_PARAM_HIGH; 171 p->host_rx_fifo_size = 192; 172 p->host_nperio_tx_fifo_size = 128; 173 p->host_perio_tx_fifo_size = 128; 174 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 175 p->phy_utmi_width = 8; 176 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; 177 p->lpm = false; 178 p->lpm_clock_gating = false; 179 p->besl = false; 180 p->hird_threshold_en = false; 181 } 182 183 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 184 { 185 struct dwc2_core_params *p = &hsotg->params; 186 187 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 188 } 189 190 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 191 { 192 struct dwc2_core_params *p = &hsotg->params; 193 194 p->otg_caps.hnp_support = false; 195 p->otg_caps.srp_support = false; 196 p->speed = DWC2_SPEED_PARAM_FULL; 197 p->host_rx_fifo_size = 128; 198 p->host_nperio_tx_fifo_size = 96; 199 p->host_perio_tx_fifo_size = 96; 200 p->max_packet_count = 256; 201 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 202 p->i2c_enable = false; 203 p->activate_stm_fs_transceiver = true; 204 } 205 206 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 207 { 208 struct dwc2_core_params *p = &hsotg->params; 209 210 p->host_rx_fifo_size = 622; 211 p->host_nperio_tx_fifo_size = 128; 212 p->host_perio_tx_fifo_size = 256; 213 } 214 215 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 216 { 217 struct dwc2_core_params *p = &hsotg->params; 218 219 p->otg_caps.hnp_support = false; 220 p->otg_caps.srp_support = false; 221 p->otg_caps.otg_rev = 0x200; 222 p->speed = DWC2_SPEED_PARAM_FULL; 223 p->host_rx_fifo_size = 128; 224 p->host_nperio_tx_fifo_size = 96; 225 p->host_perio_tx_fifo_size = 96; 226 p->max_packet_count = 256; 227 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 228 p->i2c_enable = false; 229 p->activate_stm_fs_transceiver = true; 230 p->activate_stm_id_vb_detection = true; 231 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 232 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 233 p->host_support_fs_ls_low_power = true; 234 p->host_ls_low_power_phy_clk = true; 235 } 236 237 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 238 { 239 struct dwc2_core_params *p = &hsotg->params; 240 241 p->otg_caps.hnp_support = false; 242 p->otg_caps.srp_support = false; 243 p->otg_caps.otg_rev = 0x200; 244 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 245 p->host_rx_fifo_size = 440; 246 p->host_nperio_tx_fifo_size = 256; 247 p->host_perio_tx_fifo_size = 256; 248 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 249 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 250 p->lpm = false; 251 p->lpm_clock_gating = false; 252 p->besl = false; 253 p->hird_threshold_en = false; 254 } 255 256 const struct of_device_id dwc2_of_match_table[] = { 257 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 258 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 259 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 260 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 261 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 262 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 263 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 264 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 265 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 266 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 267 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 268 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 269 { .compatible = "snps,dwc2" }, 270 { .compatible = "samsung,s3c6400-hsotg", 271 .data = dwc2_set_s3c6400_params }, 272 { .compatible = "amlogic,meson8-usb", 273 .data = dwc2_set_amlogic_params }, 274 { .compatible = "amlogic,meson8b-usb", 275 .data = dwc2_set_amlogic_params }, 276 { .compatible = "amlogic,meson-gxbb-usb", 277 .data = dwc2_set_amlogic_params }, 278 { .compatible = "amlogic,meson-g12a-usb", 279 .data = dwc2_set_amlogic_g12a_params }, 280 { .compatible = "amlogic,meson-a1-usb", 281 .data = dwc2_set_amlogic_a1_params }, 282 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 283 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 284 { .compatible = "st,stm32f4x9-fsotg", 285 .data = dwc2_set_stm32f4x9_fsotg_params }, 286 { .compatible = "st,stm32f4x9-hsotg" }, 287 { .compatible = "st,stm32f7-hsotg", 288 .data = dwc2_set_stm32f7_hsotg_params }, 289 { .compatible = "st,stm32mp15-fsotg", 290 .data = dwc2_set_stm32mp15_fsotg_params }, 291 { .compatible = "st,stm32mp15-hsotg", 292 .data = dwc2_set_stm32mp15_hsotg_params }, 293 { .compatible = "intel,socfpga-agilex-hsotg", 294 .data = dwc2_set_socfpga_agilex_params }, 295 {}, 296 }; 297 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 298 299 const struct acpi_device_id dwc2_acpi_match[] = { 300 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 301 { }, 302 }; 303 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 304 305 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 306 { 307 switch (hsotg->hw_params.op_mode) { 308 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 309 hsotg->params.otg_caps.hnp_support = true; 310 hsotg->params.otg_caps.srp_support = true; 311 break; 312 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 313 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 314 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 315 hsotg->params.otg_caps.hnp_support = false; 316 hsotg->params.otg_caps.srp_support = true; 317 break; 318 default: 319 hsotg->params.otg_caps.hnp_support = false; 320 hsotg->params.otg_caps.srp_support = false; 321 break; 322 } 323 } 324 325 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 326 { 327 int val; 328 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 329 330 val = DWC2_PHY_TYPE_PARAM_FS; 331 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 332 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 333 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 334 val = DWC2_PHY_TYPE_PARAM_UTMI; 335 else 336 val = DWC2_PHY_TYPE_PARAM_ULPI; 337 } 338 339 if (dwc2_is_fs_iot(hsotg)) 340 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 341 342 hsotg->params.phy_type = val; 343 } 344 345 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 346 { 347 int val; 348 349 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 350 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 351 352 if (dwc2_is_fs_iot(hsotg)) 353 val = DWC2_SPEED_PARAM_FULL; 354 355 if (dwc2_is_hs_iot(hsotg)) 356 val = DWC2_SPEED_PARAM_HIGH; 357 358 hsotg->params.speed = val; 359 } 360 361 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 362 { 363 int val; 364 365 val = (hsotg->hw_params.utmi_phy_data_width == 366 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 367 368 if (hsotg->phy) { 369 /* 370 * If using the generic PHY framework, check if the PHY bus 371 * width is 8-bit and set the phyif appropriately. 372 */ 373 if (phy_get_bus_width(hsotg->phy) == 8) 374 val = 8; 375 } 376 377 hsotg->params.phy_utmi_width = val; 378 } 379 380 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 381 { 382 struct dwc2_core_params *p = &hsotg->params; 383 int depth_average; 384 int fifo_count; 385 int i; 386 387 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 388 389 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 390 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 391 for (i = 1; i <= fifo_count; i++) 392 p->g_tx_fifo_size[i] = depth_average; 393 } 394 395 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 396 { 397 int val; 398 399 if (hsotg->hw_params.hibernation) 400 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 401 else if (hsotg->hw_params.power_optimized) 402 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 403 else 404 val = DWC2_POWER_DOWN_PARAM_NONE; 405 406 hsotg->params.power_down = val; 407 } 408 409 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 410 { 411 struct dwc2_core_params *p = &hsotg->params; 412 413 p->lpm = hsotg->hw_params.lpm_mode; 414 if (p->lpm) { 415 p->lpm_clock_gating = true; 416 p->besl = true; 417 p->hird_threshold_en = true; 418 p->hird_threshold = 4; 419 } else { 420 p->lpm_clock_gating = false; 421 p->besl = false; 422 p->hird_threshold_en = false; 423 } 424 } 425 426 /** 427 * dwc2_set_default_params() - Set all core parameters to their 428 * auto-detected default values. 429 * 430 * @hsotg: Programming view of the DWC_otg controller 431 * 432 */ 433 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 434 { 435 struct dwc2_hw_params *hw = &hsotg->hw_params; 436 struct dwc2_core_params *p = &hsotg->params; 437 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 438 439 dwc2_set_param_otg_cap(hsotg); 440 dwc2_set_param_phy_type(hsotg); 441 dwc2_set_param_speed(hsotg); 442 dwc2_set_param_phy_utmi_width(hsotg); 443 dwc2_set_param_power_down(hsotg); 444 dwc2_set_param_lpm(hsotg); 445 p->phy_ulpi_ddr = false; 446 p->phy_ulpi_ext_vbus = false; 447 448 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 449 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 450 p->i2c_enable = hw->i2c_enable; 451 p->acg_enable = hw->acg_enable; 452 p->ulpi_fs_ls = false; 453 p->ts_dline = false; 454 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 455 p->uframe_sched = true; 456 p->external_id_pin_ctl = false; 457 p->ipg_isoc_en = false; 458 p->service_interval = false; 459 p->max_packet_count = hw->max_packet_count; 460 p->max_transfer_size = hw->max_transfer_size; 461 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 462 p->ref_clk_per = 33333; 463 p->sof_cnt_wkup_alert = 100; 464 465 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 466 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 467 p->host_dma = dma_capable; 468 p->dma_desc_enable = false; 469 p->dma_desc_fs_enable = false; 470 p->host_support_fs_ls_low_power = false; 471 p->host_ls_low_power_phy_clk = false; 472 p->host_channels = hw->host_channels; 473 p->host_rx_fifo_size = hw->rx_fifo_size; 474 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 475 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 476 } 477 478 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 479 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 480 p->g_dma = dma_capable; 481 p->g_dma_desc = hw->dma_desc_enable; 482 483 /* 484 * The values for g_rx_fifo_size (2048) and 485 * g_np_tx_fifo_size (1024) come from the legacy s3c 486 * gadget driver. These defaults have been hard-coded 487 * for some time so many platforms depend on these 488 * values. Leave them as defaults for now and only 489 * auto-detect if the hardware does not support the 490 * default. 491 */ 492 p->g_rx_fifo_size = 2048; 493 p->g_np_tx_fifo_size = 1024; 494 dwc2_set_param_tx_fifo_sizes(hsotg); 495 } 496 } 497 498 /** 499 * dwc2_get_device_properties() - Read in device properties. 500 * 501 * @hsotg: Programming view of the DWC_otg controller 502 * 503 * Read in the device properties and adjust core parameters if needed. 504 */ 505 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 506 { 507 struct dwc2_core_params *p = &hsotg->params; 508 int num; 509 510 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 511 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 512 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 513 &p->g_rx_fifo_size); 514 515 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 516 &p->g_np_tx_fifo_size); 517 518 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 519 if (num > 0) { 520 num = min(num, 15); 521 memset(p->g_tx_fifo_size, 0, 522 sizeof(p->g_tx_fifo_size)); 523 device_property_read_u32_array(hsotg->dev, 524 "g-tx-fifo-size", 525 &p->g_tx_fifo_size[1], 526 num); 527 } 528 529 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 530 } 531 532 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); 533 } 534 535 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 536 { 537 int valid = 1; 538 539 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 540 /* check HNP && SRP capable */ 541 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 542 valid = 0; 543 } else if (!hsotg->params.otg_caps.hnp_support) { 544 /* check SRP only capable */ 545 if (hsotg->params.otg_caps.srp_support) { 546 switch (hsotg->hw_params.op_mode) { 547 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 548 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 549 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 550 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 551 break; 552 default: 553 valid = 0; 554 break; 555 } 556 } 557 /* else: NO HNP && NO SRP capable: always valid */ 558 } else { 559 valid = 0; 560 } 561 562 if (!valid) 563 dwc2_set_param_otg_cap(hsotg); 564 } 565 566 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 567 { 568 int valid = 0; 569 u32 hs_phy_type; 570 u32 fs_phy_type; 571 572 hs_phy_type = hsotg->hw_params.hs_phy_type; 573 fs_phy_type = hsotg->hw_params.fs_phy_type; 574 575 switch (hsotg->params.phy_type) { 576 case DWC2_PHY_TYPE_PARAM_FS: 577 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 578 valid = 1; 579 break; 580 case DWC2_PHY_TYPE_PARAM_UTMI: 581 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 582 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 583 valid = 1; 584 break; 585 case DWC2_PHY_TYPE_PARAM_ULPI: 586 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 587 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 588 valid = 1; 589 break; 590 default: 591 break; 592 } 593 594 if (!valid) 595 dwc2_set_param_phy_type(hsotg); 596 } 597 598 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 599 { 600 int valid = 1; 601 int phy_type = hsotg->params.phy_type; 602 int speed = hsotg->params.speed; 603 604 switch (speed) { 605 case DWC2_SPEED_PARAM_HIGH: 606 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 607 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 608 valid = 0; 609 break; 610 case DWC2_SPEED_PARAM_FULL: 611 case DWC2_SPEED_PARAM_LOW: 612 break; 613 default: 614 valid = 0; 615 break; 616 } 617 618 if (!valid) 619 dwc2_set_param_speed(hsotg); 620 } 621 622 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 623 { 624 int valid = 0; 625 int param = hsotg->params.phy_utmi_width; 626 int width = hsotg->hw_params.utmi_phy_data_width; 627 628 switch (width) { 629 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 630 valid = (param == 8); 631 break; 632 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 633 valid = (param == 16); 634 break; 635 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 636 valid = (param == 8 || param == 16); 637 break; 638 } 639 640 if (!valid) 641 dwc2_set_param_phy_utmi_width(hsotg); 642 } 643 644 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 645 { 646 int param = hsotg->params.power_down; 647 648 switch (param) { 649 case DWC2_POWER_DOWN_PARAM_NONE: 650 break; 651 case DWC2_POWER_DOWN_PARAM_PARTIAL: 652 if (hsotg->hw_params.power_optimized) 653 break; 654 dev_dbg(hsotg->dev, 655 "Partial power down isn't supported by HW\n"); 656 param = DWC2_POWER_DOWN_PARAM_NONE; 657 break; 658 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 659 if (hsotg->hw_params.hibernation) 660 break; 661 dev_dbg(hsotg->dev, 662 "Hibernation isn't supported by HW\n"); 663 param = DWC2_POWER_DOWN_PARAM_NONE; 664 break; 665 default: 666 dev_err(hsotg->dev, 667 "%s: Invalid parameter power_down=%d\n", 668 __func__, param); 669 param = DWC2_POWER_DOWN_PARAM_NONE; 670 break; 671 } 672 673 hsotg->params.power_down = param; 674 } 675 676 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 677 { 678 int fifo_count; 679 int fifo; 680 int min; 681 u32 total = 0; 682 u32 dptxfszn; 683 684 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 685 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 686 687 for (fifo = 1; fifo <= fifo_count; fifo++) 688 total += hsotg->params.g_tx_fifo_size[fifo]; 689 690 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 691 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 692 __func__); 693 dwc2_set_param_tx_fifo_sizes(hsotg); 694 } 695 696 for (fifo = 1; fifo <= fifo_count; fifo++) { 697 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 698 699 if (hsotg->params.g_tx_fifo_size[fifo] < min || 700 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 701 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 702 __func__, fifo, 703 hsotg->params.g_tx_fifo_size[fifo]); 704 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 705 } 706 } 707 } 708 709 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 710 if ((int)(hsotg->params._param) < (_min) || \ 711 (hsotg->params._param) > (_max)) { \ 712 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 713 __func__, #_param, hsotg->params._param); \ 714 hsotg->params._param = (_def); \ 715 } \ 716 } while (0) 717 718 #define CHECK_BOOL(_param, _check) do { \ 719 if (hsotg->params._param && !(_check)) { \ 720 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 721 __func__, #_param, hsotg->params._param); \ 722 hsotg->params._param = false; \ 723 } \ 724 } while (0) 725 726 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 727 { 728 struct dwc2_hw_params *hw = &hsotg->hw_params; 729 struct dwc2_core_params *p = &hsotg->params; 730 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 731 732 dwc2_check_param_otg_cap(hsotg); 733 dwc2_check_param_phy_type(hsotg); 734 dwc2_check_param_speed(hsotg); 735 dwc2_check_param_phy_utmi_width(hsotg); 736 dwc2_check_param_power_down(hsotg); 737 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 738 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 739 CHECK_BOOL(i2c_enable, hw->i2c_enable); 740 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 741 CHECK_BOOL(acg_enable, hw->acg_enable); 742 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 743 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 744 CHECK_BOOL(lpm, hw->lpm_mode); 745 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 746 CHECK_BOOL(besl, hsotg->params.lpm); 747 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 748 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 749 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 750 CHECK_BOOL(service_interval, hw->service_interval_mode); 751 CHECK_RANGE(max_packet_count, 752 15, hw->max_packet_count, 753 hw->max_packet_count); 754 CHECK_RANGE(max_transfer_size, 755 2047, hw->max_transfer_size, 756 hw->max_transfer_size); 757 758 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 759 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 760 CHECK_BOOL(host_dma, dma_capable); 761 CHECK_BOOL(dma_desc_enable, p->host_dma); 762 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 763 CHECK_BOOL(host_ls_low_power_phy_clk, 764 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 765 CHECK_RANGE(host_channels, 766 1, hw->host_channels, 767 hw->host_channels); 768 CHECK_RANGE(host_rx_fifo_size, 769 16, hw->rx_fifo_size, 770 hw->rx_fifo_size); 771 CHECK_RANGE(host_nperio_tx_fifo_size, 772 16, hw->host_nperio_tx_fifo_size, 773 hw->host_nperio_tx_fifo_size); 774 CHECK_RANGE(host_perio_tx_fifo_size, 775 16, hw->host_perio_tx_fifo_size, 776 hw->host_perio_tx_fifo_size); 777 } 778 779 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 780 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 781 CHECK_BOOL(g_dma, dma_capable); 782 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 783 CHECK_RANGE(g_rx_fifo_size, 784 16, hw->rx_fifo_size, 785 hw->rx_fifo_size); 786 CHECK_RANGE(g_np_tx_fifo_size, 787 16, hw->dev_nperio_tx_fifo_size, 788 hw->dev_nperio_tx_fifo_size); 789 dwc2_check_param_tx_fifo_sizes(hsotg); 790 } 791 } 792 793 /* 794 * Gets host hardware parameters. Forces host mode if not currently in 795 * host mode. Should be called immediately after a core soft reset in 796 * order to get the reset values. 797 */ 798 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 799 { 800 struct dwc2_hw_params *hw = &hsotg->hw_params; 801 u32 gnptxfsiz; 802 u32 hptxfsiz; 803 804 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 805 return; 806 807 dwc2_force_mode(hsotg, true); 808 809 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 810 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 811 812 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 813 FIFOSIZE_DEPTH_SHIFT; 814 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 815 FIFOSIZE_DEPTH_SHIFT; 816 } 817 818 /* 819 * Gets device hardware parameters. Forces device mode if not 820 * currently in device mode. Should be called immediately after a core 821 * soft reset in order to get the reset values. 822 */ 823 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 824 { 825 struct dwc2_hw_params *hw = &hsotg->hw_params; 826 u32 gnptxfsiz; 827 int fifo, fifo_count; 828 829 if (hsotg->dr_mode == USB_DR_MODE_HOST) 830 return; 831 832 dwc2_force_mode(hsotg, false); 833 834 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 835 836 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 837 838 for (fifo = 1; fifo <= fifo_count; fifo++) { 839 hw->g_tx_fifo_size[fifo] = 840 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 841 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 842 } 843 844 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 845 FIFOSIZE_DEPTH_SHIFT; 846 } 847 848 /** 849 * dwc2_get_hwparams() - During device initialization, read various hardware 850 * configuration registers and interpret the contents. 851 * 852 * @hsotg: Programming view of the DWC_otg controller 853 * 854 */ 855 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 856 { 857 struct dwc2_hw_params *hw = &hsotg->hw_params; 858 unsigned int width; 859 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 860 u32 grxfsiz; 861 862 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 863 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 864 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 865 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 866 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 867 868 /* hwcfg1 */ 869 hw->dev_ep_dirs = hwcfg1; 870 871 /* hwcfg2 */ 872 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 873 GHWCFG2_OP_MODE_SHIFT; 874 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 875 GHWCFG2_ARCHITECTURE_SHIFT; 876 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 877 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 878 GHWCFG2_NUM_HOST_CHAN_SHIFT); 879 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 880 GHWCFG2_HS_PHY_TYPE_SHIFT; 881 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 882 GHWCFG2_FS_PHY_TYPE_SHIFT; 883 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 884 GHWCFG2_NUM_DEV_EP_SHIFT; 885 hw->nperio_tx_q_depth = 886 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 887 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 888 hw->host_perio_tx_q_depth = 889 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 890 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 891 hw->dev_token_q_depth = 892 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 893 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 894 895 /* hwcfg3 */ 896 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 897 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 898 hw->max_transfer_size = (1 << (width + 11)) - 1; 899 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 900 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 901 hw->max_packet_count = (1 << (width + 4)) - 1; 902 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 903 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 904 GHWCFG3_DFIFO_DEPTH_SHIFT; 905 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 906 907 /* hwcfg4 */ 908 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 909 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 910 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 911 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 912 GHWCFG4_NUM_IN_EPS_SHIFT; 913 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 914 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 915 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 916 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 917 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 918 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 919 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 920 hw->service_interval_mode = !!(hwcfg4 & 921 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 922 923 /* fifo sizes */ 924 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 925 GRXFSIZ_DEPTH_SHIFT; 926 /* 927 * Host specific hardware parameters. Reading these parameters 928 * requires the controller to be in host mode. The mode will 929 * be forced, if necessary, to read these values. 930 */ 931 dwc2_get_host_hwparams(hsotg); 932 dwc2_get_dev_hwparams(hsotg); 933 934 return 0; 935 } 936 937 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 938 939 int dwc2_init_params(struct dwc2_hsotg *hsotg) 940 { 941 const struct of_device_id *match; 942 set_params_cb set_params; 943 944 dwc2_set_default_params(hsotg); 945 dwc2_get_device_properties(hsotg); 946 947 match = of_match_device(dwc2_of_match_table, hsotg->dev); 948 if (match && match->data) { 949 set_params = match->data; 950 set_params(hsotg); 951 } else { 952 const struct acpi_device_id *amatch; 953 954 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 955 if (amatch && amatch->driver_data) { 956 set_params = (set_params_cb)amatch->driver_data; 957 set_params(hsotg); 958 } 959 } 960 961 dwc2_check_params(hsotg); 962 963 return 0; 964 } 965