1 /* 2 * Copyright (C) 2004-2016 Synopsys, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions, and the following disclaimer, 9 * without modification. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The names of the above-listed copyright holders may not be used 14 * to endorse or promote products derived from this software without 15 * specific prior written permission. 16 * 17 * ALTERNATIVELY, this software may be distributed under the terms of the 18 * GNU General Public License ("GPL") as published by the Free Software 19 * Foundation; either version 2 of the License, or (at your option) any 20 * later version. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_device.h> 38 39 #include "core.h" 40 41 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 42 { 43 struct dwc2_core_params *p = &hsotg->params; 44 45 p->host_rx_fifo_size = 774; 46 p->max_transfer_size = 65535; 47 p->max_packet_count = 511; 48 p->ahbcfg = 0x10; 49 p->uframe_sched = false; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->uframe_sched = false; 71 p->change_speed_quirk = true; 72 } 73 74 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 79 p->host_rx_fifo_size = 525; 80 p->host_nperio_tx_fifo_size = 128; 81 p->host_perio_tx_fifo_size = 256; 82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 83 GAHBCFG_HBSTLEN_SHIFT; 84 } 85 86 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 87 { 88 struct dwc2_core_params *p = &hsotg->params; 89 90 p->otg_cap = 2; 91 p->host_rx_fifo_size = 288; 92 p->host_nperio_tx_fifo_size = 128; 93 p->host_perio_tx_fifo_size = 96; 94 p->max_transfer_size = 65535; 95 p->max_packet_count = 511; 96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 97 GAHBCFG_HBSTLEN_SHIFT; 98 } 99 100 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 105 p->speed = DWC2_SPEED_PARAM_HIGH; 106 p->host_rx_fifo_size = 512; 107 p->host_nperio_tx_fifo_size = 500; 108 p->host_perio_tx_fifo_size = 500; 109 p->host_channels = 16; 110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 112 GAHBCFG_HBSTLEN_SHIFT; 113 p->uframe_sched = false; 114 } 115 116 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 117 { 118 struct dwc2_core_params *p = &hsotg->params; 119 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 121 } 122 123 const struct of_device_id dwc2_of_match_table[] = { 124 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 125 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 126 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 127 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 128 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 129 { .compatible = "snps,dwc2" }, 130 { .compatible = "samsung,s3c6400-hsotg" }, 131 { .compatible = "amlogic,meson8b-usb", 132 .data = dwc2_set_amlogic_params }, 133 { .compatible = "amlogic,meson-gxbb-usb", 134 .data = dwc2_set_amlogic_params }, 135 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 136 {}, 137 }; 138 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 139 140 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 141 { 142 u8 val; 143 144 switch (hsotg->hw_params.op_mode) { 145 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 146 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 147 break; 148 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 149 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 150 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 151 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 152 break; 153 default: 154 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 155 break; 156 } 157 158 hsotg->params.otg_cap = val; 159 } 160 161 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 162 { 163 int val; 164 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 165 166 val = DWC2_PHY_TYPE_PARAM_FS; 167 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 168 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 169 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 170 val = DWC2_PHY_TYPE_PARAM_UTMI; 171 else 172 val = DWC2_PHY_TYPE_PARAM_ULPI; 173 } 174 175 if (dwc2_is_fs_iot(hsotg)) 176 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 177 178 hsotg->params.phy_type = val; 179 } 180 181 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 182 { 183 int val; 184 185 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 186 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 187 188 if (dwc2_is_fs_iot(hsotg)) 189 val = DWC2_SPEED_PARAM_FULL; 190 191 if (dwc2_is_hs_iot(hsotg)) 192 val = DWC2_SPEED_PARAM_HIGH; 193 194 hsotg->params.speed = val; 195 } 196 197 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 198 { 199 int val; 200 201 val = (hsotg->hw_params.utmi_phy_data_width == 202 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 203 204 hsotg->params.phy_utmi_width = val; 205 } 206 207 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 208 { 209 struct dwc2_core_params *p = &hsotg->params; 210 int depth_average; 211 int fifo_count; 212 int i; 213 214 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 215 216 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 217 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 218 for (i = 1; i <= fifo_count; i++) 219 p->g_tx_fifo_size[i] = depth_average; 220 } 221 222 /** 223 * dwc2_set_default_params() - Set all core parameters to their 224 * auto-detected default values. 225 */ 226 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 227 { 228 struct dwc2_hw_params *hw = &hsotg->hw_params; 229 struct dwc2_core_params *p = &hsotg->params; 230 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 231 232 dwc2_set_param_otg_cap(hsotg); 233 dwc2_set_param_phy_type(hsotg); 234 dwc2_set_param_speed(hsotg); 235 dwc2_set_param_phy_utmi_width(hsotg); 236 p->phy_ulpi_ddr = false; 237 p->phy_ulpi_ext_vbus = false; 238 239 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 240 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 241 p->i2c_enable = hw->i2c_enable; 242 p->ulpi_fs_ls = false; 243 p->ts_dline = false; 244 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 245 p->uframe_sched = true; 246 p->external_id_pin_ctl = false; 247 p->hibernation = false; 248 p->max_packet_count = hw->max_packet_count; 249 p->max_transfer_size = hw->max_transfer_size; 250 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; 251 252 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 253 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 254 p->host_dma = dma_capable; 255 p->dma_desc_enable = false; 256 p->dma_desc_fs_enable = false; 257 p->host_support_fs_ls_low_power = false; 258 p->host_ls_low_power_phy_clk = false; 259 p->host_channels = hw->host_channels; 260 p->host_rx_fifo_size = hw->rx_fifo_size; 261 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 262 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 263 } 264 265 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 266 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 267 p->g_dma = dma_capable; 268 p->g_dma_desc = hw->dma_desc_enable; 269 270 /* 271 * The values for g_rx_fifo_size (2048) and 272 * g_np_tx_fifo_size (1024) come from the legacy s3c 273 * gadget driver. These defaults have been hard-coded 274 * for some time so many platforms depend on these 275 * values. Leave them as defaults for now and only 276 * auto-detect if the hardware does not support the 277 * default. 278 */ 279 p->g_rx_fifo_size = 2048; 280 p->g_np_tx_fifo_size = 1024; 281 dwc2_set_param_tx_fifo_sizes(hsotg); 282 } 283 } 284 285 /** 286 * dwc2_get_device_properties() - Read in device properties. 287 * 288 * Read in the device properties and adjust core parameters if needed. 289 */ 290 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 291 { 292 struct dwc2_core_params *p = &hsotg->params; 293 int num; 294 295 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 296 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 297 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 298 &p->g_rx_fifo_size); 299 300 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 301 &p->g_np_tx_fifo_size); 302 303 num = device_property_read_u32_array(hsotg->dev, 304 "g-tx-fifo-size", 305 NULL, 0); 306 307 if (num > 0) { 308 num = min(num, 15); 309 memset(p->g_tx_fifo_size, 0, 310 sizeof(p->g_tx_fifo_size)); 311 device_property_read_u32_array(hsotg->dev, 312 "g-tx-fifo-size", 313 &p->g_tx_fifo_size[1], 314 num); 315 } 316 } 317 } 318 319 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 320 { 321 int valid = 1; 322 323 switch (hsotg->params.otg_cap) { 324 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 325 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 326 valid = 0; 327 break; 328 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 329 switch (hsotg->hw_params.op_mode) { 330 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 331 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 332 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 333 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 334 break; 335 default: 336 valid = 0; 337 break; 338 } 339 break; 340 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 341 /* always valid */ 342 break; 343 default: 344 valid = 0; 345 break; 346 } 347 348 if (!valid) 349 dwc2_set_param_otg_cap(hsotg); 350 } 351 352 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 353 { 354 int valid = 0; 355 u32 hs_phy_type; 356 u32 fs_phy_type; 357 358 hs_phy_type = hsotg->hw_params.hs_phy_type; 359 fs_phy_type = hsotg->hw_params.fs_phy_type; 360 361 switch (hsotg->params.phy_type) { 362 case DWC2_PHY_TYPE_PARAM_FS: 363 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 364 valid = 1; 365 break; 366 case DWC2_PHY_TYPE_PARAM_UTMI: 367 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 368 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 369 valid = 1; 370 break; 371 case DWC2_PHY_TYPE_PARAM_ULPI: 372 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 373 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 374 valid = 1; 375 break; 376 default: 377 break; 378 } 379 380 if (!valid) 381 dwc2_set_param_phy_type(hsotg); 382 } 383 384 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 385 { 386 int valid = 1; 387 int phy_type = hsotg->params.phy_type; 388 int speed = hsotg->params.speed; 389 390 switch (speed) { 391 case DWC2_SPEED_PARAM_HIGH: 392 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 393 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 394 valid = 0; 395 break; 396 case DWC2_SPEED_PARAM_FULL: 397 case DWC2_SPEED_PARAM_LOW: 398 break; 399 default: 400 valid = 0; 401 break; 402 } 403 404 if (!valid) 405 dwc2_set_param_speed(hsotg); 406 } 407 408 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 409 { 410 int valid = 0; 411 int param = hsotg->params.phy_utmi_width; 412 int width = hsotg->hw_params.utmi_phy_data_width; 413 414 switch (width) { 415 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 416 valid = (param == 8); 417 break; 418 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 419 valid = (param == 16); 420 break; 421 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 422 valid = (param == 8 || param == 16); 423 break; 424 } 425 426 if (!valid) 427 dwc2_set_param_phy_utmi_width(hsotg); 428 } 429 430 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 431 { 432 int fifo_count; 433 int fifo; 434 int min; 435 u32 total = 0; 436 u32 dptxfszn; 437 438 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 439 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 440 441 for (fifo = 1; fifo <= fifo_count; fifo++) 442 total += hsotg->params.g_tx_fifo_size[fifo]; 443 444 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 445 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 446 __func__); 447 dwc2_set_param_tx_fifo_sizes(hsotg); 448 } 449 450 for (fifo = 1; fifo <= fifo_count; fifo++) { 451 dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & 452 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 453 454 if (hsotg->params.g_tx_fifo_size[fifo] < min || 455 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 456 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 457 __func__, fifo, 458 hsotg->params.g_tx_fifo_size[fifo]); 459 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 460 } 461 } 462 } 463 464 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 465 if ((hsotg->params._param) < (_min) || \ 466 (hsotg->params._param) > (_max)) { \ 467 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 468 __func__, #_param, hsotg->params._param); \ 469 hsotg->params._param = (_def); \ 470 } \ 471 } while (0) 472 473 #define CHECK_BOOL(_param, _check) do { \ 474 if (hsotg->params._param && !(_check)) { \ 475 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 476 __func__, #_param, hsotg->params._param); \ 477 hsotg->params._param = false; \ 478 } \ 479 } while (0) 480 481 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 482 { 483 struct dwc2_hw_params *hw = &hsotg->hw_params; 484 struct dwc2_core_params *p = &hsotg->params; 485 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 486 487 dwc2_check_param_otg_cap(hsotg); 488 dwc2_check_param_phy_type(hsotg); 489 dwc2_check_param_speed(hsotg); 490 dwc2_check_param_phy_utmi_width(hsotg); 491 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 492 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 493 CHECK_BOOL(i2c_enable, hw->i2c_enable); 494 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 495 CHECK_RANGE(max_packet_count, 496 15, hw->max_packet_count, 497 hw->max_packet_count); 498 CHECK_RANGE(max_transfer_size, 499 2047, hw->max_transfer_size, 500 hw->max_transfer_size); 501 502 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 503 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 504 CHECK_BOOL(host_dma, dma_capable); 505 CHECK_BOOL(dma_desc_enable, p->host_dma); 506 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 507 CHECK_BOOL(host_ls_low_power_phy_clk, 508 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 509 CHECK_RANGE(host_channels, 510 1, hw->host_channels, 511 hw->host_channels); 512 CHECK_RANGE(host_rx_fifo_size, 513 16, hw->rx_fifo_size, 514 hw->rx_fifo_size); 515 CHECK_RANGE(host_nperio_tx_fifo_size, 516 16, hw->host_nperio_tx_fifo_size, 517 hw->host_nperio_tx_fifo_size); 518 CHECK_RANGE(host_perio_tx_fifo_size, 519 16, hw->host_perio_tx_fifo_size, 520 hw->host_perio_tx_fifo_size); 521 } 522 523 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 524 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 525 CHECK_BOOL(g_dma, dma_capable); 526 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 527 CHECK_RANGE(g_rx_fifo_size, 528 16, hw->rx_fifo_size, 529 hw->rx_fifo_size); 530 CHECK_RANGE(g_np_tx_fifo_size, 531 16, hw->dev_nperio_tx_fifo_size, 532 hw->dev_nperio_tx_fifo_size); 533 dwc2_check_param_tx_fifo_sizes(hsotg); 534 } 535 } 536 537 /* 538 * Gets host hardware parameters. Forces host mode if not currently in 539 * host mode. Should be called immediately after a core soft reset in 540 * order to get the reset values. 541 */ 542 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 543 { 544 struct dwc2_hw_params *hw = &hsotg->hw_params; 545 u32 gnptxfsiz; 546 u32 hptxfsiz; 547 bool forced; 548 549 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 550 return; 551 552 forced = dwc2_force_mode_if_needed(hsotg, true); 553 554 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 555 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 556 557 if (forced) 558 dwc2_clear_force_mode(hsotg); 559 560 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 561 FIFOSIZE_DEPTH_SHIFT; 562 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 563 FIFOSIZE_DEPTH_SHIFT; 564 } 565 566 /* 567 * Gets device hardware parameters. Forces device mode if not 568 * currently in device mode. Should be called immediately after a core 569 * soft reset in order to get the reset values. 570 */ 571 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 572 { 573 struct dwc2_hw_params *hw = &hsotg->hw_params; 574 bool forced; 575 u32 gnptxfsiz; 576 577 if (hsotg->dr_mode == USB_DR_MODE_HOST) 578 return; 579 580 forced = dwc2_force_mode_if_needed(hsotg, false); 581 582 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 583 584 if (forced) 585 dwc2_clear_force_mode(hsotg); 586 587 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 588 FIFOSIZE_DEPTH_SHIFT; 589 } 590 591 /** 592 * During device initialization, read various hardware configuration 593 * registers and interpret the contents. 594 */ 595 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 596 { 597 struct dwc2_hw_params *hw = &hsotg->hw_params; 598 unsigned int width; 599 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 600 u32 grxfsiz; 601 602 /* 603 * Attempt to ensure this device is really a DWC_otg Controller. 604 * Read and verify the GSNPSID register contents. The value should be 605 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 606 * as in "OTG version 2.xx" or "OTG version 3.xx". 607 */ 608 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 609 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 610 (hw->snpsid & 0xfffff000) != 0x4f543000 && 611 (hw->snpsid & 0xffff0000) != 0x55310000 && 612 (hw->snpsid & 0xffff0000) != 0x55320000) { 613 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 614 hw->snpsid); 615 return -ENODEV; 616 } 617 618 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 619 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 620 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 621 622 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 623 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 624 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 625 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 626 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 627 628 /* 629 * Host specific hardware parameters. Reading these parameters 630 * requires the controller to be in host mode. The mode will 631 * be forced, if necessary, to read these values. 632 */ 633 dwc2_get_host_hwparams(hsotg); 634 dwc2_get_dev_hwparams(hsotg); 635 636 /* hwcfg1 */ 637 hw->dev_ep_dirs = hwcfg1; 638 639 /* hwcfg2 */ 640 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 641 GHWCFG2_OP_MODE_SHIFT; 642 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 643 GHWCFG2_ARCHITECTURE_SHIFT; 644 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 645 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 646 GHWCFG2_NUM_HOST_CHAN_SHIFT); 647 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 648 GHWCFG2_HS_PHY_TYPE_SHIFT; 649 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 650 GHWCFG2_FS_PHY_TYPE_SHIFT; 651 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 652 GHWCFG2_NUM_DEV_EP_SHIFT; 653 hw->nperio_tx_q_depth = 654 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 655 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 656 hw->host_perio_tx_q_depth = 657 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 658 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 659 hw->dev_token_q_depth = 660 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 661 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 662 663 /* hwcfg3 */ 664 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 665 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 666 hw->max_transfer_size = (1 << (width + 11)) - 1; 667 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 668 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 669 hw->max_packet_count = (1 << (width + 4)) - 1; 670 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 671 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 672 GHWCFG3_DFIFO_DEPTH_SHIFT; 673 674 /* hwcfg4 */ 675 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 676 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 677 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 678 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 679 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 680 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 681 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 682 683 /* fifo sizes */ 684 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 685 GRXFSIZ_DEPTH_SHIFT; 686 687 return 0; 688 } 689 690 int dwc2_init_params(struct dwc2_hsotg *hsotg) 691 { 692 const struct of_device_id *match; 693 void (*set_params)(void *data); 694 695 dwc2_set_default_params(hsotg); 696 dwc2_get_device_properties(hsotg); 697 698 match = of_match_device(dwc2_of_match_table, hsotg->dev); 699 if (match && match->data) { 700 set_params = match->data; 701 set_params(hsotg); 702 } 703 704 dwc2_check_params(hsotg); 705 706 return 0; 707 } 708