1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 40 #include "core.h" 41 42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 43 { 44 struct dwc2_core_params *p = &hsotg->params; 45 46 p->host_rx_fifo_size = 774; 47 p->max_transfer_size = 65535; 48 p->max_packet_count = 511; 49 p->ahbcfg = 0x10; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->change_speed_quirk = true; 71 p->power_down = false; 72 } 73 74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->power_down = 0; 79 p->phy_utmi_width = 8; 80 } 81 82 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 83 { 84 struct dwc2_core_params *p = &hsotg->params; 85 86 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 87 p->host_rx_fifo_size = 525; 88 p->host_nperio_tx_fifo_size = 128; 89 p->host_perio_tx_fifo_size = 256; 90 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 91 GAHBCFG_HBSTLEN_SHIFT; 92 p->power_down = 0; 93 } 94 95 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 96 { 97 struct dwc2_core_params *p = &hsotg->params; 98 99 p->otg_cap = 2; 100 p->host_rx_fifo_size = 288; 101 p->host_nperio_tx_fifo_size = 128; 102 p->host_perio_tx_fifo_size = 96; 103 p->max_transfer_size = 65535; 104 p->max_packet_count = 511; 105 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 106 GAHBCFG_HBSTLEN_SHIFT; 107 } 108 109 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 110 { 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 114 p->speed = DWC2_SPEED_PARAM_HIGH; 115 p->host_rx_fifo_size = 512; 116 p->host_nperio_tx_fifo_size = 500; 117 p->host_perio_tx_fifo_size = 500; 118 p->host_channels = 16; 119 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 121 GAHBCFG_HBSTLEN_SHIFT; 122 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 123 } 124 125 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 126 { 127 struct dwc2_core_params *p = &hsotg->params; 128 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133 } 134 135 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 136 { 137 struct dwc2_core_params *p = &hsotg->params; 138 139 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 140 } 141 142 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 143 { 144 struct dwc2_core_params *p = &hsotg->params; 145 146 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 147 p->speed = DWC2_SPEED_PARAM_FULL; 148 p->host_rx_fifo_size = 128; 149 p->host_nperio_tx_fifo_size = 96; 150 p->host_perio_tx_fifo_size = 96; 151 p->max_packet_count = 256; 152 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 153 p->i2c_enable = false; 154 p->activate_stm_fs_transceiver = true; 155 } 156 157 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 158 { 159 struct dwc2_core_params *p = &hsotg->params; 160 161 p->host_rx_fifo_size = 622; 162 p->host_nperio_tx_fifo_size = 128; 163 p->host_perio_tx_fifo_size = 256; 164 } 165 166 const struct of_device_id dwc2_of_match_table[] = { 167 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 168 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 169 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 170 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 171 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 172 { .compatible = "snps,dwc2" }, 173 { .compatible = "samsung,s3c6400-hsotg", 174 .data = dwc2_set_s3c6400_params }, 175 { .compatible = "amlogic,meson8-usb", 176 .data = dwc2_set_amlogic_params }, 177 { .compatible = "amlogic,meson8b-usb", 178 .data = dwc2_set_amlogic_params }, 179 { .compatible = "amlogic,meson-gxbb-usb", 180 .data = dwc2_set_amlogic_params }, 181 { .compatible = "amlogic,meson-g12a-usb", 182 .data = dwc2_set_amlogic_g12a_params }, 183 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 184 { .compatible = "st,stm32f4x9-fsotg", 185 .data = dwc2_set_stm32f4x9_fsotg_params }, 186 { .compatible = "st,stm32f4x9-hsotg" }, 187 { .compatible = "st,stm32f7-hsotg", 188 .data = dwc2_set_stm32f7_hsotg_params }, 189 {}, 190 }; 191 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 192 193 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 194 { 195 u8 val; 196 197 switch (hsotg->hw_params.op_mode) { 198 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 199 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 200 break; 201 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 202 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 203 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 204 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 205 break; 206 default: 207 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 208 break; 209 } 210 211 hsotg->params.otg_cap = val; 212 } 213 214 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 215 { 216 int val; 217 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 218 219 val = DWC2_PHY_TYPE_PARAM_FS; 220 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 221 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 222 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 223 val = DWC2_PHY_TYPE_PARAM_UTMI; 224 else 225 val = DWC2_PHY_TYPE_PARAM_ULPI; 226 } 227 228 if (dwc2_is_fs_iot(hsotg)) 229 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 230 231 hsotg->params.phy_type = val; 232 } 233 234 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 235 { 236 int val; 237 238 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 239 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 240 241 if (dwc2_is_fs_iot(hsotg)) 242 val = DWC2_SPEED_PARAM_FULL; 243 244 if (dwc2_is_hs_iot(hsotg)) 245 val = DWC2_SPEED_PARAM_HIGH; 246 247 hsotg->params.speed = val; 248 } 249 250 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 251 { 252 int val; 253 254 val = (hsotg->hw_params.utmi_phy_data_width == 255 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 256 257 if (hsotg->phy) { 258 /* 259 * If using the generic PHY framework, check if the PHY bus 260 * width is 8-bit and set the phyif appropriately. 261 */ 262 if (phy_get_bus_width(hsotg->phy) == 8) 263 val = 8; 264 } 265 266 hsotg->params.phy_utmi_width = val; 267 } 268 269 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 270 { 271 struct dwc2_core_params *p = &hsotg->params; 272 int depth_average; 273 int fifo_count; 274 int i; 275 276 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 277 278 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 279 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 280 for (i = 1; i <= fifo_count; i++) 281 p->g_tx_fifo_size[i] = depth_average; 282 } 283 284 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 285 { 286 int val; 287 288 if (hsotg->hw_params.hibernation) 289 val = 2; 290 else if (hsotg->hw_params.power_optimized) 291 val = 1; 292 else 293 val = 0; 294 295 hsotg->params.power_down = val; 296 } 297 298 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 299 { 300 struct dwc2_core_params *p = &hsotg->params; 301 302 p->lpm = hsotg->hw_params.lpm_mode; 303 if (p->lpm) { 304 p->lpm_clock_gating = true; 305 p->besl = true; 306 p->hird_threshold_en = true; 307 p->hird_threshold = 4; 308 } else { 309 p->lpm_clock_gating = false; 310 p->besl = false; 311 p->hird_threshold_en = false; 312 } 313 } 314 315 /** 316 * dwc2_set_default_params() - Set all core parameters to their 317 * auto-detected default values. 318 * 319 * @hsotg: Programming view of the DWC_otg controller 320 * 321 */ 322 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 323 { 324 struct dwc2_hw_params *hw = &hsotg->hw_params; 325 struct dwc2_core_params *p = &hsotg->params; 326 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 327 328 dwc2_set_param_otg_cap(hsotg); 329 dwc2_set_param_phy_type(hsotg); 330 dwc2_set_param_speed(hsotg); 331 dwc2_set_param_phy_utmi_width(hsotg); 332 dwc2_set_param_power_down(hsotg); 333 dwc2_set_param_lpm(hsotg); 334 p->phy_ulpi_ddr = false; 335 p->phy_ulpi_ext_vbus = false; 336 337 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 338 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 339 p->i2c_enable = hw->i2c_enable; 340 p->acg_enable = hw->acg_enable; 341 p->ulpi_fs_ls = false; 342 p->ts_dline = false; 343 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 344 p->uframe_sched = true; 345 p->external_id_pin_ctl = false; 346 p->ipg_isoc_en = false; 347 p->service_interval = false; 348 p->max_packet_count = hw->max_packet_count; 349 p->max_transfer_size = hw->max_transfer_size; 350 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 351 p->ref_clk_per = 33333; 352 p->sof_cnt_wkup_alert = 100; 353 354 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 355 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 356 p->host_dma = dma_capable; 357 p->dma_desc_enable = false; 358 p->dma_desc_fs_enable = false; 359 p->host_support_fs_ls_low_power = false; 360 p->host_ls_low_power_phy_clk = false; 361 p->host_channels = hw->host_channels; 362 p->host_rx_fifo_size = hw->rx_fifo_size; 363 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 364 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 365 } 366 367 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 368 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 369 p->g_dma = dma_capable; 370 p->g_dma_desc = hw->dma_desc_enable; 371 372 /* 373 * The values for g_rx_fifo_size (2048) and 374 * g_np_tx_fifo_size (1024) come from the legacy s3c 375 * gadget driver. These defaults have been hard-coded 376 * for some time so many platforms depend on these 377 * values. Leave them as defaults for now and only 378 * auto-detect if the hardware does not support the 379 * default. 380 */ 381 p->g_rx_fifo_size = 2048; 382 p->g_np_tx_fifo_size = 1024; 383 dwc2_set_param_tx_fifo_sizes(hsotg); 384 } 385 } 386 387 /** 388 * dwc2_get_device_properties() - Read in device properties. 389 * 390 * @hsotg: Programming view of the DWC_otg controller 391 * 392 * Read in the device properties and adjust core parameters if needed. 393 */ 394 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 395 { 396 struct dwc2_core_params *p = &hsotg->params; 397 int num; 398 399 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 400 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 401 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 402 &p->g_rx_fifo_size); 403 404 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 405 &p->g_np_tx_fifo_size); 406 407 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 408 if (num > 0) { 409 num = min(num, 15); 410 memset(p->g_tx_fifo_size, 0, 411 sizeof(p->g_tx_fifo_size)); 412 device_property_read_u32_array(hsotg->dev, 413 "g-tx-fifo-size", 414 &p->g_tx_fifo_size[1], 415 num); 416 } 417 } 418 419 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 420 p->oc_disable = true; 421 } 422 423 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 424 { 425 int valid = 1; 426 427 switch (hsotg->params.otg_cap) { 428 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 429 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 430 valid = 0; 431 break; 432 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 433 switch (hsotg->hw_params.op_mode) { 434 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 435 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 436 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 437 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 438 break; 439 default: 440 valid = 0; 441 break; 442 } 443 break; 444 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 445 /* always valid */ 446 break; 447 default: 448 valid = 0; 449 break; 450 } 451 452 if (!valid) 453 dwc2_set_param_otg_cap(hsotg); 454 } 455 456 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 457 { 458 int valid = 0; 459 u32 hs_phy_type; 460 u32 fs_phy_type; 461 462 hs_phy_type = hsotg->hw_params.hs_phy_type; 463 fs_phy_type = hsotg->hw_params.fs_phy_type; 464 465 switch (hsotg->params.phy_type) { 466 case DWC2_PHY_TYPE_PARAM_FS: 467 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 468 valid = 1; 469 break; 470 case DWC2_PHY_TYPE_PARAM_UTMI: 471 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 472 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 473 valid = 1; 474 break; 475 case DWC2_PHY_TYPE_PARAM_ULPI: 476 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 477 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 478 valid = 1; 479 break; 480 default: 481 break; 482 } 483 484 if (!valid) 485 dwc2_set_param_phy_type(hsotg); 486 } 487 488 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 489 { 490 int valid = 1; 491 int phy_type = hsotg->params.phy_type; 492 int speed = hsotg->params.speed; 493 494 switch (speed) { 495 case DWC2_SPEED_PARAM_HIGH: 496 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 497 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 498 valid = 0; 499 break; 500 case DWC2_SPEED_PARAM_FULL: 501 case DWC2_SPEED_PARAM_LOW: 502 break; 503 default: 504 valid = 0; 505 break; 506 } 507 508 if (!valid) 509 dwc2_set_param_speed(hsotg); 510 } 511 512 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 513 { 514 int valid = 0; 515 int param = hsotg->params.phy_utmi_width; 516 int width = hsotg->hw_params.utmi_phy_data_width; 517 518 switch (width) { 519 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 520 valid = (param == 8); 521 break; 522 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 523 valid = (param == 16); 524 break; 525 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 526 valid = (param == 8 || param == 16); 527 break; 528 } 529 530 if (!valid) 531 dwc2_set_param_phy_utmi_width(hsotg); 532 } 533 534 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 535 { 536 int param = hsotg->params.power_down; 537 538 switch (param) { 539 case DWC2_POWER_DOWN_PARAM_NONE: 540 break; 541 case DWC2_POWER_DOWN_PARAM_PARTIAL: 542 if (hsotg->hw_params.power_optimized) 543 break; 544 dev_dbg(hsotg->dev, 545 "Partial power down isn't supported by HW\n"); 546 param = DWC2_POWER_DOWN_PARAM_NONE; 547 break; 548 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 549 if (hsotg->hw_params.hibernation) 550 break; 551 dev_dbg(hsotg->dev, 552 "Hibernation isn't supported by HW\n"); 553 param = DWC2_POWER_DOWN_PARAM_NONE; 554 break; 555 default: 556 dev_err(hsotg->dev, 557 "%s: Invalid parameter power_down=%d\n", 558 __func__, param); 559 param = DWC2_POWER_DOWN_PARAM_NONE; 560 break; 561 } 562 563 hsotg->params.power_down = param; 564 } 565 566 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 567 { 568 int fifo_count; 569 int fifo; 570 int min; 571 u32 total = 0; 572 u32 dptxfszn; 573 574 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 575 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 576 577 for (fifo = 1; fifo <= fifo_count; fifo++) 578 total += hsotg->params.g_tx_fifo_size[fifo]; 579 580 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 581 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 582 __func__); 583 dwc2_set_param_tx_fifo_sizes(hsotg); 584 } 585 586 for (fifo = 1; fifo <= fifo_count; fifo++) { 587 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 588 589 if (hsotg->params.g_tx_fifo_size[fifo] < min || 590 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 591 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 592 __func__, fifo, 593 hsotg->params.g_tx_fifo_size[fifo]); 594 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 595 } 596 } 597 } 598 599 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 600 if ((int)(hsotg->params._param) < (_min) || \ 601 (hsotg->params._param) > (_max)) { \ 602 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 603 __func__, #_param, hsotg->params._param); \ 604 hsotg->params._param = (_def); \ 605 } \ 606 } while (0) 607 608 #define CHECK_BOOL(_param, _check) do { \ 609 if (hsotg->params._param && !(_check)) { \ 610 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 611 __func__, #_param, hsotg->params._param); \ 612 hsotg->params._param = false; \ 613 } \ 614 } while (0) 615 616 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 617 { 618 struct dwc2_hw_params *hw = &hsotg->hw_params; 619 struct dwc2_core_params *p = &hsotg->params; 620 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 621 622 dwc2_check_param_otg_cap(hsotg); 623 dwc2_check_param_phy_type(hsotg); 624 dwc2_check_param_speed(hsotg); 625 dwc2_check_param_phy_utmi_width(hsotg); 626 dwc2_check_param_power_down(hsotg); 627 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 628 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 629 CHECK_BOOL(i2c_enable, hw->i2c_enable); 630 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 631 CHECK_BOOL(acg_enable, hw->acg_enable); 632 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 633 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 634 CHECK_BOOL(lpm, hw->lpm_mode); 635 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 636 CHECK_BOOL(besl, hsotg->params.lpm); 637 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 638 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 639 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 640 CHECK_BOOL(service_interval, hw->service_interval_mode); 641 CHECK_RANGE(max_packet_count, 642 15, hw->max_packet_count, 643 hw->max_packet_count); 644 CHECK_RANGE(max_transfer_size, 645 2047, hw->max_transfer_size, 646 hw->max_transfer_size); 647 648 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 649 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 650 CHECK_BOOL(host_dma, dma_capable); 651 CHECK_BOOL(dma_desc_enable, p->host_dma); 652 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 653 CHECK_BOOL(host_ls_low_power_phy_clk, 654 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 655 CHECK_RANGE(host_channels, 656 1, hw->host_channels, 657 hw->host_channels); 658 CHECK_RANGE(host_rx_fifo_size, 659 16, hw->rx_fifo_size, 660 hw->rx_fifo_size); 661 CHECK_RANGE(host_nperio_tx_fifo_size, 662 16, hw->host_nperio_tx_fifo_size, 663 hw->host_nperio_tx_fifo_size); 664 CHECK_RANGE(host_perio_tx_fifo_size, 665 16, hw->host_perio_tx_fifo_size, 666 hw->host_perio_tx_fifo_size); 667 } 668 669 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 670 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 671 CHECK_BOOL(g_dma, dma_capable); 672 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 673 CHECK_RANGE(g_rx_fifo_size, 674 16, hw->rx_fifo_size, 675 hw->rx_fifo_size); 676 CHECK_RANGE(g_np_tx_fifo_size, 677 16, hw->dev_nperio_tx_fifo_size, 678 hw->dev_nperio_tx_fifo_size); 679 dwc2_check_param_tx_fifo_sizes(hsotg); 680 } 681 } 682 683 /* 684 * Gets host hardware parameters. Forces host mode if not currently in 685 * host mode. Should be called immediately after a core soft reset in 686 * order to get the reset values. 687 */ 688 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 689 { 690 struct dwc2_hw_params *hw = &hsotg->hw_params; 691 u32 gnptxfsiz; 692 u32 hptxfsiz; 693 694 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 695 return; 696 697 dwc2_force_mode(hsotg, true); 698 699 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 700 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 701 702 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 703 FIFOSIZE_DEPTH_SHIFT; 704 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 705 FIFOSIZE_DEPTH_SHIFT; 706 } 707 708 /* 709 * Gets device hardware parameters. Forces device mode if not 710 * currently in device mode. Should be called immediately after a core 711 * soft reset in order to get the reset values. 712 */ 713 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 714 { 715 struct dwc2_hw_params *hw = &hsotg->hw_params; 716 u32 gnptxfsiz; 717 int fifo, fifo_count; 718 719 if (hsotg->dr_mode == USB_DR_MODE_HOST) 720 return; 721 722 dwc2_force_mode(hsotg, false); 723 724 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 725 726 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 727 728 for (fifo = 1; fifo <= fifo_count; fifo++) { 729 hw->g_tx_fifo_size[fifo] = 730 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 731 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 732 } 733 734 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 735 FIFOSIZE_DEPTH_SHIFT; 736 } 737 738 /** 739 * During device initialization, read various hardware configuration 740 * registers and interpret the contents. 741 * 742 * @hsotg: Programming view of the DWC_otg controller 743 * 744 */ 745 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 746 { 747 struct dwc2_hw_params *hw = &hsotg->hw_params; 748 unsigned int width; 749 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 750 u32 grxfsiz; 751 752 /* 753 * Attempt to ensure this device is really a DWC_otg Controller. 754 * Read and verify the GSNPSID register contents. The value should be 755 * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx 756 */ 757 758 hw->snpsid = dwc2_readl(hsotg, GSNPSID); 759 if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && 760 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && 761 (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { 762 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 763 hw->snpsid); 764 return -ENODEV; 765 } 766 767 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 768 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 769 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 770 771 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 772 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 773 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 774 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 775 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 776 777 /* hwcfg1 */ 778 hw->dev_ep_dirs = hwcfg1; 779 780 /* hwcfg2 */ 781 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 782 GHWCFG2_OP_MODE_SHIFT; 783 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 784 GHWCFG2_ARCHITECTURE_SHIFT; 785 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 786 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 787 GHWCFG2_NUM_HOST_CHAN_SHIFT); 788 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 789 GHWCFG2_HS_PHY_TYPE_SHIFT; 790 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 791 GHWCFG2_FS_PHY_TYPE_SHIFT; 792 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 793 GHWCFG2_NUM_DEV_EP_SHIFT; 794 hw->nperio_tx_q_depth = 795 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 796 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 797 hw->host_perio_tx_q_depth = 798 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 799 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 800 hw->dev_token_q_depth = 801 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 802 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 803 804 /* hwcfg3 */ 805 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 806 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 807 hw->max_transfer_size = (1 << (width + 11)) - 1; 808 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 809 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 810 hw->max_packet_count = (1 << (width + 4)) - 1; 811 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 812 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 813 GHWCFG3_DFIFO_DEPTH_SHIFT; 814 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 815 816 /* hwcfg4 */ 817 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 818 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 819 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 820 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 821 GHWCFG4_NUM_IN_EPS_SHIFT; 822 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 823 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 824 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 825 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 826 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 827 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 828 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 829 hw->service_interval_mode = !!(hwcfg4 & 830 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 831 832 /* fifo sizes */ 833 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 834 GRXFSIZ_DEPTH_SHIFT; 835 /* 836 * Host specific hardware parameters. Reading these parameters 837 * requires the controller to be in host mode. The mode will 838 * be forced, if necessary, to read these values. 839 */ 840 dwc2_get_host_hwparams(hsotg); 841 dwc2_get_dev_hwparams(hsotg); 842 843 return 0; 844 } 845 846 int dwc2_init_params(struct dwc2_hsotg *hsotg) 847 { 848 const struct of_device_id *match; 849 void (*set_params)(void *data); 850 851 dwc2_set_default_params(hsotg); 852 dwc2_get_device_properties(hsotg); 853 854 match = of_match_device(dwc2_of_match_table, hsotg->dev); 855 if (match && match->data) { 856 set_params = match->data; 857 set_params(hsotg); 858 } 859 860 dwc2_check_params(hsotg); 861 862 return 0; 863 } 864