1 /* 2 * Copyright (C) 2004-2016 Synopsys, Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions, and the following disclaimer, 9 * without modification. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. The names of the above-listed copyright holders may not be used 14 * to endorse or promote products derived from this software without 15 * specific prior written permission. 16 * 17 * ALTERNATIVELY, this software may be distributed under the terms of the 18 * GNU General Public License ("GPL") as published by the Free Software 19 * Foundation; either version 2 of the License, or (at your option) any 20 * later version. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 23 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 30 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <linux/kernel.h> 36 #include <linux/module.h> 37 #include <linux/of_device.h> 38 39 #include "core.h" 40 41 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 42 { 43 struct dwc2_core_params *p = &hsotg->params; 44 45 p->host_rx_fifo_size = 774; 46 p->max_transfer_size = 65535; 47 p->max_packet_count = 511; 48 p->ahbcfg = 0x10; 49 p->uframe_sched = false; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->uframe_sched = false; 71 p->change_speed_quirk = true; 72 } 73 74 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 79 p->host_rx_fifo_size = 525; 80 p->host_nperio_tx_fifo_size = 128; 81 p->host_perio_tx_fifo_size = 256; 82 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 83 GAHBCFG_HBSTLEN_SHIFT; 84 } 85 86 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 87 { 88 struct dwc2_core_params *p = &hsotg->params; 89 90 p->otg_cap = 2; 91 p->host_rx_fifo_size = 288; 92 p->host_nperio_tx_fifo_size = 128; 93 p->host_perio_tx_fifo_size = 96; 94 p->max_transfer_size = 65535; 95 p->max_packet_count = 511; 96 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 97 GAHBCFG_HBSTLEN_SHIFT; 98 } 99 100 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 105 p->speed = DWC2_SPEED_PARAM_HIGH; 106 p->host_rx_fifo_size = 512; 107 p->host_nperio_tx_fifo_size = 500; 108 p->host_perio_tx_fifo_size = 500; 109 p->host_channels = 16; 110 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 111 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 112 GAHBCFG_HBSTLEN_SHIFT; 113 p->uframe_sched = false; 114 } 115 116 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 117 { 118 struct dwc2_core_params *p = &hsotg->params; 119 120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 121 } 122 123 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 124 { 125 struct dwc2_core_params *p = &hsotg->params; 126 127 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 128 p->speed = DWC2_SPEED_PARAM_FULL; 129 p->host_rx_fifo_size = 128; 130 p->host_nperio_tx_fifo_size = 96; 131 p->host_perio_tx_fifo_size = 96; 132 p->max_packet_count = 256; 133 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 134 p->i2c_enable = false; 135 p->uframe_sched = false; 136 p->activate_stm_fs_transceiver = true; 137 } 138 139 const struct of_device_id dwc2_of_match_table[] = { 140 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 141 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 142 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 143 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 144 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 145 { .compatible = "snps,dwc2" }, 146 { .compatible = "samsung,s3c6400-hsotg" }, 147 { .compatible = "amlogic,meson8-usb", 148 .data = dwc2_set_amlogic_params }, 149 { .compatible = "amlogic,meson8b-usb", 150 .data = dwc2_set_amlogic_params }, 151 { .compatible = "amlogic,meson-gxbb-usb", 152 .data = dwc2_set_amlogic_params }, 153 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 154 { .compatible = "st,stm32f4x9-fsotg", 155 .data = dwc2_set_stm32f4x9_fsotg_params }, 156 { .compatible = "st,stm32f4x9-hsotg" }, 157 {}, 158 }; 159 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 160 161 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 162 { 163 u8 val; 164 165 switch (hsotg->hw_params.op_mode) { 166 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 167 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 168 break; 169 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 170 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 171 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 172 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 173 break; 174 default: 175 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 176 break; 177 } 178 179 hsotg->params.otg_cap = val; 180 } 181 182 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 183 { 184 int val; 185 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 186 187 val = DWC2_PHY_TYPE_PARAM_FS; 188 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 189 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 190 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 191 val = DWC2_PHY_TYPE_PARAM_UTMI; 192 else 193 val = DWC2_PHY_TYPE_PARAM_ULPI; 194 } 195 196 if (dwc2_is_fs_iot(hsotg)) 197 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 198 199 hsotg->params.phy_type = val; 200 } 201 202 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 203 { 204 int val; 205 206 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 207 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 208 209 if (dwc2_is_fs_iot(hsotg)) 210 val = DWC2_SPEED_PARAM_FULL; 211 212 if (dwc2_is_hs_iot(hsotg)) 213 val = DWC2_SPEED_PARAM_HIGH; 214 215 hsotg->params.speed = val; 216 } 217 218 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 219 { 220 int val; 221 222 val = (hsotg->hw_params.utmi_phy_data_width == 223 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 224 225 hsotg->params.phy_utmi_width = val; 226 } 227 228 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 229 { 230 struct dwc2_core_params *p = &hsotg->params; 231 int depth_average; 232 int fifo_count; 233 int i; 234 235 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 236 237 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 238 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 239 for (i = 1; i <= fifo_count; i++) 240 p->g_tx_fifo_size[i] = depth_average; 241 } 242 243 /** 244 * dwc2_set_default_params() - Set all core parameters to their 245 * auto-detected default values. 246 */ 247 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 248 { 249 struct dwc2_hw_params *hw = &hsotg->hw_params; 250 struct dwc2_core_params *p = &hsotg->params; 251 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 252 253 dwc2_set_param_otg_cap(hsotg); 254 dwc2_set_param_phy_type(hsotg); 255 dwc2_set_param_speed(hsotg); 256 dwc2_set_param_phy_utmi_width(hsotg); 257 p->phy_ulpi_ddr = false; 258 p->phy_ulpi_ext_vbus = false; 259 260 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 261 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 262 p->i2c_enable = hw->i2c_enable; 263 p->ulpi_fs_ls = false; 264 p->ts_dline = false; 265 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 266 p->uframe_sched = true; 267 p->external_id_pin_ctl = false; 268 p->hibernation = false; 269 p->max_packet_count = hw->max_packet_count; 270 p->max_transfer_size = hw->max_transfer_size; 271 p->ahbcfg = GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT; 272 273 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 274 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 275 p->host_dma = dma_capable; 276 p->dma_desc_enable = false; 277 p->dma_desc_fs_enable = false; 278 p->host_support_fs_ls_low_power = false; 279 p->host_ls_low_power_phy_clk = false; 280 p->host_channels = hw->host_channels; 281 p->host_rx_fifo_size = hw->rx_fifo_size; 282 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 283 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 284 } 285 286 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 287 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 288 p->g_dma = dma_capable; 289 p->g_dma_desc = hw->dma_desc_enable; 290 291 /* 292 * The values for g_rx_fifo_size (2048) and 293 * g_np_tx_fifo_size (1024) come from the legacy s3c 294 * gadget driver. These defaults have been hard-coded 295 * for some time so many platforms depend on these 296 * values. Leave them as defaults for now and only 297 * auto-detect if the hardware does not support the 298 * default. 299 */ 300 p->g_rx_fifo_size = 2048; 301 p->g_np_tx_fifo_size = 1024; 302 dwc2_set_param_tx_fifo_sizes(hsotg); 303 } 304 } 305 306 /** 307 * dwc2_get_device_properties() - Read in device properties. 308 * 309 * Read in the device properties and adjust core parameters if needed. 310 */ 311 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 312 { 313 struct dwc2_core_params *p = &hsotg->params; 314 int num; 315 316 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 317 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 318 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 319 &p->g_rx_fifo_size); 320 321 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 322 &p->g_np_tx_fifo_size); 323 324 num = device_property_read_u32_array(hsotg->dev, 325 "g-tx-fifo-size", 326 NULL, 0); 327 328 if (num > 0) { 329 num = min(num, 15); 330 memset(p->g_tx_fifo_size, 0, 331 sizeof(p->g_tx_fifo_size)); 332 device_property_read_u32_array(hsotg->dev, 333 "g-tx-fifo-size", 334 &p->g_tx_fifo_size[1], 335 num); 336 } 337 } 338 } 339 340 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 341 { 342 int valid = 1; 343 344 switch (hsotg->params.otg_cap) { 345 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 346 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 347 valid = 0; 348 break; 349 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 350 switch (hsotg->hw_params.op_mode) { 351 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 352 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 353 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 354 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 355 break; 356 default: 357 valid = 0; 358 break; 359 } 360 break; 361 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 362 /* always valid */ 363 break; 364 default: 365 valid = 0; 366 break; 367 } 368 369 if (!valid) 370 dwc2_set_param_otg_cap(hsotg); 371 } 372 373 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 374 { 375 int valid = 0; 376 u32 hs_phy_type; 377 u32 fs_phy_type; 378 379 hs_phy_type = hsotg->hw_params.hs_phy_type; 380 fs_phy_type = hsotg->hw_params.fs_phy_type; 381 382 switch (hsotg->params.phy_type) { 383 case DWC2_PHY_TYPE_PARAM_FS: 384 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 385 valid = 1; 386 break; 387 case DWC2_PHY_TYPE_PARAM_UTMI: 388 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 389 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 390 valid = 1; 391 break; 392 case DWC2_PHY_TYPE_PARAM_ULPI: 393 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 394 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 395 valid = 1; 396 break; 397 default: 398 break; 399 } 400 401 if (!valid) 402 dwc2_set_param_phy_type(hsotg); 403 } 404 405 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 406 { 407 int valid = 1; 408 int phy_type = hsotg->params.phy_type; 409 int speed = hsotg->params.speed; 410 411 switch (speed) { 412 case DWC2_SPEED_PARAM_HIGH: 413 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 414 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 415 valid = 0; 416 break; 417 case DWC2_SPEED_PARAM_FULL: 418 case DWC2_SPEED_PARAM_LOW: 419 break; 420 default: 421 valid = 0; 422 break; 423 } 424 425 if (!valid) 426 dwc2_set_param_speed(hsotg); 427 } 428 429 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 430 { 431 int valid = 0; 432 int param = hsotg->params.phy_utmi_width; 433 int width = hsotg->hw_params.utmi_phy_data_width; 434 435 switch (width) { 436 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 437 valid = (param == 8); 438 break; 439 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 440 valid = (param == 16); 441 break; 442 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 443 valid = (param == 8 || param == 16); 444 break; 445 } 446 447 if (!valid) 448 dwc2_set_param_phy_utmi_width(hsotg); 449 } 450 451 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 452 { 453 int fifo_count; 454 int fifo; 455 int min; 456 u32 total = 0; 457 u32 dptxfszn; 458 459 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 460 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 461 462 for (fifo = 1; fifo <= fifo_count; fifo++) 463 total += hsotg->params.g_tx_fifo_size[fifo]; 464 465 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 466 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 467 __func__); 468 dwc2_set_param_tx_fifo_sizes(hsotg); 469 } 470 471 for (fifo = 1; fifo <= fifo_count; fifo++) { 472 dptxfszn = (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & 473 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 474 475 if (hsotg->params.g_tx_fifo_size[fifo] < min || 476 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 477 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 478 __func__, fifo, 479 hsotg->params.g_tx_fifo_size[fifo]); 480 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 481 } 482 } 483 } 484 485 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 486 if ((hsotg->params._param) < (_min) || \ 487 (hsotg->params._param) > (_max)) { \ 488 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 489 __func__, #_param, hsotg->params._param); \ 490 hsotg->params._param = (_def); \ 491 } \ 492 } while (0) 493 494 #define CHECK_BOOL(_param, _check) do { \ 495 if (hsotg->params._param && !(_check)) { \ 496 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 497 __func__, #_param, hsotg->params._param); \ 498 hsotg->params._param = false; \ 499 } \ 500 } while (0) 501 502 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 503 { 504 struct dwc2_hw_params *hw = &hsotg->hw_params; 505 struct dwc2_core_params *p = &hsotg->params; 506 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 507 508 dwc2_check_param_otg_cap(hsotg); 509 dwc2_check_param_phy_type(hsotg); 510 dwc2_check_param_speed(hsotg); 511 dwc2_check_param_phy_utmi_width(hsotg); 512 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 513 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 514 CHECK_BOOL(i2c_enable, hw->i2c_enable); 515 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 516 CHECK_RANGE(max_packet_count, 517 15, hw->max_packet_count, 518 hw->max_packet_count); 519 CHECK_RANGE(max_transfer_size, 520 2047, hw->max_transfer_size, 521 hw->max_transfer_size); 522 523 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 524 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 525 CHECK_BOOL(host_dma, dma_capable); 526 CHECK_BOOL(dma_desc_enable, p->host_dma); 527 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 528 CHECK_BOOL(host_ls_low_power_phy_clk, 529 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 530 CHECK_RANGE(host_channels, 531 1, hw->host_channels, 532 hw->host_channels); 533 CHECK_RANGE(host_rx_fifo_size, 534 16, hw->rx_fifo_size, 535 hw->rx_fifo_size); 536 CHECK_RANGE(host_nperio_tx_fifo_size, 537 16, hw->host_nperio_tx_fifo_size, 538 hw->host_nperio_tx_fifo_size); 539 CHECK_RANGE(host_perio_tx_fifo_size, 540 16, hw->host_perio_tx_fifo_size, 541 hw->host_perio_tx_fifo_size); 542 } 543 544 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 545 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 546 CHECK_BOOL(g_dma, dma_capable); 547 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 548 CHECK_RANGE(g_rx_fifo_size, 549 16, hw->rx_fifo_size, 550 hw->rx_fifo_size); 551 CHECK_RANGE(g_np_tx_fifo_size, 552 16, hw->dev_nperio_tx_fifo_size, 553 hw->dev_nperio_tx_fifo_size); 554 dwc2_check_param_tx_fifo_sizes(hsotg); 555 } 556 } 557 558 /* 559 * Gets host hardware parameters. Forces host mode if not currently in 560 * host mode. Should be called immediately after a core soft reset in 561 * order to get the reset values. 562 */ 563 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 564 { 565 struct dwc2_hw_params *hw = &hsotg->hw_params; 566 u32 gnptxfsiz; 567 u32 hptxfsiz; 568 bool forced; 569 570 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 571 return; 572 573 forced = dwc2_force_mode_if_needed(hsotg, true); 574 575 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 576 hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); 577 578 if (forced) 579 dwc2_clear_force_mode(hsotg); 580 581 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 582 FIFOSIZE_DEPTH_SHIFT; 583 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 584 FIFOSIZE_DEPTH_SHIFT; 585 } 586 587 /* 588 * Gets device hardware parameters. Forces device mode if not 589 * currently in device mode. Should be called immediately after a core 590 * soft reset in order to get the reset values. 591 */ 592 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 593 { 594 struct dwc2_hw_params *hw = &hsotg->hw_params; 595 bool forced; 596 u32 gnptxfsiz; 597 598 if (hsotg->dr_mode == USB_DR_MODE_HOST) 599 return; 600 601 forced = dwc2_force_mode_if_needed(hsotg, false); 602 603 gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); 604 605 if (forced) 606 dwc2_clear_force_mode(hsotg); 607 608 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 609 FIFOSIZE_DEPTH_SHIFT; 610 } 611 612 /** 613 * During device initialization, read various hardware configuration 614 * registers and interpret the contents. 615 */ 616 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 617 { 618 struct dwc2_hw_params *hw = &hsotg->hw_params; 619 unsigned int width; 620 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 621 u32 grxfsiz; 622 623 /* 624 * Attempt to ensure this device is really a DWC_otg Controller. 625 * Read and verify the GSNPSID register contents. The value should be 626 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", 627 * as in "OTG version 2.xx" or "OTG version 3.xx". 628 */ 629 hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); 630 if ((hw->snpsid & 0xfffff000) != 0x4f542000 && 631 (hw->snpsid & 0xfffff000) != 0x4f543000 && 632 (hw->snpsid & 0xffff0000) != 0x55310000 && 633 (hw->snpsid & 0xffff0000) != 0x55320000) { 634 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", 635 hw->snpsid); 636 return -ENODEV; 637 } 638 639 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n", 640 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, 641 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); 642 643 hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); 644 hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); 645 hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); 646 hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); 647 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 648 649 /* 650 * Host specific hardware parameters. Reading these parameters 651 * requires the controller to be in host mode. The mode will 652 * be forced, if necessary, to read these values. 653 */ 654 dwc2_get_host_hwparams(hsotg); 655 dwc2_get_dev_hwparams(hsotg); 656 657 /* hwcfg1 */ 658 hw->dev_ep_dirs = hwcfg1; 659 660 /* hwcfg2 */ 661 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 662 GHWCFG2_OP_MODE_SHIFT; 663 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 664 GHWCFG2_ARCHITECTURE_SHIFT; 665 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 666 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 667 GHWCFG2_NUM_HOST_CHAN_SHIFT); 668 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 669 GHWCFG2_HS_PHY_TYPE_SHIFT; 670 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 671 GHWCFG2_FS_PHY_TYPE_SHIFT; 672 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 673 GHWCFG2_NUM_DEV_EP_SHIFT; 674 hw->nperio_tx_q_depth = 675 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 676 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 677 hw->host_perio_tx_q_depth = 678 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 679 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 680 hw->dev_token_q_depth = 681 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 682 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 683 684 /* hwcfg3 */ 685 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 686 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 687 hw->max_transfer_size = (1 << (width + 11)) - 1; 688 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 689 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 690 hw->max_packet_count = (1 << (width + 4)) - 1; 691 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 692 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 693 GHWCFG3_DFIFO_DEPTH_SHIFT; 694 695 /* hwcfg4 */ 696 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 697 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 698 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 699 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 700 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 701 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 702 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 703 704 /* fifo sizes */ 705 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 706 GRXFSIZ_DEPTH_SHIFT; 707 708 return 0; 709 } 710 711 int dwc2_init_params(struct dwc2_hsotg *hsotg) 712 { 713 const struct of_device_id *match; 714 void (*set_params)(void *data); 715 716 dwc2_set_default_params(hsotg); 717 dwc2_get_device_properties(hsotg); 718 719 match = of_match_device(dwc2_of_match_table, hsotg->dev); 720 if (match && match->data) { 721 set_params = match->data; 722 set_params(hsotg); 723 } 724 725 dwc2_check_params(hsotg); 726 727 return 0; 728 } 729