1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 #include <linux/usb/of.h> 40 41 #include "core.h" 42 43 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 44 { 45 struct dwc2_core_params *p = &hsotg->params; 46 47 p->host_rx_fifo_size = 774; 48 p->max_transfer_size = 65535; 49 p->max_packet_count = 511; 50 p->ahbcfg = 0x10; 51 } 52 53 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 54 { 55 struct dwc2_core_params *p = &hsotg->params; 56 57 p->otg_caps.hnp_support = false; 58 p->otg_caps.srp_support = false; 59 p->speed = DWC2_SPEED_PARAM_HIGH; 60 p->host_rx_fifo_size = 512; 61 p->host_nperio_tx_fifo_size = 512; 62 p->host_perio_tx_fifo_size = 512; 63 p->max_transfer_size = 65535; 64 p->max_packet_count = 511; 65 p->host_channels = 16; 66 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 67 p->phy_utmi_width = 8; 68 p->i2c_enable = false; 69 p->reload_ctl = false; 70 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 71 GAHBCFG_HBSTLEN_SHIFT; 72 p->change_speed_quirk = true; 73 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 74 } 75 76 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 77 { 78 struct dwc2_core_params *p = &hsotg->params; 79 80 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 81 p->no_clock_gating = true; 82 p->phy_utmi_width = 8; 83 } 84 85 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 86 { 87 struct dwc2_core_params *p = &hsotg->params; 88 89 p->otg_caps.hnp_support = false; 90 p->otg_caps.srp_support = false; 91 p->host_rx_fifo_size = 525; 92 p->host_nperio_tx_fifo_size = 128; 93 p->host_perio_tx_fifo_size = 256; 94 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 95 GAHBCFG_HBSTLEN_SHIFT; 96 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 97 } 98 99 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 100 { 101 struct dwc2_core_params *p = &hsotg->params; 102 103 p->otg_caps.hnp_support = false; 104 p->otg_caps.srp_support = false; 105 p->host_rx_fifo_size = 288; 106 p->host_nperio_tx_fifo_size = 128; 107 p->host_perio_tx_fifo_size = 96; 108 p->max_transfer_size = 65535; 109 p->max_packet_count = 511; 110 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 111 GAHBCFG_HBSTLEN_SHIFT; 112 } 113 114 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 115 { 116 struct dwc2_core_params *p = &hsotg->params; 117 118 p->otg_caps.hnp_support = false; 119 p->otg_caps.srp_support = false; 120 p->speed = DWC2_SPEED_PARAM_HIGH; 121 p->host_rx_fifo_size = 512; 122 p->host_nperio_tx_fifo_size = 500; 123 p->host_perio_tx_fifo_size = 500; 124 p->host_channels = 16; 125 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 127 GAHBCFG_HBSTLEN_SHIFT; 128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 129 } 130 131 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 132 { 133 struct dwc2_core_params *p = &hsotg->params; 134 135 p->lpm = false; 136 p->lpm_clock_gating = false; 137 p->besl = false; 138 p->hird_threshold_en = false; 139 } 140 141 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 142 { 143 struct dwc2_core_params *p = &hsotg->params; 144 145 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 146 } 147 148 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 149 { 150 struct dwc2_core_params *p = &hsotg->params; 151 152 p->otg_caps.hnp_support = false; 153 p->otg_caps.srp_support = false; 154 p->speed = DWC2_SPEED_PARAM_FULL; 155 p->host_rx_fifo_size = 128; 156 p->host_nperio_tx_fifo_size = 96; 157 p->host_perio_tx_fifo_size = 96; 158 p->max_packet_count = 256; 159 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 160 p->i2c_enable = false; 161 p->activate_stm_fs_transceiver = true; 162 } 163 164 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 165 { 166 struct dwc2_core_params *p = &hsotg->params; 167 168 p->host_rx_fifo_size = 622; 169 p->host_nperio_tx_fifo_size = 128; 170 p->host_perio_tx_fifo_size = 256; 171 } 172 173 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 174 { 175 struct dwc2_core_params *p = &hsotg->params; 176 177 p->otg_caps.hnp_support = false; 178 p->otg_caps.srp_support = false; 179 p->otg_caps.otg_rev = 0x200; 180 p->speed = DWC2_SPEED_PARAM_FULL; 181 p->host_rx_fifo_size = 128; 182 p->host_nperio_tx_fifo_size = 96; 183 p->host_perio_tx_fifo_size = 96; 184 p->max_packet_count = 256; 185 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 186 p->i2c_enable = false; 187 p->activate_stm_fs_transceiver = true; 188 p->activate_stm_id_vb_detection = true; 189 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 190 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 191 p->host_support_fs_ls_low_power = true; 192 p->host_ls_low_power_phy_clk = true; 193 } 194 195 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 196 { 197 struct dwc2_core_params *p = &hsotg->params; 198 199 p->otg_caps.hnp_support = false; 200 p->otg_caps.srp_support = false; 201 p->otg_caps.otg_rev = 0x200; 202 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 203 p->host_rx_fifo_size = 440; 204 p->host_nperio_tx_fifo_size = 256; 205 p->host_perio_tx_fifo_size = 256; 206 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 207 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 208 p->lpm = false; 209 p->lpm_clock_gating = false; 210 p->besl = false; 211 p->hird_threshold_en = false; 212 } 213 214 const struct of_device_id dwc2_of_match_table[] = { 215 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 216 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 217 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 218 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 219 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 220 { .compatible = "snps,dwc2" }, 221 { .compatible = "samsung,s3c6400-hsotg", 222 .data = dwc2_set_s3c6400_params }, 223 { .compatible = "amlogic,meson8-usb", 224 .data = dwc2_set_amlogic_params }, 225 { .compatible = "amlogic,meson8b-usb", 226 .data = dwc2_set_amlogic_params }, 227 { .compatible = "amlogic,meson-gxbb-usb", 228 .data = dwc2_set_amlogic_params }, 229 { .compatible = "amlogic,meson-g12a-usb", 230 .data = dwc2_set_amlogic_g12a_params }, 231 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 232 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 233 { .compatible = "st,stm32f4x9-fsotg", 234 .data = dwc2_set_stm32f4x9_fsotg_params }, 235 { .compatible = "st,stm32f4x9-hsotg" }, 236 { .compatible = "st,stm32f7-hsotg", 237 .data = dwc2_set_stm32f7_hsotg_params }, 238 { .compatible = "st,stm32mp15-fsotg", 239 .data = dwc2_set_stm32mp15_fsotg_params }, 240 { .compatible = "st,stm32mp15-hsotg", 241 .data = dwc2_set_stm32mp15_hsotg_params }, 242 {}, 243 }; 244 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 245 246 const struct acpi_device_id dwc2_acpi_match[] = { 247 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 248 { }, 249 }; 250 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 251 252 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 253 { 254 switch (hsotg->hw_params.op_mode) { 255 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 256 hsotg->params.otg_caps.hnp_support = true; 257 hsotg->params.otg_caps.srp_support = true; 258 break; 259 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 260 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 261 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 262 hsotg->params.otg_caps.hnp_support = false; 263 hsotg->params.otg_caps.srp_support = true; 264 break; 265 default: 266 hsotg->params.otg_caps.hnp_support = false; 267 hsotg->params.otg_caps.srp_support = false; 268 break; 269 } 270 } 271 272 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 273 { 274 int val; 275 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 276 277 val = DWC2_PHY_TYPE_PARAM_FS; 278 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 279 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 280 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 281 val = DWC2_PHY_TYPE_PARAM_UTMI; 282 else 283 val = DWC2_PHY_TYPE_PARAM_ULPI; 284 } 285 286 if (dwc2_is_fs_iot(hsotg)) 287 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 288 289 hsotg->params.phy_type = val; 290 } 291 292 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 293 { 294 int val; 295 296 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 297 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 298 299 if (dwc2_is_fs_iot(hsotg)) 300 val = DWC2_SPEED_PARAM_FULL; 301 302 if (dwc2_is_hs_iot(hsotg)) 303 val = DWC2_SPEED_PARAM_HIGH; 304 305 hsotg->params.speed = val; 306 } 307 308 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 309 { 310 int val; 311 312 val = (hsotg->hw_params.utmi_phy_data_width == 313 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 314 315 if (hsotg->phy) { 316 /* 317 * If using the generic PHY framework, check if the PHY bus 318 * width is 8-bit and set the phyif appropriately. 319 */ 320 if (phy_get_bus_width(hsotg->phy) == 8) 321 val = 8; 322 } 323 324 hsotg->params.phy_utmi_width = val; 325 } 326 327 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 328 { 329 struct dwc2_core_params *p = &hsotg->params; 330 int depth_average; 331 int fifo_count; 332 int i; 333 334 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 335 336 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 337 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 338 for (i = 1; i <= fifo_count; i++) 339 p->g_tx_fifo_size[i] = depth_average; 340 } 341 342 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 343 { 344 int val; 345 346 if (hsotg->hw_params.hibernation) 347 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 348 else if (hsotg->hw_params.power_optimized) 349 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 350 else 351 val = DWC2_POWER_DOWN_PARAM_NONE; 352 353 hsotg->params.power_down = val; 354 } 355 356 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 357 { 358 struct dwc2_core_params *p = &hsotg->params; 359 360 p->lpm = hsotg->hw_params.lpm_mode; 361 if (p->lpm) { 362 p->lpm_clock_gating = true; 363 p->besl = true; 364 p->hird_threshold_en = true; 365 p->hird_threshold = 4; 366 } else { 367 p->lpm_clock_gating = false; 368 p->besl = false; 369 p->hird_threshold_en = false; 370 } 371 } 372 373 /** 374 * dwc2_set_default_params() - Set all core parameters to their 375 * auto-detected default values. 376 * 377 * @hsotg: Programming view of the DWC_otg controller 378 * 379 */ 380 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 381 { 382 struct dwc2_hw_params *hw = &hsotg->hw_params; 383 struct dwc2_core_params *p = &hsotg->params; 384 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 385 386 dwc2_set_param_otg_cap(hsotg); 387 dwc2_set_param_phy_type(hsotg); 388 dwc2_set_param_speed(hsotg); 389 dwc2_set_param_phy_utmi_width(hsotg); 390 dwc2_set_param_power_down(hsotg); 391 dwc2_set_param_lpm(hsotg); 392 p->phy_ulpi_ddr = false; 393 p->phy_ulpi_ext_vbus = false; 394 395 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 396 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 397 p->i2c_enable = hw->i2c_enable; 398 p->acg_enable = hw->acg_enable; 399 p->ulpi_fs_ls = false; 400 p->ts_dline = false; 401 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 402 p->uframe_sched = true; 403 p->external_id_pin_ctl = false; 404 p->ipg_isoc_en = false; 405 p->service_interval = false; 406 p->max_packet_count = hw->max_packet_count; 407 p->max_transfer_size = hw->max_transfer_size; 408 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 409 p->ref_clk_per = 33333; 410 p->sof_cnt_wkup_alert = 100; 411 412 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 413 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 414 p->host_dma = dma_capable; 415 p->dma_desc_enable = false; 416 p->dma_desc_fs_enable = false; 417 p->host_support_fs_ls_low_power = false; 418 p->host_ls_low_power_phy_clk = false; 419 p->host_channels = hw->host_channels; 420 p->host_rx_fifo_size = hw->rx_fifo_size; 421 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 422 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 423 } 424 425 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 426 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 427 p->g_dma = dma_capable; 428 p->g_dma_desc = hw->dma_desc_enable; 429 430 /* 431 * The values for g_rx_fifo_size (2048) and 432 * g_np_tx_fifo_size (1024) come from the legacy s3c 433 * gadget driver. These defaults have been hard-coded 434 * for some time so many platforms depend on these 435 * values. Leave them as defaults for now and only 436 * auto-detect if the hardware does not support the 437 * default. 438 */ 439 p->g_rx_fifo_size = 2048; 440 p->g_np_tx_fifo_size = 1024; 441 dwc2_set_param_tx_fifo_sizes(hsotg); 442 } 443 } 444 445 /** 446 * dwc2_get_device_properties() - Read in device properties. 447 * 448 * @hsotg: Programming view of the DWC_otg controller 449 * 450 * Read in the device properties and adjust core parameters if needed. 451 */ 452 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 453 { 454 struct dwc2_core_params *p = &hsotg->params; 455 int num; 456 457 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 458 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 459 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 460 &p->g_rx_fifo_size); 461 462 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 463 &p->g_np_tx_fifo_size); 464 465 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 466 if (num > 0) { 467 num = min(num, 15); 468 memset(p->g_tx_fifo_size, 0, 469 sizeof(p->g_tx_fifo_size)); 470 device_property_read_u32_array(hsotg->dev, 471 "g-tx-fifo-size", 472 &p->g_tx_fifo_size[1], 473 num); 474 } 475 476 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 477 } 478 479 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 480 p->oc_disable = true; 481 } 482 483 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 484 { 485 int valid = 1; 486 487 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 488 /* check HNP && SRP capable */ 489 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 490 valid = 0; 491 } else if (!hsotg->params.otg_caps.hnp_support) { 492 /* check SRP only capable */ 493 if (hsotg->params.otg_caps.srp_support) { 494 switch (hsotg->hw_params.op_mode) { 495 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 496 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 497 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 498 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 499 break; 500 default: 501 valid = 0; 502 break; 503 } 504 } 505 /* else: NO HNP && NO SRP capable: always valid */ 506 } else { 507 valid = 0; 508 } 509 510 if (!valid) 511 dwc2_set_param_otg_cap(hsotg); 512 } 513 514 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 515 { 516 int valid = 0; 517 u32 hs_phy_type; 518 u32 fs_phy_type; 519 520 hs_phy_type = hsotg->hw_params.hs_phy_type; 521 fs_phy_type = hsotg->hw_params.fs_phy_type; 522 523 switch (hsotg->params.phy_type) { 524 case DWC2_PHY_TYPE_PARAM_FS: 525 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 526 valid = 1; 527 break; 528 case DWC2_PHY_TYPE_PARAM_UTMI: 529 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 530 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 531 valid = 1; 532 break; 533 case DWC2_PHY_TYPE_PARAM_ULPI: 534 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 535 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 536 valid = 1; 537 break; 538 default: 539 break; 540 } 541 542 if (!valid) 543 dwc2_set_param_phy_type(hsotg); 544 } 545 546 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 547 { 548 int valid = 1; 549 int phy_type = hsotg->params.phy_type; 550 int speed = hsotg->params.speed; 551 552 switch (speed) { 553 case DWC2_SPEED_PARAM_HIGH: 554 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 555 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 556 valid = 0; 557 break; 558 case DWC2_SPEED_PARAM_FULL: 559 case DWC2_SPEED_PARAM_LOW: 560 break; 561 default: 562 valid = 0; 563 break; 564 } 565 566 if (!valid) 567 dwc2_set_param_speed(hsotg); 568 } 569 570 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 571 { 572 int valid = 0; 573 int param = hsotg->params.phy_utmi_width; 574 int width = hsotg->hw_params.utmi_phy_data_width; 575 576 switch (width) { 577 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 578 valid = (param == 8); 579 break; 580 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 581 valid = (param == 16); 582 break; 583 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 584 valid = (param == 8 || param == 16); 585 break; 586 } 587 588 if (!valid) 589 dwc2_set_param_phy_utmi_width(hsotg); 590 } 591 592 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 593 { 594 int param = hsotg->params.power_down; 595 596 switch (param) { 597 case DWC2_POWER_DOWN_PARAM_NONE: 598 break; 599 case DWC2_POWER_DOWN_PARAM_PARTIAL: 600 if (hsotg->hw_params.power_optimized) 601 break; 602 dev_dbg(hsotg->dev, 603 "Partial power down isn't supported by HW\n"); 604 param = DWC2_POWER_DOWN_PARAM_NONE; 605 break; 606 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 607 if (hsotg->hw_params.hibernation) 608 break; 609 dev_dbg(hsotg->dev, 610 "Hibernation isn't supported by HW\n"); 611 param = DWC2_POWER_DOWN_PARAM_NONE; 612 break; 613 default: 614 dev_err(hsotg->dev, 615 "%s: Invalid parameter power_down=%d\n", 616 __func__, param); 617 param = DWC2_POWER_DOWN_PARAM_NONE; 618 break; 619 } 620 621 hsotg->params.power_down = param; 622 } 623 624 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 625 { 626 int fifo_count; 627 int fifo; 628 int min; 629 u32 total = 0; 630 u32 dptxfszn; 631 632 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 633 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 634 635 for (fifo = 1; fifo <= fifo_count; fifo++) 636 total += hsotg->params.g_tx_fifo_size[fifo]; 637 638 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 639 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 640 __func__); 641 dwc2_set_param_tx_fifo_sizes(hsotg); 642 } 643 644 for (fifo = 1; fifo <= fifo_count; fifo++) { 645 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 646 647 if (hsotg->params.g_tx_fifo_size[fifo] < min || 648 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 649 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 650 __func__, fifo, 651 hsotg->params.g_tx_fifo_size[fifo]); 652 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 653 } 654 } 655 } 656 657 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 658 if ((int)(hsotg->params._param) < (_min) || \ 659 (hsotg->params._param) > (_max)) { \ 660 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 661 __func__, #_param, hsotg->params._param); \ 662 hsotg->params._param = (_def); \ 663 } \ 664 } while (0) 665 666 #define CHECK_BOOL(_param, _check) do { \ 667 if (hsotg->params._param && !(_check)) { \ 668 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 669 __func__, #_param, hsotg->params._param); \ 670 hsotg->params._param = false; \ 671 } \ 672 } while (0) 673 674 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 675 { 676 struct dwc2_hw_params *hw = &hsotg->hw_params; 677 struct dwc2_core_params *p = &hsotg->params; 678 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 679 680 dwc2_check_param_otg_cap(hsotg); 681 dwc2_check_param_phy_type(hsotg); 682 dwc2_check_param_speed(hsotg); 683 dwc2_check_param_phy_utmi_width(hsotg); 684 dwc2_check_param_power_down(hsotg); 685 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 686 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 687 CHECK_BOOL(i2c_enable, hw->i2c_enable); 688 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 689 CHECK_BOOL(acg_enable, hw->acg_enable); 690 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 691 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 692 CHECK_BOOL(lpm, hw->lpm_mode); 693 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 694 CHECK_BOOL(besl, hsotg->params.lpm); 695 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 696 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 697 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 698 CHECK_BOOL(service_interval, hw->service_interval_mode); 699 CHECK_RANGE(max_packet_count, 700 15, hw->max_packet_count, 701 hw->max_packet_count); 702 CHECK_RANGE(max_transfer_size, 703 2047, hw->max_transfer_size, 704 hw->max_transfer_size); 705 706 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 707 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 708 CHECK_BOOL(host_dma, dma_capable); 709 CHECK_BOOL(dma_desc_enable, p->host_dma); 710 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 711 CHECK_BOOL(host_ls_low_power_phy_clk, 712 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 713 CHECK_RANGE(host_channels, 714 1, hw->host_channels, 715 hw->host_channels); 716 CHECK_RANGE(host_rx_fifo_size, 717 16, hw->rx_fifo_size, 718 hw->rx_fifo_size); 719 CHECK_RANGE(host_nperio_tx_fifo_size, 720 16, hw->host_nperio_tx_fifo_size, 721 hw->host_nperio_tx_fifo_size); 722 CHECK_RANGE(host_perio_tx_fifo_size, 723 16, hw->host_perio_tx_fifo_size, 724 hw->host_perio_tx_fifo_size); 725 } 726 727 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 728 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 729 CHECK_BOOL(g_dma, dma_capable); 730 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 731 CHECK_RANGE(g_rx_fifo_size, 732 16, hw->rx_fifo_size, 733 hw->rx_fifo_size); 734 CHECK_RANGE(g_np_tx_fifo_size, 735 16, hw->dev_nperio_tx_fifo_size, 736 hw->dev_nperio_tx_fifo_size); 737 dwc2_check_param_tx_fifo_sizes(hsotg); 738 } 739 } 740 741 /* 742 * Gets host hardware parameters. Forces host mode if not currently in 743 * host mode. Should be called immediately after a core soft reset in 744 * order to get the reset values. 745 */ 746 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 747 { 748 struct dwc2_hw_params *hw = &hsotg->hw_params; 749 u32 gnptxfsiz; 750 u32 hptxfsiz; 751 752 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 753 return; 754 755 dwc2_force_mode(hsotg, true); 756 757 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 758 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 759 760 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 761 FIFOSIZE_DEPTH_SHIFT; 762 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 763 FIFOSIZE_DEPTH_SHIFT; 764 } 765 766 /* 767 * Gets device hardware parameters. Forces device mode if not 768 * currently in device mode. Should be called immediately after a core 769 * soft reset in order to get the reset values. 770 */ 771 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 772 { 773 struct dwc2_hw_params *hw = &hsotg->hw_params; 774 u32 gnptxfsiz; 775 int fifo, fifo_count; 776 777 if (hsotg->dr_mode == USB_DR_MODE_HOST) 778 return; 779 780 dwc2_force_mode(hsotg, false); 781 782 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 783 784 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 785 786 for (fifo = 1; fifo <= fifo_count; fifo++) { 787 hw->g_tx_fifo_size[fifo] = 788 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 789 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 790 } 791 792 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 793 FIFOSIZE_DEPTH_SHIFT; 794 } 795 796 /** 797 * dwc2_get_hwparams() - During device initialization, read various hardware 798 * configuration registers and interpret the contents. 799 * 800 * @hsotg: Programming view of the DWC_otg controller 801 * 802 */ 803 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 804 { 805 struct dwc2_hw_params *hw = &hsotg->hw_params; 806 unsigned int width; 807 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 808 u32 grxfsiz; 809 810 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 811 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 812 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 813 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 814 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 815 816 /* hwcfg1 */ 817 hw->dev_ep_dirs = hwcfg1; 818 819 /* hwcfg2 */ 820 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 821 GHWCFG2_OP_MODE_SHIFT; 822 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 823 GHWCFG2_ARCHITECTURE_SHIFT; 824 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 825 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 826 GHWCFG2_NUM_HOST_CHAN_SHIFT); 827 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 828 GHWCFG2_HS_PHY_TYPE_SHIFT; 829 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 830 GHWCFG2_FS_PHY_TYPE_SHIFT; 831 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 832 GHWCFG2_NUM_DEV_EP_SHIFT; 833 hw->nperio_tx_q_depth = 834 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 835 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 836 hw->host_perio_tx_q_depth = 837 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 838 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 839 hw->dev_token_q_depth = 840 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 841 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 842 843 /* hwcfg3 */ 844 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 845 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 846 hw->max_transfer_size = (1 << (width + 11)) - 1; 847 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 848 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 849 hw->max_packet_count = (1 << (width + 4)) - 1; 850 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 851 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 852 GHWCFG3_DFIFO_DEPTH_SHIFT; 853 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 854 855 /* hwcfg4 */ 856 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 857 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 858 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 859 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 860 GHWCFG4_NUM_IN_EPS_SHIFT; 861 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 862 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 863 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 864 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 865 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 866 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 867 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 868 hw->service_interval_mode = !!(hwcfg4 & 869 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 870 871 /* fifo sizes */ 872 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 873 GRXFSIZ_DEPTH_SHIFT; 874 /* 875 * Host specific hardware parameters. Reading these parameters 876 * requires the controller to be in host mode. The mode will 877 * be forced, if necessary, to read these values. 878 */ 879 dwc2_get_host_hwparams(hsotg); 880 dwc2_get_dev_hwparams(hsotg); 881 882 return 0; 883 } 884 885 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 886 887 int dwc2_init_params(struct dwc2_hsotg *hsotg) 888 { 889 const struct of_device_id *match; 890 set_params_cb set_params; 891 892 dwc2_set_default_params(hsotg); 893 dwc2_get_device_properties(hsotg); 894 895 match = of_match_device(dwc2_of_match_table, hsotg->dev); 896 if (match && match->data) { 897 set_params = match->data; 898 set_params(hsotg); 899 } else { 900 const struct acpi_device_id *amatch; 901 902 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 903 if (amatch && amatch->driver_data) { 904 set_params = (set_params_cb)amatch->driver_data; 905 set_params(hsotg); 906 } 907 } 908 909 dwc2_check_params(hsotg); 910 911 return 0; 912 } 913