1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/usb/of.h> 10 #include <linux/pci_ids.h> 11 #include <linux/pci.h> 12 13 #include "core.h" 14 15 #define PCI_PRODUCT_ID_HAPS_HSOTG 0xabc0 16 #define PCI_DEVICE_ID_LOONGSON_DWC2 0x7a04 17 18 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 19 { 20 struct dwc2_core_params *p = &hsotg->params; 21 22 p->host_rx_fifo_size = 774; 23 p->max_transfer_size = 65535; 24 p->max_packet_count = 511; 25 p->ahbcfg = 0x10; 26 } 27 28 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 29 { 30 struct dwc2_core_params *p = &hsotg->params; 31 32 p->otg_caps.hnp_support = false; 33 p->otg_caps.srp_support = false; 34 p->speed = DWC2_SPEED_PARAM_HIGH; 35 p->host_rx_fifo_size = 512; 36 p->host_nperio_tx_fifo_size = 512; 37 p->host_perio_tx_fifo_size = 512; 38 p->max_transfer_size = 65535; 39 p->max_packet_count = 511; 40 p->host_channels = 16; 41 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 42 p->phy_utmi_width = 8; 43 p->i2c_enable = false; 44 p->reload_ctl = false; 45 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 46 GAHBCFG_HBSTLEN_SHIFT; 47 p->change_speed_quirk = true; 48 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 49 } 50 51 static void dwc2_set_jz4775_params(struct dwc2_hsotg *hsotg) 52 { 53 struct dwc2_core_params *p = &hsotg->params; 54 55 p->otg_caps.hnp_support = false; 56 p->speed = DWC2_SPEED_PARAM_HIGH; 57 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 58 p->phy_utmi_width = 16; 59 p->activate_ingenic_overcurrent_detection = 60 !device_property_read_bool(hsotg->dev, "disable-over-current"); 61 } 62 63 static void dwc2_set_loongson_params(struct dwc2_hsotg *hsotg) 64 { 65 struct dwc2_core_params *p = &hsotg->params; 66 67 p->phy_utmi_width = 8; 68 p->power_down = DWC2_POWER_DOWN_PARAM_PARTIAL; 69 } 70 71 static void dwc2_set_x1600_params(struct dwc2_hsotg *hsotg) 72 { 73 struct dwc2_core_params *p = &hsotg->params; 74 75 p->otg_caps.hnp_support = false; 76 p->speed = DWC2_SPEED_PARAM_HIGH; 77 p->host_channels = 16; 78 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 79 p->phy_utmi_width = 16; 80 p->activate_ingenic_overcurrent_detection = 81 !device_property_read_bool(hsotg->dev, "disable-over-current"); 82 } 83 84 static void dwc2_set_x2000_params(struct dwc2_hsotg *hsotg) 85 { 86 struct dwc2_core_params *p = &hsotg->params; 87 88 p->otg_caps.hnp_support = false; 89 p->speed = DWC2_SPEED_PARAM_HIGH; 90 p->host_rx_fifo_size = 1024; 91 p->host_nperio_tx_fifo_size = 1024; 92 p->host_perio_tx_fifo_size = 1024; 93 p->host_channels = 16; 94 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 95 p->phy_utmi_width = 16; 96 p->activate_ingenic_overcurrent_detection = 97 !device_property_read_bool(hsotg->dev, "disable-over-current"); 98 } 99 100 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 101 { 102 struct dwc2_core_params *p = &hsotg->params; 103 104 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 105 p->no_clock_gating = true; 106 p->phy_utmi_width = 8; 107 } 108 109 static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) 110 { 111 struct dwc2_core_params *p = &hsotg->params; 112 113 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 114 p->no_clock_gating = true; 115 } 116 117 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 118 { 119 struct dwc2_core_params *p = &hsotg->params; 120 121 p->otg_caps.hnp_support = false; 122 p->otg_caps.srp_support = false; 123 p->host_rx_fifo_size = 525; 124 p->host_nperio_tx_fifo_size = 128; 125 p->host_perio_tx_fifo_size = 256; 126 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 127 GAHBCFG_HBSTLEN_SHIFT; 128 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 129 p->lpm = false; 130 p->lpm_clock_gating = false; 131 p->besl = false; 132 p->hird_threshold_en = false; 133 } 134 135 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 136 { 137 struct dwc2_core_params *p = &hsotg->params; 138 139 p->otg_caps.hnp_support = false; 140 p->otg_caps.srp_support = false; 141 p->host_rx_fifo_size = 288; 142 p->host_nperio_tx_fifo_size = 128; 143 p->host_perio_tx_fifo_size = 96; 144 p->max_transfer_size = 65535; 145 p->max_packet_count = 511; 146 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 147 GAHBCFG_HBSTLEN_SHIFT; 148 } 149 150 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 151 { 152 struct dwc2_core_params *p = &hsotg->params; 153 154 p->otg_caps.hnp_support = false; 155 p->otg_caps.srp_support = false; 156 p->speed = DWC2_SPEED_PARAM_HIGH; 157 p->host_rx_fifo_size = 512; 158 p->host_nperio_tx_fifo_size = 500; 159 p->host_perio_tx_fifo_size = 500; 160 p->host_channels = 16; 161 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 162 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 163 GAHBCFG_HBSTLEN_SHIFT; 164 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 165 } 166 167 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 168 { 169 struct dwc2_core_params *p = &hsotg->params; 170 171 p->lpm = false; 172 p->lpm_clock_gating = false; 173 p->besl = false; 174 p->hird_threshold_en = false; 175 } 176 177 static void dwc2_set_amlogic_a1_params(struct dwc2_hsotg *hsotg) 178 { 179 struct dwc2_core_params *p = &hsotg->params; 180 181 p->otg_caps.hnp_support = false; 182 p->otg_caps.srp_support = false; 183 p->speed = DWC2_SPEED_PARAM_HIGH; 184 p->host_rx_fifo_size = 192; 185 p->host_nperio_tx_fifo_size = 128; 186 p->host_perio_tx_fifo_size = 128; 187 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 188 p->phy_utmi_width = 8; 189 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; 190 p->lpm = false; 191 p->lpm_clock_gating = false; 192 p->besl = false; 193 p->hird_threshold_en = false; 194 } 195 196 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 197 { 198 struct dwc2_core_params *p = &hsotg->params; 199 200 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 201 } 202 203 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 204 { 205 struct dwc2_core_params *p = &hsotg->params; 206 207 p->otg_caps.hnp_support = false; 208 p->otg_caps.srp_support = false; 209 p->speed = DWC2_SPEED_PARAM_FULL; 210 p->host_rx_fifo_size = 128; 211 p->host_nperio_tx_fifo_size = 96; 212 p->host_perio_tx_fifo_size = 96; 213 p->max_packet_count = 256; 214 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 215 p->i2c_enable = false; 216 p->activate_stm_fs_transceiver = true; 217 } 218 219 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 220 { 221 struct dwc2_core_params *p = &hsotg->params; 222 223 p->host_rx_fifo_size = 622; 224 p->host_nperio_tx_fifo_size = 128; 225 p->host_perio_tx_fifo_size = 256; 226 } 227 228 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 229 { 230 struct dwc2_core_params *p = &hsotg->params; 231 232 p->otg_caps.hnp_support = false; 233 p->otg_caps.srp_support = false; 234 p->otg_caps.otg_rev = 0x200; 235 p->speed = DWC2_SPEED_PARAM_FULL; 236 p->host_rx_fifo_size = 128; 237 p->host_nperio_tx_fifo_size = 96; 238 p->host_perio_tx_fifo_size = 96; 239 p->max_packet_count = 256; 240 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 241 p->i2c_enable = false; 242 p->activate_stm_fs_transceiver = true; 243 p->activate_stm_id_vb_detection = true; 244 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 245 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 246 p->host_support_fs_ls_low_power = true; 247 p->host_ls_low_power_phy_clk = true; 248 } 249 250 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 251 { 252 struct dwc2_core_params *p = &hsotg->params; 253 254 p->otg_caps.hnp_support = false; 255 p->otg_caps.srp_support = false; 256 p->otg_caps.otg_rev = 0x200; 257 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 258 p->host_rx_fifo_size = 440; 259 p->host_nperio_tx_fifo_size = 256; 260 p->host_perio_tx_fifo_size = 256; 261 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 262 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 263 p->lpm = false; 264 p->lpm_clock_gating = false; 265 p->besl = false; 266 p->hird_threshold_en = false; 267 } 268 269 const struct of_device_id dwc2_of_match_table[] = { 270 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 271 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 272 { .compatible = "ingenic,jz4775-otg", .data = dwc2_set_jz4775_params }, 273 { .compatible = "ingenic,jz4780-otg", .data = dwc2_set_jz4775_params }, 274 { .compatible = "ingenic,x1000-otg", .data = dwc2_set_jz4775_params }, 275 { .compatible = "ingenic,x1600-otg", .data = dwc2_set_x1600_params }, 276 { .compatible = "ingenic,x1700-otg", .data = dwc2_set_x1600_params }, 277 { .compatible = "ingenic,x1830-otg", .data = dwc2_set_x1600_params }, 278 { .compatible = "ingenic,x2000-otg", .data = dwc2_set_x2000_params }, 279 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 280 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 281 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 282 { .compatible = "snps,dwc2" }, 283 { .compatible = "samsung,s3c6400-hsotg", 284 .data = dwc2_set_s3c6400_params }, 285 { .compatible = "amlogic,meson8-usb", 286 .data = dwc2_set_amlogic_params }, 287 { .compatible = "amlogic,meson8b-usb", 288 .data = dwc2_set_amlogic_params }, 289 { .compatible = "amlogic,meson-gxbb-usb", 290 .data = dwc2_set_amlogic_params }, 291 { .compatible = "amlogic,meson-g12a-usb", 292 .data = dwc2_set_amlogic_g12a_params }, 293 { .compatible = "amlogic,meson-a1-usb", 294 .data = dwc2_set_amlogic_a1_params }, 295 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 296 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 297 { .compatible = "st,stm32f4x9-fsotg", 298 .data = dwc2_set_stm32f4x9_fsotg_params }, 299 { .compatible = "st,stm32f4x9-hsotg" }, 300 { .compatible = "st,stm32f7-hsotg", 301 .data = dwc2_set_stm32f7_hsotg_params }, 302 { .compatible = "st,stm32mp15-fsotg", 303 .data = dwc2_set_stm32mp15_fsotg_params }, 304 { .compatible = "st,stm32mp15-hsotg", 305 .data = dwc2_set_stm32mp15_hsotg_params }, 306 { .compatible = "intel,socfpga-agilex-hsotg", 307 .data = dwc2_set_socfpga_agilex_params }, 308 {}, 309 }; 310 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 311 312 const struct acpi_device_id dwc2_acpi_match[] = { 313 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 314 { }, 315 }; 316 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 317 318 const struct pci_device_id dwc2_pci_ids[] = { 319 { 320 PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, PCI_PRODUCT_ID_HAPS_HSOTG), 321 }, 322 { 323 PCI_DEVICE(PCI_VENDOR_ID_STMICRO, 324 PCI_DEVICE_ID_STMICRO_USB_OTG), 325 }, 326 { 327 PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, PCI_DEVICE_ID_LOONGSON_DWC2), 328 .driver_data = (unsigned long)dwc2_set_loongson_params, 329 }, 330 { /* end: all zeroes */ } 331 }; 332 MODULE_DEVICE_TABLE(pci, dwc2_pci_ids); 333 EXPORT_SYMBOL_GPL(dwc2_pci_ids); 334 335 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 336 { 337 switch (hsotg->hw_params.op_mode) { 338 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 339 hsotg->params.otg_caps.hnp_support = true; 340 hsotg->params.otg_caps.srp_support = true; 341 break; 342 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 343 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 344 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 345 hsotg->params.otg_caps.hnp_support = false; 346 hsotg->params.otg_caps.srp_support = true; 347 break; 348 default: 349 hsotg->params.otg_caps.hnp_support = false; 350 hsotg->params.otg_caps.srp_support = false; 351 break; 352 } 353 } 354 355 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 356 { 357 int val; 358 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 359 360 val = DWC2_PHY_TYPE_PARAM_FS; 361 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 362 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 363 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 364 val = DWC2_PHY_TYPE_PARAM_UTMI; 365 else 366 val = DWC2_PHY_TYPE_PARAM_ULPI; 367 } 368 369 if (dwc2_is_fs_iot(hsotg)) 370 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 371 372 hsotg->params.phy_type = val; 373 } 374 375 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 376 { 377 int val; 378 379 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 380 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 381 382 if (dwc2_is_fs_iot(hsotg)) 383 val = DWC2_SPEED_PARAM_FULL; 384 385 if (dwc2_is_hs_iot(hsotg)) 386 val = DWC2_SPEED_PARAM_HIGH; 387 388 hsotg->params.speed = val; 389 } 390 391 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 392 { 393 int val; 394 395 val = (hsotg->hw_params.utmi_phy_data_width == 396 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 397 398 if (hsotg->phy) { 399 /* 400 * If using the generic PHY framework, check if the PHY bus 401 * width is 8-bit and set the phyif appropriately. 402 */ 403 if (phy_get_bus_width(hsotg->phy) == 8) 404 val = 8; 405 } 406 407 hsotg->params.phy_utmi_width = val; 408 } 409 410 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 411 { 412 struct dwc2_core_params *p = &hsotg->params; 413 int depth_average; 414 int fifo_count; 415 int i; 416 417 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 418 419 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 420 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 421 for (i = 1; i <= fifo_count; i++) 422 p->g_tx_fifo_size[i] = depth_average; 423 } 424 425 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 426 { 427 int val; 428 429 if (hsotg->hw_params.hibernation) 430 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 431 else if (hsotg->hw_params.power_optimized) 432 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 433 else 434 val = DWC2_POWER_DOWN_PARAM_NONE; 435 436 hsotg->params.power_down = val; 437 } 438 439 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 440 { 441 struct dwc2_core_params *p = &hsotg->params; 442 443 p->lpm = hsotg->hw_params.lpm_mode; 444 if (p->lpm) { 445 p->lpm_clock_gating = true; 446 p->besl = true; 447 p->hird_threshold_en = true; 448 p->hird_threshold = 4; 449 } else { 450 p->lpm_clock_gating = false; 451 p->besl = false; 452 p->hird_threshold_en = false; 453 } 454 } 455 456 /** 457 * dwc2_set_default_params() - Set all core parameters to their 458 * auto-detected default values. 459 * 460 * @hsotg: Programming view of the DWC_otg controller 461 * 462 */ 463 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 464 { 465 struct dwc2_hw_params *hw = &hsotg->hw_params; 466 struct dwc2_core_params *p = &hsotg->params; 467 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 468 469 dwc2_set_param_otg_cap(hsotg); 470 dwc2_set_param_phy_type(hsotg); 471 dwc2_set_param_speed(hsotg); 472 dwc2_set_param_phy_utmi_width(hsotg); 473 dwc2_set_param_power_down(hsotg); 474 dwc2_set_param_lpm(hsotg); 475 p->phy_ulpi_ddr = false; 476 p->phy_ulpi_ext_vbus = false; 477 478 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 479 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 480 p->i2c_enable = hw->i2c_enable; 481 p->acg_enable = hw->acg_enable; 482 p->ulpi_fs_ls = false; 483 p->ts_dline = false; 484 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 485 p->uframe_sched = true; 486 p->external_id_pin_ctl = false; 487 p->ipg_isoc_en = false; 488 p->service_interval = false; 489 p->max_packet_count = hw->max_packet_count; 490 p->max_transfer_size = hw->max_transfer_size; 491 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 492 p->ref_clk_per = 33333; 493 p->sof_cnt_wkup_alert = 100; 494 495 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 496 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 497 p->host_dma = dma_capable; 498 p->dma_desc_enable = false; 499 p->dma_desc_fs_enable = false; 500 p->host_support_fs_ls_low_power = false; 501 p->host_ls_low_power_phy_clk = false; 502 p->host_channels = hw->host_channels; 503 p->host_rx_fifo_size = hw->rx_fifo_size; 504 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 505 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 506 } 507 508 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 509 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 510 p->g_dma = dma_capable; 511 p->g_dma_desc = hw->dma_desc_enable; 512 513 /* 514 * The values for g_rx_fifo_size (2048) and 515 * g_np_tx_fifo_size (1024) come from the legacy s3c 516 * gadget driver. These defaults have been hard-coded 517 * for some time so many platforms depend on these 518 * values. Leave them as defaults for now and only 519 * auto-detect if the hardware does not support the 520 * default. 521 */ 522 p->g_rx_fifo_size = 2048; 523 p->g_np_tx_fifo_size = 1024; 524 dwc2_set_param_tx_fifo_sizes(hsotg); 525 } 526 } 527 528 /** 529 * dwc2_get_device_properties() - Read in device properties. 530 * 531 * @hsotg: Programming view of the DWC_otg controller 532 * 533 * Read in the device properties and adjust core parameters if needed. 534 */ 535 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 536 { 537 struct dwc2_core_params *p = &hsotg->params; 538 int num; 539 540 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 541 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 542 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 543 &p->g_rx_fifo_size); 544 545 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 546 &p->g_np_tx_fifo_size); 547 548 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 549 if (num > 0) { 550 num = min(num, 15); 551 memset(p->g_tx_fifo_size, 0, 552 sizeof(p->g_tx_fifo_size)); 553 device_property_read_u32_array(hsotg->dev, 554 "g-tx-fifo-size", 555 &p->g_tx_fifo_size[1], 556 num); 557 } 558 559 of_usb_update_otg_caps(hsotg->dev->of_node, &p->otg_caps); 560 } 561 562 p->oc_disable = of_property_read_bool(hsotg->dev->of_node, "disable-over-current"); 563 } 564 565 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 566 { 567 int valid = 1; 568 569 if (hsotg->params.otg_caps.hnp_support && hsotg->params.otg_caps.srp_support) { 570 /* check HNP && SRP capable */ 571 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 572 valid = 0; 573 } else if (!hsotg->params.otg_caps.hnp_support) { 574 /* check SRP only capable */ 575 if (hsotg->params.otg_caps.srp_support) { 576 switch (hsotg->hw_params.op_mode) { 577 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 578 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 579 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 580 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 581 break; 582 default: 583 valid = 0; 584 break; 585 } 586 } 587 /* else: NO HNP && NO SRP capable: always valid */ 588 } else { 589 valid = 0; 590 } 591 592 if (!valid) 593 dwc2_set_param_otg_cap(hsotg); 594 } 595 596 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 597 { 598 int valid = 0; 599 u32 hs_phy_type; 600 u32 fs_phy_type; 601 602 hs_phy_type = hsotg->hw_params.hs_phy_type; 603 fs_phy_type = hsotg->hw_params.fs_phy_type; 604 605 switch (hsotg->params.phy_type) { 606 case DWC2_PHY_TYPE_PARAM_FS: 607 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 608 valid = 1; 609 break; 610 case DWC2_PHY_TYPE_PARAM_UTMI: 611 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 612 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 613 valid = 1; 614 break; 615 case DWC2_PHY_TYPE_PARAM_ULPI: 616 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 617 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 618 valid = 1; 619 break; 620 default: 621 break; 622 } 623 624 if (!valid) 625 dwc2_set_param_phy_type(hsotg); 626 } 627 628 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 629 { 630 int valid = 1; 631 int phy_type = hsotg->params.phy_type; 632 int speed = hsotg->params.speed; 633 634 switch (speed) { 635 case DWC2_SPEED_PARAM_HIGH: 636 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 637 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 638 valid = 0; 639 break; 640 case DWC2_SPEED_PARAM_FULL: 641 case DWC2_SPEED_PARAM_LOW: 642 break; 643 default: 644 valid = 0; 645 break; 646 } 647 648 if (!valid) 649 dwc2_set_param_speed(hsotg); 650 } 651 652 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 653 { 654 int valid = 0; 655 int param = hsotg->params.phy_utmi_width; 656 int width = hsotg->hw_params.utmi_phy_data_width; 657 658 switch (width) { 659 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 660 valid = (param == 8); 661 break; 662 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 663 valid = (param == 16); 664 break; 665 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 666 valid = (param == 8 || param == 16); 667 break; 668 } 669 670 if (!valid) 671 dwc2_set_param_phy_utmi_width(hsotg); 672 } 673 674 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 675 { 676 int param = hsotg->params.power_down; 677 678 switch (param) { 679 case DWC2_POWER_DOWN_PARAM_NONE: 680 break; 681 case DWC2_POWER_DOWN_PARAM_PARTIAL: 682 if (hsotg->hw_params.power_optimized) 683 break; 684 dev_dbg(hsotg->dev, 685 "Partial power down isn't supported by HW\n"); 686 param = DWC2_POWER_DOWN_PARAM_NONE; 687 break; 688 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 689 if (hsotg->hw_params.hibernation) 690 break; 691 dev_dbg(hsotg->dev, 692 "Hibernation isn't supported by HW\n"); 693 param = DWC2_POWER_DOWN_PARAM_NONE; 694 break; 695 default: 696 dev_err(hsotg->dev, 697 "%s: Invalid parameter power_down=%d\n", 698 __func__, param); 699 param = DWC2_POWER_DOWN_PARAM_NONE; 700 break; 701 } 702 703 hsotg->params.power_down = param; 704 } 705 706 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 707 { 708 int fifo_count; 709 int fifo; 710 int min; 711 u32 total = 0; 712 u32 dptxfszn; 713 714 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 715 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 716 717 for (fifo = 1; fifo <= fifo_count; fifo++) 718 total += hsotg->params.g_tx_fifo_size[fifo]; 719 720 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 721 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 722 __func__); 723 dwc2_set_param_tx_fifo_sizes(hsotg); 724 } 725 726 for (fifo = 1; fifo <= fifo_count; fifo++) { 727 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 728 729 if (hsotg->params.g_tx_fifo_size[fifo] < min || 730 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 731 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 732 __func__, fifo, 733 hsotg->params.g_tx_fifo_size[fifo]); 734 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 735 } 736 } 737 } 738 739 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 740 if ((int)(hsotg->params._param) < (_min) || \ 741 (hsotg->params._param) > (_max)) { \ 742 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 743 __func__, #_param, hsotg->params._param); \ 744 hsotg->params._param = (_def); \ 745 } \ 746 } while (0) 747 748 #define CHECK_BOOL(_param, _check) do { \ 749 if (hsotg->params._param && !(_check)) { \ 750 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 751 __func__, #_param, hsotg->params._param); \ 752 hsotg->params._param = false; \ 753 } \ 754 } while (0) 755 756 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 757 { 758 struct dwc2_hw_params *hw = &hsotg->hw_params; 759 struct dwc2_core_params *p = &hsotg->params; 760 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 761 762 dwc2_check_param_otg_cap(hsotg); 763 dwc2_check_param_phy_type(hsotg); 764 dwc2_check_param_speed(hsotg); 765 dwc2_check_param_phy_utmi_width(hsotg); 766 dwc2_check_param_power_down(hsotg); 767 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 768 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 769 CHECK_BOOL(i2c_enable, hw->i2c_enable); 770 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 771 CHECK_BOOL(acg_enable, hw->acg_enable); 772 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 773 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 774 CHECK_BOOL(lpm, hw->lpm_mode); 775 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 776 CHECK_BOOL(besl, hsotg->params.lpm); 777 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 778 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 779 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 780 CHECK_BOOL(service_interval, hw->service_interval_mode); 781 CHECK_RANGE(max_packet_count, 782 15, hw->max_packet_count, 783 hw->max_packet_count); 784 CHECK_RANGE(max_transfer_size, 785 2047, hw->max_transfer_size, 786 hw->max_transfer_size); 787 788 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 789 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 790 CHECK_BOOL(host_dma, dma_capable); 791 CHECK_BOOL(dma_desc_enable, p->host_dma); 792 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 793 CHECK_BOOL(host_ls_low_power_phy_clk, 794 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 795 CHECK_RANGE(host_channels, 796 1, hw->host_channels, 797 hw->host_channels); 798 CHECK_RANGE(host_rx_fifo_size, 799 16, hw->rx_fifo_size, 800 hw->rx_fifo_size); 801 CHECK_RANGE(host_nperio_tx_fifo_size, 802 16, hw->host_nperio_tx_fifo_size, 803 hw->host_nperio_tx_fifo_size); 804 CHECK_RANGE(host_perio_tx_fifo_size, 805 16, hw->host_perio_tx_fifo_size, 806 hw->host_perio_tx_fifo_size); 807 } 808 809 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 810 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 811 CHECK_BOOL(g_dma, dma_capable); 812 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 813 CHECK_RANGE(g_rx_fifo_size, 814 16, hw->rx_fifo_size, 815 hw->rx_fifo_size); 816 CHECK_RANGE(g_np_tx_fifo_size, 817 16, hw->dev_nperio_tx_fifo_size, 818 hw->dev_nperio_tx_fifo_size); 819 dwc2_check_param_tx_fifo_sizes(hsotg); 820 } 821 } 822 823 /* 824 * Gets host hardware parameters. Forces host mode if not currently in 825 * host mode. Should be called immediately after a core soft reset in 826 * order to get the reset values. 827 */ 828 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 829 { 830 struct dwc2_hw_params *hw = &hsotg->hw_params; 831 u32 gnptxfsiz; 832 u32 hptxfsiz; 833 834 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 835 return; 836 837 dwc2_force_mode(hsotg, true); 838 839 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 840 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 841 842 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 843 FIFOSIZE_DEPTH_SHIFT; 844 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 845 FIFOSIZE_DEPTH_SHIFT; 846 } 847 848 /* 849 * Gets device hardware parameters. Forces device mode if not 850 * currently in device mode. Should be called immediately after a core 851 * soft reset in order to get the reset values. 852 */ 853 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 854 { 855 struct dwc2_hw_params *hw = &hsotg->hw_params; 856 u32 gnptxfsiz; 857 int fifo, fifo_count; 858 859 if (hsotg->dr_mode == USB_DR_MODE_HOST) 860 return; 861 862 dwc2_force_mode(hsotg, false); 863 864 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 865 866 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 867 868 for (fifo = 1; fifo <= fifo_count; fifo++) { 869 hw->g_tx_fifo_size[fifo] = 870 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 871 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 872 } 873 874 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 875 FIFOSIZE_DEPTH_SHIFT; 876 } 877 878 /** 879 * dwc2_get_hwparams() - During device initialization, read various hardware 880 * configuration registers and interpret the contents. 881 * 882 * @hsotg: Programming view of the DWC_otg controller 883 * 884 */ 885 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 886 { 887 struct dwc2_hw_params *hw = &hsotg->hw_params; 888 unsigned int width; 889 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 890 u32 grxfsiz; 891 892 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 893 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 894 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 895 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 896 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 897 898 /* hwcfg1 */ 899 hw->dev_ep_dirs = hwcfg1; 900 901 /* hwcfg2 */ 902 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 903 GHWCFG2_OP_MODE_SHIFT; 904 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 905 GHWCFG2_ARCHITECTURE_SHIFT; 906 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 907 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 908 GHWCFG2_NUM_HOST_CHAN_SHIFT); 909 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 910 GHWCFG2_HS_PHY_TYPE_SHIFT; 911 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 912 GHWCFG2_FS_PHY_TYPE_SHIFT; 913 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 914 GHWCFG2_NUM_DEV_EP_SHIFT; 915 hw->nperio_tx_q_depth = 916 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 917 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 918 hw->host_perio_tx_q_depth = 919 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 920 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 921 hw->dev_token_q_depth = 922 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 923 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 924 925 /* hwcfg3 */ 926 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 927 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 928 hw->max_transfer_size = (1 << (width + 11)) - 1; 929 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 930 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 931 hw->max_packet_count = (1 << (width + 4)) - 1; 932 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 933 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 934 GHWCFG3_DFIFO_DEPTH_SHIFT; 935 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 936 937 /* hwcfg4 */ 938 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 939 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 940 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 941 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 942 GHWCFG4_NUM_IN_EPS_SHIFT; 943 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 944 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 945 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 946 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 947 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 948 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 949 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 950 hw->service_interval_mode = !!(hwcfg4 & 951 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 952 953 /* fifo sizes */ 954 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 955 GRXFSIZ_DEPTH_SHIFT; 956 /* 957 * Host specific hardware parameters. Reading these parameters 958 * requires the controller to be in host mode. The mode will 959 * be forced, if necessary, to read these values. 960 */ 961 dwc2_get_host_hwparams(hsotg); 962 dwc2_get_dev_hwparams(hsotg); 963 964 return 0; 965 } 966 967 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 968 969 int dwc2_init_params(struct dwc2_hsotg *hsotg) 970 { 971 const struct of_device_id *match; 972 set_params_cb set_params; 973 974 dwc2_set_default_params(hsotg); 975 dwc2_get_device_properties(hsotg); 976 977 match = of_match_device(dwc2_of_match_table, hsotg->dev); 978 if (match && match->data) { 979 set_params = match->data; 980 set_params(hsotg); 981 } else if (!match) { 982 const struct acpi_device_id *amatch; 983 const struct pci_device_id *pmatch = NULL; 984 985 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 986 if (amatch && amatch->driver_data) { 987 set_params = (set_params_cb)amatch->driver_data; 988 set_params(hsotg); 989 } else if (!amatch) 990 pmatch = pci_match_id(dwc2_pci_ids, to_pci_dev(hsotg->dev->parent)); 991 992 if (pmatch && pmatch->driver_data) { 993 set_params = (set_params_cb)pmatch->driver_data; 994 set_params(hsotg); 995 } 996 } 997 998 dwc2_check_params(hsotg); 999 1000 return 0; 1001 } 1002