1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) 2004-2016 Synopsys, Inc. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the above-listed copyright holders may not be used 15 * to endorse or promote products derived from this software without 16 * specific prior written permission. 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation; either version 2 of the License, or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 24 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 25 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 27 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 28 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 29 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 31 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 32 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/of_device.h> 39 40 #include "core.h" 41 42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) 43 { 44 struct dwc2_core_params *p = &hsotg->params; 45 46 p->host_rx_fifo_size = 774; 47 p->max_transfer_size = 65535; 48 p->max_packet_count = 511; 49 p->ahbcfg = 0x10; 50 } 51 52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) 53 { 54 struct dwc2_core_params *p = &hsotg->params; 55 56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 57 p->speed = DWC2_SPEED_PARAM_HIGH; 58 p->host_rx_fifo_size = 512; 59 p->host_nperio_tx_fifo_size = 512; 60 p->host_perio_tx_fifo_size = 512; 61 p->max_transfer_size = 65535; 62 p->max_packet_count = 511; 63 p->host_channels = 16; 64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 65 p->phy_utmi_width = 8; 66 p->i2c_enable = false; 67 p->reload_ctl = false; 68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 69 GAHBCFG_HBSTLEN_SHIFT; 70 p->change_speed_quirk = true; 71 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 72 } 73 74 static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) 75 { 76 struct dwc2_core_params *p = &hsotg->params; 77 78 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 79 p->no_clock_gating = true; 80 p->phy_utmi_width = 8; 81 } 82 83 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) 84 { 85 struct dwc2_core_params *p = &hsotg->params; 86 87 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 88 p->host_rx_fifo_size = 525; 89 p->host_nperio_tx_fifo_size = 128; 90 p->host_perio_tx_fifo_size = 256; 91 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 92 GAHBCFG_HBSTLEN_SHIFT; 93 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 94 } 95 96 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg) 97 { 98 struct dwc2_core_params *p = &hsotg->params; 99 100 p->otg_cap = 2; 101 p->host_rx_fifo_size = 288; 102 p->host_nperio_tx_fifo_size = 128; 103 p->host_perio_tx_fifo_size = 96; 104 p->max_transfer_size = 65535; 105 p->max_packet_count = 511; 106 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << 107 GAHBCFG_HBSTLEN_SHIFT; 108 } 109 110 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) 111 { 112 struct dwc2_core_params *p = &hsotg->params; 113 114 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 115 p->speed = DWC2_SPEED_PARAM_HIGH; 116 p->host_rx_fifo_size = 512; 117 p->host_nperio_tx_fifo_size = 500; 118 p->host_perio_tx_fifo_size = 500; 119 p->host_channels = 16; 120 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; 121 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << 122 GAHBCFG_HBSTLEN_SHIFT; 123 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 124 } 125 126 static void dwc2_set_amlogic_g12a_params(struct dwc2_hsotg *hsotg) 127 { 128 struct dwc2_core_params *p = &hsotg->params; 129 130 p->lpm = false; 131 p->lpm_clock_gating = false; 132 p->besl = false; 133 p->hird_threshold_en = false; 134 } 135 136 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) 137 { 138 struct dwc2_core_params *p = &hsotg->params; 139 140 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 141 } 142 143 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) 144 { 145 struct dwc2_core_params *p = &hsotg->params; 146 147 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 148 p->speed = DWC2_SPEED_PARAM_FULL; 149 p->host_rx_fifo_size = 128; 150 p->host_nperio_tx_fifo_size = 96; 151 p->host_perio_tx_fifo_size = 96; 152 p->max_packet_count = 256; 153 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 154 p->i2c_enable = false; 155 p->activate_stm_fs_transceiver = true; 156 } 157 158 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg) 159 { 160 struct dwc2_core_params *p = &hsotg->params; 161 162 p->host_rx_fifo_size = 622; 163 p->host_nperio_tx_fifo_size = 128; 164 p->host_perio_tx_fifo_size = 256; 165 } 166 167 static void dwc2_set_stm32mp15_fsotg_params(struct dwc2_hsotg *hsotg) 168 { 169 struct dwc2_core_params *p = &hsotg->params; 170 171 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 172 p->speed = DWC2_SPEED_PARAM_FULL; 173 p->host_rx_fifo_size = 128; 174 p->host_nperio_tx_fifo_size = 96; 175 p->host_perio_tx_fifo_size = 96; 176 p->max_packet_count = 256; 177 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; 178 p->i2c_enable = false; 179 p->activate_stm_fs_transceiver = true; 180 p->activate_stm_id_vb_detection = true; 181 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 182 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 183 p->host_support_fs_ls_low_power = true; 184 p->host_ls_low_power_phy_clk = true; 185 } 186 187 static void dwc2_set_stm32mp15_hsotg_params(struct dwc2_hsotg *hsotg) 188 { 189 struct dwc2_core_params *p = &hsotg->params; 190 191 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 192 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); 193 p->host_rx_fifo_size = 440; 194 p->host_nperio_tx_fifo_size = 256; 195 p->host_perio_tx_fifo_size = 256; 196 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; 197 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; 198 p->lpm = false; 199 p->lpm_clock_gating = false; 200 p->besl = false; 201 p->hird_threshold_en = false; 202 } 203 204 const struct of_device_id dwc2_of_match_table[] = { 205 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params }, 206 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params }, 207 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params }, 208 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params }, 209 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params }, 210 { .compatible = "snps,dwc2" }, 211 { .compatible = "samsung,s3c6400-hsotg", 212 .data = dwc2_set_s3c6400_params }, 213 { .compatible = "amlogic,meson8-usb", 214 .data = dwc2_set_amlogic_params }, 215 { .compatible = "amlogic,meson8b-usb", 216 .data = dwc2_set_amlogic_params }, 217 { .compatible = "amlogic,meson-gxbb-usb", 218 .data = dwc2_set_amlogic_params }, 219 { .compatible = "amlogic,meson-g12a-usb", 220 .data = dwc2_set_amlogic_g12a_params }, 221 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params }, 222 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params }, 223 { .compatible = "st,stm32f4x9-fsotg", 224 .data = dwc2_set_stm32f4x9_fsotg_params }, 225 { .compatible = "st,stm32f4x9-hsotg" }, 226 { .compatible = "st,stm32f7-hsotg", 227 .data = dwc2_set_stm32f7_hsotg_params }, 228 { .compatible = "st,stm32mp15-fsotg", 229 .data = dwc2_set_stm32mp15_fsotg_params }, 230 { .compatible = "st,stm32mp15-hsotg", 231 .data = dwc2_set_stm32mp15_hsotg_params }, 232 {}, 233 }; 234 MODULE_DEVICE_TABLE(of, dwc2_of_match_table); 235 236 const struct acpi_device_id dwc2_acpi_match[] = { 237 { "BCM2848", (kernel_ulong_t)dwc2_set_bcm_params }, 238 { }, 239 }; 240 MODULE_DEVICE_TABLE(acpi, dwc2_acpi_match); 241 242 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg) 243 { 244 u8 val; 245 246 switch (hsotg->hw_params.op_mode) { 247 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 248 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE; 249 break; 250 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 251 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 252 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 253 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE; 254 break; 255 default: 256 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; 257 break; 258 } 259 260 hsotg->params.otg_cap = val; 261 } 262 263 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg) 264 { 265 int val; 266 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; 267 268 val = DWC2_PHY_TYPE_PARAM_FS; 269 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) { 270 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI || 271 hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI) 272 val = DWC2_PHY_TYPE_PARAM_UTMI; 273 else 274 val = DWC2_PHY_TYPE_PARAM_ULPI; 275 } 276 277 if (dwc2_is_fs_iot(hsotg)) 278 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; 279 280 hsotg->params.phy_type = val; 281 } 282 283 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg) 284 { 285 int val; 286 287 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? 288 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH; 289 290 if (dwc2_is_fs_iot(hsotg)) 291 val = DWC2_SPEED_PARAM_FULL; 292 293 if (dwc2_is_hs_iot(hsotg)) 294 val = DWC2_SPEED_PARAM_HIGH; 295 296 hsotg->params.speed = val; 297 } 298 299 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 300 { 301 int val; 302 303 val = (hsotg->hw_params.utmi_phy_data_width == 304 GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16; 305 306 if (hsotg->phy) { 307 /* 308 * If using the generic PHY framework, check if the PHY bus 309 * width is 8-bit and set the phyif appropriately. 310 */ 311 if (phy_get_bus_width(hsotg->phy) == 8) 312 val = 8; 313 } 314 315 hsotg->params.phy_utmi_width = val; 316 } 317 318 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 319 { 320 struct dwc2_core_params *p = &hsotg->params; 321 int depth_average; 322 int fifo_count; 323 int i; 324 325 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 326 327 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); 328 depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg); 329 for (i = 1; i <= fifo_count; i++) 330 p->g_tx_fifo_size[i] = depth_average; 331 } 332 333 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg) 334 { 335 int val; 336 337 if (hsotg->hw_params.hibernation) 338 val = DWC2_POWER_DOWN_PARAM_HIBERNATION; 339 else if (hsotg->hw_params.power_optimized) 340 val = DWC2_POWER_DOWN_PARAM_PARTIAL; 341 else 342 val = DWC2_POWER_DOWN_PARAM_NONE; 343 344 hsotg->params.power_down = val; 345 } 346 347 static void dwc2_set_param_lpm(struct dwc2_hsotg *hsotg) 348 { 349 struct dwc2_core_params *p = &hsotg->params; 350 351 p->lpm = hsotg->hw_params.lpm_mode; 352 if (p->lpm) { 353 p->lpm_clock_gating = true; 354 p->besl = true; 355 p->hird_threshold_en = true; 356 p->hird_threshold = 4; 357 } else { 358 p->lpm_clock_gating = false; 359 p->besl = false; 360 p->hird_threshold_en = false; 361 } 362 } 363 364 /** 365 * dwc2_set_default_params() - Set all core parameters to their 366 * auto-detected default values. 367 * 368 * @hsotg: Programming view of the DWC_otg controller 369 * 370 */ 371 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg) 372 { 373 struct dwc2_hw_params *hw = &hsotg->hw_params; 374 struct dwc2_core_params *p = &hsotg->params; 375 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 376 377 dwc2_set_param_otg_cap(hsotg); 378 dwc2_set_param_phy_type(hsotg); 379 dwc2_set_param_speed(hsotg); 380 dwc2_set_param_phy_utmi_width(hsotg); 381 dwc2_set_param_power_down(hsotg); 382 dwc2_set_param_lpm(hsotg); 383 p->phy_ulpi_ddr = false; 384 p->phy_ulpi_ext_vbus = false; 385 386 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; 387 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; 388 p->i2c_enable = hw->i2c_enable; 389 p->acg_enable = hw->acg_enable; 390 p->ulpi_fs_ls = false; 391 p->ts_dline = false; 392 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); 393 p->uframe_sched = true; 394 p->external_id_pin_ctl = false; 395 p->ipg_isoc_en = false; 396 p->service_interval = false; 397 p->max_packet_count = hw->max_packet_count; 398 p->max_transfer_size = hw->max_transfer_size; 399 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; 400 p->ref_clk_per = 33333; 401 p->sof_cnt_wkup_alert = 100; 402 403 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 404 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 405 p->host_dma = dma_capable; 406 p->dma_desc_enable = false; 407 p->dma_desc_fs_enable = false; 408 p->host_support_fs_ls_low_power = false; 409 p->host_ls_low_power_phy_clk = false; 410 p->host_channels = hw->host_channels; 411 p->host_rx_fifo_size = hw->rx_fifo_size; 412 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; 413 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; 414 } 415 416 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 417 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 418 p->g_dma = dma_capable; 419 p->g_dma_desc = hw->dma_desc_enable; 420 421 /* 422 * The values for g_rx_fifo_size (2048) and 423 * g_np_tx_fifo_size (1024) come from the legacy s3c 424 * gadget driver. These defaults have been hard-coded 425 * for some time so many platforms depend on these 426 * values. Leave them as defaults for now and only 427 * auto-detect if the hardware does not support the 428 * default. 429 */ 430 p->g_rx_fifo_size = 2048; 431 p->g_np_tx_fifo_size = 1024; 432 dwc2_set_param_tx_fifo_sizes(hsotg); 433 } 434 } 435 436 /** 437 * dwc2_get_device_properties() - Read in device properties. 438 * 439 * @hsotg: Programming view of the DWC_otg controller 440 * 441 * Read in the device properties and adjust core parameters if needed. 442 */ 443 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg) 444 { 445 struct dwc2_core_params *p = &hsotg->params; 446 int num; 447 448 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 449 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 450 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", 451 &p->g_rx_fifo_size); 452 453 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", 454 &p->g_np_tx_fifo_size); 455 456 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); 457 if (num > 0) { 458 num = min(num, 15); 459 memset(p->g_tx_fifo_size, 0, 460 sizeof(p->g_tx_fifo_size)); 461 device_property_read_u32_array(hsotg->dev, 462 "g-tx-fifo-size", 463 &p->g_tx_fifo_size[1], 464 num); 465 } 466 } 467 468 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) 469 p->oc_disable = true; 470 } 471 472 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg) 473 { 474 int valid = 1; 475 476 switch (hsotg->params.otg_cap) { 477 case DWC2_CAP_PARAM_HNP_SRP_CAPABLE: 478 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) 479 valid = 0; 480 break; 481 case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE: 482 switch (hsotg->hw_params.op_mode) { 483 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 484 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 485 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 486 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 487 break; 488 default: 489 valid = 0; 490 break; 491 } 492 break; 493 case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE: 494 /* always valid */ 495 break; 496 default: 497 valid = 0; 498 break; 499 } 500 501 if (!valid) 502 dwc2_set_param_otg_cap(hsotg); 503 } 504 505 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg) 506 { 507 int valid = 0; 508 u32 hs_phy_type; 509 u32 fs_phy_type; 510 511 hs_phy_type = hsotg->hw_params.hs_phy_type; 512 fs_phy_type = hsotg->hw_params.fs_phy_type; 513 514 switch (hsotg->params.phy_type) { 515 case DWC2_PHY_TYPE_PARAM_FS: 516 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 517 valid = 1; 518 break; 519 case DWC2_PHY_TYPE_PARAM_UTMI: 520 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 521 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 522 valid = 1; 523 break; 524 case DWC2_PHY_TYPE_PARAM_ULPI: 525 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) || 526 (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)) 527 valid = 1; 528 break; 529 default: 530 break; 531 } 532 533 if (!valid) 534 dwc2_set_param_phy_type(hsotg); 535 } 536 537 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg) 538 { 539 int valid = 1; 540 int phy_type = hsotg->params.phy_type; 541 int speed = hsotg->params.speed; 542 543 switch (speed) { 544 case DWC2_SPEED_PARAM_HIGH: 545 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && 546 (phy_type == DWC2_PHY_TYPE_PARAM_FS)) 547 valid = 0; 548 break; 549 case DWC2_SPEED_PARAM_FULL: 550 case DWC2_SPEED_PARAM_LOW: 551 break; 552 default: 553 valid = 0; 554 break; 555 } 556 557 if (!valid) 558 dwc2_set_param_speed(hsotg); 559 } 560 561 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg) 562 { 563 int valid = 0; 564 int param = hsotg->params.phy_utmi_width; 565 int width = hsotg->hw_params.utmi_phy_data_width; 566 567 switch (width) { 568 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8: 569 valid = (param == 8); 570 break; 571 case GHWCFG4_UTMI_PHY_DATA_WIDTH_16: 572 valid = (param == 16); 573 break; 574 case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16: 575 valid = (param == 8 || param == 16); 576 break; 577 } 578 579 if (!valid) 580 dwc2_set_param_phy_utmi_width(hsotg); 581 } 582 583 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg) 584 { 585 int param = hsotg->params.power_down; 586 587 switch (param) { 588 case DWC2_POWER_DOWN_PARAM_NONE: 589 break; 590 case DWC2_POWER_DOWN_PARAM_PARTIAL: 591 if (hsotg->hw_params.power_optimized) 592 break; 593 dev_dbg(hsotg->dev, 594 "Partial power down isn't supported by HW\n"); 595 param = DWC2_POWER_DOWN_PARAM_NONE; 596 break; 597 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 598 if (hsotg->hw_params.hibernation) 599 break; 600 dev_dbg(hsotg->dev, 601 "Hibernation isn't supported by HW\n"); 602 param = DWC2_POWER_DOWN_PARAM_NONE; 603 break; 604 default: 605 dev_err(hsotg->dev, 606 "%s: Invalid parameter power_down=%d\n", 607 __func__, param); 608 param = DWC2_POWER_DOWN_PARAM_NONE; 609 break; 610 } 611 612 hsotg->params.power_down = param; 613 } 614 615 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg) 616 { 617 int fifo_count; 618 int fifo; 619 int min; 620 u32 total = 0; 621 u32 dptxfszn; 622 623 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 624 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; 625 626 for (fifo = 1; fifo <= fifo_count; fifo++) 627 total += hsotg->params.g_tx_fifo_size[fifo]; 628 629 if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) { 630 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", 631 __func__); 632 dwc2_set_param_tx_fifo_sizes(hsotg); 633 } 634 635 for (fifo = 1; fifo <= fifo_count; fifo++) { 636 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; 637 638 if (hsotg->params.g_tx_fifo_size[fifo] < min || 639 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { 640 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", 641 __func__, fifo, 642 hsotg->params.g_tx_fifo_size[fifo]); 643 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; 644 } 645 } 646 } 647 648 #define CHECK_RANGE(_param, _min, _max, _def) do { \ 649 if ((int)(hsotg->params._param) < (_min) || \ 650 (hsotg->params._param) > (_max)) { \ 651 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 652 __func__, #_param, hsotg->params._param); \ 653 hsotg->params._param = (_def); \ 654 } \ 655 } while (0) 656 657 #define CHECK_BOOL(_param, _check) do { \ 658 if (hsotg->params._param && !(_check)) { \ 659 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \ 660 __func__, #_param, hsotg->params._param); \ 661 hsotg->params._param = false; \ 662 } \ 663 } while (0) 664 665 static void dwc2_check_params(struct dwc2_hsotg *hsotg) 666 { 667 struct dwc2_hw_params *hw = &hsotg->hw_params; 668 struct dwc2_core_params *p = &hsotg->params; 669 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); 670 671 dwc2_check_param_otg_cap(hsotg); 672 dwc2_check_param_phy_type(hsotg); 673 dwc2_check_param_speed(hsotg); 674 dwc2_check_param_phy_utmi_width(hsotg); 675 dwc2_check_param_power_down(hsotg); 676 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); 677 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); 678 CHECK_BOOL(i2c_enable, hw->i2c_enable); 679 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); 680 CHECK_BOOL(acg_enable, hw->acg_enable); 681 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); 682 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); 683 CHECK_BOOL(lpm, hw->lpm_mode); 684 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); 685 CHECK_BOOL(besl, hsotg->params.lpm); 686 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); 687 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); 688 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); 689 CHECK_BOOL(service_interval, hw->service_interval_mode); 690 CHECK_RANGE(max_packet_count, 691 15, hw->max_packet_count, 692 hw->max_packet_count); 693 CHECK_RANGE(max_transfer_size, 694 2047, hw->max_transfer_size, 695 hw->max_transfer_size); 696 697 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || 698 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 699 CHECK_BOOL(host_dma, dma_capable); 700 CHECK_BOOL(dma_desc_enable, p->host_dma); 701 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); 702 CHECK_BOOL(host_ls_low_power_phy_clk, 703 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); 704 CHECK_RANGE(host_channels, 705 1, hw->host_channels, 706 hw->host_channels); 707 CHECK_RANGE(host_rx_fifo_size, 708 16, hw->rx_fifo_size, 709 hw->rx_fifo_size); 710 CHECK_RANGE(host_nperio_tx_fifo_size, 711 16, hw->host_nperio_tx_fifo_size, 712 hw->host_nperio_tx_fifo_size); 713 CHECK_RANGE(host_perio_tx_fifo_size, 714 16, hw->host_perio_tx_fifo_size, 715 hw->host_perio_tx_fifo_size); 716 } 717 718 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || 719 (hsotg->dr_mode == USB_DR_MODE_OTG)) { 720 CHECK_BOOL(g_dma, dma_capable); 721 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); 722 CHECK_RANGE(g_rx_fifo_size, 723 16, hw->rx_fifo_size, 724 hw->rx_fifo_size); 725 CHECK_RANGE(g_np_tx_fifo_size, 726 16, hw->dev_nperio_tx_fifo_size, 727 hw->dev_nperio_tx_fifo_size); 728 dwc2_check_param_tx_fifo_sizes(hsotg); 729 } 730 } 731 732 /* 733 * Gets host hardware parameters. Forces host mode if not currently in 734 * host mode. Should be called immediately after a core soft reset in 735 * order to get the reset values. 736 */ 737 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) 738 { 739 struct dwc2_hw_params *hw = &hsotg->hw_params; 740 u32 gnptxfsiz; 741 u32 hptxfsiz; 742 743 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) 744 return; 745 746 dwc2_force_mode(hsotg, true); 747 748 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 749 hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 750 751 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 752 FIFOSIZE_DEPTH_SHIFT; 753 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> 754 FIFOSIZE_DEPTH_SHIFT; 755 } 756 757 /* 758 * Gets device hardware parameters. Forces device mode if not 759 * currently in device mode. Should be called immediately after a core 760 * soft reset in order to get the reset values. 761 */ 762 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) 763 { 764 struct dwc2_hw_params *hw = &hsotg->hw_params; 765 u32 gnptxfsiz; 766 int fifo, fifo_count; 767 768 if (hsotg->dr_mode == USB_DR_MODE_HOST) 769 return; 770 771 dwc2_force_mode(hsotg, false); 772 773 gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 774 775 fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); 776 777 for (fifo = 1; fifo <= fifo_count; fifo++) { 778 hw->g_tx_fifo_size[fifo] = 779 (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & 780 FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; 781 } 782 783 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> 784 FIFOSIZE_DEPTH_SHIFT; 785 } 786 787 /** 788 * dwc2_get_hwparams() - During device initialization, read various hardware 789 * configuration registers and interpret the contents. 790 * 791 * @hsotg: Programming view of the DWC_otg controller 792 * 793 */ 794 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) 795 { 796 struct dwc2_hw_params *hw = &hsotg->hw_params; 797 unsigned int width; 798 u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4; 799 u32 grxfsiz; 800 801 hwcfg1 = dwc2_readl(hsotg, GHWCFG1); 802 hwcfg2 = dwc2_readl(hsotg, GHWCFG2); 803 hwcfg3 = dwc2_readl(hsotg, GHWCFG3); 804 hwcfg4 = dwc2_readl(hsotg, GHWCFG4); 805 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 806 807 /* hwcfg1 */ 808 hw->dev_ep_dirs = hwcfg1; 809 810 /* hwcfg2 */ 811 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> 812 GHWCFG2_OP_MODE_SHIFT; 813 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> 814 GHWCFG2_ARCHITECTURE_SHIFT; 815 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); 816 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> 817 GHWCFG2_NUM_HOST_CHAN_SHIFT); 818 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> 819 GHWCFG2_HS_PHY_TYPE_SHIFT; 820 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> 821 GHWCFG2_FS_PHY_TYPE_SHIFT; 822 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> 823 GHWCFG2_NUM_DEV_EP_SHIFT; 824 hw->nperio_tx_q_depth = 825 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >> 826 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1; 827 hw->host_perio_tx_q_depth = 828 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >> 829 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1; 830 hw->dev_token_q_depth = 831 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >> 832 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT; 833 834 /* hwcfg3 */ 835 width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >> 836 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT; 837 hw->max_transfer_size = (1 << (width + 11)) - 1; 838 width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >> 839 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT; 840 hw->max_packet_count = (1 << (width + 4)) - 1; 841 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); 842 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> 843 GHWCFG3_DFIFO_DEPTH_SHIFT; 844 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); 845 846 /* hwcfg4 */ 847 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); 848 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> 849 GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT; 850 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> 851 GHWCFG4_NUM_IN_EPS_SHIFT; 852 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); 853 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); 854 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); 855 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> 856 GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT; 857 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); 858 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); 859 hw->service_interval_mode = !!(hwcfg4 & 860 GHWCFG4_SERVICE_INTERVAL_SUPPORTED); 861 862 /* fifo sizes */ 863 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> 864 GRXFSIZ_DEPTH_SHIFT; 865 /* 866 * Host specific hardware parameters. Reading these parameters 867 * requires the controller to be in host mode. The mode will 868 * be forced, if necessary, to read these values. 869 */ 870 dwc2_get_host_hwparams(hsotg); 871 dwc2_get_dev_hwparams(hsotg); 872 873 return 0; 874 } 875 876 typedef void (*set_params_cb)(struct dwc2_hsotg *data); 877 878 int dwc2_init_params(struct dwc2_hsotg *hsotg) 879 { 880 const struct of_device_id *match; 881 set_params_cb set_params; 882 883 dwc2_set_default_params(hsotg); 884 dwc2_get_device_properties(hsotg); 885 886 match = of_match_device(dwc2_of_match_table, hsotg->dev); 887 if (match && match->data) { 888 set_params = match->data; 889 set_params(hsotg); 890 } else { 891 const struct acpi_device_id *amatch; 892 893 amatch = acpi_match_device(dwc2_acpi_match, hsotg->dev); 894 if (amatch && amatch->driver_data) { 895 set_params = (set_params_cb)amatch->driver_data; 896 set_params(hsotg); 897 } 898 } 899 900 dwc2_check_params(hsotg); 901 902 return 0; 903 } 904