xref: /openbmc/linux/drivers/usb/dwc2/hw.h (revision b34e08d5)
1 /*
2  * hw.h - DesignWare HS OTG Controller hardware definitions
3  *
4  * Copyright 2004-2013 Synopsys, Inc.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer,
11  *    without modification.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The names of the above-listed copyright holders may not be used
16  *    to endorse or promote products derived from this software without
17  *    specific prior written permission.
18  *
19  * ALTERNATIVELY, this software may be distributed under the terms of the
20  * GNU General Public License ("GPL") as published by the Free Software
21  * Foundation; either version 2 of the License, or (at your option) any
22  * later version.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 #ifndef __DWC2_HW_H__
38 #define __DWC2_HW_H__
39 
40 #define HSOTG_REG(x)	(x)
41 
42 #define GOTGCTL				HSOTG_REG(0x000)
43 #define GOTGCTL_CHIRPEN			(1 << 27)
44 #define GOTGCTL_MULT_VALID_BC_MASK	(0x1f << 22)
45 #define GOTGCTL_MULT_VALID_BC_SHIFT	22
46 #define GOTGCTL_OTGVER			(1 << 20)
47 #define GOTGCTL_BSESVLD			(1 << 19)
48 #define GOTGCTL_ASESVLD			(1 << 18)
49 #define GOTGCTL_DBNC_SHORT		(1 << 17)
50 #define GOTGCTL_CONID_B			(1 << 16)
51 #define GOTGCTL_DEVHNPEN		(1 << 11)
52 #define GOTGCTL_HSTSETHNPEN		(1 << 10)
53 #define GOTGCTL_HNPREQ			(1 << 9)
54 #define GOTGCTL_HSTNEGSCS		(1 << 8)
55 #define GOTGCTL_SESREQ			(1 << 1)
56 #define GOTGCTL_SESREQSCS		(1 << 0)
57 
58 #define GOTGINT				HSOTG_REG(0x004)
59 #define GOTGINT_DBNCE_DONE		(1 << 19)
60 #define GOTGINT_A_DEV_TOUT_CHG		(1 << 18)
61 #define GOTGINT_HST_NEG_DET		(1 << 17)
62 #define GOTGINT_HST_NEG_SUC_STS_CHNG	(1 << 9)
63 #define GOTGINT_SES_REQ_SUC_STS_CHNG	(1 << 8)
64 #define GOTGINT_SES_END_DET		(1 << 2)
65 
66 #define GAHBCFG				HSOTG_REG(0x008)
67 #define GAHBCFG_AHB_SINGLE		(1 << 23)
68 #define GAHBCFG_NOTI_ALL_DMA_WRIT	(1 << 22)
69 #define GAHBCFG_REM_MEM_SUPP		(1 << 21)
70 #define GAHBCFG_P_TXF_EMP_LVL		(1 << 8)
71 #define GAHBCFG_NP_TXF_EMP_LVL		(1 << 7)
72 #define GAHBCFG_DMA_EN			(1 << 5)
73 #define GAHBCFG_HBSTLEN_MASK		(0xf << 1)
74 #define GAHBCFG_HBSTLEN_SHIFT		1
75 #define GAHBCFG_HBSTLEN_SINGLE		0
76 #define GAHBCFG_HBSTLEN_INCR		1
77 #define GAHBCFG_HBSTLEN_INCR4		3
78 #define GAHBCFG_HBSTLEN_INCR8		5
79 #define GAHBCFG_HBSTLEN_INCR16		7
80 #define GAHBCFG_GLBL_INTR_EN		(1 << 0)
81 #define GAHBCFG_CTRL_MASK		(GAHBCFG_P_TXF_EMP_LVL | \
82 					 GAHBCFG_NP_TXF_EMP_LVL | \
83 					 GAHBCFG_DMA_EN | \
84 					 GAHBCFG_GLBL_INTR_EN)
85 
86 #define GUSBCFG				HSOTG_REG(0x00C)
87 #define GUSBCFG_FORCEDEVMODE		(1 << 30)
88 #define GUSBCFG_FORCEHOSTMODE		(1 << 29)
89 #define GUSBCFG_TXENDDELAY		(1 << 28)
90 #define GUSBCFG_ICTRAFFICPULLREMOVE	(1 << 27)
91 #define GUSBCFG_ICUSBCAP		(1 << 26)
92 #define GUSBCFG_ULPI_INT_PROT_DIS	(1 << 25)
93 #define GUSBCFG_INDICATORPASSTHROUGH	(1 << 24)
94 #define GUSBCFG_INDICATORCOMPLEMENT	(1 << 23)
95 #define GUSBCFG_TERMSELDLPULSE		(1 << 22)
96 #define GUSBCFG_ULPI_INT_VBUS_IND	(1 << 21)
97 #define GUSBCFG_ULPI_EXT_VBUS_DRV	(1 << 20)
98 #define GUSBCFG_ULPI_CLK_SUSP_M		(1 << 19)
99 #define GUSBCFG_ULPI_AUTO_RES		(1 << 18)
100 #define GUSBCFG_ULPI_FS_LS		(1 << 17)
101 #define GUSBCFG_OTG_UTMI_FS_SEL		(1 << 16)
102 #define GUSBCFG_PHY_LP_CLK_SEL		(1 << 15)
103 #define GUSBCFG_USBTRDTIM_MASK		(0xf << 10)
104 #define GUSBCFG_USBTRDTIM_SHIFT		10
105 #define GUSBCFG_HNPCAP			(1 << 9)
106 #define GUSBCFG_SRPCAP			(1 << 8)
107 #define GUSBCFG_DDRSEL			(1 << 7)
108 #define GUSBCFG_PHYSEL			(1 << 6)
109 #define GUSBCFG_FSINTF			(1 << 5)
110 #define GUSBCFG_ULPI_UTMI_SEL		(1 << 4)
111 #define GUSBCFG_PHYIF16			(1 << 3)
112 #define GUSBCFG_TOUTCAL_MASK		(0x7 << 0)
113 #define GUSBCFG_TOUTCAL_SHIFT		0
114 #define GUSBCFG_TOUTCAL_LIMIT		0x7
115 #define GUSBCFG_TOUTCAL(_x)		((_x) << 0)
116 
117 #define GRSTCTL				HSOTG_REG(0x010)
118 #define GRSTCTL_AHBIDLE			(1 << 31)
119 #define GRSTCTL_DMAREQ			(1 << 30)
120 #define GRSTCTL_TXFNUM_MASK		(0x1f << 6)
121 #define GRSTCTL_TXFNUM_SHIFT		6
122 #define GRSTCTL_TXFNUM_LIMIT		0x1f
123 #define GRSTCTL_TXFNUM(_x)		((_x) << 6)
124 #define GRSTCTL_TXFFLSH			(1 << 5)
125 #define GRSTCTL_RXFFLSH			(1 << 4)
126 #define GRSTCTL_IN_TKNQ_FLSH		(1 << 3)
127 #define GRSTCTL_FRMCNTRRST		(1 << 2)
128 #define GRSTCTL_HSFTRST			(1 << 1)
129 #define GRSTCTL_CSFTRST			(1 << 0)
130 
131 #define GINTSTS				HSOTG_REG(0x014)
132 #define GINTMSK				HSOTG_REG(0x018)
133 #define GINTSTS_WKUPINT			(1 << 31)
134 #define GINTSTS_SESSREQINT		(1 << 30)
135 #define GINTSTS_DISCONNINT		(1 << 29)
136 #define GINTSTS_CONIDSTSCHNG		(1 << 28)
137 #define GINTSTS_LPMTRANRCVD		(1 << 27)
138 #define GINTSTS_PTXFEMP			(1 << 26)
139 #define GINTSTS_HCHINT			(1 << 25)
140 #define GINTSTS_PRTINT			(1 << 24)
141 #define GINTSTS_RESETDET		(1 << 23)
142 #define GINTSTS_FET_SUSP		(1 << 22)
143 #define GINTSTS_INCOMPL_IP		(1 << 21)
144 #define GINTSTS_INCOMPL_SOIN		(1 << 20)
145 #define GINTSTS_OEPINT			(1 << 19)
146 #define GINTSTS_IEPINT			(1 << 18)
147 #define GINTSTS_EPMIS			(1 << 17)
148 #define GINTSTS_RESTOREDONE		(1 << 16)
149 #define GINTSTS_EOPF			(1 << 15)
150 #define GINTSTS_ISOUTDROP		(1 << 14)
151 #define GINTSTS_ENUMDONE		(1 << 13)
152 #define GINTSTS_USBRST			(1 << 12)
153 #define GINTSTS_USBSUSP			(1 << 11)
154 #define GINTSTS_ERLYSUSP		(1 << 10)
155 #define GINTSTS_I2CINT			(1 << 9)
156 #define GINTSTS_ULPI_CK_INT		(1 << 8)
157 #define GINTSTS_GOUTNAKEFF		(1 << 7)
158 #define GINTSTS_GINNAKEFF		(1 << 6)
159 #define GINTSTS_NPTXFEMP		(1 << 5)
160 #define GINTSTS_RXFLVL			(1 << 4)
161 #define GINTSTS_SOF			(1 << 3)
162 #define GINTSTS_OTGINT			(1 << 2)
163 #define GINTSTS_MODEMIS			(1 << 1)
164 #define GINTSTS_CURMODE_HOST		(1 << 0)
165 
166 #define GRXSTSR				HSOTG_REG(0x01C)
167 #define GRXSTSP				HSOTG_REG(0x020)
168 #define GRXSTS_FN_MASK			(0x7f << 25)
169 #define GRXSTS_FN_SHIFT			25
170 #define GRXSTS_PKTSTS_MASK		(0xf << 17)
171 #define GRXSTS_PKTSTS_SHIFT		17
172 #define GRXSTS_PKTSTS_GLOBALOUTNAK	1
173 #define GRXSTS_PKTSTS_OUTRX		2
174 #define GRXSTS_PKTSTS_HCHIN		2
175 #define GRXSTS_PKTSTS_OUTDONE		3
176 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP	3
177 #define GRXSTS_PKTSTS_SETUPDONE		4
178 #define GRXSTS_PKTSTS_DATATOGGLEERR	5
179 #define GRXSTS_PKTSTS_SETUPRX		6
180 #define GRXSTS_PKTSTS_HCHHALTED		7
181 #define GRXSTS_HCHNUM_MASK		(0xf << 0)
182 #define GRXSTS_HCHNUM_SHIFT		0
183 #define GRXSTS_DPID_MASK		(0x3 << 15)
184 #define GRXSTS_DPID_SHIFT		15
185 #define GRXSTS_BYTECNT_MASK		(0x7ff << 4)
186 #define GRXSTS_BYTECNT_SHIFT		4
187 #define GRXSTS_EPNUM_MASK		(0xf << 0)
188 #define GRXSTS_EPNUM_SHIFT		0
189 
190 #define GRXFSIZ				HSOTG_REG(0x024)
191 #define GRXFSIZ_DEPTH_MASK		(0xffff << 0)
192 #define GRXFSIZ_DEPTH_SHIFT		0
193 
194 #define GNPTXFSIZ			HSOTG_REG(0x028)
195 /* Use FIFOSIZE_* constants to access this register */
196 
197 #define GNPTXSTS			HSOTG_REG(0x02C)
198 #define GNPTXSTS_NP_TXQ_TOP_MASK		(0x7f << 24)
199 #define GNPTXSTS_NP_TXQ_TOP_SHIFT		24
200 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK		(0xff << 16)
201 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT		16
202 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v)	(((_v) >> 16) & 0xff)
203 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK		(0xffff << 0)
204 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT		0
205 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v)	(((_v) >> 0) & 0xffff)
206 
207 #define GI2CCTL				HSOTG_REG(0x0030)
208 #define GI2CCTL_BSYDNE			(1 << 31)
209 #define GI2CCTL_RW			(1 << 30)
210 #define GI2CCTL_I2CDATSE0		(1 << 28)
211 #define GI2CCTL_I2CDEVADDR_MASK		(0x3 << 26)
212 #define GI2CCTL_I2CDEVADDR_SHIFT	26
213 #define GI2CCTL_I2CSUSPCTL		(1 << 25)
214 #define GI2CCTL_ACK			(1 << 24)
215 #define GI2CCTL_I2CEN			(1 << 23)
216 #define GI2CCTL_ADDR_MASK		(0x7f << 16)
217 #define GI2CCTL_ADDR_SHIFT		16
218 #define GI2CCTL_REGADDR_MASK		(0xff << 8)
219 #define GI2CCTL_REGADDR_SHIFT		8
220 #define GI2CCTL_RWDATA_MASK		(0xff << 0)
221 #define GI2CCTL_RWDATA_SHIFT		0
222 
223 #define GPVNDCTL			HSOTG_REG(0x0034)
224 #define GGPIO				HSOTG_REG(0x0038)
225 #define GUID				HSOTG_REG(0x003c)
226 #define GSNPSID				HSOTG_REG(0x0040)
227 #define GHWCFG1				HSOTG_REG(0x0044)
228 
229 #define GHWCFG2				HSOTG_REG(0x0048)
230 #define GHWCFG2_OTG_ENABLE_IC_USB		(1 << 31)
231 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1f << 26)
232 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT		26
233 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK	(0x3 << 24)
234 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT	24
235 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK	(0x3 << 22)
236 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT	22
237 #define GHWCFG2_MULTI_PROC_INT			(1 << 20)
238 #define GHWCFG2_DYNAMIC_FIFO			(1 << 19)
239 #define GHWCFG2_PERIO_EP_SUPPORTED		(1 << 18)
240 #define GHWCFG2_NUM_HOST_CHAN_MASK		(0xf << 14)
241 #define GHWCFG2_NUM_HOST_CHAN_SHIFT		14
242 #define GHWCFG2_NUM_DEV_EP_MASK			(0xf << 10)
243 #define GHWCFG2_NUM_DEV_EP_SHIFT		10
244 #define GHWCFG2_FS_PHY_TYPE_MASK		(0x3 << 8)
245 #define GHWCFG2_FS_PHY_TYPE_SHIFT		8
246 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED	0
247 #define GHWCFG2_FS_PHY_TYPE_DEDICATED		1
248 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI		2
249 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI		3
250 #define GHWCFG2_HS_PHY_TYPE_MASK		(0x3 << 6)
251 #define GHWCFG2_HS_PHY_TYPE_SHIFT		6
252 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED	0
253 #define GHWCFG2_HS_PHY_TYPE_UTMI		1
254 #define GHWCFG2_HS_PHY_TYPE_ULPI		2
255 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI		3
256 #define GHWCFG2_POINT2POINT			(1 << 5)
257 #define GHWCFG2_ARCHITECTURE_MASK		(0x3 << 3)
258 #define GHWCFG2_ARCHITECTURE_SHIFT		3
259 #define GHWCFG2_SLAVE_ONLY_ARCH			0
260 #define GHWCFG2_EXT_DMA_ARCH			1
261 #define GHWCFG2_INT_DMA_ARCH			2
262 #define GHWCFG2_OP_MODE_MASK			(0x7 << 0)
263 #define GHWCFG2_OP_MODE_SHIFT			0
264 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE		0
265 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE	1
266 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE	2
267 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE	3
268 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE	4
269 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST	5
270 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST	6
271 #define GHWCFG2_OP_MODE_UNDEFINED		7
272 
273 #define GHWCFG3				HSOTG_REG(0x004c)
274 #define GHWCFG3_DFIFO_DEPTH_MASK		(0xffff << 16)
275 #define GHWCFG3_DFIFO_DEPTH_SHIFT		16
276 #define GHWCFG3_OTG_LPM_EN			(1 << 15)
277 #define GHWCFG3_BC_SUPPORT			(1 << 14)
278 #define GHWCFG3_OTG_ENABLE_HSIC			(1 << 13)
279 #define GHWCFG3_ADP_SUPP			(1 << 12)
280 #define GHWCFG3_SYNCH_RESET_TYPE		(1 << 11)
281 #define GHWCFG3_OPTIONAL_FEATURES		(1 << 10)
282 #define GHWCFG3_VENDOR_CTRL_IF			(1 << 9)
283 #define GHWCFG3_I2C				(1 << 8)
284 #define GHWCFG3_OTG_FUNC			(1 << 7)
285 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK	(0x7 << 4)
286 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT	4
287 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK	(0xf << 0)
288 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT	0
289 
290 #define GHWCFG4				HSOTG_REG(0x0050)
291 #define GHWCFG4_DESC_DMA_DYN			(1 << 31)
292 #define GHWCFG4_DESC_DMA			(1 << 30)
293 #define GHWCFG4_NUM_IN_EPS_MASK			(0xf << 26)
294 #define GHWCFG4_NUM_IN_EPS_SHIFT		26
295 #define GHWCFG4_DED_FIFO_EN			(1 << 25)
296 #define GHWCFG4_SESSION_END_FILT_EN		(1 << 24)
297 #define GHWCFG4_B_VALID_FILT_EN			(1 << 23)
298 #define GHWCFG4_A_VALID_FILT_EN			(1 << 22)
299 #define GHWCFG4_VBUS_VALID_FILT_EN		(1 << 21)
300 #define GHWCFG4_IDDIG_FILT_EN			(1 << 20)
301 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK	(0xf << 16)
302 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT	16
303 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK	(0x3 << 14)
304 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT	14
305 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8		0
306 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16		1
307 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16	2
308 #define GHWCFG4_XHIBER				(1 << 7)
309 #define GHWCFG4_HIBER				(1 << 6)
310 #define GHWCFG4_MIN_AHB_FREQ			(1 << 5)
311 #define GHWCFG4_POWER_OPTIMIZ			(1 << 4)
312 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK	(0xf << 0)
313 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT	0
314 
315 #define GLPMCFG				HSOTG_REG(0x0054)
316 #define GLPMCFG_INV_SEL_HSIC		(1 << 31)
317 #define GLPMCFG_HSIC_CONNECT		(1 << 30)
318 #define GLPMCFG_RETRY_COUNT_STS_MASK	(0x7 << 25)
319 #define GLPMCFG_RETRY_COUNT_STS_SHIFT	25
320 #define GLPMCFG_SEND_LPM		(1 << 24)
321 #define GLPMCFG_RETRY_COUNT_MASK	(0x7 << 21)
322 #define GLPMCFG_RETRY_COUNT_SHIFT	21
323 #define GLPMCFG_LPM_CHAN_INDEX_MASK	(0xf << 17)
324 #define GLPMCFG_LPM_CHAN_INDEX_SHIFT	17
325 #define GLPMCFG_SLEEP_STATE_RESUMEOK	(1 << 16)
326 #define GLPMCFG_PRT_SLEEP_STS		(1 << 15)
327 #define GLPMCFG_LPM_RESP_MASK		(0x3 << 13)
328 #define GLPMCFG_LPM_RESP_SHIFT		13
329 #define GLPMCFG_HIRD_THRES_MASK		(0x1f << 8)
330 #define GLPMCFG_HIRD_THRES_SHIFT	8
331 #define GLPMCFG_HIRD_THRES_EN			(0x10 << 8)
332 #define GLPMCFG_EN_UTMI_SLEEP		(1 << 7)
333 #define GLPMCFG_REM_WKUP_EN		(1 << 6)
334 #define GLPMCFG_HIRD_MASK		(0xf << 2)
335 #define GLPMCFG_HIRD_SHIFT		2
336 #define GLPMCFG_APPL_RESP		(1 << 1)
337 #define GLPMCFG_LPM_CAP_EN		(1 << 0)
338 
339 #define GPWRDN				HSOTG_REG(0x0058)
340 #define GPWRDN_MULT_VAL_ID_BC_MASK	(0x1f << 24)
341 #define GPWRDN_MULT_VAL_ID_BC_SHIFT	24
342 #define GPWRDN_ADP_INT			(1 << 23)
343 #define GPWRDN_BSESSVLD			(1 << 22)
344 #define GPWRDN_IDSTS			(1 << 21)
345 #define GPWRDN_LINESTATE_MASK		(0x3 << 19)
346 #define GPWRDN_LINESTATE_SHIFT		19
347 #define GPWRDN_STS_CHGINT_MSK		(1 << 18)
348 #define GPWRDN_STS_CHGINT		(1 << 17)
349 #define GPWRDN_SRP_DET_MSK		(1 << 16)
350 #define GPWRDN_SRP_DET			(1 << 15)
351 #define GPWRDN_CONNECT_DET_MSK		(1 << 14)
352 #define GPWRDN_CONNECT_DET		(1 << 13)
353 #define GPWRDN_DISCONN_DET_MSK		(1 << 12)
354 #define GPWRDN_DISCONN_DET		(1 << 11)
355 #define GPWRDN_RST_DET_MSK		(1 << 10)
356 #define GPWRDN_RST_DET			(1 << 9)
357 #define GPWRDN_LNSTSCHG_MSK		(1 << 8)
358 #define GPWRDN_LNSTSCHG			(1 << 7)
359 #define GPWRDN_DIS_VBUS			(1 << 6)
360 #define GPWRDN_PWRDNSWTCH		(1 << 5)
361 #define GPWRDN_PWRDNRSTN		(1 << 4)
362 #define GPWRDN_PWRDNCLMP		(1 << 3)
363 #define GPWRDN_RESTORE			(1 << 2)
364 #define GPWRDN_PMUACTV			(1 << 1)
365 #define GPWRDN_PMUINTSEL		(1 << 0)
366 
367 #define GDFIFOCFG			HSOTG_REG(0x005c)
368 #define GDFIFOCFG_EPINFOBASE_MASK	(0xffff << 16)
369 #define GDFIFOCFG_EPINFOBASE_SHIFT	16
370 #define GDFIFOCFG_GDFIFOCFG_MASK	(0xffff << 0)
371 #define GDFIFOCFG_GDFIFOCFG_SHIFT	0
372 
373 #define ADPCTL				HSOTG_REG(0x0060)
374 #define ADPCTL_AR_MASK			(0x3 << 27)
375 #define ADPCTL_AR_SHIFT			27
376 #define ADPCTL_ADP_TMOUT_INT_MSK	(1 << 26)
377 #define ADPCTL_ADP_SNS_INT_MSK		(1 << 25)
378 #define ADPCTL_ADP_PRB_INT_MSK		(1 << 24)
379 #define ADPCTL_ADP_TMOUT_INT		(1 << 23)
380 #define ADPCTL_ADP_SNS_INT		(1 << 22)
381 #define ADPCTL_ADP_PRB_INT		(1 << 21)
382 #define ADPCTL_ADPENA			(1 << 20)
383 #define ADPCTL_ADPRES			(1 << 19)
384 #define ADPCTL_ENASNS			(1 << 18)
385 #define ADPCTL_ENAPRB			(1 << 17)
386 #define ADPCTL_RTIM_MASK		(0x7ff << 6)
387 #define ADPCTL_RTIM_SHIFT		6
388 #define ADPCTL_PRB_PER_MASK		(0x3 << 4)
389 #define ADPCTL_PRB_PER_SHIFT		4
390 #define ADPCTL_PRB_DELTA_MASK		(0x3 << 2)
391 #define ADPCTL_PRB_DELTA_SHIFT		2
392 #define ADPCTL_PRB_DSCHRG_MASK		(0x3 << 0)
393 #define ADPCTL_PRB_DSCHRG_SHIFT		0
394 
395 #define HPTXFSIZ			HSOTG_REG(0x100)
396 /* Use FIFOSIZE_* constants to access this register */
397 
398 #define DPTXFSIZN(_a)			HSOTG_REG(0x104 + (((_a) - 1) * 4))
399 /* Use FIFOSIZE_* constants to access this register */
400 
401 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
402 #define FIFOSIZE_DEPTH_MASK		(0xffff << 16)
403 #define FIFOSIZE_DEPTH_SHIFT		16
404 #define FIFOSIZE_STARTADDR_MASK		(0xffff << 0)
405 #define FIFOSIZE_STARTADDR_SHIFT	0
406 
407 /* Device mode registers */
408 
409 #define DCFG				HSOTG_REG(0x800)
410 #define DCFG_EPMISCNT_MASK		(0x1f << 18)
411 #define DCFG_EPMISCNT_SHIFT		18
412 #define DCFG_EPMISCNT_LIMIT		0x1f
413 #define DCFG_EPMISCNT(_x)		((_x) << 18)
414 #define DCFG_PERFRINT_MASK		(0x3 << 11)
415 #define DCFG_PERFRINT_SHIFT		11
416 #define DCFG_PERFRINT_LIMIT		0x3
417 #define DCFG_PERFRINT(_x)		((_x) << 11)
418 #define DCFG_DEVADDR_MASK		(0x7f << 4)
419 #define DCFG_DEVADDR_SHIFT		4
420 #define DCFG_DEVADDR_LIMIT		0x7f
421 #define DCFG_DEVADDR(_x)		((_x) << 4)
422 #define DCFG_NZ_STS_OUT_HSHK		(1 << 2)
423 #define DCFG_DEVSPD_MASK		(0x3 << 0)
424 #define DCFG_DEVSPD_SHIFT		0
425 #define DCFG_DEVSPD_HS			0
426 #define DCFG_DEVSPD_FS			1
427 #define DCFG_DEVSPD_LS			2
428 #define DCFG_DEVSPD_FS48		3
429 
430 #define DCTL				HSOTG_REG(0x804)
431 #define DCTL_PWRONPRGDONE		(1 << 11)
432 #define DCTL_CGOUTNAK			(1 << 10)
433 #define DCTL_SGOUTNAK			(1 << 9)
434 #define DCTL_CGNPINNAK			(1 << 8)
435 #define DCTL_SGNPINNAK			(1 << 7)
436 #define DCTL_TSTCTL_MASK		(0x7 << 4)
437 #define DCTL_TSTCTL_SHIFT		4
438 #define DCTL_GOUTNAKSTS			(1 << 3)
439 #define DCTL_GNPINNAKSTS		(1 << 2)
440 #define DCTL_SFTDISCON			(1 << 1)
441 #define DCTL_RMTWKUPSIG			(1 << 0)
442 
443 #define DSTS				HSOTG_REG(0x808)
444 #define DSTS_SOFFN_MASK			(0x3fff << 8)
445 #define DSTS_SOFFN_SHIFT		8
446 #define DSTS_SOFFN_LIMIT		0x3fff
447 #define DSTS_SOFFN(_x)			((_x) << 8)
448 #define DSTS_ERRATICERR			(1 << 3)
449 #define DSTS_ENUMSPD_MASK		(0x3 << 1)
450 #define DSTS_ENUMSPD_SHIFT		1
451 #define DSTS_ENUMSPD_HS			0
452 #define DSTS_ENUMSPD_FS			1
453 #define DSTS_ENUMSPD_LS			2
454 #define DSTS_ENUMSPD_FS48		3
455 #define DSTS_SUSPSTS			(1 << 0)
456 
457 #define DIEPMSK				HSOTG_REG(0x810)
458 #define DIEPMSK_TXFIFOEMPTY		(1 << 7)
459 #define DIEPMSK_INEPNAKEFFMSK		(1 << 6)
460 #define DIEPMSK_INTKNEPMISMSK		(1 << 5)
461 #define DIEPMSK_INTKNTXFEMPMSK		(1 << 4)
462 #define DIEPMSK_TIMEOUTMSK		(1 << 3)
463 #define DIEPMSK_AHBERRMSK		(1 << 2)
464 #define DIEPMSK_EPDISBLDMSK		(1 << 1)
465 #define DIEPMSK_XFERCOMPLMSK		(1 << 0)
466 
467 #define DOEPMSK				HSOTG_REG(0x814)
468 #define DOEPMSK_BACK2BACKSETUP		(1 << 6)
469 #define DOEPMSK_OUTTKNEPDISMSK		(1 << 4)
470 #define DOEPMSK_SETUPMSK		(1 << 3)
471 #define DOEPMSK_AHBERRMSK		(1 << 2)
472 #define DOEPMSK_EPDISBLDMSK		(1 << 1)
473 #define DOEPMSK_XFERCOMPLMSK		(1 << 0)
474 
475 #define DAINT				HSOTG_REG(0x818)
476 #define DAINTMSK			HSOTG_REG(0x81C)
477 #define DAINT_OUTEP_SHIFT		16
478 #define DAINT_OUTEP(_x)			(1 << ((_x) + 16))
479 #define DAINT_INEP(_x)			(1 << (_x))
480 
481 #define DTKNQR1				HSOTG_REG(0x820)
482 #define DTKNQR2				HSOTG_REG(0x824)
483 #define DTKNQR3				HSOTG_REG(0x830)
484 #define DTKNQR4				HSOTG_REG(0x834)
485 
486 #define DVBUSDIS			HSOTG_REG(0x828)
487 #define DVBUSPULSE			HSOTG_REG(0x82C)
488 
489 #define DIEPCTL0			HSOTG_REG(0x900)
490 #define DIEPCTL(_a)			HSOTG_REG(0x900 + ((_a) * 0x20))
491 
492 #define DOEPCTL0			HSOTG_REG(0xB00)
493 #define DOEPCTL(_a)			HSOTG_REG(0xB00 + ((_a) * 0x20))
494 
495 /* EP0 specialness:
496  * bits[29..28] - reserved (no SetD0PID, SetD1PID)
497  * bits[25..22] - should always be zero, this isn't a periodic endpoint
498  * bits[10..0]  - MPS setting different for EP0
499  */
500 #define D0EPCTL_MPS_MASK		(0x3 << 0)
501 #define D0EPCTL_MPS_SHIFT		0
502 #define D0EPCTL_MPS_64			0
503 #define D0EPCTL_MPS_32			1
504 #define D0EPCTL_MPS_16			2
505 #define D0EPCTL_MPS_8			3
506 
507 #define DXEPCTL_EPENA			(1 << 31)
508 #define DXEPCTL_EPDIS			(1 << 30)
509 #define DXEPCTL_SETD1PID		(1 << 29)
510 #define DXEPCTL_SETODDFR		(1 << 29)
511 #define DXEPCTL_SETD0PID		(1 << 28)
512 #define DXEPCTL_SETEVENFR		(1 << 28)
513 #define DXEPCTL_SNAK			(1 << 27)
514 #define DXEPCTL_CNAK			(1 << 26)
515 #define DXEPCTL_TXFNUM_MASK		(0xf << 22)
516 #define DXEPCTL_TXFNUM_SHIFT		22
517 #define DXEPCTL_TXFNUM_LIMIT		0xf
518 #define DXEPCTL_TXFNUM(_x)		((_x) << 22)
519 #define DXEPCTL_STALL			(1 << 21)
520 #define DXEPCTL_SNP			(1 << 20)
521 #define DXEPCTL_EPTYPE_MASK		(0x3 << 18)
522 #define DXEPCTL_EPTYPE_SHIFT		18
523 #define DXEPCTL_EPTYPE_CONTROL		0
524 #define DXEPCTL_EPTYPE_ISO		1
525 #define DXEPCTL_EPTYPE_BULK		2
526 #define DXEPCTL_EPTYPE_INTTERUPT	3
527 #define DXEPCTL_NAKSTS			(1 << 17)
528 #define DXEPCTL_DPID			(1 << 16)
529 #define DXEPCTL_EOFRNUM			(1 << 16)
530 #define DXEPCTL_USBACTEP		(1 << 15)
531 #define DXEPCTL_NEXTEP_MASK		(0xf << 11)
532 #define DXEPCTL_NEXTEP_SHIFT		11
533 #define DXEPCTL_NEXTEP_LIMIT		0xf
534 #define DXEPCTL_NEXTEP(_x)		((_x) << 11)
535 #define DXEPCTL_MPS_MASK		(0x7ff << 0)
536 #define DXEPCTL_MPS_SHIFT		0
537 #define DXEPCTL_MPS_LIMIT		0x7ff
538 #define DXEPCTL_MPS(_x)			((_x) << 0)
539 
540 #define DIEPINT(_a)			HSOTG_REG(0x908 + ((_a) * 0x20))
541 #define DOEPINT(_a)			HSOTG_REG(0xB08 + ((_a) * 0x20))
542 #define DXEPINT_INEPNAKEFF		(1 << 6)
543 #define DXEPINT_BACK2BACKSETUP		(1 << 6)
544 #define DXEPINT_INTKNEPMIS		(1 << 5)
545 #define DXEPINT_INTKNTXFEMP		(1 << 4)
546 #define DXEPINT_OUTTKNEPDIS		(1 << 4)
547 #define DXEPINT_TIMEOUT			(1 << 3)
548 #define DXEPINT_SETUP			(1 << 3)
549 #define DXEPINT_AHBERR			(1 << 2)
550 #define DXEPINT_EPDISBLD		(1 << 1)
551 #define DXEPINT_XFERCOMPL		(1 << 0)
552 
553 #define DIEPTSIZ0			HSOTG_REG(0x910)
554 #define DIEPTSIZ0_PKTCNT_MASK		(0x3 << 19)
555 #define DIEPTSIZ0_PKTCNT_SHIFT		19
556 #define DIEPTSIZ0_PKTCNT_LIMIT		0x3
557 #define DIEPTSIZ0_PKTCNT(_x)		((_x) << 19)
558 #define DIEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
559 #define DIEPTSIZ0_XFERSIZE_SHIFT	0
560 #define DIEPTSIZ0_XFERSIZE_LIMIT	0x7f
561 #define DIEPTSIZ0_XFERSIZE(_x)		((_x) << 0)
562 
563 #define DOEPTSIZ0			HSOTG_REG(0xB10)
564 #define DOEPTSIZ0_SUPCNT_MASK		(0x3 << 29)
565 #define DOEPTSIZ0_SUPCNT_SHIFT		29
566 #define DOEPTSIZ0_SUPCNT_LIMIT		0x3
567 #define DOEPTSIZ0_SUPCNT(_x)		((_x) << 29)
568 #define DOEPTSIZ0_PKTCNT		(1 << 19)
569 #define DOEPTSIZ0_XFERSIZE_MASK		(0x7f << 0)
570 #define DOEPTSIZ0_XFERSIZE_SHIFT	0
571 
572 #define DIEPTSIZ(_a)			HSOTG_REG(0x910 + ((_a) * 0x20))
573 #define DOEPTSIZ(_a)			HSOTG_REG(0xB10 + ((_a) * 0x20))
574 #define DXEPTSIZ_MC_MASK		(0x3 << 29)
575 #define DXEPTSIZ_MC_SHIFT		29
576 #define DXEPTSIZ_MC_LIMIT		0x3
577 #define DXEPTSIZ_MC(_x)			((_x) << 29)
578 #define DXEPTSIZ_PKTCNT_MASK		(0x3ff << 19)
579 #define DXEPTSIZ_PKTCNT_SHIFT		19
580 #define DXEPTSIZ_PKTCNT_LIMIT		0x3ff
581 #define DXEPTSIZ_PKTCNT_GET(_v)		(((_v) >> 19) & 0x3ff)
582 #define DXEPTSIZ_PKTCNT(_x)		((_x) << 19)
583 #define DXEPTSIZ_XFERSIZE_MASK		(0x7ffff << 0)
584 #define DXEPTSIZ_XFERSIZE_SHIFT		0
585 #define DXEPTSIZ_XFERSIZE_LIMIT		0x7ffff
586 #define DXEPTSIZ_XFERSIZE_GET(_v)	(((_v) >> 0) & 0x7ffff)
587 #define DXEPTSIZ_XFERSIZE(_x)		((_x) << 0)
588 
589 #define DIEPDMA(_a)			HSOTG_REG(0x914 + ((_a) * 0x20))
590 #define DOEPDMA(_a)			HSOTG_REG(0xB14 + ((_a) * 0x20))
591 
592 #define DTXFSTS(_a)			HSOTG_REG(0x918 + ((_a) * 0x20))
593 
594 #define PCGCTL				HSOTG_REG(0x0e00)
595 #define PCGCTL_IF_DEV_MODE		(1 << 31)
596 #define PCGCTL_P2HD_PRT_SPD_MASK	(0x3 << 29)
597 #define PCGCTL_P2HD_PRT_SPD_SHIFT	29
598 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3 << 27)
599 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT	27
600 #define PCGCTL_MAC_DEV_ADDR_MASK	(0x7f << 20)
601 #define PCGCTL_MAC_DEV_ADDR_SHIFT	20
602 #define PCGCTL_MAX_TERMSEL		(1 << 19)
603 #define PCGCTL_MAX_XCVRSELECT_MASK	(0x3 << 17)
604 #define PCGCTL_MAX_XCVRSELECT_SHIFT	17
605 #define PCGCTL_PORT_POWER		(1 << 16)
606 #define PCGCTL_PRT_CLK_SEL_MASK		(0x3 << 14)
607 #define PCGCTL_PRT_CLK_SEL_SHIFT	14
608 #define PCGCTL_ESS_REG_RESTORED		(1 << 13)
609 #define PCGCTL_EXTND_HIBER_SWITCH	(1 << 12)
610 #define PCGCTL_EXTND_HIBER_PWRCLMP	(1 << 11)
611 #define PCGCTL_ENBL_EXTND_HIBER		(1 << 10)
612 #define PCGCTL_RESTOREMODE		(1 << 9)
613 #define PCGCTL_RESETAFTSUSP		(1 << 8)
614 #define PCGCTL_DEEP_SLEEP		(1 << 7)
615 #define PCGCTL_PHY_IN_SLEEP		(1 << 6)
616 #define PCGCTL_ENBL_SLEEP_GATING	(1 << 5)
617 #define PCGCTL_RSTPDWNMODULE		(1 << 3)
618 #define PCGCTL_PWRCLMP			(1 << 2)
619 #define PCGCTL_GATEHCLK			(1 << 1)
620 #define PCGCTL_STOPPCLK			(1 << 0)
621 
622 #define EPFIFO(_a)			HSOTG_REG(0x1000 + ((_a) * 0x1000))
623 
624 /* Host Mode Registers */
625 
626 #define HCFG				HSOTG_REG(0x0400)
627 #define HCFG_MODECHTIMEN		(1 << 31)
628 #define HCFG_PERSCHEDENA		(1 << 26)
629 #define HCFG_FRLISTEN_MASK		(0x3 << 24)
630 #define HCFG_FRLISTEN_SHIFT		24
631 #define HCFG_FRLISTEN_8				(0 << 24)
632 #define FRLISTEN_8_SIZE				8
633 #define HCFG_FRLISTEN_16			(1 << 24)
634 #define FRLISTEN_16_SIZE			16
635 #define HCFG_FRLISTEN_32			(2 << 24)
636 #define FRLISTEN_32_SIZE			32
637 #define HCFG_FRLISTEN_64			(3 << 24)
638 #define FRLISTEN_64_SIZE			64
639 #define HCFG_DESCDMA			(1 << 23)
640 #define HCFG_RESVALID_MASK		(0xff << 8)
641 #define HCFG_RESVALID_SHIFT		8
642 #define HCFG_ENA32KHZ			(1 << 7)
643 #define HCFG_FSLSSUPP			(1 << 2)
644 #define HCFG_FSLSPCLKSEL_MASK		(0x3 << 0)
645 #define HCFG_FSLSPCLKSEL_SHIFT		0
646 #define HCFG_FSLSPCLKSEL_30_60_MHZ	0
647 #define HCFG_FSLSPCLKSEL_48_MHZ		1
648 #define HCFG_FSLSPCLKSEL_6_MHZ		2
649 
650 #define HFIR				HSOTG_REG(0x0404)
651 #define HFIR_FRINT_MASK			(0xffff << 0)
652 #define HFIR_FRINT_SHIFT		0
653 #define HFIR_RLDCTRL			(1 << 16)
654 
655 #define HFNUM				HSOTG_REG(0x0408)
656 #define HFNUM_FRREM_MASK		(0xffff << 16)
657 #define HFNUM_FRREM_SHIFT		16
658 #define HFNUM_FRNUM_MASK		(0xffff << 0)
659 #define HFNUM_FRNUM_SHIFT		0
660 #define HFNUM_MAX_FRNUM			0x3fff
661 
662 #define HPTXSTS				HSOTG_REG(0x0410)
663 #define TXSTS_QTOP_ODD			(1 << 31)
664 #define TXSTS_QTOP_CHNEP_MASK		(0xf << 27)
665 #define TXSTS_QTOP_CHNEP_SHIFT		27
666 #define TXSTS_QTOP_TOKEN_MASK		(0x3 << 25)
667 #define TXSTS_QTOP_TOKEN_SHIFT		25
668 #define TXSTS_QTOP_TERMINATE		(1 << 24)
669 #define TXSTS_QSPCAVAIL_MASK		(0xff << 16)
670 #define TXSTS_QSPCAVAIL_SHIFT		16
671 #define TXSTS_FSPCAVAIL_MASK		(0xffff << 0)
672 #define TXSTS_FSPCAVAIL_SHIFT		0
673 
674 #define HAINT				HSOTG_REG(0x0414)
675 #define HAINTMSK			HSOTG_REG(0x0418)
676 #define HFLBADDR			HSOTG_REG(0x041c)
677 
678 #define HPRT0				HSOTG_REG(0x0440)
679 #define HPRT0_SPD_MASK			(0x3 << 17)
680 #define HPRT0_SPD_SHIFT			17
681 #define HPRT0_SPD_HIGH_SPEED		0
682 #define HPRT0_SPD_FULL_SPEED		1
683 #define HPRT0_SPD_LOW_SPEED		2
684 #define HPRT0_TSTCTL_MASK		(0xf << 13)
685 #define HPRT0_TSTCTL_SHIFT		13
686 #define HPRT0_PWR			(1 << 12)
687 #define HPRT0_LNSTS_MASK		(0x3 << 10)
688 #define HPRT0_LNSTS_SHIFT		10
689 #define HPRT0_RST			(1 << 8)
690 #define HPRT0_SUSP			(1 << 7)
691 #define HPRT0_RES			(1 << 6)
692 #define HPRT0_OVRCURRCHG		(1 << 5)
693 #define HPRT0_OVRCURRACT		(1 << 4)
694 #define HPRT0_ENACHG			(1 << 3)
695 #define HPRT0_ENA			(1 << 2)
696 #define HPRT0_CONNDET			(1 << 1)
697 #define HPRT0_CONNSTS			(1 << 0)
698 
699 #define HCCHAR(_ch)			HSOTG_REG(0x0500 + 0x20 * (_ch))
700 #define HCCHAR_CHENA			(1 << 31)
701 #define HCCHAR_CHDIS			(1 << 30)
702 #define HCCHAR_ODDFRM			(1 << 29)
703 #define HCCHAR_DEVADDR_MASK		(0x7f << 22)
704 #define HCCHAR_DEVADDR_SHIFT		22
705 #define HCCHAR_MULTICNT_MASK		(0x3 << 20)
706 #define HCCHAR_MULTICNT_SHIFT		20
707 #define HCCHAR_EPTYPE_MASK		(0x3 << 18)
708 #define HCCHAR_EPTYPE_SHIFT		18
709 #define HCCHAR_LSPDDEV			(1 << 17)
710 #define HCCHAR_EPDIR			(1 << 15)
711 #define HCCHAR_EPNUM_MASK		(0xf << 11)
712 #define HCCHAR_EPNUM_SHIFT		11
713 #define HCCHAR_MPS_MASK			(0x7ff << 0)
714 #define HCCHAR_MPS_SHIFT		0
715 
716 #define HCSPLT(_ch)			HSOTG_REG(0x0504 + 0x20 * (_ch))
717 #define HCSPLT_SPLTENA			(1 << 31)
718 #define HCSPLT_COMPSPLT			(1 << 16)
719 #define HCSPLT_XACTPOS_MASK		(0x3 << 14)
720 #define HCSPLT_XACTPOS_SHIFT		14
721 #define HCSPLT_XACTPOS_MID		0
722 #define HCSPLT_XACTPOS_END		1
723 #define HCSPLT_XACTPOS_BEGIN		2
724 #define HCSPLT_XACTPOS_ALL		3
725 #define HCSPLT_HUBADDR_MASK		(0x7f << 7)
726 #define HCSPLT_HUBADDR_SHIFT		7
727 #define HCSPLT_PRTADDR_MASK		(0x7f << 0)
728 #define HCSPLT_PRTADDR_SHIFT		0
729 
730 #define HCINT(_ch)			HSOTG_REG(0x0508 + 0x20 * (_ch))
731 #define HCINTMSK(_ch)			HSOTG_REG(0x050c + 0x20 * (_ch))
732 #define HCINTMSK_RESERVED14_31		(0x3ffff << 14)
733 #define HCINTMSK_FRM_LIST_ROLL		(1 << 13)
734 #define HCINTMSK_XCS_XACT		(1 << 12)
735 #define HCINTMSK_BNA			(1 << 11)
736 #define HCINTMSK_DATATGLERR		(1 << 10)
737 #define HCINTMSK_FRMOVRUN		(1 << 9)
738 #define HCINTMSK_BBLERR			(1 << 8)
739 #define HCINTMSK_XACTERR		(1 << 7)
740 #define HCINTMSK_NYET			(1 << 6)
741 #define HCINTMSK_ACK			(1 << 5)
742 #define HCINTMSK_NAK			(1 << 4)
743 #define HCINTMSK_STALL			(1 << 3)
744 #define HCINTMSK_AHBERR			(1 << 2)
745 #define HCINTMSK_CHHLTD			(1 << 1)
746 #define HCINTMSK_XFERCOMPL		(1 << 0)
747 
748 #define HCTSIZ(_ch)			HSOTG_REG(0x0510 + 0x20 * (_ch))
749 #define TSIZ_DOPNG			(1 << 31)
750 #define TSIZ_SC_MC_PID_MASK		(0x3 << 29)
751 #define TSIZ_SC_MC_PID_SHIFT		29
752 #define TSIZ_SC_MC_PID_DATA0		0
753 #define TSIZ_SC_MC_PID_DATA2		1
754 #define TSIZ_SC_MC_PID_DATA1		2
755 #define TSIZ_SC_MC_PID_MDATA		3
756 #define TSIZ_SC_MC_PID_SETUP		3
757 #define TSIZ_PKTCNT_MASK		(0x3ff << 19)
758 #define TSIZ_PKTCNT_SHIFT		19
759 #define TSIZ_NTD_MASK			(0xff << 8)
760 #define TSIZ_NTD_SHIFT			8
761 #define TSIZ_SCHINFO_MASK		(0xff << 0)
762 #define TSIZ_SCHINFO_SHIFT		0
763 #define TSIZ_XFERSIZE_MASK		(0x7ffff << 0)
764 #define TSIZ_XFERSIZE_SHIFT		0
765 
766 #define HCDMA(_ch)			HSOTG_REG(0x0514 + 0x20 * (_ch))
767 #define HCDMA_DMA_ADDR_MASK		(0x1fffff << 11)
768 #define HCDMA_DMA_ADDR_SHIFT		11
769 #define HCDMA_CTD_MASK			(0xff << 3)
770 #define HCDMA_CTD_SHIFT			3
771 
772 #define HCDMAB(_ch)			HSOTG_REG(0x051c + 0x20 * (_ch))
773 
774 #define HCFIFO(_ch)			HSOTG_REG(0x1000 + 0x1000 * (_ch))
775 
776 /**
777  * struct dwc2_hcd_dma_desc - Host-mode DMA descriptor structure
778  *
779  * @status: DMA descriptor status quadlet
780  * @buf:    DMA descriptor data buffer pointer
781  *
782  * DMA Descriptor structure contains two quadlets:
783  * Status quadlet and Data buffer pointer.
784  */
785 struct dwc2_hcd_dma_desc {
786 	u32 status;
787 	u32 buf;
788 };
789 
790 #define HOST_DMA_A			(1 << 31)
791 #define HOST_DMA_STS_MASK		(0x3 << 28)
792 #define HOST_DMA_STS_SHIFT		28
793 #define HOST_DMA_STS_PKTERR		(1 << 28)
794 #define HOST_DMA_EOL			(1 << 26)
795 #define HOST_DMA_IOC			(1 << 25)
796 #define HOST_DMA_SUP			(1 << 24)
797 #define HOST_DMA_ALT_QTD		(1 << 23)
798 #define HOST_DMA_QTD_OFFSET_MASK	(0x3f << 17)
799 #define HOST_DMA_QTD_OFFSET_SHIFT	17
800 #define HOST_DMA_ISOC_NBYTES_MASK	(0xfff << 0)
801 #define HOST_DMA_ISOC_NBYTES_SHIFT	0
802 #define HOST_DMA_NBYTES_MASK		(0x1ffff << 0)
803 #define HOST_DMA_NBYTES_SHIFT		0
804 
805 #define MAX_DMA_DESC_SIZE		131071
806 #define MAX_DMA_DESC_NUM_GENERIC	64
807 #define MAX_DMA_DESC_NUM_HS_ISOC	256
808 
809 #endif /* __DWC2_HW_H__ */
810