1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8 /* 9 * This file contains the functions to manage Queue Heads and Queue 10 * Transfer Descriptors for Host mode 11 */ 12 #include <linux/gcd.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/interrupt.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/io.h> 19 #include <linux/slab.h> 20 #include <linux/usb.h> 21 22 #include <linux/usb/hcd.h> 23 #include <linux/usb/ch11.h> 24 25 #include "core.h" 26 #include "hcd.h" 27 28 /* Wait this long before releasing periodic reservation */ 29 #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5)) 30 31 /* If we get a NAK, wait this long before retrying */ 32 #define DWC2_RETRY_WAIT_DELAY (1 * NSEC_PER_MSEC) 33 34 /** 35 * dwc2_periodic_channel_available() - Checks that a channel is available for a 36 * periodic transfer 37 * 38 * @hsotg: The HCD state structure for the DWC OTG controller 39 * 40 * Return: 0 if successful, negative error code otherwise 41 */ 42 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 43 { 44 /* 45 * Currently assuming that there is a dedicated host channel for 46 * each periodic transaction plus at least one host channel for 47 * non-periodic transactions 48 */ 49 int status; 50 int num_channels; 51 52 num_channels = hsotg->params.host_channels; 53 if ((hsotg->periodic_channels + hsotg->non_periodic_channels < 54 num_channels) && (hsotg->periodic_channels < num_channels - 1)) { 55 status = 0; 56 } else { 57 dev_dbg(hsotg->dev, 58 "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", 59 __func__, num_channels, 60 hsotg->periodic_channels, hsotg->non_periodic_channels); 61 status = -ENOSPC; 62 } 63 64 return status; 65 } 66 67 /** 68 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 69 * for the specified QH in the periodic schedule 70 * 71 * @hsotg: The HCD state structure for the DWC OTG controller 72 * @qh: QH containing periodic bandwidth required 73 * 74 * Return: 0 if successful, negative error code otherwise 75 * 76 * For simplicity, this calculation assumes that all the transfers in the 77 * periodic schedule may occur in the same (micro)frame 78 */ 79 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 80 struct dwc2_qh *qh) 81 { 82 int status; 83 s16 max_claimed_usecs; 84 85 status = 0; 86 87 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 88 /* 89 * High speed mode 90 * Max periodic usecs is 80% x 125 usec = 100 usec 91 */ 92 max_claimed_usecs = 100 - qh->host_us; 93 } else { 94 /* 95 * Full speed mode 96 * Max periodic usecs is 90% x 1000 usec = 900 usec 97 */ 98 max_claimed_usecs = 900 - qh->host_us; 99 } 100 101 if (hsotg->periodic_usecs > max_claimed_usecs) { 102 dev_err(hsotg->dev, 103 "%s: already claimed usecs %d, required usecs %d\n", 104 __func__, hsotg->periodic_usecs, qh->host_us); 105 status = -ENOSPC; 106 } 107 108 return status; 109 } 110 111 /** 112 * pmap_schedule() - Schedule time in a periodic bitmap (pmap). 113 * 114 * @map: The bitmap representing the schedule; will be updated 115 * upon success. 116 * @bits_per_period: The schedule represents several periods. This is how many 117 * bits are in each period. It's assumed that the beginning 118 * of the schedule will repeat after its end. 119 * @periods_in_map: The number of periods in the schedule. 120 * @num_bits: The number of bits we need per period we want to reserve 121 * in this function call. 122 * @interval: How often we need to be scheduled for the reservation this 123 * time. 1 means every period. 2 means every other period. 124 * ...you get the picture? 125 * @start: The bit number to start at. Normally 0. Must be within 126 * the interval or we return failure right away. 127 * @only_one_period: Normally we'll allow picking a start anywhere within the 128 * first interval, since we can still make all repetition 129 * requirements by doing that. However, if you pass true 130 * here then we'll return failure if we can't fit within 131 * the period that "start" is in. 132 * 133 * The idea here is that we want to schedule time for repeating events that all 134 * want the same resource. The resource is divided into fixed-sized periods 135 * and the events want to repeat every "interval" periods. The schedule 136 * granularity is one bit. 137 * 138 * To keep things "simple", we'll represent our schedule with a bitmap that 139 * contains a fixed number of periods. This gets rid of a lot of complexity 140 * but does mean that we need to handle things specially (and non-ideally) if 141 * the number of the periods in the schedule doesn't match well with the 142 * intervals that we're trying to schedule. 143 * 144 * Here's an explanation of the scheme we'll implement, assuming 8 periods. 145 * - If interval is 1, we need to take up space in each of the 8 146 * periods we're scheduling. Easy. 147 * - If interval is 2, we need to take up space in half of the 148 * periods. Again, easy. 149 * - If interval is 3, we actually need to fall back to interval 1. 150 * Why? Because we might need time in any period. AKA for the 151 * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be 152 * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to 153 * 0, 3, and 6. Since we could be in any frame we need to reserve 154 * for all of them. Sucks, but that's what you gotta do. Note that 155 * if we were instead scheduling 8 * 3 = 24 we'd do much better, but 156 * then we need more memory and time to do scheduling. 157 * - If interval is 4, easy. 158 * - If interval is 5, we again need interval 1. The schedule will be 159 * 0, 5, 2, 7, 4, 1, 6, 3, 0 160 * - If interval is 6, we need interval 2. 0, 6, 4, 2. 161 * - If interval is 7, we need interval 1. 162 * - If interval is 8, we need interval 8. 163 * 164 * If you do the math, you'll see that we need to pretend that interval is 165 * equal to the greatest_common_divisor(interval, periods_in_map). 166 * 167 * Note that at the moment this function tends to front-pack the schedule. 168 * In some cases that's really non-ideal (it's hard to schedule things that 169 * need to repeat every period). In other cases it's perfect (you can easily 170 * schedule bigger, less often repeating things). 171 * 172 * Here's the algorithm in action (8 periods, 5 bits per period): 173 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 174 * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2 175 * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5 176 * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2 177 * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2 178 * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3 179 * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6 180 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4 181 * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1 182 * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0 183 * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5 184 * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2 185 * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3 186 * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6 187 * | | | | | | | | | Remv 1 bits, intv 1 at 4 188 * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 189 * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2 190 * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3 191 * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5 192 * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6 193 * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8 194 * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12 195 * 196 * This function is pretty generic and could be easily abstracted if anything 197 * needed similar scheduling. 198 * 199 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the 200 * unschedule routine. The map bitmap will be updated on a non-error result. 201 */ 202 static int pmap_schedule(unsigned long *map, int bits_per_period, 203 int periods_in_map, int num_bits, 204 int interval, int start, bool only_one_period) 205 { 206 int interval_bits; 207 int to_reserve; 208 int first_end; 209 int i; 210 211 if (num_bits > bits_per_period) 212 return -ENOSPC; 213 214 /* Adjust interval as per description */ 215 interval = gcd(interval, periods_in_map); 216 217 interval_bits = bits_per_period * interval; 218 to_reserve = periods_in_map / interval; 219 220 /* If start has gotten us past interval then we can't schedule */ 221 if (start >= interval_bits) 222 return -ENOSPC; 223 224 if (only_one_period) 225 /* Must fit within same period as start; end at begin of next */ 226 first_end = (start / bits_per_period + 1) * bits_per_period; 227 else 228 /* Can fit anywhere in the first interval */ 229 first_end = interval_bits; 230 231 /* 232 * We'll try to pick the first repetition, then see if that time 233 * is free for each of the subsequent repetitions. If it's not 234 * we'll adjust the start time for the next search of the first 235 * repetition. 236 */ 237 while (start + num_bits <= first_end) { 238 int end; 239 240 /* Need to stay within this period */ 241 end = (start / bits_per_period + 1) * bits_per_period; 242 243 /* Look for num_bits us in this microframe starting at start */ 244 start = bitmap_find_next_zero_area(map, end, start, num_bits, 245 0); 246 247 /* 248 * We should get start >= end if we fail. We might be 249 * able to check the next microframe depending on the 250 * interval, so continue on (start already updated). 251 */ 252 if (start >= end) { 253 start = end; 254 continue; 255 } 256 257 /* At this point we have a valid point for first one */ 258 for (i = 1; i < to_reserve; i++) { 259 int ith_start = start + interval_bits * i; 260 int ith_end = end + interval_bits * i; 261 int ret; 262 263 /* Use this as a dumb "check if bits are 0" */ 264 ret = bitmap_find_next_zero_area( 265 map, ith_start + num_bits, ith_start, num_bits, 266 0); 267 268 /* We got the right place, continue checking */ 269 if (ret == ith_start) 270 continue; 271 272 /* Move start up for next time and exit for loop */ 273 ith_start = bitmap_find_next_zero_area( 274 map, ith_end, ith_start, num_bits, 0); 275 if (ith_start >= ith_end) 276 /* Need a while new period next time */ 277 start = end; 278 else 279 start = ith_start - interval_bits * i; 280 break; 281 } 282 283 /* If didn't exit the for loop with a break, we have success */ 284 if (i == to_reserve) 285 break; 286 } 287 288 if (start + num_bits > first_end) 289 return -ENOSPC; 290 291 for (i = 0; i < to_reserve; i++) { 292 int ith_start = start + interval_bits * i; 293 294 bitmap_set(map, ith_start, num_bits); 295 } 296 297 return start; 298 } 299 300 /** 301 * pmap_unschedule() - Undo work done by pmap_schedule() 302 * 303 * @map: See pmap_schedule(). 304 * @bits_per_period: See pmap_schedule(). 305 * @periods_in_map: See pmap_schedule(). 306 * @num_bits: The number of bits that was passed to schedule. 307 * @interval: The interval that was passed to schedule. 308 * @start: The return value from pmap_schedule(). 309 */ 310 static void pmap_unschedule(unsigned long *map, int bits_per_period, 311 int periods_in_map, int num_bits, 312 int interval, int start) 313 { 314 int interval_bits; 315 int to_release; 316 int i; 317 318 /* Adjust interval as per description in pmap_schedule() */ 319 interval = gcd(interval, periods_in_map); 320 321 interval_bits = bits_per_period * interval; 322 to_release = periods_in_map / interval; 323 324 for (i = 0; i < to_release; i++) { 325 int ith_start = start + interval_bits * i; 326 327 bitmap_clear(map, ith_start, num_bits); 328 } 329 } 330 331 /** 332 * dwc2_get_ls_map() - Get the map used for the given qh 333 * 334 * @hsotg: The HCD state structure for the DWC OTG controller. 335 * @qh: QH for the periodic transfer. 336 * 337 * We'll always get the periodic map out of our TT. Note that even if we're 338 * running the host straight in low speed / full speed mode it appears as if 339 * a TT is allocated for us, so we'll use it. If that ever changes we can 340 * add logic here to get a map out of "hsotg" if !qh->do_split. 341 * 342 * Returns: the map or NULL if a map couldn't be found. 343 */ 344 static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg, 345 struct dwc2_qh *qh) 346 { 347 unsigned long *map; 348 349 /* Don't expect to be missing a TT and be doing low speed scheduling */ 350 if (WARN_ON(!qh->dwc_tt)) 351 return NULL; 352 353 /* Get the map and adjust if this is a multi_tt hub */ 354 map = qh->dwc_tt->periodic_bitmaps; 355 if (qh->dwc_tt->usb_tt->multi) 356 map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1); 357 358 return map; 359 } 360 361 #ifdef DWC2_PRINT_SCHEDULE 362 /* 363 * cat_printf() - A printf() + strcat() helper 364 * 365 * This is useful for concatenating a bunch of strings where each string is 366 * constructed using printf. 367 * 368 * @buf: The destination buffer; will be updated to point after the printed 369 * data. 370 * @size: The number of bytes in the buffer (includes space for '\0'). 371 * @fmt: The format for printf. 372 * @...: The args for printf. 373 */ 374 static __printf(3, 4) 375 void cat_printf(char **buf, size_t *size, const char *fmt, ...) 376 { 377 va_list args; 378 int i; 379 380 if (*size == 0) 381 return; 382 383 va_start(args, fmt); 384 i = vsnprintf(*buf, *size, fmt, args); 385 va_end(args); 386 387 if (i >= *size) { 388 (*buf)[*size - 1] = '\0'; 389 *buf += *size; 390 *size = 0; 391 } else { 392 *buf += i; 393 *size -= i; 394 } 395 } 396 397 /* 398 * pmap_print() - Print the given periodic map 399 * 400 * Will attempt to print out the periodic schedule. 401 * 402 * @map: See pmap_schedule(). 403 * @bits_per_period: See pmap_schedule(). 404 * @periods_in_map: See pmap_schedule(). 405 * @period_name: The name of 1 period, like "uFrame" 406 * @units: The name of the units, like "us". 407 * @print_fn: The function to call for printing. 408 * @print_data: Opaque data to pass to the print function. 409 */ 410 static void pmap_print(unsigned long *map, int bits_per_period, 411 int periods_in_map, const char *period_name, 412 const char *units, 413 void (*print_fn)(const char *str, void *data), 414 void *print_data) 415 { 416 int period; 417 418 for (period = 0; period < periods_in_map; period++) { 419 char tmp[64]; 420 char *buf = tmp; 421 size_t buf_size = sizeof(tmp); 422 int period_start = period * bits_per_period; 423 int period_end = period_start + bits_per_period; 424 int start = 0; 425 int count = 0; 426 bool printed = false; 427 int i; 428 429 for (i = period_start; i < period_end + 1; i++) { 430 /* Handle case when ith bit is set */ 431 if (i < period_end && 432 bitmap_find_next_zero_area(map, i + 1, 433 i, 1, 0) != i) { 434 if (count == 0) 435 start = i - period_start; 436 count++; 437 continue; 438 } 439 440 /* ith bit isn't set; don't care if count == 0 */ 441 if (count == 0) 442 continue; 443 444 if (!printed) 445 cat_printf(&buf, &buf_size, "%s %d: ", 446 period_name, period); 447 else 448 cat_printf(&buf, &buf_size, ", "); 449 printed = true; 450 451 cat_printf(&buf, &buf_size, "%d %s -%3d %s", start, 452 units, start + count - 1, units); 453 count = 0; 454 } 455 456 if (printed) 457 print_fn(tmp, print_data); 458 } 459 } 460 461 struct dwc2_qh_print_data { 462 struct dwc2_hsotg *hsotg; 463 struct dwc2_qh *qh; 464 }; 465 466 /** 467 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print() 468 * 469 * @str: The string to print 470 * @data: A pointer to a struct dwc2_qh_print_data 471 */ 472 static void dwc2_qh_print(const char *str, void *data) 473 { 474 struct dwc2_qh_print_data *print_data = data; 475 476 dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str); 477 } 478 479 /** 480 * dwc2_qh_schedule_print() - Print the periodic schedule 481 * 482 * @hsotg: The HCD state structure for the DWC OTG controller. 483 * @qh: QH to print. 484 */ 485 static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 486 struct dwc2_qh *qh) 487 { 488 struct dwc2_qh_print_data print_data = { hsotg, qh }; 489 int i; 490 491 /* 492 * The printing functions are quite slow and inefficient. 493 * If we don't have tracing turned on, don't run unless the special 494 * define is turned on. 495 */ 496 497 if (qh->schedule_low_speed) { 498 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 499 500 dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us", 501 qh, qh->device_us, 502 DWC2_ROUND_US_TO_SLICE(qh->device_us), 503 DWC2_US_PER_SLICE * qh->ls_start_schedule_slice); 504 505 if (map) { 506 dwc2_sch_dbg(hsotg, 507 "QH=%p Whole low/full speed map %p now:\n", 508 qh, map); 509 pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 510 DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices", 511 dwc2_qh_print, &print_data); 512 } 513 } 514 515 for (i = 0; i < qh->num_hs_transfers; i++) { 516 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i; 517 int uframe = trans_time->start_schedule_us / 518 DWC2_HS_PERIODIC_US_PER_UFRAME; 519 int rel_us = trans_time->start_schedule_us % 520 DWC2_HS_PERIODIC_US_PER_UFRAME; 521 522 dwc2_sch_dbg(hsotg, 523 "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n", 524 qh, i, trans_time->duration_us, uframe, rel_us); 525 } 526 if (qh->num_hs_transfers) { 527 dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh); 528 pmap_print(hsotg->hs_periodic_bitmap, 529 DWC2_HS_PERIODIC_US_PER_UFRAME, 530 DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us", 531 dwc2_qh_print, &print_data); 532 } 533 } 534 #else 535 static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 536 struct dwc2_qh *qh) {}; 537 #endif 538 539 /** 540 * dwc2_ls_pmap_schedule() - Schedule a low speed QH 541 * 542 * @hsotg: The HCD state structure for the DWC OTG controller. 543 * @qh: QH for the periodic transfer. 544 * @search_slice: We'll start trying to schedule at the passed slice. 545 * Remember that slices are the units of the low speed 546 * schedule (think 25us or so). 547 * 548 * Wraps pmap_schedule() with the right parameters for low speed scheduling. 549 * 550 * Normally we schedule low speed devices on the map associated with the TT. 551 * 552 * Returns: 0 for success or an error code. 553 */ 554 static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 555 int search_slice) 556 { 557 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 558 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 559 int slice; 560 561 if (!map) 562 return -EINVAL; 563 564 /* 565 * Schedule on the proper low speed map with our low speed scheduling 566 * parameters. Note that we use the "device_interval" here since 567 * we want the low speed interval and the only way we'd be in this 568 * function is if the device is low speed. 569 * 570 * If we happen to be doing low speed and high speed scheduling for the 571 * same transaction (AKA we have a split) we always do low speed first. 572 * That means we can always pass "false" for only_one_period (that 573 * parameters is only useful when we're trying to get one schedule to 574 * match what we already planned in the other schedule). 575 */ 576 slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 577 DWC2_LS_SCHEDULE_FRAMES, slices, 578 qh->device_interval, search_slice, false); 579 580 if (slice < 0) 581 return slice; 582 583 qh->ls_start_schedule_slice = slice; 584 return 0; 585 } 586 587 /** 588 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule() 589 * 590 * @hsotg: The HCD state structure for the DWC OTG controller. 591 * @qh: QH for the periodic transfer. 592 */ 593 static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg, 594 struct dwc2_qh *qh) 595 { 596 int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 597 unsigned long *map = dwc2_get_ls_map(hsotg, qh); 598 599 /* Schedule should have failed, so no worries about no error code */ 600 if (!map) 601 return; 602 603 pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 604 DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval, 605 qh->ls_start_schedule_slice); 606 } 607 608 /** 609 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule 610 * 611 * This will schedule something on the main dwc2 schedule. 612 * 613 * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll 614 * update this with the result upon success. We also use the duration from 615 * the same structure. 616 * 617 * @hsotg: The HCD state structure for the DWC OTG controller. 618 * @qh: QH for the periodic transfer. 619 * @only_one_period: If true we will limit ourselves to just looking at 620 * one period (aka one 100us chunk). This is used if we have 621 * already scheduled something on the low speed schedule and 622 * need to find something that matches on the high speed one. 623 * @index: The index into qh->hs_transfers that we're working with. 624 * 625 * Returns: 0 for success or an error code. Upon success the 626 * dwc2_hs_transfer_time specified by "index" will be updated. 627 */ 628 static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 629 bool only_one_period, int index) 630 { 631 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 632 int us; 633 634 us = pmap_schedule(hsotg->hs_periodic_bitmap, 635 DWC2_HS_PERIODIC_US_PER_UFRAME, 636 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 637 qh->host_interval, trans_time->start_schedule_us, 638 only_one_period); 639 640 if (us < 0) 641 return us; 642 643 trans_time->start_schedule_us = us; 644 return 0; 645 } 646 647 /** 648 * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule() 649 * 650 * @hsotg: The HCD state structure for the DWC OTG controller. 651 * @qh: QH for the periodic transfer. 652 * @index: Transfer index 653 */ 654 static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg, 655 struct dwc2_qh *qh, int index) 656 { 657 struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 658 659 pmap_unschedule(hsotg->hs_periodic_bitmap, 660 DWC2_HS_PERIODIC_US_PER_UFRAME, 661 DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 662 qh->host_interval, trans_time->start_schedule_us); 663 } 664 665 /** 666 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer. 667 * 668 * This is the most complicated thing in USB. We have to find matching time 669 * in both the global high speed schedule for the port and the low speed 670 * schedule for the TT associated with the given device. 671 * 672 * Being here means that the host must be running in high speed mode and the 673 * device is in low or full speed mode (and behind a hub). 674 * 675 * @hsotg: The HCD state structure for the DWC OTG controller. 676 * @qh: QH for the periodic transfer. 677 */ 678 static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg, 679 struct dwc2_qh *qh) 680 { 681 int bytecount = qh->maxp_mult * qh->maxp; 682 int ls_search_slice; 683 int err = 0; 684 int host_interval_in_sched; 685 686 /* 687 * The interval (how often to repeat) in the actual host schedule. 688 * See pmap_schedule() for gcd() explanation. 689 */ 690 host_interval_in_sched = gcd(qh->host_interval, 691 DWC2_HS_SCHEDULE_UFRAMES); 692 693 /* 694 * We always try to find space in the low speed schedule first, then 695 * try to find high speed time that matches. If we don't, we'll bump 696 * up the place we start searching in the low speed schedule and try 697 * again. To start we'll look right at the beginning of the low speed 698 * schedule. 699 * 700 * Note that this will tend to front-load the high speed schedule. 701 * We may eventually want to try to avoid this by either considering 702 * both schedules together or doing some sort of round robin. 703 */ 704 ls_search_slice = 0; 705 706 while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) { 707 int start_s_uframe; 708 int ssplit_s_uframe; 709 int second_s_uframe; 710 int rel_uframe; 711 int first_count; 712 int middle_count; 713 int end_count; 714 int first_data_bytes; 715 int other_data_bytes; 716 int i; 717 718 if (qh->schedule_low_speed) { 719 err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice); 720 721 /* 722 * If we got an error here there's no other magic we 723 * can do, so bail. All the looping above is only 724 * helpful to redo things if we got a low speed slot 725 * and then couldn't find a matching high speed slot. 726 */ 727 if (err) 728 return err; 729 } else { 730 /* Must be missing the tt structure? Why? */ 731 WARN_ON_ONCE(1); 732 } 733 734 /* 735 * This will give us a number 0 - 7 if 736 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ... 737 */ 738 start_s_uframe = qh->ls_start_schedule_slice / 739 DWC2_SLICES_PER_UFRAME; 740 741 /* Get a number that's always 0 - 7 */ 742 rel_uframe = (start_s_uframe % 8); 743 744 /* 745 * If we were going to start in uframe 7 then we would need to 746 * issue a start split in uframe 6, which spec says is not OK. 747 * Move on to the next full frame (assuming there is one). 748 * 749 * See 11.18.4 Host Split Transaction Scheduling Requirements 750 * bullet 1. 751 */ 752 if (rel_uframe == 7) { 753 if (qh->schedule_low_speed) 754 dwc2_ls_pmap_unschedule(hsotg, qh); 755 ls_search_slice = 756 (qh->ls_start_schedule_slice / 757 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) * 758 DWC2_LS_PERIODIC_SLICES_PER_FRAME; 759 continue; 760 } 761 762 /* 763 * For ISOC in: 764 * - start split (frame -1) 765 * - complete split w/ data (frame +1) 766 * - complete split w/ data (frame +2) 767 * - ... 768 * - complete split w/ data (frame +num_data_packets) 769 * - complete split w/ data (frame +num_data_packets+1) 770 * - complete split w/ data (frame +num_data_packets+2, max 8) 771 * ...though if frame was "0" then max is 7... 772 * 773 * For ISOC out we might need to do: 774 * - start split w/ data (frame -1) 775 * - start split w/ data (frame +0) 776 * - ... 777 * - start split w/ data (frame +num_data_packets-2) 778 * 779 * For INTERRUPT in we might need to do: 780 * - start split (frame -1) 781 * - complete split w/ data (frame +1) 782 * - complete split w/ data (frame +2) 783 * - complete split w/ data (frame +3, max 8) 784 * 785 * For INTERRUPT out we might need to do: 786 * - start split w/ data (frame -1) 787 * - complete split (frame +1) 788 * - complete split (frame +2) 789 * - complete split (frame +3, max 8) 790 * 791 * Start adjusting! 792 */ 793 ssplit_s_uframe = (start_s_uframe + 794 host_interval_in_sched - 1) % 795 host_interval_in_sched; 796 if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in) 797 second_s_uframe = start_s_uframe; 798 else 799 second_s_uframe = start_s_uframe + 1; 800 801 /* First data transfer might not be all 188 bytes. */ 802 first_data_bytes = 188 - 803 DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice % 804 DWC2_SLICES_PER_UFRAME), 805 DWC2_SLICES_PER_UFRAME); 806 if (first_data_bytes > bytecount) 807 first_data_bytes = bytecount; 808 other_data_bytes = bytecount - first_data_bytes; 809 810 /* 811 * For now, skip OUT xfers where first xfer is partial 812 * 813 * Main dwc2 code assumes: 814 * - INT transfers never get split in two. 815 * - ISOC transfers can always transfer 188 bytes the first 816 * time. 817 * 818 * Until that code is fixed, try again if the first transfer 819 * couldn't transfer everything. 820 * 821 * This code can be removed if/when the rest of dwc2 handles 822 * the above cases. Until it's fixed we just won't be able 823 * to schedule quite as tightly. 824 */ 825 if (!qh->ep_is_in && 826 (first_data_bytes != min_t(int, 188, bytecount))) { 827 dwc2_sch_dbg(hsotg, 828 "QH=%p avoiding broken 1st xfer (%d, %d)\n", 829 qh, first_data_bytes, bytecount); 830 if (qh->schedule_low_speed) 831 dwc2_ls_pmap_unschedule(hsotg, qh); 832 ls_search_slice = (start_s_uframe + 1) * 833 DWC2_SLICES_PER_UFRAME; 834 continue; 835 } 836 837 /* Start by assuming transfers for the bytes */ 838 qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188); 839 840 /* 841 * Everything except ISOC OUT has extra transfers. Rules are 842 * complicated. See 11.18.4 Host Split Transaction Scheduling 843 * Requirements bullet 3. 844 */ 845 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 846 if (rel_uframe == 6) 847 qh->num_hs_transfers += 2; 848 else 849 qh->num_hs_transfers += 3; 850 851 if (qh->ep_is_in) { 852 /* 853 * First is start split, middle/end is data. 854 * Allocate full data bytes for all data. 855 */ 856 first_count = 4; 857 middle_count = bytecount; 858 end_count = bytecount; 859 } else { 860 /* 861 * First is data, middle/end is complete. 862 * First transfer and second can have data. 863 * Rest should just have complete split. 864 */ 865 first_count = first_data_bytes; 866 middle_count = max_t(int, 4, other_data_bytes); 867 end_count = 4; 868 } 869 } else { 870 if (qh->ep_is_in) { 871 int last; 872 873 /* Account for the start split */ 874 qh->num_hs_transfers++; 875 876 /* Calculate "L" value from spec */ 877 last = rel_uframe + qh->num_hs_transfers + 1; 878 879 /* Start with basic case */ 880 if (last <= 6) 881 qh->num_hs_transfers += 2; 882 else 883 qh->num_hs_transfers += 1; 884 885 /* Adjust downwards */ 886 if (last >= 6 && rel_uframe == 0) 887 qh->num_hs_transfers--; 888 889 /* 1st = start; rest can contain data */ 890 first_count = 4; 891 middle_count = min_t(int, 188, bytecount); 892 end_count = middle_count; 893 } else { 894 /* All contain data, last might be smaller */ 895 first_count = first_data_bytes; 896 middle_count = min_t(int, 188, 897 other_data_bytes); 898 end_count = other_data_bytes % 188; 899 } 900 } 901 902 /* Assign durations per uFrame */ 903 qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count); 904 for (i = 1; i < qh->num_hs_transfers - 1; i++) 905 qh->hs_transfers[i].duration_us = 906 HS_USECS_ISO(middle_count); 907 if (qh->num_hs_transfers > 1) 908 qh->hs_transfers[qh->num_hs_transfers - 1].duration_us = 909 HS_USECS_ISO(end_count); 910 911 /* 912 * Assign start us. The call below to dwc2_hs_pmap_schedule() 913 * will start with these numbers but may adjust within the same 914 * microframe. 915 */ 916 qh->hs_transfers[0].start_schedule_us = 917 ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME; 918 for (i = 1; i < qh->num_hs_transfers; i++) 919 qh->hs_transfers[i].start_schedule_us = 920 ((second_s_uframe + i - 1) % 921 DWC2_HS_SCHEDULE_UFRAMES) * 922 DWC2_HS_PERIODIC_US_PER_UFRAME; 923 924 /* Try to schedule with filled in hs_transfers above */ 925 for (i = 0; i < qh->num_hs_transfers; i++) { 926 err = dwc2_hs_pmap_schedule(hsotg, qh, true, i); 927 if (err) 928 break; 929 } 930 931 /* If we scheduled all w/out breaking out then we're all good */ 932 if (i == qh->num_hs_transfers) 933 break; 934 935 for (; i >= 0; i--) 936 dwc2_hs_pmap_unschedule(hsotg, qh, i); 937 938 if (qh->schedule_low_speed) 939 dwc2_ls_pmap_unschedule(hsotg, qh); 940 941 /* Try again starting in the next microframe */ 942 ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME; 943 } 944 945 if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES) 946 return -ENOSPC; 947 948 return 0; 949 } 950 951 /** 952 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer. 953 * 954 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean 955 * interface. 956 * 957 * @hsotg: The HCD state structure for the DWC OTG controller. 958 * @qh: QH for the periodic transfer. 959 */ 960 static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 961 { 962 /* In non-split host and device time are the same */ 963 WARN_ON(qh->host_us != qh->device_us); 964 WARN_ON(qh->host_interval != qh->device_interval); 965 WARN_ON(qh->num_hs_transfers != 1); 966 967 /* We'll have one transfer; init start to 0 before calling scheduler */ 968 qh->hs_transfers[0].start_schedule_us = 0; 969 qh->hs_transfers[0].duration_us = qh->host_us; 970 971 return dwc2_hs_pmap_schedule(hsotg, qh, false, 0); 972 } 973 974 /** 975 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer. 976 * 977 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean 978 * interface. 979 * 980 * @hsotg: The HCD state structure for the DWC OTG controller. 981 * @qh: QH for the periodic transfer. 982 */ 983 static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 984 { 985 /* In non-split host and device time are the same */ 986 WARN_ON(qh->host_us != qh->device_us); 987 WARN_ON(qh->host_interval != qh->device_interval); 988 WARN_ON(!qh->schedule_low_speed); 989 990 /* Run on the main low speed schedule (no split = no hub = no TT) */ 991 return dwc2_ls_pmap_schedule(hsotg, qh, 0); 992 } 993 994 /** 995 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer. 996 * 997 * Calls one of the 3 sub-function depending on what type of transfer this QH 998 * is for. Also adds some printing. 999 * 1000 * @hsotg: The HCD state structure for the DWC OTG controller. 1001 * @qh: QH for the periodic transfer. 1002 */ 1003 static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1004 { 1005 int ret; 1006 1007 if (qh->dev_speed == USB_SPEED_HIGH) 1008 ret = dwc2_uframe_schedule_hs(hsotg, qh); 1009 else if (!qh->do_split) 1010 ret = dwc2_uframe_schedule_ls(hsotg, qh); 1011 else 1012 ret = dwc2_uframe_schedule_split(hsotg, qh); 1013 1014 if (ret) 1015 dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret); 1016 else 1017 dwc2_qh_schedule_print(hsotg, qh); 1018 1019 return ret; 1020 } 1021 1022 /** 1023 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule(). 1024 * 1025 * @hsotg: The HCD state structure for the DWC OTG controller. 1026 * @qh: QH for the periodic transfer. 1027 */ 1028 static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1029 { 1030 int i; 1031 1032 for (i = 0; i < qh->num_hs_transfers; i++) 1033 dwc2_hs_pmap_unschedule(hsotg, qh, i); 1034 1035 if (qh->schedule_low_speed) 1036 dwc2_ls_pmap_unschedule(hsotg, qh); 1037 1038 dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh); 1039 } 1040 1041 /** 1042 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled 1043 * 1044 * Takes a qh that has already been scheduled (which means we know we have the 1045 * bandwdith reserved for us) and set the next_active_frame and the 1046 * start_active_frame. 1047 * 1048 * This is expected to be called on qh's that weren't previously actively 1049 * running. It just picks the next frame that we can fit into without any 1050 * thought about the past. 1051 * 1052 * @hsotg: The HCD state structure for the DWC OTG controller 1053 * @qh: QH for a periodic endpoint 1054 * 1055 */ 1056 static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1057 { 1058 u16 frame_number; 1059 u16 earliest_frame; 1060 u16 next_active_frame; 1061 u16 relative_frame; 1062 u16 interval; 1063 1064 /* 1065 * Use the real frame number rather than the cached value as of the 1066 * last SOF to give us a little extra slop. 1067 */ 1068 frame_number = dwc2_hcd_get_frame_number(hsotg); 1069 1070 /* 1071 * We wouldn't want to start any earlier than the next frame just in 1072 * case the frame number ticks as we're doing this calculation. 1073 * 1074 * NOTE: if we could quantify how long till we actually get scheduled 1075 * we might be able to avoid the "+ 1" by looking at the upper part of 1076 * HFNUM (the FRREM field). For now we'll just use the + 1 though. 1077 */ 1078 earliest_frame = dwc2_frame_num_inc(frame_number, 1); 1079 next_active_frame = earliest_frame; 1080 1081 /* Get the "no microframe scheduler" out of the way... */ 1082 if (!hsotg->params.uframe_sched) { 1083 if (qh->do_split) 1084 /* Splits are active at microframe 0 minus 1 */ 1085 next_active_frame |= 0x7; 1086 goto exit; 1087 } 1088 1089 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 1090 /* 1091 * We're either at high speed or we're doing a split (which 1092 * means we're talking high speed to a hub). In any case 1093 * the first frame should be based on when the first scheduled 1094 * event is. 1095 */ 1096 WARN_ON(qh->num_hs_transfers < 1); 1097 1098 relative_frame = qh->hs_transfers[0].start_schedule_us / 1099 DWC2_HS_PERIODIC_US_PER_UFRAME; 1100 1101 /* Adjust interval as per high speed schedule */ 1102 interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES); 1103 1104 } else { 1105 /* 1106 * Low or full speed directly on dwc2. Just about the same 1107 * as high speed but on a different schedule and with slightly 1108 * different adjustments. Note that this works because when 1109 * the host and device are both low speed then frames in the 1110 * controller tick at low speed. 1111 */ 1112 relative_frame = qh->ls_start_schedule_slice / 1113 DWC2_LS_PERIODIC_SLICES_PER_FRAME; 1114 interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES); 1115 } 1116 1117 /* Scheduler messed up if frame is past interval */ 1118 WARN_ON(relative_frame >= interval); 1119 1120 /* 1121 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've 1122 * done the gcd(), so it's safe to move to the beginning of the current 1123 * interval like this. 1124 * 1125 * After this we might be before earliest_frame, but don't worry, 1126 * we'll fix it... 1127 */ 1128 next_active_frame = (next_active_frame / interval) * interval; 1129 1130 /* 1131 * Actually choose to start at the frame number we've been 1132 * scheduled for. 1133 */ 1134 next_active_frame = dwc2_frame_num_inc(next_active_frame, 1135 relative_frame); 1136 1137 /* 1138 * We actually need 1 frame before since the next_active_frame is 1139 * the frame number we'll be put on the ready list and we won't be on 1140 * the bus until 1 frame later. 1141 */ 1142 next_active_frame = dwc2_frame_num_dec(next_active_frame, 1); 1143 1144 /* 1145 * By now we might actually be before the earliest_frame. Let's move 1146 * up intervals until we're not. 1147 */ 1148 while (dwc2_frame_num_gt(earliest_frame, next_active_frame)) 1149 next_active_frame = dwc2_frame_num_inc(next_active_frame, 1150 interval); 1151 1152 exit: 1153 qh->next_active_frame = next_active_frame; 1154 qh->start_active_frame = next_active_frame; 1155 1156 dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n", 1157 qh, frame_number, qh->next_active_frame); 1158 } 1159 1160 /** 1161 * dwc2_do_reserve() - Make a periodic reservation 1162 * 1163 * Try to allocate space in the periodic schedule. Depending on parameters 1164 * this might use the microframe scheduler or the dumb scheduler. 1165 * 1166 * @hsotg: The HCD state structure for the DWC OTG controller 1167 * @qh: QH for the periodic transfer. 1168 * 1169 * Returns: 0 upon success; error upon failure. 1170 */ 1171 static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1172 { 1173 int status; 1174 1175 if (hsotg->params.uframe_sched) { 1176 status = dwc2_uframe_schedule(hsotg, qh); 1177 } else { 1178 status = dwc2_periodic_channel_available(hsotg); 1179 if (status) { 1180 dev_info(hsotg->dev, 1181 "%s: No host channel available for periodic transfer\n", 1182 __func__); 1183 return status; 1184 } 1185 1186 status = dwc2_check_periodic_bandwidth(hsotg, qh); 1187 } 1188 1189 if (status) { 1190 dev_dbg(hsotg->dev, 1191 "%s: Insufficient periodic bandwidth for periodic transfer\n", 1192 __func__); 1193 return status; 1194 } 1195 1196 if (!hsotg->params.uframe_sched) 1197 /* Reserve periodic channel */ 1198 hsotg->periodic_channels++; 1199 1200 /* Update claimed usecs per (micro)frame */ 1201 hsotg->periodic_usecs += qh->host_us; 1202 1203 dwc2_pick_first_frame(hsotg, qh); 1204 1205 return 0; 1206 } 1207 1208 /** 1209 * dwc2_do_unreserve() - Actually release the periodic reservation 1210 * 1211 * This function actually releases the periodic bandwidth that was reserved 1212 * by the given qh. 1213 * 1214 * @hsotg: The HCD state structure for the DWC OTG controller 1215 * @qh: QH for the periodic transfer. 1216 */ 1217 static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1218 { 1219 assert_spin_locked(&hsotg->lock); 1220 1221 WARN_ON(!qh->unreserve_pending); 1222 1223 /* No more unreserve pending--we're doing it */ 1224 qh->unreserve_pending = false; 1225 1226 if (WARN_ON(!list_empty(&qh->qh_list_entry))) 1227 list_del_init(&qh->qh_list_entry); 1228 1229 /* Update claimed usecs per (micro)frame */ 1230 hsotg->periodic_usecs -= qh->host_us; 1231 1232 if (hsotg->params.uframe_sched) { 1233 dwc2_uframe_unschedule(hsotg, qh); 1234 } else { 1235 /* Release periodic channel reservation */ 1236 hsotg->periodic_channels--; 1237 } 1238 } 1239 1240 /** 1241 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation 1242 * 1243 * According to the kernel doc for usb_submit_urb() (specifically the part about 1244 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as 1245 * long as a device driver keeps submitting. Since we're using HCD_BH to give 1246 * back the URB we need to give the driver a little bit of time before we 1247 * release the reservation. This worker is called after the appropriate 1248 * delay. 1249 * 1250 * @t: Address to a qh unreserve_work. 1251 */ 1252 static void dwc2_unreserve_timer_fn(struct timer_list *t) 1253 { 1254 struct dwc2_qh *qh = from_timer(qh, t, unreserve_timer); 1255 struct dwc2_hsotg *hsotg = qh->hsotg; 1256 unsigned long flags; 1257 1258 /* 1259 * Wait for the lock, or for us to be scheduled again. We 1260 * could be scheduled again if: 1261 * - We started executing but didn't get the lock yet. 1262 * - A new reservation came in, but cancel didn't take effect 1263 * because we already started executing. 1264 * - The timer has been kicked again. 1265 * In that case cancel and wait for the next call. 1266 */ 1267 while (!spin_trylock_irqsave(&hsotg->lock, flags)) { 1268 if (timer_pending(&qh->unreserve_timer)) 1269 return; 1270 } 1271 1272 /* 1273 * Might be no more unreserve pending if: 1274 * - We started executing but didn't get the lock yet. 1275 * - A new reservation came in, but cancel didn't take effect 1276 * because we already started executing. 1277 * 1278 * We can't put this in the loop above because unreserve_pending needs 1279 * to be accessed under lock, so we can only check it once we got the 1280 * lock. 1281 */ 1282 if (qh->unreserve_pending) 1283 dwc2_do_unreserve(hsotg, qh); 1284 1285 spin_unlock_irqrestore(&hsotg->lock, flags); 1286 } 1287 1288 /** 1289 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 1290 * host channel is large enough to handle the maximum data transfer in a single 1291 * (micro)frame for a periodic transfer 1292 * 1293 * @hsotg: The HCD state structure for the DWC OTG controller 1294 * @qh: QH for a periodic endpoint 1295 * 1296 * Return: 0 if successful, negative error code otherwise 1297 */ 1298 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 1299 struct dwc2_qh *qh) 1300 { 1301 u32 max_xfer_size; 1302 u32 max_channel_xfer_size; 1303 int status = 0; 1304 1305 max_xfer_size = qh->maxp * qh->maxp_mult; 1306 max_channel_xfer_size = hsotg->params.max_transfer_size; 1307 1308 if (max_xfer_size > max_channel_xfer_size) { 1309 dev_err(hsotg->dev, 1310 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 1311 __func__, max_xfer_size, max_channel_xfer_size); 1312 status = -ENOSPC; 1313 } 1314 1315 return status; 1316 } 1317 1318 /** 1319 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 1320 * the periodic schedule 1321 * 1322 * @hsotg: The HCD state structure for the DWC OTG controller 1323 * @qh: QH for the periodic transfer. The QH should already contain the 1324 * scheduling information. 1325 * 1326 * Return: 0 if successful, negative error code otherwise 1327 */ 1328 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1329 { 1330 int status; 1331 1332 status = dwc2_check_max_xfer_size(hsotg, qh); 1333 if (status) { 1334 dev_dbg(hsotg->dev, 1335 "%s: Channel max transfer size too small for periodic transfer\n", 1336 __func__); 1337 return status; 1338 } 1339 1340 /* Cancel pending unreserve; if canceled OK, unreserve was pending */ 1341 if (del_timer(&qh->unreserve_timer)) 1342 WARN_ON(!qh->unreserve_pending); 1343 1344 /* 1345 * Only need to reserve if there's not an unreserve pending, since if an 1346 * unreserve is pending then by definition our old reservation is still 1347 * valid. Unreserve might still be pending even if we didn't cancel if 1348 * dwc2_unreserve_timer_fn() already started. Code in the timer handles 1349 * that case. 1350 */ 1351 if (!qh->unreserve_pending) { 1352 status = dwc2_do_reserve(hsotg, qh); 1353 if (status) 1354 return status; 1355 } else { 1356 /* 1357 * It might have been a while, so make sure that frame_number 1358 * is still good. Note: we could also try to use the similar 1359 * dwc2_next_periodic_start() but that schedules much more 1360 * tightly and we might need to hurry and queue things up. 1361 */ 1362 if (dwc2_frame_num_le(qh->next_active_frame, 1363 hsotg->frame_number)) 1364 dwc2_pick_first_frame(hsotg, qh); 1365 } 1366 1367 qh->unreserve_pending = 0; 1368 1369 if (hsotg->params.dma_desc_enable) 1370 /* Don't rely on SOF and start in ready schedule */ 1371 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 1372 else 1373 /* Always start in inactive schedule */ 1374 list_add_tail(&qh->qh_list_entry, 1375 &hsotg->periodic_sched_inactive); 1376 1377 return 0; 1378 } 1379 1380 /** 1381 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 1382 * from the periodic schedule 1383 * 1384 * @hsotg: The HCD state structure for the DWC OTG controller 1385 * @qh: QH for the periodic transfer 1386 */ 1387 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 1388 struct dwc2_qh *qh) 1389 { 1390 bool did_modify; 1391 1392 assert_spin_locked(&hsotg->lock); 1393 1394 /* 1395 * Schedule the unreserve to happen in a little bit. Cases here: 1396 * - Unreserve worker might be sitting there waiting to grab the lock. 1397 * In this case it will notice it's been schedule again and will 1398 * quit. 1399 * - Unreserve worker might not be scheduled. 1400 * 1401 * We should never already be scheduled since dwc2_schedule_periodic() 1402 * should have canceled the scheduled unreserve timer (hence the 1403 * warning on did_modify). 1404 * 1405 * We add + 1 to the timer to guarantee that at least 1 jiffy has 1406 * passed (otherwise if the jiffy counter might tick right after we 1407 * read it and we'll get no delay). 1408 */ 1409 did_modify = mod_timer(&qh->unreserve_timer, 1410 jiffies + DWC2_UNRESERVE_DELAY + 1); 1411 WARN_ON(did_modify); 1412 qh->unreserve_pending = 1; 1413 1414 list_del_init(&qh->qh_list_entry); 1415 } 1416 1417 /** 1418 * dwc2_wait_timer_fn() - Timer function to re-queue after waiting 1419 * 1420 * As per the spec, a NAK indicates that "a function is temporarily unable to 1421 * transmit or receive data, but will eventually be able to do so without need 1422 * of host intervention". 1423 * 1424 * That means that when we encounter a NAK we're supposed to retry. 1425 * 1426 * ...but if we retry right away (from the interrupt handler that saw the NAK) 1427 * then we can end up with an interrupt storm (if the other side keeps NAKing 1428 * us) because on slow enough CPUs it could take us longer to get out of the 1429 * interrupt routine than it takes for the device to send another NAK. That 1430 * leads to a constant stream of NAK interrupts and the CPU locks. 1431 * 1432 * ...so instead of retrying right away in the case of a NAK we'll set a timer 1433 * to retry some time later. This function handles that timer and moves the 1434 * qh back to the "inactive" list, then queues transactions. 1435 * 1436 * @t: Pointer to wait_timer in a qh. 1437 * 1438 * Return: HRTIMER_NORESTART to not automatically restart this timer. 1439 */ 1440 static enum hrtimer_restart dwc2_wait_timer_fn(struct hrtimer *t) 1441 { 1442 struct dwc2_qh *qh = container_of(t, struct dwc2_qh, wait_timer); 1443 struct dwc2_hsotg *hsotg = qh->hsotg; 1444 unsigned long flags; 1445 1446 spin_lock_irqsave(&hsotg->lock, flags); 1447 1448 /* 1449 * We'll set wait_timer_cancel to true if we want to cancel this 1450 * operation in dwc2_hcd_qh_unlink(). 1451 */ 1452 if (!qh->wait_timer_cancel) { 1453 enum dwc2_transaction_type tr_type; 1454 1455 qh->want_wait = false; 1456 1457 list_move(&qh->qh_list_entry, 1458 &hsotg->non_periodic_sched_inactive); 1459 1460 tr_type = dwc2_hcd_select_transactions(hsotg); 1461 if (tr_type != DWC2_TRANSACTION_NONE) 1462 dwc2_hcd_queue_transactions(hsotg, tr_type); 1463 } 1464 1465 spin_unlock_irqrestore(&hsotg->lock, flags); 1466 return HRTIMER_NORESTART; 1467 } 1468 1469 /** 1470 * dwc2_qh_init() - Initializes a QH structure 1471 * 1472 * @hsotg: The HCD state structure for the DWC OTG controller 1473 * @qh: The QH to init 1474 * @urb: Holds the information about the device/endpoint needed to initialize 1475 * the QH 1476 * @mem_flags: Flags for allocating memory. 1477 */ 1478 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1479 struct dwc2_hcd_urb *urb, gfp_t mem_flags) 1480 { 1481 int dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1482 u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 1483 bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); 1484 bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); 1485 bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); 1486 u32 hprt = dwc2_readl(hsotg, HPRT0); 1487 u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1488 bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && 1489 dev_speed != USB_SPEED_HIGH); 1490 int maxp = dwc2_hcd_get_maxp(&urb->pipe_info); 1491 int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info); 1492 int bytecount = maxp_mult * maxp; 1493 char *speed, *type; 1494 1495 /* Initialize QH */ 1496 qh->hsotg = hsotg; 1497 timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0); 1498 hrtimer_init(&qh->wait_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1499 qh->wait_timer.function = &dwc2_wait_timer_fn; 1500 qh->ep_type = ep_type; 1501 qh->ep_is_in = ep_is_in; 1502 1503 qh->data_toggle = DWC2_HC_PID_DATA0; 1504 qh->maxp = maxp; 1505 qh->maxp_mult = maxp_mult; 1506 INIT_LIST_HEAD(&qh->qtd_list); 1507 INIT_LIST_HEAD(&qh->qh_list_entry); 1508 1509 qh->do_split = do_split; 1510 qh->dev_speed = dev_speed; 1511 1512 if (ep_is_int || ep_is_isoc) { 1513 /* Compute scheduling parameters once and save them */ 1514 int host_speed = do_split ? USB_SPEED_HIGH : dev_speed; 1515 struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv, 1516 mem_flags, 1517 &qh->ttport); 1518 int device_ns; 1519 1520 qh->dwc_tt = dwc_tt; 1521 1522 qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in, 1523 ep_is_isoc, bytecount)); 1524 device_ns = usb_calc_bus_time(dev_speed, ep_is_in, 1525 ep_is_isoc, bytecount); 1526 1527 if (do_split && dwc_tt) 1528 device_ns += dwc_tt->usb_tt->think_time; 1529 qh->device_us = NS_TO_US(device_ns); 1530 1531 qh->device_interval = urb->interval; 1532 qh->host_interval = urb->interval * (do_split ? 8 : 1); 1533 1534 /* 1535 * Schedule low speed if we're running the host in low or 1536 * full speed OR if we've got a "TT" to deal with to access this 1537 * device. 1538 */ 1539 qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED || 1540 dwc_tt; 1541 1542 if (do_split) { 1543 /* We won't know num transfers until we schedule */ 1544 qh->num_hs_transfers = -1; 1545 } else if (dev_speed == USB_SPEED_HIGH) { 1546 qh->num_hs_transfers = 1; 1547 } else { 1548 qh->num_hs_transfers = 0; 1549 } 1550 1551 /* We'll schedule later when we have something to do */ 1552 } 1553 1554 switch (dev_speed) { 1555 case USB_SPEED_LOW: 1556 speed = "low"; 1557 break; 1558 case USB_SPEED_FULL: 1559 speed = "full"; 1560 break; 1561 case USB_SPEED_HIGH: 1562 speed = "high"; 1563 break; 1564 default: 1565 speed = "?"; 1566 break; 1567 } 1568 1569 switch (qh->ep_type) { 1570 case USB_ENDPOINT_XFER_ISOC: 1571 type = "isochronous"; 1572 break; 1573 case USB_ENDPOINT_XFER_INT: 1574 type = "interrupt"; 1575 break; 1576 case USB_ENDPOINT_XFER_CONTROL: 1577 type = "control"; 1578 break; 1579 case USB_ENDPOINT_XFER_BULK: 1580 type = "bulk"; 1581 break; 1582 default: 1583 type = "?"; 1584 break; 1585 } 1586 1587 dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type, 1588 speed, bytecount); 1589 dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh, 1590 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1591 dwc2_hcd_get_ep_num(&urb->pipe_info), 1592 ep_is_in ? "IN" : "OUT"); 1593 if (ep_is_int || ep_is_isoc) { 1594 dwc2_sch_dbg(hsotg, 1595 "QH=%p ...duration: host=%d us, device=%d us\n", 1596 qh, qh->host_us, qh->device_us); 1597 dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n", 1598 qh, qh->host_interval, qh->device_interval); 1599 if (qh->schedule_low_speed) 1600 dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n", 1601 qh, dwc2_get_ls_map(hsotg, qh)); 1602 } 1603 } 1604 1605 /** 1606 * dwc2_hcd_qh_create() - Allocates and initializes a QH 1607 * 1608 * @hsotg: The HCD state structure for the DWC OTG controller 1609 * @urb: Holds the information about the device/endpoint needed 1610 * to initialize the QH 1611 * @mem_flags: Flags for allocating memory. 1612 * 1613 * Return: Pointer to the newly allocated QH, or NULL on error 1614 */ 1615 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 1616 struct dwc2_hcd_urb *urb, 1617 gfp_t mem_flags) 1618 { 1619 struct dwc2_qh *qh; 1620 1621 if (!urb->priv) 1622 return NULL; 1623 1624 /* Allocate memory */ 1625 qh = kzalloc(sizeof(*qh), mem_flags); 1626 if (!qh) 1627 return NULL; 1628 1629 dwc2_qh_init(hsotg, qh, urb, mem_flags); 1630 1631 if (hsotg->params.dma_desc_enable && 1632 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 1633 dwc2_hcd_qh_free(hsotg, qh); 1634 return NULL; 1635 } 1636 1637 return qh; 1638 } 1639 1640 /** 1641 * dwc2_hcd_qh_free() - Frees the QH 1642 * 1643 * @hsotg: HCD instance 1644 * @qh: The QH to free 1645 * 1646 * QH should already be removed from the list. QTD list should already be empty 1647 * if called from URB Dequeue. 1648 * 1649 * Must NOT be called with interrupt disabled or spinlock held 1650 */ 1651 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1652 { 1653 /* Make sure any unreserve work is finished. */ 1654 if (del_timer_sync(&qh->unreserve_timer)) { 1655 unsigned long flags; 1656 1657 spin_lock_irqsave(&hsotg->lock, flags); 1658 dwc2_do_unreserve(hsotg, qh); 1659 spin_unlock_irqrestore(&hsotg->lock, flags); 1660 } 1661 1662 /* 1663 * We don't have the lock so we can safely wait until the wait timer 1664 * finishes. Of course, at this point in time we'd better have set 1665 * wait_timer_active to false so if this timer was still pending it 1666 * won't do anything anyway, but we want it to finish before we free 1667 * memory. 1668 */ 1669 hrtimer_cancel(&qh->wait_timer); 1670 1671 dwc2_host_put_tt_info(hsotg, qh->dwc_tt); 1672 1673 if (qh->desc_list) 1674 dwc2_hcd_qh_free_ddma(hsotg, qh); 1675 else if (hsotg->unaligned_cache && qh->dw_align_buf) 1676 kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf); 1677 1678 kfree(qh); 1679 } 1680 1681 /** 1682 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 1683 * schedule if it is not already in the schedule. If the QH is already in 1684 * the schedule, no action is taken. 1685 * 1686 * @hsotg: The HCD state structure for the DWC OTG controller 1687 * @qh: The QH to add 1688 * 1689 * Return: 0 if successful, negative error code otherwise 1690 */ 1691 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1692 { 1693 int status; 1694 u32 intr_mask; 1695 ktime_t delay; 1696 1697 if (dbg_qh(qh)) 1698 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1699 1700 if (!list_empty(&qh->qh_list_entry)) 1701 /* QH already in a schedule */ 1702 return 0; 1703 1704 /* Add the new QH to the appropriate schedule */ 1705 if (dwc2_qh_is_non_per(qh)) { 1706 /* Schedule right away */ 1707 qh->start_active_frame = hsotg->frame_number; 1708 qh->next_active_frame = qh->start_active_frame; 1709 1710 if (qh->want_wait) { 1711 list_add_tail(&qh->qh_list_entry, 1712 &hsotg->non_periodic_sched_waiting); 1713 qh->wait_timer_cancel = false; 1714 delay = ktime_set(0, DWC2_RETRY_WAIT_DELAY); 1715 hrtimer_start(&qh->wait_timer, delay, HRTIMER_MODE_REL); 1716 } else { 1717 list_add_tail(&qh->qh_list_entry, 1718 &hsotg->non_periodic_sched_inactive); 1719 } 1720 return 0; 1721 } 1722 1723 status = dwc2_schedule_periodic(hsotg, qh); 1724 if (status) 1725 return status; 1726 if (!hsotg->periodic_qh_count) { 1727 intr_mask = dwc2_readl(hsotg, GINTMSK); 1728 intr_mask |= GINTSTS_SOF; 1729 dwc2_writel(hsotg, intr_mask, GINTMSK); 1730 } 1731 hsotg->periodic_qh_count++; 1732 1733 return 0; 1734 } 1735 1736 /** 1737 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 1738 * schedule. Memory is not freed. 1739 * 1740 * @hsotg: The HCD state structure 1741 * @qh: QH to remove from schedule 1742 */ 1743 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1744 { 1745 u32 intr_mask; 1746 1747 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1748 1749 /* If the wait_timer is pending, this will stop it from acting */ 1750 qh->wait_timer_cancel = true; 1751 1752 if (list_empty(&qh->qh_list_entry)) 1753 /* QH is not in a schedule */ 1754 return; 1755 1756 if (dwc2_qh_is_non_per(qh)) { 1757 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 1758 hsotg->non_periodic_qh_ptr = 1759 hsotg->non_periodic_qh_ptr->next; 1760 list_del_init(&qh->qh_list_entry); 1761 return; 1762 } 1763 1764 dwc2_deschedule_periodic(hsotg, qh); 1765 hsotg->periodic_qh_count--; 1766 if (!hsotg->periodic_qh_count && 1767 !hsotg->params.dma_desc_enable) { 1768 intr_mask = dwc2_readl(hsotg, GINTMSK); 1769 intr_mask &= ~GINTSTS_SOF; 1770 dwc2_writel(hsotg, intr_mask, GINTMSK); 1771 } 1772 } 1773 1774 /** 1775 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split. 1776 * 1777 * This is called for setting next_active_frame for periodic splits for all but 1778 * the first packet of the split. Confusing? I thought so... 1779 * 1780 * Periodic splits are single low/full speed transfers that we end up splitting 1781 * up into several high speed transfers. They always fit into one full (1 ms) 1782 * frame but might be split over several microframes (125 us each). We to put 1783 * each of the parts on a very specific high speed frame. 1784 * 1785 * This function figures out where the next active uFrame needs to be. 1786 * 1787 * @hsotg: The HCD state structure 1788 * @qh: QH for the periodic transfer. 1789 * @frame_number: The current frame number. 1790 * 1791 * Return: number missed by (or 0 if we didn't miss). 1792 */ 1793 static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, 1794 struct dwc2_qh *qh, u16 frame_number) 1795 { 1796 u16 old_frame = qh->next_active_frame; 1797 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1798 int missed = 0; 1799 u16 incr; 1800 1801 /* 1802 * See dwc2_uframe_schedule_split() for split scheduling. 1803 * 1804 * Basically: increment 1 normally, but 2 right after the start split 1805 * (except for ISOC out). 1806 */ 1807 if (old_frame == qh->start_active_frame && 1808 !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)) 1809 incr = 2; 1810 else 1811 incr = 1; 1812 1813 qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr); 1814 1815 /* 1816 * Note that it's OK for frame_number to be 1 frame past 1817 * next_active_frame. Remember that next_active_frame is supposed to 1818 * be 1 frame _before_ when we want to be scheduled. If we're 1 frame 1819 * past it just means schedule ASAP. 1820 * 1821 * It's _not_ OK, however, if we're more than one frame past. 1822 */ 1823 if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) { 1824 /* 1825 * OOPS, we missed. That's actually pretty bad since 1826 * the hub will be unhappy; try ASAP I guess. 1827 */ 1828 missed = dwc2_frame_num_dec(prev_frame_number, 1829 qh->next_active_frame); 1830 qh->next_active_frame = frame_number; 1831 } 1832 1833 return missed; 1834 } 1835 1836 /** 1837 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start 1838 * 1839 * This is called for setting next_active_frame for a periodic transfer for 1840 * all cases other than midway through a periodic split. This will also update 1841 * start_active_frame. 1842 * 1843 * Since we _always_ keep start_active_frame as the start of the previous 1844 * transfer this is normally pretty easy: we just add our interval to 1845 * start_active_frame and we've got our answer. 1846 * 1847 * The tricks come into play if we miss. In that case we'll look for the next 1848 * slot we can fit into. 1849 * 1850 * @hsotg: The HCD state structure 1851 * @qh: QH for the periodic transfer. 1852 * @frame_number: The current frame number. 1853 * 1854 * Return: number missed by (or 0 if we didn't miss). 1855 */ 1856 static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg, 1857 struct dwc2_qh *qh, u16 frame_number) 1858 { 1859 int missed = 0; 1860 u16 interval = qh->host_interval; 1861 u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1862 1863 qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame, 1864 interval); 1865 1866 /* 1867 * The dwc2_frame_num_gt() function used below won't work terribly well 1868 * with if we just incremented by a really large intervals since the 1869 * frame counter only goes to 0x3fff. It's terribly unlikely that we 1870 * will have missed in this case anyway. Just go to exit. If we want 1871 * to try to do better we'll need to keep track of a bigger counter 1872 * somewhere in the driver and handle overflows. 1873 */ 1874 if (interval >= 0x1000) 1875 goto exit; 1876 1877 /* 1878 * Test for misses, which is when it's too late to schedule. 1879 * 1880 * A few things to note: 1881 * - We compare against prev_frame_number since start_active_frame 1882 * and next_active_frame are always 1 frame before we want things 1883 * to be active and we assume we can still get scheduled in the 1884 * current frame number. 1885 * - It's possible for start_active_frame (now incremented) to be 1886 * next_active_frame if we got an EO MISS (even_odd miss) which 1887 * basically means that we detected there wasn't enough time for 1888 * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us 1889 * at the last second. We want to make sure we don't schedule 1890 * another transfer for the same frame. My test webcam doesn't seem 1891 * terribly upset by missing a transfer but really doesn't like when 1892 * we do two transfers in the same frame. 1893 * - Some misses are expected. Specifically, in order to work 1894 * perfectly dwc2 really needs quite spectacular interrupt latency 1895 * requirements. It needs to be able to handle its interrupts 1896 * completely within 125 us of them being asserted. That not only 1897 * means that the dwc2 interrupt handler needs to be fast but it 1898 * means that nothing else in the system has to block dwc2 for a long 1899 * time. We can help with the dwc2 parts of this, but it's hard to 1900 * guarantee that a system will have interrupt latency < 125 us, so 1901 * we have to be robust to some misses. 1902 */ 1903 if (qh->start_active_frame == qh->next_active_frame || 1904 dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) { 1905 u16 ideal_start = qh->start_active_frame; 1906 int periods_in_map; 1907 1908 /* 1909 * Adjust interval as per gcd with map size. 1910 * See pmap_schedule() for more details here. 1911 */ 1912 if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH) 1913 periods_in_map = DWC2_HS_SCHEDULE_UFRAMES; 1914 else 1915 periods_in_map = DWC2_LS_SCHEDULE_FRAMES; 1916 interval = gcd(interval, periods_in_map); 1917 1918 do { 1919 qh->start_active_frame = dwc2_frame_num_inc( 1920 qh->start_active_frame, interval); 1921 } while (dwc2_frame_num_gt(prev_frame_number, 1922 qh->start_active_frame)); 1923 1924 missed = dwc2_frame_num_dec(qh->start_active_frame, 1925 ideal_start); 1926 } 1927 1928 exit: 1929 qh->next_active_frame = qh->start_active_frame; 1930 1931 return missed; 1932 } 1933 1934 /* 1935 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 1936 * non-periodic schedule. The QH is added to the inactive non-periodic 1937 * schedule if any QTDs are still attached to the QH. 1938 * 1939 * For periodic QHs, the QH is removed from the periodic queued schedule. If 1940 * there are any QTDs still attached to the QH, the QH is added to either the 1941 * periodic inactive schedule or the periodic ready schedule and its next 1942 * scheduled frame is calculated. The QH is placed in the ready schedule if 1943 * the scheduled frame has been reached already. Otherwise it's placed in the 1944 * inactive schedule. If there are no QTDs attached to the QH, the QH is 1945 * completely removed from the periodic schedule. 1946 */ 1947 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1948 int sched_next_periodic_split) 1949 { 1950 u16 old_frame = qh->next_active_frame; 1951 u16 frame_number; 1952 int missed; 1953 1954 if (dbg_qh(qh)) 1955 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1956 1957 if (dwc2_qh_is_non_per(qh)) { 1958 dwc2_hcd_qh_unlink(hsotg, qh); 1959 if (!list_empty(&qh->qtd_list)) 1960 /* Add back to inactive/waiting non-periodic schedule */ 1961 dwc2_hcd_qh_add(hsotg, qh); 1962 return; 1963 } 1964 1965 /* 1966 * Use the real frame number rather than the cached value as of the 1967 * last SOF just to get us a little closer to reality. Note that 1968 * means we don't actually know if we've already handled the SOF 1969 * interrupt for this frame. 1970 */ 1971 frame_number = dwc2_hcd_get_frame_number(hsotg); 1972 1973 if (sched_next_periodic_split) 1974 missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number); 1975 else 1976 missed = dwc2_next_periodic_start(hsotg, qh, frame_number); 1977 1978 dwc2_sch_vdbg(hsotg, 1979 "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n", 1980 qh, sched_next_periodic_split, frame_number, old_frame, 1981 qh->next_active_frame, 1982 dwc2_frame_num_dec(qh->next_active_frame, old_frame), 1983 missed, missed ? "MISS" : ""); 1984 1985 if (list_empty(&qh->qtd_list)) { 1986 dwc2_hcd_qh_unlink(hsotg, qh); 1987 return; 1988 } 1989 1990 /* 1991 * Remove from periodic_sched_queued and move to 1992 * appropriate queue 1993 * 1994 * Note: we purposely use the frame_number from the "hsotg" structure 1995 * since we know SOF interrupt will handle future frames. 1996 */ 1997 if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number)) 1998 list_move_tail(&qh->qh_list_entry, 1999 &hsotg->periodic_sched_ready); 2000 else 2001 list_move_tail(&qh->qh_list_entry, 2002 &hsotg->periodic_sched_inactive); 2003 } 2004 2005 /** 2006 * dwc2_hcd_qtd_init() - Initializes a QTD structure 2007 * 2008 * @qtd: The QTD to initialize 2009 * @urb: The associated URB 2010 */ 2011 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2012 { 2013 qtd->urb = urb; 2014 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 2015 USB_ENDPOINT_XFER_CONTROL) { 2016 /* 2017 * The only time the QTD data toggle is used is on the data 2018 * phase of control transfers. This phase always starts with 2019 * DATA1. 2020 */ 2021 qtd->data_toggle = DWC2_HC_PID_DATA1; 2022 qtd->control_phase = DWC2_CONTROL_SETUP; 2023 } 2024 2025 /* Start split */ 2026 qtd->complete_split = 0; 2027 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 2028 qtd->isoc_split_offset = 0; 2029 qtd->in_process = 0; 2030 2031 /* Store the qtd ptr in the urb to reference the QTD */ 2032 urb->qtd = qtd; 2033 } 2034 2035 /** 2036 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 2037 * Caller must hold driver lock. 2038 * 2039 * @hsotg: The DWC HCD structure 2040 * @qtd: The QTD to add 2041 * @qh: Queue head to add qtd to 2042 * 2043 * Return: 0 if successful, negative error code otherwise 2044 * 2045 * If the QH to which the QTD is added is not currently scheduled, it is placed 2046 * into the proper schedule based on its EP type. 2047 */ 2048 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2049 struct dwc2_qh *qh) 2050 { 2051 int retval; 2052 2053 if (unlikely(!qh)) { 2054 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 2055 retval = -EINVAL; 2056 goto fail; 2057 } 2058 2059 retval = dwc2_hcd_qh_add(hsotg, qh); 2060 if (retval) 2061 goto fail; 2062 2063 qtd->qh = qh; 2064 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 2065 2066 return 0; 2067 fail: 2068 return retval; 2069 } 2070