1 /* 2 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the functions to manage Queue Heads and Queue 39 * Transfer Descriptors for Host mode 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/io.h> 47 #include <linux/slab.h> 48 #include <linux/usb.h> 49 50 #include <linux/usb/hcd.h> 51 #include <linux/usb/ch11.h> 52 53 #include "core.h" 54 #include "hcd.h" 55 56 /** 57 * dwc2_qh_init() - Initializes a QH structure 58 * 59 * @hsotg: The HCD state structure for the DWC OTG controller 60 * @qh: The QH to init 61 * @urb: Holds the information about the device/endpoint needed to initialize 62 * the QH 63 */ 64 #define SCHEDULE_SLOP 10 65 static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 66 struct dwc2_hcd_urb *urb) 67 { 68 int dev_speed, hub_addr, hub_port; 69 char *speed, *type; 70 71 dev_vdbg(hsotg->dev, "%s()\n", __func__); 72 73 /* Initialize QH */ 74 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 75 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 76 77 qh->data_toggle = DWC2_HC_PID_DATA0; 78 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 79 INIT_LIST_HEAD(&qh->qtd_list); 80 INIT_LIST_HEAD(&qh->qh_list_entry); 81 82 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 83 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 84 85 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 86 87 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 88 hub_addr != 0 && hub_addr != 1) { 89 dev_vdbg(hsotg->dev, 90 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 91 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 92 hub_port); 93 qh->do_split = 1; 94 } 95 96 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 97 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 98 /* Compute scheduling parameters once and save them */ 99 u32 hprt, prtspd; 100 101 /* Todo: Account for split transfers in the bus time */ 102 int bytecount = 103 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 104 105 qh->usecs = NS_TO_US(usb_calc_bus_time(qh->do_split ? 106 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 107 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 108 bytecount)); 109 /* Start in a slightly future (micro)frame */ 110 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 111 SCHEDULE_SLOP); 112 qh->interval = urb->interval; 113 #if 0 114 /* Increase interrupt polling rate for debugging */ 115 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 116 qh->interval = 8; 117 #endif 118 hprt = readl(hsotg->regs + HPRT0); 119 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 120 if (prtspd == HPRT0_SPD_HIGH_SPEED && 121 (dev_speed == USB_SPEED_LOW || 122 dev_speed == USB_SPEED_FULL)) { 123 qh->interval *= 8; 124 qh->sched_frame |= 0x7; 125 qh->start_split_frame = qh->sched_frame; 126 } 127 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 128 } 129 130 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 131 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 132 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 133 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 134 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 135 dwc2_hcd_get_ep_num(&urb->pipe_info), 136 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 137 138 qh->dev_speed = dev_speed; 139 140 switch (dev_speed) { 141 case USB_SPEED_LOW: 142 speed = "low"; 143 break; 144 case USB_SPEED_FULL: 145 speed = "full"; 146 break; 147 case USB_SPEED_HIGH: 148 speed = "high"; 149 break; 150 default: 151 speed = "?"; 152 break; 153 } 154 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 155 156 switch (qh->ep_type) { 157 case USB_ENDPOINT_XFER_ISOC: 158 type = "isochronous"; 159 break; 160 case USB_ENDPOINT_XFER_INT: 161 type = "interrupt"; 162 break; 163 case USB_ENDPOINT_XFER_CONTROL: 164 type = "control"; 165 break; 166 case USB_ENDPOINT_XFER_BULK: 167 type = "bulk"; 168 break; 169 default: 170 type = "?"; 171 break; 172 } 173 174 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 175 176 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 177 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 178 qh->usecs); 179 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 180 qh->interval); 181 } 182 } 183 184 /** 185 * dwc2_hcd_qh_create() - Allocates and initializes a QH 186 * 187 * @hsotg: The HCD state structure for the DWC OTG controller 188 * @urb: Holds the information about the device/endpoint needed 189 * to initialize the QH 190 * @atomic_alloc: Flag to do atomic allocation if needed 191 * 192 * Return: Pointer to the newly allocated QH, or NULL on error 193 */ 194 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 195 struct dwc2_hcd_urb *urb, 196 gfp_t mem_flags) 197 { 198 struct dwc2_qh *qh; 199 200 if (!urb->priv) 201 return NULL; 202 203 /* Allocate memory */ 204 qh = kzalloc(sizeof(*qh), mem_flags); 205 if (!qh) 206 return NULL; 207 208 dwc2_qh_init(hsotg, qh, urb); 209 210 if (hsotg->core_params->dma_desc_enable > 0 && 211 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 212 dwc2_hcd_qh_free(hsotg, qh); 213 return NULL; 214 } 215 216 return qh; 217 } 218 219 /** 220 * dwc2_hcd_qh_free() - Frees the QH 221 * 222 * @hsotg: HCD instance 223 * @qh: The QH to free 224 * 225 * QH should already be removed from the list. QTD list should already be empty 226 * if called from URB Dequeue. 227 * 228 * Must NOT be called with interrupt disabled or spinlock held 229 */ 230 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 231 { 232 if (hsotg->core_params->dma_desc_enable > 0) { 233 dwc2_hcd_qh_free_ddma(hsotg, qh); 234 } else { 235 /* kfree(NULL) is safe */ 236 kfree(qh->dw_align_buf); 237 qh->dw_align_buf_dma = (dma_addr_t)0; 238 } 239 kfree(qh); 240 } 241 242 /** 243 * dwc2_periodic_channel_available() - Checks that a channel is available for a 244 * periodic transfer 245 * 246 * @hsotg: The HCD state structure for the DWC OTG controller 247 * 248 * Return: 0 if successful, negative error code otherwise 249 */ 250 static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 251 { 252 /* 253 * Currently assuming that there is a dedicated host channel for 254 * each periodic transaction plus at least one host channel for 255 * non-periodic transactions 256 */ 257 int status; 258 int num_channels; 259 260 num_channels = hsotg->core_params->host_channels; 261 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 262 num_channels 263 && hsotg->periodic_channels < num_channels - 1) { 264 status = 0; 265 } else { 266 dev_dbg(hsotg->dev, 267 "%s: Total channels: %d, Periodic: %d, " 268 "Non-periodic: %d\n", __func__, num_channels, 269 hsotg->periodic_channels, hsotg->non_periodic_channels); 270 status = -ENOSPC; 271 } 272 273 return status; 274 } 275 276 /** 277 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 278 * for the specified QH in the periodic schedule 279 * 280 * @hsotg: The HCD state structure for the DWC OTG controller 281 * @qh: QH containing periodic bandwidth required 282 * 283 * Return: 0 if successful, negative error code otherwise 284 * 285 * For simplicity, this calculation assumes that all the transfers in the 286 * periodic schedule may occur in the same (micro)frame 287 */ 288 static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 289 struct dwc2_qh *qh) 290 { 291 int status; 292 s16 max_claimed_usecs; 293 294 status = 0; 295 296 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 297 /* 298 * High speed mode 299 * Max periodic usecs is 80% x 125 usec = 100 usec 300 */ 301 max_claimed_usecs = 100 - qh->usecs; 302 } else { 303 /* 304 * Full speed mode 305 * Max periodic usecs is 90% x 1000 usec = 900 usec 306 */ 307 max_claimed_usecs = 900 - qh->usecs; 308 } 309 310 if (hsotg->periodic_usecs > max_claimed_usecs) { 311 dev_err(hsotg->dev, 312 "%s: already claimed usecs %d, required usecs %d\n", 313 __func__, hsotg->periodic_usecs, qh->usecs); 314 status = -ENOSPC; 315 } 316 317 return status; 318 } 319 320 /** 321 * Microframe scheduler 322 * track the total use in hsotg->frame_usecs 323 * keep each qh use in qh->frame_usecs 324 * when surrendering the qh then donate the time back 325 */ 326 static const unsigned short max_uframe_usecs[] = { 327 100, 100, 100, 100, 100, 100, 30, 0 328 }; 329 330 void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 331 { 332 int i; 333 334 for (i = 0; i < 8; i++) 335 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 336 } 337 338 static int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 339 { 340 unsigned short utime = qh->usecs; 341 int i; 342 343 for (i = 0; i < 8; i++) { 344 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 345 if (utime <= hsotg->frame_usecs[i]) { 346 hsotg->frame_usecs[i] -= utime; 347 qh->frame_usecs[i] += utime; 348 return i; 349 } 350 } 351 return -ENOSPC; 352 } 353 354 /* 355 * use this for FS apps that can span multiple uframes 356 */ 357 static int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 358 { 359 unsigned short utime = qh->usecs; 360 unsigned short xtime; 361 int t_left; 362 int i; 363 int j; 364 int k; 365 366 for (i = 0; i < 8; i++) { 367 if (hsotg->frame_usecs[i] <= 0) 368 continue; 369 370 /* 371 * we need n consecutive slots so use j as a start slot 372 * j plus j+1 must be enough time (for now) 373 */ 374 xtime = hsotg->frame_usecs[i]; 375 for (j = i + 1; j < 8; j++) { 376 /* 377 * if we add this frame remaining time to xtime we may 378 * be OK, if not we need to test j for a complete frame 379 */ 380 if (xtime + hsotg->frame_usecs[j] < utime) { 381 if (hsotg->frame_usecs[j] < 382 max_uframe_usecs[j]) 383 continue; 384 } 385 if (xtime >= utime) { 386 t_left = utime; 387 for (k = i; k < 8; k++) { 388 t_left -= hsotg->frame_usecs[k]; 389 if (t_left <= 0) { 390 qh->frame_usecs[k] += 391 hsotg->frame_usecs[k] 392 + t_left; 393 hsotg->frame_usecs[k] = -t_left; 394 return i; 395 } else { 396 qh->frame_usecs[k] += 397 hsotg->frame_usecs[k]; 398 hsotg->frame_usecs[k] = 0; 399 } 400 } 401 } 402 /* add the frame time to x time */ 403 xtime += hsotg->frame_usecs[j]; 404 /* we must have a fully available next frame or break */ 405 if (xtime < utime && 406 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 407 continue; 408 } 409 } 410 return -ENOSPC; 411 } 412 413 static int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 414 { 415 int ret; 416 417 if (qh->dev_speed == USB_SPEED_HIGH) { 418 /* if this is a hs transaction we need a full frame */ 419 ret = dwc2_find_single_uframe(hsotg, qh); 420 } else { 421 /* 422 * if this is a fs transaction we may need a sequence 423 * of frames 424 */ 425 ret = dwc2_find_multi_uframe(hsotg, qh); 426 } 427 return ret; 428 } 429 430 /** 431 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 432 * host channel is large enough to handle the maximum data transfer in a single 433 * (micro)frame for a periodic transfer 434 * 435 * @hsotg: The HCD state structure for the DWC OTG controller 436 * @qh: QH for a periodic endpoint 437 * 438 * Return: 0 if successful, negative error code otherwise 439 */ 440 static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 441 struct dwc2_qh *qh) 442 { 443 u32 max_xfer_size; 444 u32 max_channel_xfer_size; 445 int status = 0; 446 447 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 448 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 449 450 if (max_xfer_size > max_channel_xfer_size) { 451 dev_err(hsotg->dev, 452 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 453 __func__, max_xfer_size, max_channel_xfer_size); 454 status = -ENOSPC; 455 } 456 457 return status; 458 } 459 460 /** 461 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 462 * the periodic schedule 463 * 464 * @hsotg: The HCD state structure for the DWC OTG controller 465 * @qh: QH for the periodic transfer. The QH should already contain the 466 * scheduling information. 467 * 468 * Return: 0 if successful, negative error code otherwise 469 */ 470 static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 471 { 472 int status; 473 474 if (hsotg->core_params->uframe_sched > 0) { 475 int frame = -1; 476 477 status = dwc2_find_uframe(hsotg, qh); 478 if (status == 0) 479 frame = 7; 480 else if (status > 0) 481 frame = status - 1; 482 483 /* Set the new frame up */ 484 if (frame >= 0) { 485 qh->sched_frame &= ~0x7; 486 qh->sched_frame |= (frame & 7); 487 } 488 489 if (status > 0) 490 status = 0; 491 } else { 492 status = dwc2_periodic_channel_available(hsotg); 493 if (status) { 494 dev_info(hsotg->dev, 495 "%s: No host channel available for periodic transfer\n", 496 __func__); 497 return status; 498 } 499 500 status = dwc2_check_periodic_bandwidth(hsotg, qh); 501 } 502 503 if (status) { 504 dev_dbg(hsotg->dev, 505 "%s: Insufficient periodic bandwidth for periodic transfer\n", 506 __func__); 507 return status; 508 } 509 510 status = dwc2_check_max_xfer_size(hsotg, qh); 511 if (status) { 512 dev_dbg(hsotg->dev, 513 "%s: Channel max transfer size too small for periodic transfer\n", 514 __func__); 515 return status; 516 } 517 518 if (hsotg->core_params->dma_desc_enable > 0) 519 /* Don't rely on SOF and start in ready schedule */ 520 list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 521 else 522 /* Always start in inactive schedule */ 523 list_add_tail(&qh->qh_list_entry, 524 &hsotg->periodic_sched_inactive); 525 526 if (hsotg->core_params->uframe_sched <= 0) 527 /* Reserve periodic channel */ 528 hsotg->periodic_channels++; 529 530 /* Update claimed usecs per (micro)frame */ 531 hsotg->periodic_usecs += qh->usecs; 532 533 return status; 534 } 535 536 /** 537 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 538 * from the periodic schedule 539 * 540 * @hsotg: The HCD state structure for the DWC OTG controller 541 * @qh: QH for the periodic transfer 542 */ 543 static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 544 struct dwc2_qh *qh) 545 { 546 int i; 547 548 list_del_init(&qh->qh_list_entry); 549 550 /* Update claimed usecs per (micro)frame */ 551 hsotg->periodic_usecs -= qh->usecs; 552 553 if (hsotg->core_params->uframe_sched > 0) { 554 for (i = 0; i < 8; i++) { 555 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 556 qh->frame_usecs[i] = 0; 557 } 558 } else { 559 /* Release periodic channel reservation */ 560 hsotg->periodic_channels--; 561 } 562 } 563 564 /** 565 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 566 * schedule if it is not already in the schedule. If the QH is already in 567 * the schedule, no action is taken. 568 * 569 * @hsotg: The HCD state structure for the DWC OTG controller 570 * @qh: The QH to add 571 * 572 * Return: 0 if successful, negative error code otherwise 573 */ 574 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 575 { 576 int status; 577 u32 intr_mask; 578 579 if (dbg_qh(qh)) 580 dev_vdbg(hsotg->dev, "%s()\n", __func__); 581 582 if (!list_empty(&qh->qh_list_entry)) 583 /* QH already in a schedule */ 584 return 0; 585 586 /* Add the new QH to the appropriate schedule */ 587 if (dwc2_qh_is_non_per(qh)) { 588 /* Always start in inactive schedule */ 589 list_add_tail(&qh->qh_list_entry, 590 &hsotg->non_periodic_sched_inactive); 591 return 0; 592 } 593 594 status = dwc2_schedule_periodic(hsotg, qh); 595 if (status) 596 return status; 597 if (!hsotg->periodic_qh_count) { 598 intr_mask = readl(hsotg->regs + GINTMSK); 599 intr_mask |= GINTSTS_SOF; 600 writel(intr_mask, hsotg->regs + GINTMSK); 601 } 602 hsotg->periodic_qh_count++; 603 604 return 0; 605 } 606 607 /** 608 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 609 * schedule. Memory is not freed. 610 * 611 * @hsotg: The HCD state structure 612 * @qh: QH to remove from schedule 613 */ 614 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 615 { 616 u32 intr_mask; 617 618 dev_vdbg(hsotg->dev, "%s()\n", __func__); 619 620 if (list_empty(&qh->qh_list_entry)) 621 /* QH is not in a schedule */ 622 return; 623 624 if (dwc2_qh_is_non_per(qh)) { 625 if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 626 hsotg->non_periodic_qh_ptr = 627 hsotg->non_periodic_qh_ptr->next; 628 list_del_init(&qh->qh_list_entry); 629 return; 630 } 631 632 dwc2_deschedule_periodic(hsotg, qh); 633 hsotg->periodic_qh_count--; 634 if (!hsotg->periodic_qh_count) { 635 intr_mask = readl(hsotg->regs + GINTMSK); 636 intr_mask &= ~GINTSTS_SOF; 637 writel(intr_mask, hsotg->regs + GINTMSK); 638 } 639 } 640 641 /* 642 * Schedule the next continuing periodic split transfer 643 */ 644 static void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 645 struct dwc2_qh *qh, u16 frame_number, 646 int sched_next_periodic_split) 647 { 648 u16 incr; 649 650 if (sched_next_periodic_split) { 651 qh->sched_frame = frame_number; 652 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 653 if (dwc2_frame_num_le(frame_number, incr)) { 654 /* 655 * Allow one frame to elapse after start split 656 * microframe before scheduling complete split, but 657 * DON'T if we are doing the next start split in the 658 * same frame for an ISOC out 659 */ 660 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 661 qh->ep_is_in != 0) { 662 qh->sched_frame = 663 dwc2_frame_num_inc(qh->sched_frame, 1); 664 } 665 } 666 } else { 667 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 668 qh->interval); 669 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 670 qh->sched_frame = frame_number; 671 qh->sched_frame |= 0x7; 672 qh->start_split_frame = qh->sched_frame; 673 } 674 } 675 676 /* 677 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 678 * non-periodic schedule. The QH is added to the inactive non-periodic 679 * schedule if any QTDs are still attached to the QH. 680 * 681 * For periodic QHs, the QH is removed from the periodic queued schedule. If 682 * there are any QTDs still attached to the QH, the QH is added to either the 683 * periodic inactive schedule or the periodic ready schedule and its next 684 * scheduled frame is calculated. The QH is placed in the ready schedule if 685 * the scheduled frame has been reached already. Otherwise it's placed in the 686 * inactive schedule. If there are no QTDs attached to the QH, the QH is 687 * completely removed from the periodic schedule. 688 */ 689 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 690 int sched_next_periodic_split) 691 { 692 u16 frame_number; 693 694 if (dbg_qh(qh)) 695 dev_vdbg(hsotg->dev, "%s()\n", __func__); 696 697 if (dwc2_qh_is_non_per(qh)) { 698 dwc2_hcd_qh_unlink(hsotg, qh); 699 if (!list_empty(&qh->qtd_list)) 700 /* Add back to inactive non-periodic schedule */ 701 dwc2_hcd_qh_add(hsotg, qh); 702 return; 703 } 704 705 frame_number = dwc2_hcd_get_frame_number(hsotg); 706 707 if (qh->do_split) { 708 dwc2_sched_periodic_split(hsotg, qh, frame_number, 709 sched_next_periodic_split); 710 } else { 711 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 712 qh->interval); 713 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 714 qh->sched_frame = frame_number; 715 } 716 717 if (list_empty(&qh->qtd_list)) { 718 dwc2_hcd_qh_unlink(hsotg, qh); 719 return; 720 } 721 /* 722 * Remove from periodic_sched_queued and move to 723 * appropriate queue 724 */ 725 if ((hsotg->core_params->uframe_sched > 0 && 726 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 727 (hsotg->core_params->uframe_sched <= 0 && 728 qh->sched_frame == frame_number)) 729 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 730 else 731 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_inactive); 732 } 733 734 /** 735 * dwc2_hcd_qtd_init() - Initializes a QTD structure 736 * 737 * @qtd: The QTD to initialize 738 * @urb: The associated URB 739 */ 740 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 741 { 742 qtd->urb = urb; 743 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 744 USB_ENDPOINT_XFER_CONTROL) { 745 /* 746 * The only time the QTD data toggle is used is on the data 747 * phase of control transfers. This phase always starts with 748 * DATA1. 749 */ 750 qtd->data_toggle = DWC2_HC_PID_DATA1; 751 qtd->control_phase = DWC2_CONTROL_SETUP; 752 } 753 754 /* Start split */ 755 qtd->complete_split = 0; 756 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 757 qtd->isoc_split_offset = 0; 758 qtd->in_process = 0; 759 760 /* Store the qtd ptr in the urb to reference the QTD */ 761 urb->qtd = qtd; 762 } 763 764 /** 765 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 766 * Caller must hold driver lock. 767 * 768 * @hsotg: The DWC HCD structure 769 * @qtd: The QTD to add 770 * @qh: Queue head to add qtd to 771 * 772 * Return: 0 if successful, negative error code otherwise 773 * 774 * If the QH to which the QTD is added is not currently scheduled, it is placed 775 * into the proper schedule based on its EP type. 776 */ 777 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 778 struct dwc2_qh *qh) 779 { 780 int retval; 781 782 if (unlikely(!qh)) { 783 dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 784 retval = -EINVAL; 785 goto fail; 786 } 787 788 retval = dwc2_hcd_qh_add(hsotg, qh); 789 if (retval) 790 goto fail; 791 792 qtd->qh = qh; 793 list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 794 795 return 0; 796 fail: 797 return retval; 798 } 799