15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2197ba5f4SPaul Zimmerman /*
3197ba5f4SPaul Zimmerman * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
4197ba5f4SPaul Zimmerman *
5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc.
6197ba5f4SPaul Zimmerman */
7197ba5f4SPaul Zimmerman
8197ba5f4SPaul Zimmerman /*
9197ba5f4SPaul Zimmerman * This file contains the functions to manage Queue Heads and Queue
10197ba5f4SPaul Zimmerman * Transfer Descriptors for Host mode
11197ba5f4SPaul Zimmerman */
12fb616e3fSDouglas Anderson #include <linux/gcd.h>
13197ba5f4SPaul Zimmerman #include <linux/kernel.h>
14197ba5f4SPaul Zimmerman #include <linux/module.h>
15197ba5f4SPaul Zimmerman #include <linux/spinlock.h>
16197ba5f4SPaul Zimmerman #include <linux/interrupt.h>
17197ba5f4SPaul Zimmerman #include <linux/dma-mapping.h>
18197ba5f4SPaul Zimmerman #include <linux/io.h>
19197ba5f4SPaul Zimmerman #include <linux/slab.h>
20197ba5f4SPaul Zimmerman #include <linux/usb.h>
21197ba5f4SPaul Zimmerman
22197ba5f4SPaul Zimmerman #include <linux/usb/hcd.h>
23197ba5f4SPaul Zimmerman #include <linux/usb/ch11.h>
24197ba5f4SPaul Zimmerman
25197ba5f4SPaul Zimmerman #include "core.h"
26197ba5f4SPaul Zimmerman #include "hcd.h"
27197ba5f4SPaul Zimmerman
2817dd5b64SDouglas Anderson /* Wait this long before releasing periodic reservation */
2917dd5b64SDouglas Anderson #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
3017dd5b64SDouglas Anderson
3138d2b5fbSDouglas Anderson /* If we get a NAK, wait this long before retrying */
32310780e8SNathan Chancellor #define DWC2_RETRY_WAIT_DELAY (1 * NSEC_PER_MSEC)
3338d2b5fbSDouglas Anderson
3417dd5b64SDouglas Anderson /**
35b951c6c7SDouglas Anderson * dwc2_periodic_channel_available() - Checks that a channel is available for a
36b951c6c7SDouglas Anderson * periodic transfer
37b951c6c7SDouglas Anderson *
38b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
39b951c6c7SDouglas Anderson *
40b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise
41b951c6c7SDouglas Anderson */
dwc2_periodic_channel_available(struct dwc2_hsotg * hsotg)42b951c6c7SDouglas Anderson static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
43b951c6c7SDouglas Anderson {
44b951c6c7SDouglas Anderson /*
45b951c6c7SDouglas Anderson * Currently assuming that there is a dedicated host channel for
46b951c6c7SDouglas Anderson * each periodic transaction plus at least one host channel for
47b951c6c7SDouglas Anderson * non-periodic transactions
48b951c6c7SDouglas Anderson */
49b951c6c7SDouglas Anderson int status;
50b951c6c7SDouglas Anderson int num_channels;
51b951c6c7SDouglas Anderson
52bea8e86cSJohn Youn num_channels = hsotg->params.host_channels;
53ab283202SJohn Youn if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
54ab283202SJohn Youn num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
55b951c6c7SDouglas Anderson status = 0;
56b951c6c7SDouglas Anderson } else {
57b951c6c7SDouglas Anderson dev_dbg(hsotg->dev,
589da51974SJohn Youn "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
599da51974SJohn Youn __func__, num_channels,
60b951c6c7SDouglas Anderson hsotg->periodic_channels, hsotg->non_periodic_channels);
61b951c6c7SDouglas Anderson status = -ENOSPC;
62b951c6c7SDouglas Anderson }
63b951c6c7SDouglas Anderson
64b951c6c7SDouglas Anderson return status;
65b951c6c7SDouglas Anderson }
66b951c6c7SDouglas Anderson
67b951c6c7SDouglas Anderson /**
68b951c6c7SDouglas Anderson * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
69b951c6c7SDouglas Anderson * for the specified QH in the periodic schedule
70b951c6c7SDouglas Anderson *
71b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
72b951c6c7SDouglas Anderson * @qh: QH containing periodic bandwidth required
73b951c6c7SDouglas Anderson *
74b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise
75b951c6c7SDouglas Anderson *
76b951c6c7SDouglas Anderson * For simplicity, this calculation assumes that all the transfers in the
77b951c6c7SDouglas Anderson * periodic schedule may occur in the same (micro)frame
78b951c6c7SDouglas Anderson */
dwc2_check_periodic_bandwidth(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)79b951c6c7SDouglas Anderson static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
80b951c6c7SDouglas Anderson struct dwc2_qh *qh)
81b951c6c7SDouglas Anderson {
82b951c6c7SDouglas Anderson int status;
83b951c6c7SDouglas Anderson s16 max_claimed_usecs;
84b951c6c7SDouglas Anderson
85b951c6c7SDouglas Anderson status = 0;
86b951c6c7SDouglas Anderson
87b951c6c7SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
88b951c6c7SDouglas Anderson /*
89b951c6c7SDouglas Anderson * High speed mode
90b951c6c7SDouglas Anderson * Max periodic usecs is 80% x 125 usec = 100 usec
91b951c6c7SDouglas Anderson */
92b951c6c7SDouglas Anderson max_claimed_usecs = 100 - qh->host_us;
93b951c6c7SDouglas Anderson } else {
94b951c6c7SDouglas Anderson /*
95b951c6c7SDouglas Anderson * Full speed mode
96b951c6c7SDouglas Anderson * Max periodic usecs is 90% x 1000 usec = 900 usec
97b951c6c7SDouglas Anderson */
98b951c6c7SDouglas Anderson max_claimed_usecs = 900 - qh->host_us;
99b951c6c7SDouglas Anderson }
100b951c6c7SDouglas Anderson
101b951c6c7SDouglas Anderson if (hsotg->periodic_usecs > max_claimed_usecs) {
102b951c6c7SDouglas Anderson dev_err(hsotg->dev,
103b951c6c7SDouglas Anderson "%s: already claimed usecs %d, required usecs %d\n",
104b951c6c7SDouglas Anderson __func__, hsotg->periodic_usecs, qh->host_us);
105b951c6c7SDouglas Anderson status = -ENOSPC;
106b951c6c7SDouglas Anderson }
107b951c6c7SDouglas Anderson
108b951c6c7SDouglas Anderson return status;
109b951c6c7SDouglas Anderson }
110b951c6c7SDouglas Anderson
111b951c6c7SDouglas Anderson /**
1129f9f09b0SDouglas Anderson * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
1139f9f09b0SDouglas Anderson *
1149f9f09b0SDouglas Anderson * @map: The bitmap representing the schedule; will be updated
1159f9f09b0SDouglas Anderson * upon success.
1169f9f09b0SDouglas Anderson * @bits_per_period: The schedule represents several periods. This is how many
1179f9f09b0SDouglas Anderson * bits are in each period. It's assumed that the beginning
1189f9f09b0SDouglas Anderson * of the schedule will repeat after its end.
1199f9f09b0SDouglas Anderson * @periods_in_map: The number of periods in the schedule.
1209f9f09b0SDouglas Anderson * @num_bits: The number of bits we need per period we want to reserve
1219f9f09b0SDouglas Anderson * in this function call.
1229f9f09b0SDouglas Anderson * @interval: How often we need to be scheduled for the reservation this
1239f9f09b0SDouglas Anderson * time. 1 means every period. 2 means every other period.
1249f9f09b0SDouglas Anderson * ...you get the picture?
1259f9f09b0SDouglas Anderson * @start: The bit number to start at. Normally 0. Must be within
1269f9f09b0SDouglas Anderson * the interval or we return failure right away.
1279f9f09b0SDouglas Anderson * @only_one_period: Normally we'll allow picking a start anywhere within the
1289f9f09b0SDouglas Anderson * first interval, since we can still make all repetition
1299f9f09b0SDouglas Anderson * requirements by doing that. However, if you pass true
1309f9f09b0SDouglas Anderson * here then we'll return failure if we can't fit within
1319f9f09b0SDouglas Anderson * the period that "start" is in.
1329f9f09b0SDouglas Anderson *
1339f9f09b0SDouglas Anderson * The idea here is that we want to schedule time for repeating events that all
1349f9f09b0SDouglas Anderson * want the same resource. The resource is divided into fixed-sized periods
1359f9f09b0SDouglas Anderson * and the events want to repeat every "interval" periods. The schedule
1369f9f09b0SDouglas Anderson * granularity is one bit.
1379f9f09b0SDouglas Anderson *
1389f9f09b0SDouglas Anderson * To keep things "simple", we'll represent our schedule with a bitmap that
1399f9f09b0SDouglas Anderson * contains a fixed number of periods. This gets rid of a lot of complexity
1409f9f09b0SDouglas Anderson * but does mean that we need to handle things specially (and non-ideally) if
1419f9f09b0SDouglas Anderson * the number of the periods in the schedule doesn't match well with the
1429f9f09b0SDouglas Anderson * intervals that we're trying to schedule.
1439f9f09b0SDouglas Anderson *
1449f9f09b0SDouglas Anderson * Here's an explanation of the scheme we'll implement, assuming 8 periods.
1459f9f09b0SDouglas Anderson * - If interval is 1, we need to take up space in each of the 8
1469f9f09b0SDouglas Anderson * periods we're scheduling. Easy.
1479f9f09b0SDouglas Anderson * - If interval is 2, we need to take up space in half of the
1489f9f09b0SDouglas Anderson * periods. Again, easy.
1499f9f09b0SDouglas Anderson * - If interval is 3, we actually need to fall back to interval 1.
1509f9f09b0SDouglas Anderson * Why? Because we might need time in any period. AKA for the
1519f9f09b0SDouglas Anderson * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be
1529f9f09b0SDouglas Anderson * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to
1539f9f09b0SDouglas Anderson * 0, 3, and 6. Since we could be in any frame we need to reserve
1549f9f09b0SDouglas Anderson * for all of them. Sucks, but that's what you gotta do. Note that
1559f9f09b0SDouglas Anderson * if we were instead scheduling 8 * 3 = 24 we'd do much better, but
1569f9f09b0SDouglas Anderson * then we need more memory and time to do scheduling.
1579f9f09b0SDouglas Anderson * - If interval is 4, easy.
1589f9f09b0SDouglas Anderson * - If interval is 5, we again need interval 1. The schedule will be
1599f9f09b0SDouglas Anderson * 0, 5, 2, 7, 4, 1, 6, 3, 0
1609f9f09b0SDouglas Anderson * - If interval is 6, we need interval 2. 0, 6, 4, 2.
1619f9f09b0SDouglas Anderson * - If interval is 7, we need interval 1.
1629f9f09b0SDouglas Anderson * - If interval is 8, we need interval 8.
1639f9f09b0SDouglas Anderson *
1649f9f09b0SDouglas Anderson * If you do the math, you'll see that we need to pretend that interval is
1659f9f09b0SDouglas Anderson * equal to the greatest_common_divisor(interval, periods_in_map).
1669f9f09b0SDouglas Anderson *
1679f9f09b0SDouglas Anderson * Note that at the moment this function tends to front-pack the schedule.
1689f9f09b0SDouglas Anderson * In some cases that's really non-ideal (it's hard to schedule things that
1699f9f09b0SDouglas Anderson * need to repeat every period). In other cases it's perfect (you can easily
1709f9f09b0SDouglas Anderson * schedule bigger, less often repeating things).
1719f9f09b0SDouglas Anderson *
1729f9f09b0SDouglas Anderson * Here's the algorithm in action (8 periods, 5 bits per period):
1739f9f09b0SDouglas Anderson * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
1749f9f09b0SDouglas Anderson * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2
1759f9f09b0SDouglas Anderson * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5
1769f9f09b0SDouglas Anderson * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2
1779f9f09b0SDouglas Anderson * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2
1789f9f09b0SDouglas Anderson * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3
1799f9f09b0SDouglas Anderson * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6
1809f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4
1819f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
1829f9f09b0SDouglas Anderson * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0
1839f9f09b0SDouglas Anderson * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5
1849f9f09b0SDouglas Anderson * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2
1859f9f09b0SDouglas Anderson * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3
1869f9f09b0SDouglas Anderson * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6
1879f9f09b0SDouglas Anderson * | | | | | | | | | Remv 1 bits, intv 1 at 4
1889f9f09b0SDouglas Anderson * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0
1899f9f09b0SDouglas Anderson * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2
1909f9f09b0SDouglas Anderson * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3
1919f9f09b0SDouglas Anderson * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5
1929f9f09b0SDouglas Anderson * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6
1939f9f09b0SDouglas Anderson * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8
1949f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12
1959f9f09b0SDouglas Anderson *
1969f9f09b0SDouglas Anderson * This function is pretty generic and could be easily abstracted if anything
1979f9f09b0SDouglas Anderson * needed similar scheduling.
1989f9f09b0SDouglas Anderson *
1999f9f09b0SDouglas Anderson * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
2009f9f09b0SDouglas Anderson * unschedule routine. The map bitmap will be updated on a non-error result.
201b951c6c7SDouglas Anderson */
pmap_schedule(unsigned long * map,int bits_per_period,int periods_in_map,int num_bits,int interval,int start,bool only_one_period)2029f9f09b0SDouglas Anderson static int pmap_schedule(unsigned long *map, int bits_per_period,
2039f9f09b0SDouglas Anderson int periods_in_map, int num_bits,
2049f9f09b0SDouglas Anderson int interval, int start, bool only_one_period)
2059f9f09b0SDouglas Anderson {
2069f9f09b0SDouglas Anderson int interval_bits;
2079f9f09b0SDouglas Anderson int to_reserve;
2089f9f09b0SDouglas Anderson int first_end;
2099f9f09b0SDouglas Anderson int i;
2109f9f09b0SDouglas Anderson
2119f9f09b0SDouglas Anderson if (num_bits > bits_per_period)
2129f9f09b0SDouglas Anderson return -ENOSPC;
2139f9f09b0SDouglas Anderson
2149f9f09b0SDouglas Anderson /* Adjust interval as per description */
2159f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map);
2169f9f09b0SDouglas Anderson
2179f9f09b0SDouglas Anderson interval_bits = bits_per_period * interval;
2189f9f09b0SDouglas Anderson to_reserve = periods_in_map / interval;
2199f9f09b0SDouglas Anderson
2209f9f09b0SDouglas Anderson /* If start has gotten us past interval then we can't schedule */
2219f9f09b0SDouglas Anderson if (start >= interval_bits)
2229f9f09b0SDouglas Anderson return -ENOSPC;
2239f9f09b0SDouglas Anderson
2249f9f09b0SDouglas Anderson if (only_one_period)
2259f9f09b0SDouglas Anderson /* Must fit within same period as start; end at begin of next */
2269f9f09b0SDouglas Anderson first_end = (start / bits_per_period + 1) * bits_per_period;
2279f9f09b0SDouglas Anderson else
2289f9f09b0SDouglas Anderson /* Can fit anywhere in the first interval */
2299f9f09b0SDouglas Anderson first_end = interval_bits;
2309f9f09b0SDouglas Anderson
2319f9f09b0SDouglas Anderson /*
2329f9f09b0SDouglas Anderson * We'll try to pick the first repetition, then see if that time
2339f9f09b0SDouglas Anderson * is free for each of the subsequent repetitions. If it's not
2349f9f09b0SDouglas Anderson * we'll adjust the start time for the next search of the first
2359f9f09b0SDouglas Anderson * repetition.
2369f9f09b0SDouglas Anderson */
2379f9f09b0SDouglas Anderson while (start + num_bits <= first_end) {
2389f9f09b0SDouglas Anderson int end;
2399f9f09b0SDouglas Anderson
2409f9f09b0SDouglas Anderson /* Need to stay within this period */
2419f9f09b0SDouglas Anderson end = (start / bits_per_period + 1) * bits_per_period;
2429f9f09b0SDouglas Anderson
2439f9f09b0SDouglas Anderson /* Look for num_bits us in this microframe starting at start */
2449f9f09b0SDouglas Anderson start = bitmap_find_next_zero_area(map, end, start, num_bits,
2459f9f09b0SDouglas Anderson 0);
2469f9f09b0SDouglas Anderson
2479f9f09b0SDouglas Anderson /*
2489f9f09b0SDouglas Anderson * We should get start >= end if we fail. We might be
2499f9f09b0SDouglas Anderson * able to check the next microframe depending on the
2509f9f09b0SDouglas Anderson * interval, so continue on (start already updated).
2519f9f09b0SDouglas Anderson */
2529f9f09b0SDouglas Anderson if (start >= end) {
2539f9f09b0SDouglas Anderson start = end;
2549f9f09b0SDouglas Anderson continue;
2559f9f09b0SDouglas Anderson }
2569f9f09b0SDouglas Anderson
2579f9f09b0SDouglas Anderson /* At this point we have a valid point for first one */
2589f9f09b0SDouglas Anderson for (i = 1; i < to_reserve; i++) {
2599f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i;
2609f9f09b0SDouglas Anderson int ith_end = end + interval_bits * i;
2619f9f09b0SDouglas Anderson int ret;
2629f9f09b0SDouglas Anderson
2639f9f09b0SDouglas Anderson /* Use this as a dumb "check if bits are 0" */
2649f9f09b0SDouglas Anderson ret = bitmap_find_next_zero_area(
2659f9f09b0SDouglas Anderson map, ith_start + num_bits, ith_start, num_bits,
2669f9f09b0SDouglas Anderson 0);
2679f9f09b0SDouglas Anderson
2689f9f09b0SDouglas Anderson /* We got the right place, continue checking */
2699f9f09b0SDouglas Anderson if (ret == ith_start)
2709f9f09b0SDouglas Anderson continue;
2719f9f09b0SDouglas Anderson
2729f9f09b0SDouglas Anderson /* Move start up for next time and exit for loop */
2739f9f09b0SDouglas Anderson ith_start = bitmap_find_next_zero_area(
2749f9f09b0SDouglas Anderson map, ith_end, ith_start, num_bits, 0);
2759f9f09b0SDouglas Anderson if (ith_start >= ith_end)
2769f9f09b0SDouglas Anderson /* Need a while new period next time */
2779f9f09b0SDouglas Anderson start = end;
2789f9f09b0SDouglas Anderson else
2799f9f09b0SDouglas Anderson start = ith_start - interval_bits * i;
2809f9f09b0SDouglas Anderson break;
2819f9f09b0SDouglas Anderson }
2829f9f09b0SDouglas Anderson
2839f9f09b0SDouglas Anderson /* If didn't exit the for loop with a break, we have success */
2849f9f09b0SDouglas Anderson if (i == to_reserve)
2859f9f09b0SDouglas Anderson break;
2869f9f09b0SDouglas Anderson }
2879f9f09b0SDouglas Anderson
2889f9f09b0SDouglas Anderson if (start + num_bits > first_end)
2899f9f09b0SDouglas Anderson return -ENOSPC;
2909f9f09b0SDouglas Anderson
2919f9f09b0SDouglas Anderson for (i = 0; i < to_reserve; i++) {
2929f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i;
2939f9f09b0SDouglas Anderson
2949f9f09b0SDouglas Anderson bitmap_set(map, ith_start, num_bits);
2959f9f09b0SDouglas Anderson }
2969f9f09b0SDouglas Anderson
2979f9f09b0SDouglas Anderson return start;
2989f9f09b0SDouglas Anderson }
2999f9f09b0SDouglas Anderson
3009f9f09b0SDouglas Anderson /**
3019f9f09b0SDouglas Anderson * pmap_unschedule() - Undo work done by pmap_schedule()
3029f9f09b0SDouglas Anderson *
3039f9f09b0SDouglas Anderson * @map: See pmap_schedule().
3049f9f09b0SDouglas Anderson * @bits_per_period: See pmap_schedule().
3059f9f09b0SDouglas Anderson * @periods_in_map: See pmap_schedule().
3069f9f09b0SDouglas Anderson * @num_bits: The number of bits that was passed to schedule.
3079f9f09b0SDouglas Anderson * @interval: The interval that was passed to schedule.
3089f9f09b0SDouglas Anderson * @start: The return value from pmap_schedule().
3099f9f09b0SDouglas Anderson */
pmap_unschedule(unsigned long * map,int bits_per_period,int periods_in_map,int num_bits,int interval,int start)3109f9f09b0SDouglas Anderson static void pmap_unschedule(unsigned long *map, int bits_per_period,
3119f9f09b0SDouglas Anderson int periods_in_map, int num_bits,
3129f9f09b0SDouglas Anderson int interval, int start)
3139f9f09b0SDouglas Anderson {
3149f9f09b0SDouglas Anderson int interval_bits;
3159f9f09b0SDouglas Anderson int to_release;
3169f9f09b0SDouglas Anderson int i;
3179f9f09b0SDouglas Anderson
3189f9f09b0SDouglas Anderson /* Adjust interval as per description in pmap_schedule() */
3199f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map);
3209f9f09b0SDouglas Anderson
3219f9f09b0SDouglas Anderson interval_bits = bits_per_period * interval;
3229f9f09b0SDouglas Anderson to_release = periods_in_map / interval;
3239f9f09b0SDouglas Anderson
3249f9f09b0SDouglas Anderson for (i = 0; i < to_release; i++) {
3259f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i;
3269f9f09b0SDouglas Anderson
3279f9f09b0SDouglas Anderson bitmap_clear(map, ith_start, num_bits);
3289f9f09b0SDouglas Anderson }
3299f9f09b0SDouglas Anderson }
3309f9f09b0SDouglas Anderson
3313c220370SVardan Mikayelyan /**
3323c220370SVardan Mikayelyan * dwc2_get_ls_map() - Get the map used for the given qh
3333c220370SVardan Mikayelyan *
3343c220370SVardan Mikayelyan * @hsotg: The HCD state structure for the DWC OTG controller.
3353c220370SVardan Mikayelyan * @qh: QH for the periodic transfer.
3363c220370SVardan Mikayelyan *
3373c220370SVardan Mikayelyan * We'll always get the periodic map out of our TT. Note that even if we're
3383c220370SVardan Mikayelyan * running the host straight in low speed / full speed mode it appears as if
3393c220370SVardan Mikayelyan * a TT is allocated for us, so we'll use it. If that ever changes we can
3403c220370SVardan Mikayelyan * add logic here to get a map out of "hsotg" if !qh->do_split.
3413c220370SVardan Mikayelyan *
3423c220370SVardan Mikayelyan * Returns: the map or NULL if a map couldn't be found.
3433c220370SVardan Mikayelyan */
dwc2_get_ls_map(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)3443c220370SVardan Mikayelyan static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
3453c220370SVardan Mikayelyan struct dwc2_qh *qh)
3463c220370SVardan Mikayelyan {
3473c220370SVardan Mikayelyan unsigned long *map;
3483c220370SVardan Mikayelyan
3493c220370SVardan Mikayelyan /* Don't expect to be missing a TT and be doing low speed scheduling */
3503c220370SVardan Mikayelyan if (WARN_ON(!qh->dwc_tt))
3513c220370SVardan Mikayelyan return NULL;
3523c220370SVardan Mikayelyan
3533c220370SVardan Mikayelyan /* Get the map and adjust if this is a multi_tt hub */
3543c220370SVardan Mikayelyan map = qh->dwc_tt->periodic_bitmaps;
3553c220370SVardan Mikayelyan if (qh->dwc_tt->usb_tt->multi)
35687606759SWilliam Wu map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1);
3573c220370SVardan Mikayelyan
3583c220370SVardan Mikayelyan return map;
3593c220370SVardan Mikayelyan }
3603c220370SVardan Mikayelyan
3613c220370SVardan Mikayelyan #ifdef DWC2_PRINT_SCHEDULE
3629f9f09b0SDouglas Anderson /*
3639f9f09b0SDouglas Anderson * cat_printf() - A printf() + strcat() helper
3649f9f09b0SDouglas Anderson *
3659f9f09b0SDouglas Anderson * This is useful for concatenating a bunch of strings where each string is
3669f9f09b0SDouglas Anderson * constructed using printf.
3679f9f09b0SDouglas Anderson *
3689f9f09b0SDouglas Anderson * @buf: The destination buffer; will be updated to point after the printed
3699f9f09b0SDouglas Anderson * data.
3709f9f09b0SDouglas Anderson * @size: The number of bytes in the buffer (includes space for '\0').
3719f9f09b0SDouglas Anderson * @fmt: The format for printf.
3729f9f09b0SDouglas Anderson * @...: The args for printf.
3739f9f09b0SDouglas Anderson */
374e135ab74SNicolas Iooss static __printf(3, 4)
cat_printf(char ** buf,size_t * size,const char * fmt,...)375e135ab74SNicolas Iooss void cat_printf(char **buf, size_t *size, const char *fmt, ...)
3769f9f09b0SDouglas Anderson {
3779f9f09b0SDouglas Anderson va_list args;
3789f9f09b0SDouglas Anderson int i;
3799f9f09b0SDouglas Anderson
3809f9f09b0SDouglas Anderson if (*size == 0)
3819f9f09b0SDouglas Anderson return;
3829f9f09b0SDouglas Anderson
3839f9f09b0SDouglas Anderson va_start(args, fmt);
3849f9f09b0SDouglas Anderson i = vsnprintf(*buf, *size, fmt, args);
3859f9f09b0SDouglas Anderson va_end(args);
3869f9f09b0SDouglas Anderson
3879f9f09b0SDouglas Anderson if (i >= *size) {
3889f9f09b0SDouglas Anderson (*buf)[*size - 1] = '\0';
3899f9f09b0SDouglas Anderson *buf += *size;
3909f9f09b0SDouglas Anderson *size = 0;
3919f9f09b0SDouglas Anderson } else {
3929f9f09b0SDouglas Anderson *buf += i;
3939f9f09b0SDouglas Anderson *size -= i;
3949f9f09b0SDouglas Anderson }
3959f9f09b0SDouglas Anderson }
3969f9f09b0SDouglas Anderson
3979f9f09b0SDouglas Anderson /*
3989f9f09b0SDouglas Anderson * pmap_print() - Print the given periodic map
3999f9f09b0SDouglas Anderson *
4009f9f09b0SDouglas Anderson * Will attempt to print out the periodic schedule.
4019f9f09b0SDouglas Anderson *
4029f9f09b0SDouglas Anderson * @map: See pmap_schedule().
4039f9f09b0SDouglas Anderson * @bits_per_period: See pmap_schedule().
4049f9f09b0SDouglas Anderson * @periods_in_map: See pmap_schedule().
4059f9f09b0SDouglas Anderson * @period_name: The name of 1 period, like "uFrame"
4069f9f09b0SDouglas Anderson * @units: The name of the units, like "us".
4079f9f09b0SDouglas Anderson * @print_fn: The function to call for printing.
4089f9f09b0SDouglas Anderson * @print_data: Opaque data to pass to the print function.
4099f9f09b0SDouglas Anderson */
pmap_print(unsigned long * map,int bits_per_period,int periods_in_map,const char * period_name,const char * units,void (* print_fn)(const char * str,void * data),void * print_data)4109f9f09b0SDouglas Anderson static void pmap_print(unsigned long *map, int bits_per_period,
4119f9f09b0SDouglas Anderson int periods_in_map, const char *period_name,
4129f9f09b0SDouglas Anderson const char *units,
4139f9f09b0SDouglas Anderson void (*print_fn)(const char *str, void *data),
4149f9f09b0SDouglas Anderson void *print_data)
4159f9f09b0SDouglas Anderson {
4169f9f09b0SDouglas Anderson int period;
4179f9f09b0SDouglas Anderson
4189f9f09b0SDouglas Anderson for (period = 0; period < periods_in_map; period++) {
4199f9f09b0SDouglas Anderson char tmp[64];
4209f9f09b0SDouglas Anderson char *buf = tmp;
4219f9f09b0SDouglas Anderson size_t buf_size = sizeof(tmp);
4229f9f09b0SDouglas Anderson int period_start = period * bits_per_period;
4239f9f09b0SDouglas Anderson int period_end = period_start + bits_per_period;
4249f9f09b0SDouglas Anderson int start = 0;
4259f9f09b0SDouglas Anderson int count = 0;
4269f9f09b0SDouglas Anderson bool printed = false;
4279f9f09b0SDouglas Anderson int i;
4289f9f09b0SDouglas Anderson
4299f9f09b0SDouglas Anderson for (i = period_start; i < period_end + 1; i++) {
4309f9f09b0SDouglas Anderson /* Handle case when ith bit is set */
4319f9f09b0SDouglas Anderson if (i < period_end &&
4329f9f09b0SDouglas Anderson bitmap_find_next_zero_area(map, i + 1,
4339f9f09b0SDouglas Anderson i, 1, 0) != i) {
4349f9f09b0SDouglas Anderson if (count == 0)
4359f9f09b0SDouglas Anderson start = i - period_start;
4369f9f09b0SDouglas Anderson count++;
4379f9f09b0SDouglas Anderson continue;
4389f9f09b0SDouglas Anderson }
4399f9f09b0SDouglas Anderson
4409f9f09b0SDouglas Anderson /* ith bit isn't set; don't care if count == 0 */
4419f9f09b0SDouglas Anderson if (count == 0)
4429f9f09b0SDouglas Anderson continue;
4439f9f09b0SDouglas Anderson
4449f9f09b0SDouglas Anderson if (!printed)
4459f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, "%s %d: ",
4469f9f09b0SDouglas Anderson period_name, period);
4479f9f09b0SDouglas Anderson else
4489f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, ", ");
4499f9f09b0SDouglas Anderson printed = true;
4509f9f09b0SDouglas Anderson
4519f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
4529f9f09b0SDouglas Anderson units, start + count - 1, units);
4539f9f09b0SDouglas Anderson count = 0;
4549f9f09b0SDouglas Anderson }
4559f9f09b0SDouglas Anderson
4569f9f09b0SDouglas Anderson if (printed)
4579f9f09b0SDouglas Anderson print_fn(tmp, print_data);
4589f9f09b0SDouglas Anderson }
4599f9f09b0SDouglas Anderson }
4609f9f09b0SDouglas Anderson
4619f9f09b0SDouglas Anderson struct dwc2_qh_print_data {
4629f9f09b0SDouglas Anderson struct dwc2_hsotg *hsotg;
4639f9f09b0SDouglas Anderson struct dwc2_qh *qh;
464b951c6c7SDouglas Anderson };
465b951c6c7SDouglas Anderson
4669f9f09b0SDouglas Anderson /**
4679f9f09b0SDouglas Anderson * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
4689f9f09b0SDouglas Anderson *
4699f9f09b0SDouglas Anderson * @str: The string to print
4709f9f09b0SDouglas Anderson * @data: A pointer to a struct dwc2_qh_print_data
4719f9f09b0SDouglas Anderson */
dwc2_qh_print(const char * str,void * data)4729f9f09b0SDouglas Anderson static void dwc2_qh_print(const char *str, void *data)
473b951c6c7SDouglas Anderson {
4749f9f09b0SDouglas Anderson struct dwc2_qh_print_data *print_data = data;
4759f9f09b0SDouglas Anderson
4769f9f09b0SDouglas Anderson dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
4779f9f09b0SDouglas Anderson }
4789f9f09b0SDouglas Anderson
4799f9f09b0SDouglas Anderson /**
4809f9f09b0SDouglas Anderson * dwc2_qh_schedule_print() - Print the periodic schedule
4819f9f09b0SDouglas Anderson *
4829f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
4839f9f09b0SDouglas Anderson * @qh: QH to print.
4849f9f09b0SDouglas Anderson */
dwc2_qh_schedule_print(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)4859f9f09b0SDouglas Anderson static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
4869f9f09b0SDouglas Anderson struct dwc2_qh *qh)
4879f9f09b0SDouglas Anderson {
4889f9f09b0SDouglas Anderson struct dwc2_qh_print_data print_data = { hsotg, qh };
489b951c6c7SDouglas Anderson int i;
490b951c6c7SDouglas Anderson
4919f9f09b0SDouglas Anderson /*
4929f9f09b0SDouglas Anderson * The printing functions are quite slow and inefficient.
4939f9f09b0SDouglas Anderson * If we don't have tracing turned on, don't run unless the special
4949f9f09b0SDouglas Anderson * define is turned on.
4959f9f09b0SDouglas Anderson */
4969f9f09b0SDouglas Anderson
4979f9f09b0SDouglas Anderson if (qh->schedule_low_speed) {
4989f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh);
4999f9f09b0SDouglas Anderson
5009f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
5019f9f09b0SDouglas Anderson qh, qh->device_us,
5029f9f09b0SDouglas Anderson DWC2_ROUND_US_TO_SLICE(qh->device_us),
5039f9f09b0SDouglas Anderson DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
5049f9f09b0SDouglas Anderson
5059f9f09b0SDouglas Anderson if (map) {
5069f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg,
5079f9f09b0SDouglas Anderson "QH=%p Whole low/full speed map %p now:\n",
5089f9f09b0SDouglas Anderson qh, map);
5099f9f09b0SDouglas Anderson pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
5109f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
5119f9f09b0SDouglas Anderson dwc2_qh_print, &print_data);
5129f9f09b0SDouglas Anderson }
513b951c6c7SDouglas Anderson }
514b951c6c7SDouglas Anderson
5159f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++) {
5169f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
5179f9f09b0SDouglas Anderson int uframe = trans_time->start_schedule_us /
5189f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME;
5199f9f09b0SDouglas Anderson int rel_us = trans_time->start_schedule_us %
5209f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME;
5219f9f09b0SDouglas Anderson
5229f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg,
5239f9f09b0SDouglas Anderson "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
5249f9f09b0SDouglas Anderson qh, i, trans_time->duration_us, uframe, rel_us);
5259f9f09b0SDouglas Anderson }
5269f9f09b0SDouglas Anderson if (qh->num_hs_transfers) {
5279f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
5289f9f09b0SDouglas Anderson pmap_print(hsotg->hs_periodic_bitmap,
5299f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME,
5309f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
5319f9f09b0SDouglas Anderson dwc2_qh_print, &print_data);
5329f9f09b0SDouglas Anderson }
5339f9f09b0SDouglas Anderson }
5343c220370SVardan Mikayelyan #else
dwc2_qh_schedule_print(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)5353c220370SVardan Mikayelyan static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
5363c220370SVardan Mikayelyan struct dwc2_qh *qh) {};
5373c220370SVardan Mikayelyan #endif
5389f9f09b0SDouglas Anderson
5399f9f09b0SDouglas Anderson /**
5409f9f09b0SDouglas Anderson * dwc2_ls_pmap_schedule() - Schedule a low speed QH
5419f9f09b0SDouglas Anderson *
5429f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
5439f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
5449f9f09b0SDouglas Anderson * @search_slice: We'll start trying to schedule at the passed slice.
5459f9f09b0SDouglas Anderson * Remember that slices are the units of the low speed
5469f9f09b0SDouglas Anderson * schedule (think 25us or so).
5479f9f09b0SDouglas Anderson *
5489f9f09b0SDouglas Anderson * Wraps pmap_schedule() with the right parameters for low speed scheduling.
5499f9f09b0SDouglas Anderson *
5509f9f09b0SDouglas Anderson * Normally we schedule low speed devices on the map associated with the TT.
5519f9f09b0SDouglas Anderson *
5529f9f09b0SDouglas Anderson * Returns: 0 for success or an error code.
5539f9f09b0SDouglas Anderson */
dwc2_ls_pmap_schedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int search_slice)5549f9f09b0SDouglas Anderson static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
5559f9f09b0SDouglas Anderson int search_slice)
556b951c6c7SDouglas Anderson {
5579f9f09b0SDouglas Anderson int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
5589f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh);
5599f9f09b0SDouglas Anderson int slice;
5609f9f09b0SDouglas Anderson
5619da51974SJohn Youn if (!map)
5629f9f09b0SDouglas Anderson return -EINVAL;
5639f9f09b0SDouglas Anderson
5649f9f09b0SDouglas Anderson /*
5659f9f09b0SDouglas Anderson * Schedule on the proper low speed map with our low speed scheduling
5669f9f09b0SDouglas Anderson * parameters. Note that we use the "device_interval" here since
5679f9f09b0SDouglas Anderson * we want the low speed interval and the only way we'd be in this
5689f9f09b0SDouglas Anderson * function is if the device is low speed.
5699f9f09b0SDouglas Anderson *
5709f9f09b0SDouglas Anderson * If we happen to be doing low speed and high speed scheduling for the
5719f9f09b0SDouglas Anderson * same transaction (AKA we have a split) we always do low speed first.
5729f9f09b0SDouglas Anderson * That means we can always pass "false" for only_one_period (that
5739f9f09b0SDouglas Anderson * parameters is only useful when we're trying to get one schedule to
5749f9f09b0SDouglas Anderson * match what we already planned in the other schedule).
5759f9f09b0SDouglas Anderson */
5769f9f09b0SDouglas Anderson slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
5779f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, slices,
5789f9f09b0SDouglas Anderson qh->device_interval, search_slice, false);
5799f9f09b0SDouglas Anderson
5809f9f09b0SDouglas Anderson if (slice < 0)
5819f9f09b0SDouglas Anderson return slice;
5829f9f09b0SDouglas Anderson
5839f9f09b0SDouglas Anderson qh->ls_start_schedule_slice = slice;
5849f9f09b0SDouglas Anderson return 0;
5859f9f09b0SDouglas Anderson }
5869f9f09b0SDouglas Anderson
5879f9f09b0SDouglas Anderson /**
5889f9f09b0SDouglas Anderson * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
5899f9f09b0SDouglas Anderson *
5909f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
5919f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
5929f9f09b0SDouglas Anderson */
dwc2_ls_pmap_unschedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)5939f9f09b0SDouglas Anderson static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
5949f9f09b0SDouglas Anderson struct dwc2_qh *qh)
5959f9f09b0SDouglas Anderson {
5969f9f09b0SDouglas Anderson int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
5979f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh);
5989f9f09b0SDouglas Anderson
5999f9f09b0SDouglas Anderson /* Schedule should have failed, so no worries about no error code */
6009da51974SJohn Youn if (!map)
6019f9f09b0SDouglas Anderson return;
6029f9f09b0SDouglas Anderson
6039f9f09b0SDouglas Anderson pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
6049f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
6059f9f09b0SDouglas Anderson qh->ls_start_schedule_slice);
6069f9f09b0SDouglas Anderson }
6079f9f09b0SDouglas Anderson
6089f9f09b0SDouglas Anderson /**
6099f9f09b0SDouglas Anderson * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
6109f9f09b0SDouglas Anderson *
6119f9f09b0SDouglas Anderson * This will schedule something on the main dwc2 schedule.
6129f9f09b0SDouglas Anderson *
6139f9f09b0SDouglas Anderson * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll
6149f9f09b0SDouglas Anderson * update this with the result upon success. We also use the duration from
6159f9f09b0SDouglas Anderson * the same structure.
6169f9f09b0SDouglas Anderson *
6179f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
6189f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
6199f9f09b0SDouglas Anderson * @only_one_period: If true we will limit ourselves to just looking at
6209f9f09b0SDouglas Anderson * one period (aka one 100us chunk). This is used if we have
6219f9f09b0SDouglas Anderson * already scheduled something on the low speed schedule and
6229f9f09b0SDouglas Anderson * need to find something that matches on the high speed one.
6239f9f09b0SDouglas Anderson * @index: The index into qh->hs_transfers that we're working with.
6249f9f09b0SDouglas Anderson *
6259f9f09b0SDouglas Anderson * Returns: 0 for success or an error code. Upon success the
6269f9f09b0SDouglas Anderson * dwc2_hs_transfer_time specified by "index" will be updated.
6279f9f09b0SDouglas Anderson */
dwc2_hs_pmap_schedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,bool only_one_period,int index)6289f9f09b0SDouglas Anderson static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
6299f9f09b0SDouglas Anderson bool only_one_period, int index)
6309f9f09b0SDouglas Anderson {
6319f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
6329f9f09b0SDouglas Anderson int us;
6339f9f09b0SDouglas Anderson
6349f9f09b0SDouglas Anderson us = pmap_schedule(hsotg->hs_periodic_bitmap,
6359f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME,
6369f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
6379f9f09b0SDouglas Anderson qh->host_interval, trans_time->start_schedule_us,
6389f9f09b0SDouglas Anderson only_one_period);
6399f9f09b0SDouglas Anderson
6409f9f09b0SDouglas Anderson if (us < 0)
6419f9f09b0SDouglas Anderson return us;
6429f9f09b0SDouglas Anderson
6439f9f09b0SDouglas Anderson trans_time->start_schedule_us = us;
6449f9f09b0SDouglas Anderson return 0;
6459f9f09b0SDouglas Anderson }
6469f9f09b0SDouglas Anderson
6479f9f09b0SDouglas Anderson /**
648a63acbdeSLee Jones * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
6499f9f09b0SDouglas Anderson *
6509f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
6519f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
6526fb914d7SGrigor Tovmasyan * @index: Transfer index
6539f9f09b0SDouglas Anderson */
dwc2_hs_pmap_unschedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int index)6549f9f09b0SDouglas Anderson static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
6559f9f09b0SDouglas Anderson struct dwc2_qh *qh, int index)
6569f9f09b0SDouglas Anderson {
6579f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
6589f9f09b0SDouglas Anderson
6599f9f09b0SDouglas Anderson pmap_unschedule(hsotg->hs_periodic_bitmap,
6609f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME,
6619f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
6629f9f09b0SDouglas Anderson qh->host_interval, trans_time->start_schedule_us);
6639f9f09b0SDouglas Anderson }
6649f9f09b0SDouglas Anderson
6659f9f09b0SDouglas Anderson /**
6669f9f09b0SDouglas Anderson * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
6679f9f09b0SDouglas Anderson *
6689f9f09b0SDouglas Anderson * This is the most complicated thing in USB. We have to find matching time
6699f9f09b0SDouglas Anderson * in both the global high speed schedule for the port and the low speed
6709f9f09b0SDouglas Anderson * schedule for the TT associated with the given device.
6719f9f09b0SDouglas Anderson *
6729f9f09b0SDouglas Anderson * Being here means that the host must be running in high speed mode and the
6739f9f09b0SDouglas Anderson * device is in low or full speed mode (and behind a hub).
6749f9f09b0SDouglas Anderson *
6759f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
6769f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
6779f9f09b0SDouglas Anderson */
dwc2_uframe_schedule_split(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)6789f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
6799f9f09b0SDouglas Anderson struct dwc2_qh *qh)
6809f9f09b0SDouglas Anderson {
681babd1839SDouglas Anderson int bytecount = qh->maxp_mult * qh->maxp;
6829f9f09b0SDouglas Anderson int ls_search_slice;
6839f9f09b0SDouglas Anderson int err = 0;
6849f9f09b0SDouglas Anderson int host_interval_in_sched;
6859f9f09b0SDouglas Anderson
6869f9f09b0SDouglas Anderson /*
6879f9f09b0SDouglas Anderson * The interval (how often to repeat) in the actual host schedule.
6889f9f09b0SDouglas Anderson * See pmap_schedule() for gcd() explanation.
6899f9f09b0SDouglas Anderson */
6909f9f09b0SDouglas Anderson host_interval_in_sched = gcd(qh->host_interval,
6919f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES);
6929f9f09b0SDouglas Anderson
6939f9f09b0SDouglas Anderson /*
6949f9f09b0SDouglas Anderson * We always try to find space in the low speed schedule first, then
6959f9f09b0SDouglas Anderson * try to find high speed time that matches. If we don't, we'll bump
6969f9f09b0SDouglas Anderson * up the place we start searching in the low speed schedule and try
6979f9f09b0SDouglas Anderson * again. To start we'll look right at the beginning of the low speed
6989f9f09b0SDouglas Anderson * schedule.
6999f9f09b0SDouglas Anderson *
7009f9f09b0SDouglas Anderson * Note that this will tend to front-load the high speed schedule.
7019f9f09b0SDouglas Anderson * We may eventually want to try to avoid this by either considering
7029f9f09b0SDouglas Anderson * both schedules together or doing some sort of round robin.
7039f9f09b0SDouglas Anderson */
7049f9f09b0SDouglas Anderson ls_search_slice = 0;
7059f9f09b0SDouglas Anderson
7069f9f09b0SDouglas Anderson while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
7079f9f09b0SDouglas Anderson int start_s_uframe;
7089f9f09b0SDouglas Anderson int ssplit_s_uframe;
7099f9f09b0SDouglas Anderson int second_s_uframe;
7109f9f09b0SDouglas Anderson int rel_uframe;
7119f9f09b0SDouglas Anderson int first_count;
7129f9f09b0SDouglas Anderson int middle_count;
7139f9f09b0SDouglas Anderson int end_count;
7149f9f09b0SDouglas Anderson int first_data_bytes;
7159f9f09b0SDouglas Anderson int other_data_bytes;
716b951c6c7SDouglas Anderson int i;
717b951c6c7SDouglas Anderson
7189f9f09b0SDouglas Anderson if (qh->schedule_low_speed) {
7199f9f09b0SDouglas Anderson err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
720b951c6c7SDouglas Anderson
721b951c6c7SDouglas Anderson /*
7229f9f09b0SDouglas Anderson * If we got an error here there's no other magic we
7239f9f09b0SDouglas Anderson * can do, so bail. All the looping above is only
7249f9f09b0SDouglas Anderson * helpful to redo things if we got a low speed slot
7259f9f09b0SDouglas Anderson * and then couldn't find a matching high speed slot.
726b951c6c7SDouglas Anderson */
7279f9f09b0SDouglas Anderson if (err)
7289f9f09b0SDouglas Anderson return err;
729b951c6c7SDouglas Anderson } else {
7309f9f09b0SDouglas Anderson /* Must be missing the tt structure? Why? */
7319f9f09b0SDouglas Anderson WARN_ON_ONCE(1);
732b951c6c7SDouglas Anderson }
733b951c6c7SDouglas Anderson
7349f9f09b0SDouglas Anderson /*
7359f9f09b0SDouglas Anderson * This will give us a number 0 - 7 if
7369f9f09b0SDouglas Anderson * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
7379f9f09b0SDouglas Anderson */
7389f9f09b0SDouglas Anderson start_s_uframe = qh->ls_start_schedule_slice /
7399f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME;
7409f9f09b0SDouglas Anderson
7419f9f09b0SDouglas Anderson /* Get a number that's always 0 - 7 */
7429f9f09b0SDouglas Anderson rel_uframe = (start_s_uframe % 8);
7439f9f09b0SDouglas Anderson
7449f9f09b0SDouglas Anderson /*
7459f9f09b0SDouglas Anderson * If we were going to start in uframe 7 then we would need to
7469f9f09b0SDouglas Anderson * issue a start split in uframe 6, which spec says is not OK.
7479f9f09b0SDouglas Anderson * Move on to the next full frame (assuming there is one).
7489f9f09b0SDouglas Anderson *
7499f9f09b0SDouglas Anderson * See 11.18.4 Host Split Transaction Scheduling Requirements
7509f9f09b0SDouglas Anderson * bullet 1.
7519f9f09b0SDouglas Anderson */
7529f9f09b0SDouglas Anderson if (rel_uframe == 7) {
7539f9f09b0SDouglas Anderson if (qh->schedule_low_speed)
7549f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh);
7559f9f09b0SDouglas Anderson ls_search_slice =
7569f9f09b0SDouglas Anderson (qh->ls_start_schedule_slice /
7579f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
7589f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME;
7599f9f09b0SDouglas Anderson continue;
7609f9f09b0SDouglas Anderson }
7619f9f09b0SDouglas Anderson
7629f9f09b0SDouglas Anderson /*
7639f9f09b0SDouglas Anderson * For ISOC in:
7649f9f09b0SDouglas Anderson * - start split (frame -1)
7659f9f09b0SDouglas Anderson * - complete split w/ data (frame +1)
7669f9f09b0SDouglas Anderson * - complete split w/ data (frame +2)
7679f9f09b0SDouglas Anderson * - ...
7689f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets)
7699f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets+1)
7709f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets+2, max 8)
7719f9f09b0SDouglas Anderson * ...though if frame was "0" then max is 7...
7729f9f09b0SDouglas Anderson *
7739f9f09b0SDouglas Anderson * For ISOC out we might need to do:
7749f9f09b0SDouglas Anderson * - start split w/ data (frame -1)
7759f9f09b0SDouglas Anderson * - start split w/ data (frame +0)
7769f9f09b0SDouglas Anderson * - ...
7779f9f09b0SDouglas Anderson * - start split w/ data (frame +num_data_packets-2)
7789f9f09b0SDouglas Anderson *
7799f9f09b0SDouglas Anderson * For INTERRUPT in we might need to do:
7809f9f09b0SDouglas Anderson * - start split (frame -1)
7819f9f09b0SDouglas Anderson * - complete split w/ data (frame +1)
7829f9f09b0SDouglas Anderson * - complete split w/ data (frame +2)
7839f9f09b0SDouglas Anderson * - complete split w/ data (frame +3, max 8)
7849f9f09b0SDouglas Anderson *
7859f9f09b0SDouglas Anderson * For INTERRUPT out we might need to do:
7869f9f09b0SDouglas Anderson * - start split w/ data (frame -1)
7879f9f09b0SDouglas Anderson * - complete split (frame +1)
7889f9f09b0SDouglas Anderson * - complete split (frame +2)
7899f9f09b0SDouglas Anderson * - complete split (frame +3, max 8)
7909f9f09b0SDouglas Anderson *
7919f9f09b0SDouglas Anderson * Start adjusting!
7929f9f09b0SDouglas Anderson */
7939f9f09b0SDouglas Anderson ssplit_s_uframe = (start_s_uframe +
7949f9f09b0SDouglas Anderson host_interval_in_sched - 1) %
7959f9f09b0SDouglas Anderson host_interval_in_sched;
7969f9f09b0SDouglas Anderson if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
7979f9f09b0SDouglas Anderson second_s_uframe = start_s_uframe;
7989f9f09b0SDouglas Anderson else
7999f9f09b0SDouglas Anderson second_s_uframe = start_s_uframe + 1;
8009f9f09b0SDouglas Anderson
8019f9f09b0SDouglas Anderson /* First data transfer might not be all 188 bytes. */
8029f9f09b0SDouglas Anderson first_data_bytes = 188 -
8039f9f09b0SDouglas Anderson DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
8049f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME),
8059f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME);
8069f9f09b0SDouglas Anderson if (first_data_bytes > bytecount)
8079f9f09b0SDouglas Anderson first_data_bytes = bytecount;
8089f9f09b0SDouglas Anderson other_data_bytes = bytecount - first_data_bytes;
8099f9f09b0SDouglas Anderson
8109f9f09b0SDouglas Anderson /*
8119f9f09b0SDouglas Anderson * For now, skip OUT xfers where first xfer is partial
8129f9f09b0SDouglas Anderson *
8139f9f09b0SDouglas Anderson * Main dwc2 code assumes:
8149f9f09b0SDouglas Anderson * - INT transfers never get split in two.
8159f9f09b0SDouglas Anderson * - ISOC transfers can always transfer 188 bytes the first
8169f9f09b0SDouglas Anderson * time.
8179f9f09b0SDouglas Anderson *
8189f9f09b0SDouglas Anderson * Until that code is fixed, try again if the first transfer
8199f9f09b0SDouglas Anderson * couldn't transfer everything.
8209f9f09b0SDouglas Anderson *
8219f9f09b0SDouglas Anderson * This code can be removed if/when the rest of dwc2 handles
8229f9f09b0SDouglas Anderson * the above cases. Until it's fixed we just won't be able
8239f9f09b0SDouglas Anderson * to schedule quite as tightly.
8249f9f09b0SDouglas Anderson */
8259f9f09b0SDouglas Anderson if (!qh->ep_is_in &&
8269f9f09b0SDouglas Anderson (first_data_bytes != min_t(int, 188, bytecount))) {
8279f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg,
8289f9f09b0SDouglas Anderson "QH=%p avoiding broken 1st xfer (%d, %d)\n",
8299f9f09b0SDouglas Anderson qh, first_data_bytes, bytecount);
8309f9f09b0SDouglas Anderson if (qh->schedule_low_speed)
8319f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh);
8329f9f09b0SDouglas Anderson ls_search_slice = (start_s_uframe + 1) *
8339f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME;
8349f9f09b0SDouglas Anderson continue;
8359f9f09b0SDouglas Anderson }
8369f9f09b0SDouglas Anderson
8379f9f09b0SDouglas Anderson /* Start by assuming transfers for the bytes */
8389f9f09b0SDouglas Anderson qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
8399f9f09b0SDouglas Anderson
8409f9f09b0SDouglas Anderson /*
8419f9f09b0SDouglas Anderson * Everything except ISOC OUT has extra transfers. Rules are
8429f9f09b0SDouglas Anderson * complicated. See 11.18.4 Host Split Transaction Scheduling
8439f9f09b0SDouglas Anderson * Requirements bullet 3.
8449f9f09b0SDouglas Anderson */
8459f9f09b0SDouglas Anderson if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
8469f9f09b0SDouglas Anderson if (rel_uframe == 6)
8479f9f09b0SDouglas Anderson qh->num_hs_transfers += 2;
8489f9f09b0SDouglas Anderson else
8499f9f09b0SDouglas Anderson qh->num_hs_transfers += 3;
8509f9f09b0SDouglas Anderson
8519f9f09b0SDouglas Anderson if (qh->ep_is_in) {
8529f9f09b0SDouglas Anderson /*
8539f9f09b0SDouglas Anderson * First is start split, middle/end is data.
8549f9f09b0SDouglas Anderson * Allocate full data bytes for all data.
8559f9f09b0SDouglas Anderson */
8569f9f09b0SDouglas Anderson first_count = 4;
8579f9f09b0SDouglas Anderson middle_count = bytecount;
8589f9f09b0SDouglas Anderson end_count = bytecount;
8599f9f09b0SDouglas Anderson } else {
8609f9f09b0SDouglas Anderson /*
8619f9f09b0SDouglas Anderson * First is data, middle/end is complete.
8629f9f09b0SDouglas Anderson * First transfer and second can have data.
8639f9f09b0SDouglas Anderson * Rest should just have complete split.
8649f9f09b0SDouglas Anderson */
8659f9f09b0SDouglas Anderson first_count = first_data_bytes;
8669f9f09b0SDouglas Anderson middle_count = max_t(int, 4, other_data_bytes);
8679f9f09b0SDouglas Anderson end_count = 4;
8689f9f09b0SDouglas Anderson }
8699f9f09b0SDouglas Anderson } else {
8709f9f09b0SDouglas Anderson if (qh->ep_is_in) {
8719f9f09b0SDouglas Anderson int last;
8729f9f09b0SDouglas Anderson
8739f9f09b0SDouglas Anderson /* Account for the start split */
8749f9f09b0SDouglas Anderson qh->num_hs_transfers++;
8759f9f09b0SDouglas Anderson
8769f9f09b0SDouglas Anderson /* Calculate "L" value from spec */
8779f9f09b0SDouglas Anderson last = rel_uframe + qh->num_hs_transfers + 1;
8789f9f09b0SDouglas Anderson
8799f9f09b0SDouglas Anderson /* Start with basic case */
8809f9f09b0SDouglas Anderson if (last <= 6)
8819f9f09b0SDouglas Anderson qh->num_hs_transfers += 2;
8829f9f09b0SDouglas Anderson else
8839f9f09b0SDouglas Anderson qh->num_hs_transfers += 1;
8849f9f09b0SDouglas Anderson
8859f9f09b0SDouglas Anderson /* Adjust downwards */
8869f9f09b0SDouglas Anderson if (last >= 6 && rel_uframe == 0)
8879f9f09b0SDouglas Anderson qh->num_hs_transfers--;
8889f9f09b0SDouglas Anderson
8899f9f09b0SDouglas Anderson /* 1st = start; rest can contain data */
8909f9f09b0SDouglas Anderson first_count = 4;
8919f9f09b0SDouglas Anderson middle_count = min_t(int, 188, bytecount);
8929f9f09b0SDouglas Anderson end_count = middle_count;
8939f9f09b0SDouglas Anderson } else {
8949f9f09b0SDouglas Anderson /* All contain data, last might be smaller */
8959f9f09b0SDouglas Anderson first_count = first_data_bytes;
8969f9f09b0SDouglas Anderson middle_count = min_t(int, 188,
8979f9f09b0SDouglas Anderson other_data_bytes);
8989f9f09b0SDouglas Anderson end_count = other_data_bytes % 188;
8999f9f09b0SDouglas Anderson }
9009f9f09b0SDouglas Anderson }
9019f9f09b0SDouglas Anderson
9029f9f09b0SDouglas Anderson /* Assign durations per uFrame */
9039f9f09b0SDouglas Anderson qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
9049f9f09b0SDouglas Anderson for (i = 1; i < qh->num_hs_transfers - 1; i++)
9059f9f09b0SDouglas Anderson qh->hs_transfers[i].duration_us =
9069f9f09b0SDouglas Anderson HS_USECS_ISO(middle_count);
9079f9f09b0SDouglas Anderson if (qh->num_hs_transfers > 1)
9089f9f09b0SDouglas Anderson qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
9099f9f09b0SDouglas Anderson HS_USECS_ISO(end_count);
9109f9f09b0SDouglas Anderson
9119f9f09b0SDouglas Anderson /*
9129f9f09b0SDouglas Anderson * Assign start us. The call below to dwc2_hs_pmap_schedule()
9139f9f09b0SDouglas Anderson * will start with these numbers but may adjust within the same
9149f9f09b0SDouglas Anderson * microframe.
9159f9f09b0SDouglas Anderson */
9169f9f09b0SDouglas Anderson qh->hs_transfers[0].start_schedule_us =
9179f9f09b0SDouglas Anderson ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
9189f9f09b0SDouglas Anderson for (i = 1; i < qh->num_hs_transfers; i++)
9199f9f09b0SDouglas Anderson qh->hs_transfers[i].start_schedule_us =
9209f9f09b0SDouglas Anderson ((second_s_uframe + i - 1) %
9219f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES) *
9229f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME;
9239f9f09b0SDouglas Anderson
9249f9f09b0SDouglas Anderson /* Try to schedule with filled in hs_transfers above */
9259f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++) {
9269f9f09b0SDouglas Anderson err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
9279f9f09b0SDouglas Anderson if (err)
9289f9f09b0SDouglas Anderson break;
9299f9f09b0SDouglas Anderson }
9309f9f09b0SDouglas Anderson
9319f9f09b0SDouglas Anderson /* If we scheduled all w/out breaking out then we're all good */
9329f9f09b0SDouglas Anderson if (i == qh->num_hs_transfers)
9339f9f09b0SDouglas Anderson break;
9349f9f09b0SDouglas Anderson
9359f9f09b0SDouglas Anderson for (; i >= 0; i--)
9369f9f09b0SDouglas Anderson dwc2_hs_pmap_unschedule(hsotg, qh, i);
9379f9f09b0SDouglas Anderson
9389f9f09b0SDouglas Anderson if (qh->schedule_low_speed)
9399f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh);
9409f9f09b0SDouglas Anderson
9419f9f09b0SDouglas Anderson /* Try again starting in the next microframe */
9429f9f09b0SDouglas Anderson ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
9439f9f09b0SDouglas Anderson }
9449f9f09b0SDouglas Anderson
9459f9f09b0SDouglas Anderson if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
9469f9f09b0SDouglas Anderson return -ENOSPC;
9479f9f09b0SDouglas Anderson
9489f9f09b0SDouglas Anderson return 0;
9499f9f09b0SDouglas Anderson }
9509f9f09b0SDouglas Anderson
9519f9f09b0SDouglas Anderson /**
9529f9f09b0SDouglas Anderson * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
9539f9f09b0SDouglas Anderson *
9549f9f09b0SDouglas Anderson * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
9559f9f09b0SDouglas Anderson * interface.
9569f9f09b0SDouglas Anderson *
9579f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
9589f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
9599f9f09b0SDouglas Anderson */
dwc2_uframe_schedule_hs(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)9609f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
9619f9f09b0SDouglas Anderson {
9629f9f09b0SDouglas Anderson /* In non-split host and device time are the same */
9639f9f09b0SDouglas Anderson WARN_ON(qh->host_us != qh->device_us);
9649f9f09b0SDouglas Anderson WARN_ON(qh->host_interval != qh->device_interval);
9659f9f09b0SDouglas Anderson WARN_ON(qh->num_hs_transfers != 1);
9669f9f09b0SDouglas Anderson
9679f9f09b0SDouglas Anderson /* We'll have one transfer; init start to 0 before calling scheduler */
9689f9f09b0SDouglas Anderson qh->hs_transfers[0].start_schedule_us = 0;
9699f9f09b0SDouglas Anderson qh->hs_transfers[0].duration_us = qh->host_us;
9709f9f09b0SDouglas Anderson
9719f9f09b0SDouglas Anderson return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
9729f9f09b0SDouglas Anderson }
9739f9f09b0SDouglas Anderson
9749f9f09b0SDouglas Anderson /**
9759f9f09b0SDouglas Anderson * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
9769f9f09b0SDouglas Anderson *
9779f9f09b0SDouglas Anderson * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
9789f9f09b0SDouglas Anderson * interface.
9799f9f09b0SDouglas Anderson *
9809f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
9819f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
9829f9f09b0SDouglas Anderson */
dwc2_uframe_schedule_ls(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)9839f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
9849f9f09b0SDouglas Anderson {
9859f9f09b0SDouglas Anderson /* In non-split host and device time are the same */
9869f9f09b0SDouglas Anderson WARN_ON(qh->host_us != qh->device_us);
9879f9f09b0SDouglas Anderson WARN_ON(qh->host_interval != qh->device_interval);
9889f9f09b0SDouglas Anderson WARN_ON(!qh->schedule_low_speed);
9899f9f09b0SDouglas Anderson
9909f9f09b0SDouglas Anderson /* Run on the main low speed schedule (no split = no hub = no TT) */
9919f9f09b0SDouglas Anderson return dwc2_ls_pmap_schedule(hsotg, qh, 0);
9929f9f09b0SDouglas Anderson }
9939f9f09b0SDouglas Anderson
9949f9f09b0SDouglas Anderson /**
9959f9f09b0SDouglas Anderson * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
9969f9f09b0SDouglas Anderson *
9979f9f09b0SDouglas Anderson * Calls one of the 3 sub-function depending on what type of transfer this QH
9989f9f09b0SDouglas Anderson * is for. Also adds some printing.
9999f9f09b0SDouglas Anderson *
10009f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
10019f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
10029f9f09b0SDouglas Anderson */
dwc2_uframe_schedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)10039f9f09b0SDouglas Anderson static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1004b951c6c7SDouglas Anderson {
1005b951c6c7SDouglas Anderson int ret;
1006b951c6c7SDouglas Anderson
10079f9f09b0SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH)
10089f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_hs(hsotg, qh);
10099f9f09b0SDouglas Anderson else if (!qh->do_split)
10109f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_ls(hsotg, qh);
10119f9f09b0SDouglas Anderson else
10129f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_split(hsotg, qh);
10139f9f09b0SDouglas Anderson
10149f9f09b0SDouglas Anderson if (ret)
10159f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
10169f9f09b0SDouglas Anderson else
10179f9f09b0SDouglas Anderson dwc2_qh_schedule_print(hsotg, qh);
10189f9f09b0SDouglas Anderson
1019b951c6c7SDouglas Anderson return ret;
1020b951c6c7SDouglas Anderson }
1021b951c6c7SDouglas Anderson
1022b951c6c7SDouglas Anderson /**
10239f9f09b0SDouglas Anderson * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
10249f9f09b0SDouglas Anderson *
10259f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller.
10269f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer.
10279f9f09b0SDouglas Anderson */
dwc2_uframe_unschedule(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)10289f9f09b0SDouglas Anderson static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
10299f9f09b0SDouglas Anderson {
10309f9f09b0SDouglas Anderson int i;
10319f9f09b0SDouglas Anderson
10329f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++)
10339f9f09b0SDouglas Anderson dwc2_hs_pmap_unschedule(hsotg, qh, i);
10349f9f09b0SDouglas Anderson
10359f9f09b0SDouglas Anderson if (qh->schedule_low_speed)
10369f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh);
10379f9f09b0SDouglas Anderson
10389f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
10399f9f09b0SDouglas Anderson }
10409f9f09b0SDouglas Anderson
10419f9f09b0SDouglas Anderson /**
1042fb616e3fSDouglas Anderson * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1043fb616e3fSDouglas Anderson *
1044fb616e3fSDouglas Anderson * Takes a qh that has already been scheduled (which means we know we have the
1045fb616e3fSDouglas Anderson * bandwdith reserved for us) and set the next_active_frame and the
1046fb616e3fSDouglas Anderson * start_active_frame.
1047fb616e3fSDouglas Anderson *
1048fb616e3fSDouglas Anderson * This is expected to be called on qh's that weren't previously actively
1049fb616e3fSDouglas Anderson * running. It just picks the next frame that we can fit into without any
1050fb616e3fSDouglas Anderson * thought about the past.
1051fb616e3fSDouglas Anderson *
1052fb616e3fSDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
1053fb616e3fSDouglas Anderson * @qh: QH for a periodic endpoint
1054fb616e3fSDouglas Anderson *
1055fb616e3fSDouglas Anderson */
dwc2_pick_first_frame(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1056fb616e3fSDouglas Anderson static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1057fb616e3fSDouglas Anderson {
1058fb616e3fSDouglas Anderson u16 frame_number;
1059fb616e3fSDouglas Anderson u16 earliest_frame;
1060fb616e3fSDouglas Anderson u16 next_active_frame;
10619f9f09b0SDouglas Anderson u16 relative_frame;
1062fb616e3fSDouglas Anderson u16 interval;
1063fb616e3fSDouglas Anderson
1064fb616e3fSDouglas Anderson /*
1065fb616e3fSDouglas Anderson * Use the real frame number rather than the cached value as of the
1066fb616e3fSDouglas Anderson * last SOF to give us a little extra slop.
1067fb616e3fSDouglas Anderson */
1068fb616e3fSDouglas Anderson frame_number = dwc2_hcd_get_frame_number(hsotg);
1069fb616e3fSDouglas Anderson
1070fb616e3fSDouglas Anderson /*
1071fb616e3fSDouglas Anderson * We wouldn't want to start any earlier than the next frame just in
1072fb616e3fSDouglas Anderson * case the frame number ticks as we're doing this calculation.
1073fb616e3fSDouglas Anderson *
1074fb616e3fSDouglas Anderson * NOTE: if we could quantify how long till we actually get scheduled
1075fb616e3fSDouglas Anderson * we might be able to avoid the "+ 1" by looking at the upper part of
1076fb616e3fSDouglas Anderson * HFNUM (the FRREM field). For now we'll just use the + 1 though.
1077fb616e3fSDouglas Anderson */
1078fb616e3fSDouglas Anderson earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1079fb616e3fSDouglas Anderson next_active_frame = earliest_frame;
1080fb616e3fSDouglas Anderson
1081*df9ba6a2SDeming Wang /* Get the "no microframe scheduler" out of the way... */
108295832c00SJohn Youn if (!hsotg->params.uframe_sched) {
1083fb616e3fSDouglas Anderson if (qh->do_split)
1084fb616e3fSDouglas Anderson /* Splits are active at microframe 0 minus 1 */
1085fb616e3fSDouglas Anderson next_active_frame |= 0x7;
1086fb616e3fSDouglas Anderson goto exit;
1087fb616e3fSDouglas Anderson }
1088fb616e3fSDouglas Anderson
10899f9f09b0SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
10909f9f09b0SDouglas Anderson /*
10919f9f09b0SDouglas Anderson * We're either at high speed or we're doing a split (which
10929f9f09b0SDouglas Anderson * means we're talking high speed to a hub). In any case
10939f9f09b0SDouglas Anderson * the first frame should be based on when the first scheduled
10949f9f09b0SDouglas Anderson * event is.
10959f9f09b0SDouglas Anderson */
10969f9f09b0SDouglas Anderson WARN_ON(qh->num_hs_transfers < 1);
10979f9f09b0SDouglas Anderson
10989f9f09b0SDouglas Anderson relative_frame = qh->hs_transfers[0].start_schedule_us /
10999f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME;
11009f9f09b0SDouglas Anderson
11019f9f09b0SDouglas Anderson /* Adjust interval as per high speed schedule */
11029f9f09b0SDouglas Anderson interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
11039f9f09b0SDouglas Anderson
11049f9f09b0SDouglas Anderson } else {
11059f9f09b0SDouglas Anderson /*
11069f9f09b0SDouglas Anderson * Low or full speed directly on dwc2. Just about the same
11079f9f09b0SDouglas Anderson * as high speed but on a different schedule and with slightly
11089f9f09b0SDouglas Anderson * different adjustments. Note that this works because when
11099f9f09b0SDouglas Anderson * the host and device are both low speed then frames in the
11109f9f09b0SDouglas Anderson * controller tick at low speed.
11119f9f09b0SDouglas Anderson */
11129f9f09b0SDouglas Anderson relative_frame = qh->ls_start_schedule_slice /
11139f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME;
11149f9f09b0SDouglas Anderson interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
11159f9f09b0SDouglas Anderson }
11169f9f09b0SDouglas Anderson
11179f9f09b0SDouglas Anderson /* Scheduler messed up if frame is past interval */
11189f9f09b0SDouglas Anderson WARN_ON(relative_frame >= interval);
1119fb616e3fSDouglas Anderson
1120fb616e3fSDouglas Anderson /*
1121fb616e3fSDouglas Anderson * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1122fb616e3fSDouglas Anderson * done the gcd(), so it's safe to move to the beginning of the current
1123fb616e3fSDouglas Anderson * interval like this.
1124fb616e3fSDouglas Anderson *
1125fb616e3fSDouglas Anderson * After this we might be before earliest_frame, but don't worry,
1126fb616e3fSDouglas Anderson * we'll fix it...
1127fb616e3fSDouglas Anderson */
1128fb616e3fSDouglas Anderson next_active_frame = (next_active_frame / interval) * interval;
1129fb616e3fSDouglas Anderson
1130fb616e3fSDouglas Anderson /*
1131fb616e3fSDouglas Anderson * Actually choose to start at the frame number we've been
1132fb616e3fSDouglas Anderson * scheduled for.
1133fb616e3fSDouglas Anderson */
1134fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_inc(next_active_frame,
11359f9f09b0SDouglas Anderson relative_frame);
1136fb616e3fSDouglas Anderson
1137fb616e3fSDouglas Anderson /*
1138fb616e3fSDouglas Anderson * We actually need 1 frame before since the next_active_frame is
1139fb616e3fSDouglas Anderson * the frame number we'll be put on the ready list and we won't be on
1140fb616e3fSDouglas Anderson * the bus until 1 frame later.
1141fb616e3fSDouglas Anderson */
1142fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1143fb616e3fSDouglas Anderson
1144fb616e3fSDouglas Anderson /*
1145fb616e3fSDouglas Anderson * By now we might actually be before the earliest_frame. Let's move
1146fb616e3fSDouglas Anderson * up intervals until we're not.
1147fb616e3fSDouglas Anderson */
1148fb616e3fSDouglas Anderson while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1149fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_inc(next_active_frame,
1150fb616e3fSDouglas Anderson interval);
1151fb616e3fSDouglas Anderson
1152fb616e3fSDouglas Anderson exit:
1153fb616e3fSDouglas Anderson qh->next_active_frame = next_active_frame;
1154fb616e3fSDouglas Anderson qh->start_active_frame = next_active_frame;
1155fb616e3fSDouglas Anderson
1156fb616e3fSDouglas Anderson dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1157fb616e3fSDouglas Anderson qh, frame_number, qh->next_active_frame);
1158fb616e3fSDouglas Anderson }
1159fb616e3fSDouglas Anderson
1160fb616e3fSDouglas Anderson /**
11612d3f1398SDouglas Anderson * dwc2_do_reserve() - Make a periodic reservation
11622d3f1398SDouglas Anderson *
11632d3f1398SDouglas Anderson * Try to allocate space in the periodic schedule. Depending on parameters
11642d3f1398SDouglas Anderson * this might use the microframe scheduler or the dumb scheduler.
11652d3f1398SDouglas Anderson *
11662d3f1398SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
11672d3f1398SDouglas Anderson * @qh: QH for the periodic transfer.
11682d3f1398SDouglas Anderson *
11692d3f1398SDouglas Anderson * Returns: 0 upon success; error upon failure.
11702d3f1398SDouglas Anderson */
dwc2_do_reserve(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)11712d3f1398SDouglas Anderson static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
11722d3f1398SDouglas Anderson {
11732d3f1398SDouglas Anderson int status;
11742d3f1398SDouglas Anderson
117595832c00SJohn Youn if (hsotg->params.uframe_sched) {
11769f9f09b0SDouglas Anderson status = dwc2_uframe_schedule(hsotg, qh);
11772d3f1398SDouglas Anderson } else {
11782d3f1398SDouglas Anderson status = dwc2_periodic_channel_available(hsotg);
11792d3f1398SDouglas Anderson if (status) {
11802d3f1398SDouglas Anderson dev_info(hsotg->dev,
11812d3f1398SDouglas Anderson "%s: No host channel available for periodic transfer\n",
11822d3f1398SDouglas Anderson __func__);
11832d3f1398SDouglas Anderson return status;
11842d3f1398SDouglas Anderson }
11852d3f1398SDouglas Anderson
11862d3f1398SDouglas Anderson status = dwc2_check_periodic_bandwidth(hsotg, qh);
11872d3f1398SDouglas Anderson }
11882d3f1398SDouglas Anderson
11892d3f1398SDouglas Anderson if (status) {
11902d3f1398SDouglas Anderson dev_dbg(hsotg->dev,
11912d3f1398SDouglas Anderson "%s: Insufficient periodic bandwidth for periodic transfer\n",
11922d3f1398SDouglas Anderson __func__);
11932d3f1398SDouglas Anderson return status;
11942d3f1398SDouglas Anderson }
11952d3f1398SDouglas Anderson
119695832c00SJohn Youn if (!hsotg->params.uframe_sched)
11972d3f1398SDouglas Anderson /* Reserve periodic channel */
11982d3f1398SDouglas Anderson hsotg->periodic_channels++;
11992d3f1398SDouglas Anderson
12002d3f1398SDouglas Anderson /* Update claimed usecs per (micro)frame */
12012d3f1398SDouglas Anderson hsotg->periodic_usecs += qh->host_us;
12022d3f1398SDouglas Anderson
1203fb616e3fSDouglas Anderson dwc2_pick_first_frame(hsotg, qh);
1204fb616e3fSDouglas Anderson
12052d3f1398SDouglas Anderson return 0;
12062d3f1398SDouglas Anderson }
12072d3f1398SDouglas Anderson
12082d3f1398SDouglas Anderson /**
120917dd5b64SDouglas Anderson * dwc2_do_unreserve() - Actually release the periodic reservation
121017dd5b64SDouglas Anderson *
121117dd5b64SDouglas Anderson * This function actually releases the periodic bandwidth that was reserved
121217dd5b64SDouglas Anderson * by the given qh.
121317dd5b64SDouglas Anderson *
121417dd5b64SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
121517dd5b64SDouglas Anderson * @qh: QH for the periodic transfer.
121617dd5b64SDouglas Anderson */
dwc2_do_unreserve(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)121717dd5b64SDouglas Anderson static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
121817dd5b64SDouglas Anderson {
121917dd5b64SDouglas Anderson assert_spin_locked(&hsotg->lock);
122017dd5b64SDouglas Anderson
122117dd5b64SDouglas Anderson WARN_ON(!qh->unreserve_pending);
122217dd5b64SDouglas Anderson
122317dd5b64SDouglas Anderson /* No more unreserve pending--we're doing it */
122417dd5b64SDouglas Anderson qh->unreserve_pending = false;
122517dd5b64SDouglas Anderson
122617dd5b64SDouglas Anderson if (WARN_ON(!list_empty(&qh->qh_list_entry)))
122717dd5b64SDouglas Anderson list_del_init(&qh->qh_list_entry);
122817dd5b64SDouglas Anderson
122917dd5b64SDouglas Anderson /* Update claimed usecs per (micro)frame */
1230ced9eee1SDouglas Anderson hsotg->periodic_usecs -= qh->host_us;
123117dd5b64SDouglas Anderson
123295832c00SJohn Youn if (hsotg->params.uframe_sched) {
12339f9f09b0SDouglas Anderson dwc2_uframe_unschedule(hsotg, qh);
123417dd5b64SDouglas Anderson } else {
123517dd5b64SDouglas Anderson /* Release periodic channel reservation */
123617dd5b64SDouglas Anderson hsotg->periodic_channels--;
123717dd5b64SDouglas Anderson }
123817dd5b64SDouglas Anderson }
123917dd5b64SDouglas Anderson
124017dd5b64SDouglas Anderson /**
124117dd5b64SDouglas Anderson * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
124217dd5b64SDouglas Anderson *
124317dd5b64SDouglas Anderson * According to the kernel doc for usb_submit_urb() (specifically the part about
124417dd5b64SDouglas Anderson * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
124517dd5b64SDouglas Anderson * long as a device driver keeps submitting. Since we're using HCD_BH to give
124617dd5b64SDouglas Anderson * back the URB we need to give the driver a little bit of time before we
124717dd5b64SDouglas Anderson * release the reservation. This worker is called after the appropriate
124817dd5b64SDouglas Anderson * delay.
124917dd5b64SDouglas Anderson *
12506fb914d7SGrigor Tovmasyan * @t: Address to a qh unreserve_work.
125117dd5b64SDouglas Anderson */
dwc2_unreserve_timer_fn(struct timer_list * t)1252e99e88a9SKees Cook static void dwc2_unreserve_timer_fn(struct timer_list *t)
125317dd5b64SDouglas Anderson {
1254e99e88a9SKees Cook struct dwc2_qh *qh = from_timer(qh, t, unreserve_timer);
125517dd5b64SDouglas Anderson struct dwc2_hsotg *hsotg = qh->hsotg;
125617dd5b64SDouglas Anderson unsigned long flags;
125717dd5b64SDouglas Anderson
125817dd5b64SDouglas Anderson /*
125917dd5b64SDouglas Anderson * Wait for the lock, or for us to be scheduled again. We
126017dd5b64SDouglas Anderson * could be scheduled again if:
126117dd5b64SDouglas Anderson * - We started executing but didn't get the lock yet.
126217dd5b64SDouglas Anderson * - A new reservation came in, but cancel didn't take effect
126317dd5b64SDouglas Anderson * because we already started executing.
126417dd5b64SDouglas Anderson * - The timer has been kicked again.
126517dd5b64SDouglas Anderson * In that case cancel and wait for the next call.
126617dd5b64SDouglas Anderson */
126717dd5b64SDouglas Anderson while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
126817dd5b64SDouglas Anderson if (timer_pending(&qh->unreserve_timer))
126917dd5b64SDouglas Anderson return;
127017dd5b64SDouglas Anderson }
127117dd5b64SDouglas Anderson
127217dd5b64SDouglas Anderson /*
127317dd5b64SDouglas Anderson * Might be no more unreserve pending if:
127417dd5b64SDouglas Anderson * - We started executing but didn't get the lock yet.
127517dd5b64SDouglas Anderson * - A new reservation came in, but cancel didn't take effect
127617dd5b64SDouglas Anderson * because we already started executing.
127717dd5b64SDouglas Anderson *
127817dd5b64SDouglas Anderson * We can't put this in the loop above because unreserve_pending needs
127917dd5b64SDouglas Anderson * to be accessed under lock, so we can only check it once we got the
128017dd5b64SDouglas Anderson * lock.
128117dd5b64SDouglas Anderson */
128217dd5b64SDouglas Anderson if (qh->unreserve_pending)
128317dd5b64SDouglas Anderson dwc2_do_unreserve(hsotg, qh);
128417dd5b64SDouglas Anderson
128517dd5b64SDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags);
128617dd5b64SDouglas Anderson }
128717dd5b64SDouglas Anderson
1288197ba5f4SPaul Zimmerman /**
1289b951c6c7SDouglas Anderson * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1290b951c6c7SDouglas Anderson * host channel is large enough to handle the maximum data transfer in a single
1291b951c6c7SDouglas Anderson * (micro)frame for a periodic transfer
1292b951c6c7SDouglas Anderson *
1293b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
1294b951c6c7SDouglas Anderson * @qh: QH for a periodic endpoint
1295b951c6c7SDouglas Anderson *
1296b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise
1297b951c6c7SDouglas Anderson */
dwc2_check_max_xfer_size(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1298b951c6c7SDouglas Anderson static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1299b951c6c7SDouglas Anderson struct dwc2_qh *qh)
1300b951c6c7SDouglas Anderson {
1301b951c6c7SDouglas Anderson u32 max_xfer_size;
1302b951c6c7SDouglas Anderson u32 max_channel_xfer_size;
1303b951c6c7SDouglas Anderson int status = 0;
1304b951c6c7SDouglas Anderson
1305babd1839SDouglas Anderson max_xfer_size = qh->maxp * qh->maxp_mult;
1306bea8e86cSJohn Youn max_channel_xfer_size = hsotg->params.max_transfer_size;
1307b951c6c7SDouglas Anderson
1308b951c6c7SDouglas Anderson if (max_xfer_size > max_channel_xfer_size) {
1309b951c6c7SDouglas Anderson dev_err(hsotg->dev,
1310b951c6c7SDouglas Anderson "%s: Periodic xfer length %d > max xfer length for channel %d\n",
1311b951c6c7SDouglas Anderson __func__, max_xfer_size, max_channel_xfer_size);
1312b951c6c7SDouglas Anderson status = -ENOSPC;
1313b951c6c7SDouglas Anderson }
1314b951c6c7SDouglas Anderson
1315b951c6c7SDouglas Anderson return status;
1316b951c6c7SDouglas Anderson }
1317b951c6c7SDouglas Anderson
1318b951c6c7SDouglas Anderson /**
1319b951c6c7SDouglas Anderson * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1320b951c6c7SDouglas Anderson * the periodic schedule
1321b951c6c7SDouglas Anderson *
1322b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
1323b951c6c7SDouglas Anderson * @qh: QH for the periodic transfer. The QH should already contain the
1324b951c6c7SDouglas Anderson * scheduling information.
1325b951c6c7SDouglas Anderson *
1326b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise
1327b951c6c7SDouglas Anderson */
dwc2_schedule_periodic(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1328b951c6c7SDouglas Anderson static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1329b951c6c7SDouglas Anderson {
1330b951c6c7SDouglas Anderson int status;
1331b951c6c7SDouglas Anderson
1332b951c6c7SDouglas Anderson status = dwc2_check_max_xfer_size(hsotg, qh);
1333b951c6c7SDouglas Anderson if (status) {
1334b951c6c7SDouglas Anderson dev_dbg(hsotg->dev,
1335b951c6c7SDouglas Anderson "%s: Channel max transfer size too small for periodic transfer\n",
1336b951c6c7SDouglas Anderson __func__);
1337b951c6c7SDouglas Anderson return status;
1338b951c6c7SDouglas Anderson }
1339b951c6c7SDouglas Anderson
1340b951c6c7SDouglas Anderson /* Cancel pending unreserve; if canceled OK, unreserve was pending */
1341b951c6c7SDouglas Anderson if (del_timer(&qh->unreserve_timer))
1342b951c6c7SDouglas Anderson WARN_ON(!qh->unreserve_pending);
1343b951c6c7SDouglas Anderson
1344b951c6c7SDouglas Anderson /*
1345b951c6c7SDouglas Anderson * Only need to reserve if there's not an unreserve pending, since if an
1346b951c6c7SDouglas Anderson * unreserve is pending then by definition our old reservation is still
1347b951c6c7SDouglas Anderson * valid. Unreserve might still be pending even if we didn't cancel if
1348b951c6c7SDouglas Anderson * dwc2_unreserve_timer_fn() already started. Code in the timer handles
1349b951c6c7SDouglas Anderson * that case.
1350b951c6c7SDouglas Anderson */
1351b951c6c7SDouglas Anderson if (!qh->unreserve_pending) {
13522d3f1398SDouglas Anderson status = dwc2_do_reserve(hsotg, qh);
13532d3f1398SDouglas Anderson if (status)
1354b951c6c7SDouglas Anderson return status;
1355fb616e3fSDouglas Anderson } else {
1356fb616e3fSDouglas Anderson /*
1357fb616e3fSDouglas Anderson * It might have been a while, so make sure that frame_number
1358fb616e3fSDouglas Anderson * is still good. Note: we could also try to use the similar
1359fb616e3fSDouglas Anderson * dwc2_next_periodic_start() but that schedules much more
1360fb616e3fSDouglas Anderson * tightly and we might need to hurry and queue things up.
1361fb616e3fSDouglas Anderson */
1362fb616e3fSDouglas Anderson if (dwc2_frame_num_le(qh->next_active_frame,
1363fb616e3fSDouglas Anderson hsotg->frame_number))
1364fb616e3fSDouglas Anderson dwc2_pick_first_frame(hsotg, qh);
1365b951c6c7SDouglas Anderson }
1366b951c6c7SDouglas Anderson
1367b951c6c7SDouglas Anderson qh->unreserve_pending = 0;
1368b951c6c7SDouglas Anderson
136995832c00SJohn Youn if (hsotg->params.dma_desc_enable)
1370b951c6c7SDouglas Anderson /* Don't rely on SOF and start in ready schedule */
1371b951c6c7SDouglas Anderson list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1372b951c6c7SDouglas Anderson else
1373b951c6c7SDouglas Anderson /* Always start in inactive schedule */
1374b951c6c7SDouglas Anderson list_add_tail(&qh->qh_list_entry,
1375b951c6c7SDouglas Anderson &hsotg->periodic_sched_inactive);
1376b951c6c7SDouglas Anderson
13772d3f1398SDouglas Anderson return 0;
1378b951c6c7SDouglas Anderson }
1379b951c6c7SDouglas Anderson
1380b951c6c7SDouglas Anderson /**
1381b951c6c7SDouglas Anderson * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1382b951c6c7SDouglas Anderson * from the periodic schedule
1383b951c6c7SDouglas Anderson *
1384b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller
1385b951c6c7SDouglas Anderson * @qh: QH for the periodic transfer
1386b951c6c7SDouglas Anderson */
dwc2_deschedule_periodic(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1387b951c6c7SDouglas Anderson static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1388b951c6c7SDouglas Anderson struct dwc2_qh *qh)
1389b951c6c7SDouglas Anderson {
1390b951c6c7SDouglas Anderson bool did_modify;
1391b951c6c7SDouglas Anderson
1392b951c6c7SDouglas Anderson assert_spin_locked(&hsotg->lock);
1393b951c6c7SDouglas Anderson
1394b951c6c7SDouglas Anderson /*
1395b951c6c7SDouglas Anderson * Schedule the unreserve to happen in a little bit. Cases here:
1396b951c6c7SDouglas Anderson * - Unreserve worker might be sitting there waiting to grab the lock.
1397b951c6c7SDouglas Anderson * In this case it will notice it's been schedule again and will
1398b951c6c7SDouglas Anderson * quit.
1399b951c6c7SDouglas Anderson * - Unreserve worker might not be scheduled.
1400b951c6c7SDouglas Anderson *
1401b951c6c7SDouglas Anderson * We should never already be scheduled since dwc2_schedule_periodic()
1402b951c6c7SDouglas Anderson * should have canceled the scheduled unreserve timer (hence the
1403b951c6c7SDouglas Anderson * warning on did_modify).
1404b951c6c7SDouglas Anderson *
1405b951c6c7SDouglas Anderson * We add + 1 to the timer to guarantee that at least 1 jiffy has
1406b951c6c7SDouglas Anderson * passed (otherwise if the jiffy counter might tick right after we
1407b951c6c7SDouglas Anderson * read it and we'll get no delay).
1408b951c6c7SDouglas Anderson */
1409b951c6c7SDouglas Anderson did_modify = mod_timer(&qh->unreserve_timer,
1410b951c6c7SDouglas Anderson jiffies + DWC2_UNRESERVE_DELAY + 1);
1411b951c6c7SDouglas Anderson WARN_ON(did_modify);
1412b951c6c7SDouglas Anderson qh->unreserve_pending = 1;
1413b951c6c7SDouglas Anderson
1414b951c6c7SDouglas Anderson list_del_init(&qh->qh_list_entry);
1415b951c6c7SDouglas Anderson }
1416b951c6c7SDouglas Anderson
1417b951c6c7SDouglas Anderson /**
141838d2b5fbSDouglas Anderson * dwc2_wait_timer_fn() - Timer function to re-queue after waiting
141938d2b5fbSDouglas Anderson *
142038d2b5fbSDouglas Anderson * As per the spec, a NAK indicates that "a function is temporarily unable to
142138d2b5fbSDouglas Anderson * transmit or receive data, but will eventually be able to do so without need
142238d2b5fbSDouglas Anderson * of host intervention".
142338d2b5fbSDouglas Anderson *
142438d2b5fbSDouglas Anderson * That means that when we encounter a NAK we're supposed to retry.
142538d2b5fbSDouglas Anderson *
142638d2b5fbSDouglas Anderson * ...but if we retry right away (from the interrupt handler that saw the NAK)
142738d2b5fbSDouglas Anderson * then we can end up with an interrupt storm (if the other side keeps NAKing
142838d2b5fbSDouglas Anderson * us) because on slow enough CPUs it could take us longer to get out of the
142938d2b5fbSDouglas Anderson * interrupt routine than it takes for the device to send another NAK. That
143038d2b5fbSDouglas Anderson * leads to a constant stream of NAK interrupts and the CPU locks.
143138d2b5fbSDouglas Anderson *
143238d2b5fbSDouglas Anderson * ...so instead of retrying right away in the case of a NAK we'll set a timer
143338d2b5fbSDouglas Anderson * to retry some time later. This function handles that timer and moves the
143438d2b5fbSDouglas Anderson * qh back to the "inactive" list, then queues transactions.
143538d2b5fbSDouglas Anderson *
143638d2b5fbSDouglas Anderson * @t: Pointer to wait_timer in a qh.
14376ed30a7dSTerin Stock *
14386ed30a7dSTerin Stock * Return: HRTIMER_NORESTART to not automatically restart this timer.
143938d2b5fbSDouglas Anderson */
dwc2_wait_timer_fn(struct hrtimer * t)14406ed30a7dSTerin Stock static enum hrtimer_restart dwc2_wait_timer_fn(struct hrtimer *t)
144138d2b5fbSDouglas Anderson {
14426ed30a7dSTerin Stock struct dwc2_qh *qh = container_of(t, struct dwc2_qh, wait_timer);
144338d2b5fbSDouglas Anderson struct dwc2_hsotg *hsotg = qh->hsotg;
144438d2b5fbSDouglas Anderson unsigned long flags;
144538d2b5fbSDouglas Anderson
144638d2b5fbSDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags);
144738d2b5fbSDouglas Anderson
144838d2b5fbSDouglas Anderson /*
144938d2b5fbSDouglas Anderson * We'll set wait_timer_cancel to true if we want to cancel this
145038d2b5fbSDouglas Anderson * operation in dwc2_hcd_qh_unlink().
145138d2b5fbSDouglas Anderson */
145238d2b5fbSDouglas Anderson if (!qh->wait_timer_cancel) {
145338d2b5fbSDouglas Anderson enum dwc2_transaction_type tr_type;
145438d2b5fbSDouglas Anderson
145538d2b5fbSDouglas Anderson qh->want_wait = false;
145638d2b5fbSDouglas Anderson
145738d2b5fbSDouglas Anderson list_move(&qh->qh_list_entry,
145838d2b5fbSDouglas Anderson &hsotg->non_periodic_sched_inactive);
145938d2b5fbSDouglas Anderson
146038d2b5fbSDouglas Anderson tr_type = dwc2_hcd_select_transactions(hsotg);
146138d2b5fbSDouglas Anderson if (tr_type != DWC2_TRANSACTION_NONE)
146238d2b5fbSDouglas Anderson dwc2_hcd_queue_transactions(hsotg, tr_type);
146338d2b5fbSDouglas Anderson }
146438d2b5fbSDouglas Anderson
146538d2b5fbSDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags);
14666ed30a7dSTerin Stock return HRTIMER_NORESTART;
146738d2b5fbSDouglas Anderson }
146838d2b5fbSDouglas Anderson
146938d2b5fbSDouglas Anderson /**
1470197ba5f4SPaul Zimmerman * dwc2_qh_init() - Initializes a QH structure
1471197ba5f4SPaul Zimmerman *
1472197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller
1473197ba5f4SPaul Zimmerman * @qh: The QH to init
1474197ba5f4SPaul Zimmerman * @urb: Holds the information about the device/endpoint needed to initialize
1475197ba5f4SPaul Zimmerman * the QH
14769f9f09b0SDouglas Anderson * @mem_flags: Flags for allocating memory.
1477197ba5f4SPaul Zimmerman */
dwc2_qh_init(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,struct dwc2_hcd_urb * urb,gfp_t mem_flags)1478197ba5f4SPaul Zimmerman static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
14799f9f09b0SDouglas Anderson struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1480197ba5f4SPaul Zimmerman {
14819f9f09b0SDouglas Anderson int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
14829f9f09b0SDouglas Anderson u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
14839f9f09b0SDouglas Anderson bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
14849f9f09b0SDouglas Anderson bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
14859f9f09b0SDouglas Anderson bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1486f25c42b8SGevorg Sahakyan u32 hprt = dwc2_readl(hsotg, HPRT0);
14879f9f09b0SDouglas Anderson u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
14889f9f09b0SDouglas Anderson bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
14899f9f09b0SDouglas Anderson dev_speed != USB_SPEED_HIGH);
1490babd1839SDouglas Anderson int maxp = dwc2_hcd_get_maxp(&urb->pipe_info);
1491babd1839SDouglas Anderson int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info);
1492babd1839SDouglas Anderson int bytecount = maxp_mult * maxp;
1493197ba5f4SPaul Zimmerman char *speed, *type;
1494197ba5f4SPaul Zimmerman
1495197ba5f4SPaul Zimmerman /* Initialize QH */
149617dd5b64SDouglas Anderson qh->hsotg = hsotg;
1497e99e88a9SKees Cook timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0);
14986ed30a7dSTerin Stock hrtimer_init(&qh->wait_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
14996ed30a7dSTerin Stock qh->wait_timer.function = &dwc2_wait_timer_fn;
15009f9f09b0SDouglas Anderson qh->ep_type = ep_type;
15019f9f09b0SDouglas Anderson qh->ep_is_in = ep_is_in;
1502197ba5f4SPaul Zimmerman
1503197ba5f4SPaul Zimmerman qh->data_toggle = DWC2_HC_PID_DATA0;
15049f9f09b0SDouglas Anderson qh->maxp = maxp;
1505babd1839SDouglas Anderson qh->maxp_mult = maxp_mult;
1506197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&qh->qtd_list);
1507197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&qh->qh_list_entry);
1508197ba5f4SPaul Zimmerman
15099f9f09b0SDouglas Anderson qh->do_split = do_split;
1510197ba5f4SPaul Zimmerman qh->dev_speed = dev_speed;
1511197ba5f4SPaul Zimmerman
15129f9f09b0SDouglas Anderson if (ep_is_int || ep_is_isoc) {
15139f9f09b0SDouglas Anderson /* Compute scheduling parameters once and save them */
15149f9f09b0SDouglas Anderson int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
15159f9f09b0SDouglas Anderson struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
15169f9f09b0SDouglas Anderson mem_flags,
15179f9f09b0SDouglas Anderson &qh->ttport);
15189f9f09b0SDouglas Anderson int device_ns;
15199f9f09b0SDouglas Anderson
15209f9f09b0SDouglas Anderson qh->dwc_tt = dwc_tt;
15219f9f09b0SDouglas Anderson
15229f9f09b0SDouglas Anderson qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in,
15239f9f09b0SDouglas Anderson ep_is_isoc, bytecount));
15249f9f09b0SDouglas Anderson device_ns = usb_calc_bus_time(dev_speed, ep_is_in,
15259f9f09b0SDouglas Anderson ep_is_isoc, bytecount);
15269f9f09b0SDouglas Anderson
15279f9f09b0SDouglas Anderson if (do_split && dwc_tt)
15289f9f09b0SDouglas Anderson device_ns += dwc_tt->usb_tt->think_time;
15299f9f09b0SDouglas Anderson qh->device_us = NS_TO_US(device_ns);
15309f9f09b0SDouglas Anderson
15319f9f09b0SDouglas Anderson qh->device_interval = urb->interval;
15329f9f09b0SDouglas Anderson qh->host_interval = urb->interval * (do_split ? 8 : 1);
15339f9f09b0SDouglas Anderson
15349f9f09b0SDouglas Anderson /*
15359f9f09b0SDouglas Anderson * Schedule low speed if we're running the host in low or
15369f9f09b0SDouglas Anderson * full speed OR if we've got a "TT" to deal with to access this
15379f9f09b0SDouglas Anderson * device.
15389f9f09b0SDouglas Anderson */
15399f9f09b0SDouglas Anderson qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
15409f9f09b0SDouglas Anderson dwc_tt;
15419f9f09b0SDouglas Anderson
15429f9f09b0SDouglas Anderson if (do_split) {
15439f9f09b0SDouglas Anderson /* We won't know num transfers until we schedule */
15449f9f09b0SDouglas Anderson qh->num_hs_transfers = -1;
15459f9f09b0SDouglas Anderson } else if (dev_speed == USB_SPEED_HIGH) {
15469f9f09b0SDouglas Anderson qh->num_hs_transfers = 1;
15479f9f09b0SDouglas Anderson } else {
15489f9f09b0SDouglas Anderson qh->num_hs_transfers = 0;
15499f9f09b0SDouglas Anderson }
15509f9f09b0SDouglas Anderson
15519f9f09b0SDouglas Anderson /* We'll schedule later when we have something to do */
15529f9f09b0SDouglas Anderson }
15539f9f09b0SDouglas Anderson
1554197ba5f4SPaul Zimmerman switch (dev_speed) {
1555197ba5f4SPaul Zimmerman case USB_SPEED_LOW:
1556197ba5f4SPaul Zimmerman speed = "low";
1557197ba5f4SPaul Zimmerman break;
1558197ba5f4SPaul Zimmerman case USB_SPEED_FULL:
1559197ba5f4SPaul Zimmerman speed = "full";
1560197ba5f4SPaul Zimmerman break;
1561197ba5f4SPaul Zimmerman case USB_SPEED_HIGH:
1562197ba5f4SPaul Zimmerman speed = "high";
1563197ba5f4SPaul Zimmerman break;
1564197ba5f4SPaul Zimmerman default:
1565197ba5f4SPaul Zimmerman speed = "?";
1566197ba5f4SPaul Zimmerman break;
1567197ba5f4SPaul Zimmerman }
1568197ba5f4SPaul Zimmerman
1569197ba5f4SPaul Zimmerman switch (qh->ep_type) {
1570197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_ISOC:
1571197ba5f4SPaul Zimmerman type = "isochronous";
1572197ba5f4SPaul Zimmerman break;
1573197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_INT:
1574197ba5f4SPaul Zimmerman type = "interrupt";
1575197ba5f4SPaul Zimmerman break;
1576197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_CONTROL:
1577197ba5f4SPaul Zimmerman type = "control";
1578197ba5f4SPaul Zimmerman break;
1579197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_BULK:
1580197ba5f4SPaul Zimmerman type = "bulk";
1581197ba5f4SPaul Zimmerman break;
1582197ba5f4SPaul Zimmerman default:
1583197ba5f4SPaul Zimmerman type = "?";
1584197ba5f4SPaul Zimmerman break;
1585197ba5f4SPaul Zimmerman }
1586197ba5f4SPaul Zimmerman
15879f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
15889f9f09b0SDouglas Anderson speed, bytecount);
15899f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
15909f9f09b0SDouglas Anderson dwc2_hcd_get_dev_addr(&urb->pipe_info),
15919f9f09b0SDouglas Anderson dwc2_hcd_get_ep_num(&urb->pipe_info),
15929f9f09b0SDouglas Anderson ep_is_in ? "IN" : "OUT");
15939f9f09b0SDouglas Anderson if (ep_is_int || ep_is_isoc) {
15949f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg,
15959f9f09b0SDouglas Anderson "QH=%p ...duration: host=%d us, device=%d us\n",
15969f9f09b0SDouglas Anderson qh, qh->host_us, qh->device_us);
15979f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
15989f9f09b0SDouglas Anderson qh, qh->host_interval, qh->device_interval);
15999f9f09b0SDouglas Anderson if (qh->schedule_low_speed)
16009f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
16019f9f09b0SDouglas Anderson qh, dwc2_get_ls_map(hsotg, qh));
1602197ba5f4SPaul Zimmerman }
1603197ba5f4SPaul Zimmerman }
1604197ba5f4SPaul Zimmerman
1605197ba5f4SPaul Zimmerman /**
1606197ba5f4SPaul Zimmerman * dwc2_hcd_qh_create() - Allocates and initializes a QH
1607197ba5f4SPaul Zimmerman *
1608197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller
1609197ba5f4SPaul Zimmerman * @urb: Holds the information about the device/endpoint needed
1610197ba5f4SPaul Zimmerman * to initialize the QH
16116fb914d7SGrigor Tovmasyan * @mem_flags: Flags for allocating memory.
1612197ba5f4SPaul Zimmerman *
1613197ba5f4SPaul Zimmerman * Return: Pointer to the newly allocated QH, or NULL on error
1614197ba5f4SPaul Zimmerman */
dwc2_hcd_qh_create(struct dwc2_hsotg * hsotg,struct dwc2_hcd_urb * urb,gfp_t mem_flags)1615b58e6ceeSMian Yousaf Kaukab struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1616197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb,
1617197ba5f4SPaul Zimmerman gfp_t mem_flags)
1618197ba5f4SPaul Zimmerman {
1619197ba5f4SPaul Zimmerman struct dwc2_qh *qh;
1620197ba5f4SPaul Zimmerman
1621197ba5f4SPaul Zimmerman if (!urb->priv)
1622197ba5f4SPaul Zimmerman return NULL;
1623197ba5f4SPaul Zimmerman
1624197ba5f4SPaul Zimmerman /* Allocate memory */
1625197ba5f4SPaul Zimmerman qh = kzalloc(sizeof(*qh), mem_flags);
1626197ba5f4SPaul Zimmerman if (!qh)
1627197ba5f4SPaul Zimmerman return NULL;
1628197ba5f4SPaul Zimmerman
16299f9f09b0SDouglas Anderson dwc2_qh_init(hsotg, qh, urb, mem_flags);
1630197ba5f4SPaul Zimmerman
163195832c00SJohn Youn if (hsotg->params.dma_desc_enable &&
1632197ba5f4SPaul Zimmerman dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1633197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh);
1634197ba5f4SPaul Zimmerman return NULL;
1635197ba5f4SPaul Zimmerman }
1636197ba5f4SPaul Zimmerman
1637197ba5f4SPaul Zimmerman return qh;
1638197ba5f4SPaul Zimmerman }
1639197ba5f4SPaul Zimmerman
1640197ba5f4SPaul Zimmerman /**
1641197ba5f4SPaul Zimmerman * dwc2_hcd_qh_free() - Frees the QH
1642197ba5f4SPaul Zimmerman *
1643197ba5f4SPaul Zimmerman * @hsotg: HCD instance
1644197ba5f4SPaul Zimmerman * @qh: The QH to free
1645197ba5f4SPaul Zimmerman *
1646197ba5f4SPaul Zimmerman * QH should already be removed from the list. QTD list should already be empty
1647197ba5f4SPaul Zimmerman * if called from URB Dequeue.
1648197ba5f4SPaul Zimmerman *
1649197ba5f4SPaul Zimmerman * Must NOT be called with interrupt disabled or spinlock held
1650197ba5f4SPaul Zimmerman */
dwc2_hcd_qh_free(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1651197ba5f4SPaul Zimmerman void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1652197ba5f4SPaul Zimmerman {
165317dd5b64SDouglas Anderson /* Make sure any unreserve work is finished. */
165417dd5b64SDouglas Anderson if (del_timer_sync(&qh->unreserve_timer)) {
165517dd5b64SDouglas Anderson unsigned long flags;
165617dd5b64SDouglas Anderson
165717dd5b64SDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags);
165817dd5b64SDouglas Anderson dwc2_do_unreserve(hsotg, qh);
165917dd5b64SDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags);
166017dd5b64SDouglas Anderson }
166138d2b5fbSDouglas Anderson
166238d2b5fbSDouglas Anderson /*
166338d2b5fbSDouglas Anderson * We don't have the lock so we can safely wait until the wait timer
166438d2b5fbSDouglas Anderson * finishes. Of course, at this point in time we'd better have set
166538d2b5fbSDouglas Anderson * wait_timer_active to false so if this timer was still pending it
166638d2b5fbSDouglas Anderson * won't do anything anyway, but we want it to finish before we free
166738d2b5fbSDouglas Anderson * memory.
166838d2b5fbSDouglas Anderson */
16696ed30a7dSTerin Stock hrtimer_cancel(&qh->wait_timer);
167038d2b5fbSDouglas Anderson
16719f9f09b0SDouglas Anderson dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
167217dd5b64SDouglas Anderson
16733bc04e28SDouglas Anderson if (qh->desc_list)
1674197ba5f4SPaul Zimmerman dwc2_hcd_qh_free_ddma(hsotg, qh);
1675af424a41SWilliam Wu else if (hsotg->unaligned_cache && qh->dw_align_buf)
1676af424a41SWilliam Wu kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf);
1677af424a41SWilliam Wu
1678197ba5f4SPaul Zimmerman kfree(qh);
1679197ba5f4SPaul Zimmerman }
1680197ba5f4SPaul Zimmerman
1681197ba5f4SPaul Zimmerman /**
1682197ba5f4SPaul Zimmerman * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1683197ba5f4SPaul Zimmerman * schedule if it is not already in the schedule. If the QH is already in
1684197ba5f4SPaul Zimmerman * the schedule, no action is taken.
1685197ba5f4SPaul Zimmerman *
1686197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller
1687197ba5f4SPaul Zimmerman * @qh: The QH to add
1688197ba5f4SPaul Zimmerman *
1689197ba5f4SPaul Zimmerman * Return: 0 if successful, negative error code otherwise
1690197ba5f4SPaul Zimmerman */
dwc2_hcd_qh_add(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1691197ba5f4SPaul Zimmerman int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1692197ba5f4SPaul Zimmerman {
1693197ba5f4SPaul Zimmerman int status;
1694197ba5f4SPaul Zimmerman u32 intr_mask;
16956ed30a7dSTerin Stock ktime_t delay;
1696197ba5f4SPaul Zimmerman
1697197ba5f4SPaul Zimmerman if (dbg_qh(qh))
1698197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__);
1699197ba5f4SPaul Zimmerman
1700197ba5f4SPaul Zimmerman if (!list_empty(&qh->qh_list_entry))
1701197ba5f4SPaul Zimmerman /* QH already in a schedule */
1702197ba5f4SPaul Zimmerman return 0;
1703197ba5f4SPaul Zimmerman
1704197ba5f4SPaul Zimmerman /* Add the new QH to the appropriate schedule */
1705197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) {
1706fb616e3fSDouglas Anderson /* Schedule right away */
1707fb616e3fSDouglas Anderson qh->start_active_frame = hsotg->frame_number;
1708fb616e3fSDouglas Anderson qh->next_active_frame = qh->start_active_frame;
1709fb616e3fSDouglas Anderson
171038d2b5fbSDouglas Anderson if (qh->want_wait) {
171138d2b5fbSDouglas Anderson list_add_tail(&qh->qh_list_entry,
171238d2b5fbSDouglas Anderson &hsotg->non_periodic_sched_waiting);
171338d2b5fbSDouglas Anderson qh->wait_timer_cancel = false;
17146ed30a7dSTerin Stock delay = ktime_set(0, DWC2_RETRY_WAIT_DELAY);
17156ed30a7dSTerin Stock hrtimer_start(&qh->wait_timer, delay, HRTIMER_MODE_REL);
171638d2b5fbSDouglas Anderson } else {
1717197ba5f4SPaul Zimmerman list_add_tail(&qh->qh_list_entry,
1718197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_inactive);
171938d2b5fbSDouglas Anderson }
1720197ba5f4SPaul Zimmerman return 0;
1721197ba5f4SPaul Zimmerman }
1722197ba5f4SPaul Zimmerman
1723197ba5f4SPaul Zimmerman status = dwc2_schedule_periodic(hsotg, qh);
1724197ba5f4SPaul Zimmerman if (status)
1725197ba5f4SPaul Zimmerman return status;
1726197ba5f4SPaul Zimmerman if (!hsotg->periodic_qh_count) {
1727f25c42b8SGevorg Sahakyan intr_mask = dwc2_readl(hsotg, GINTMSK);
1728197ba5f4SPaul Zimmerman intr_mask |= GINTSTS_SOF;
1729f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, intr_mask, GINTMSK);
1730197ba5f4SPaul Zimmerman }
1731197ba5f4SPaul Zimmerman hsotg->periodic_qh_count++;
1732197ba5f4SPaul Zimmerman
1733197ba5f4SPaul Zimmerman return 0;
1734197ba5f4SPaul Zimmerman }
1735197ba5f4SPaul Zimmerman
1736197ba5f4SPaul Zimmerman /**
1737197ba5f4SPaul Zimmerman * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1738197ba5f4SPaul Zimmerman * schedule. Memory is not freed.
1739197ba5f4SPaul Zimmerman *
1740197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure
1741197ba5f4SPaul Zimmerman * @qh: QH to remove from schedule
1742197ba5f4SPaul Zimmerman */
dwc2_hcd_qh_unlink(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh)1743197ba5f4SPaul Zimmerman void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1744197ba5f4SPaul Zimmerman {
1745197ba5f4SPaul Zimmerman u32 intr_mask;
1746197ba5f4SPaul Zimmerman
1747197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__);
1748197ba5f4SPaul Zimmerman
174938d2b5fbSDouglas Anderson /* If the wait_timer is pending, this will stop it from acting */
175038d2b5fbSDouglas Anderson qh->wait_timer_cancel = true;
175138d2b5fbSDouglas Anderson
1752197ba5f4SPaul Zimmerman if (list_empty(&qh->qh_list_entry))
1753197ba5f4SPaul Zimmerman /* QH is not in a schedule */
1754197ba5f4SPaul Zimmerman return;
1755197ba5f4SPaul Zimmerman
1756197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) {
1757197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1758197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr =
1759197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr->next;
1760197ba5f4SPaul Zimmerman list_del_init(&qh->qh_list_entry);
1761197ba5f4SPaul Zimmerman return;
1762197ba5f4SPaul Zimmerman }
1763197ba5f4SPaul Zimmerman
1764197ba5f4SPaul Zimmerman dwc2_deschedule_periodic(hsotg, qh);
1765197ba5f4SPaul Zimmerman hsotg->periodic_qh_count--;
1766907a4447SSevak Arakelyan if (!hsotg->periodic_qh_count &&
176795832c00SJohn Youn !hsotg->params.dma_desc_enable) {
1768f25c42b8SGevorg Sahakyan intr_mask = dwc2_readl(hsotg, GINTMSK);
1769197ba5f4SPaul Zimmerman intr_mask &= ~GINTSTS_SOF;
1770f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, intr_mask, GINTMSK);
1771197ba5f4SPaul Zimmerman }
1772197ba5f4SPaul Zimmerman }
1773197ba5f4SPaul Zimmerman
1774fb616e3fSDouglas Anderson /**
1775fb616e3fSDouglas Anderson * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1776fb616e3fSDouglas Anderson *
1777fb616e3fSDouglas Anderson * This is called for setting next_active_frame for periodic splits for all but
1778fb616e3fSDouglas Anderson * the first packet of the split. Confusing? I thought so...
1779fb616e3fSDouglas Anderson *
1780fb616e3fSDouglas Anderson * Periodic splits are single low/full speed transfers that we end up splitting
1781fb616e3fSDouglas Anderson * up into several high speed transfers. They always fit into one full (1 ms)
1782fb616e3fSDouglas Anderson * frame but might be split over several microframes (125 us each). We to put
1783fb616e3fSDouglas Anderson * each of the parts on a very specific high speed frame.
1784fb616e3fSDouglas Anderson *
1785fb616e3fSDouglas Anderson * This function figures out where the next active uFrame needs to be.
1786fb616e3fSDouglas Anderson *
1787fb616e3fSDouglas Anderson * @hsotg: The HCD state structure
1788fb616e3fSDouglas Anderson * @qh: QH for the periodic transfer.
1789fb616e3fSDouglas Anderson * @frame_number: The current frame number.
1790fb616e3fSDouglas Anderson *
1791fb616e3fSDouglas Anderson * Return: number missed by (or 0 if we didn't miss).
1792197ba5f4SPaul Zimmerman */
dwc2_next_for_periodic_split(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,u16 frame_number)1793fb616e3fSDouglas Anderson static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1794fb616e3fSDouglas Anderson struct dwc2_qh *qh, u16 frame_number)
1795197ba5f4SPaul Zimmerman {
1796ced9eee1SDouglas Anderson u16 old_frame = qh->next_active_frame;
1797fb616e3fSDouglas Anderson u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1798fb616e3fSDouglas Anderson int missed = 0;
1799fb616e3fSDouglas Anderson u16 incr;
1800197ba5f4SPaul Zimmerman
1801197ba5f4SPaul Zimmerman /*
18029f9f09b0SDouglas Anderson * See dwc2_uframe_schedule_split() for split scheduling.
18039f9f09b0SDouglas Anderson *
1804fb616e3fSDouglas Anderson * Basically: increment 1 normally, but 2 right after the start split
1805fb616e3fSDouglas Anderson * (except for ISOC out).
1806197ba5f4SPaul Zimmerman */
1807fb616e3fSDouglas Anderson if (old_frame == qh->start_active_frame &&
1808fb616e3fSDouglas Anderson !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1809fb616e3fSDouglas Anderson incr = 2;
1810fb616e3fSDouglas Anderson else
1811fb616e3fSDouglas Anderson incr = 1;
1812fb616e3fSDouglas Anderson
1813fb616e3fSDouglas Anderson qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1814fb616e3fSDouglas Anderson
1815fb616e3fSDouglas Anderson /*
1816fb616e3fSDouglas Anderson * Note that it's OK for frame_number to be 1 frame past
1817fb616e3fSDouglas Anderson * next_active_frame. Remember that next_active_frame is supposed to
1818fb616e3fSDouglas Anderson * be 1 frame _before_ when we want to be scheduled. If we're 1 frame
1819fb616e3fSDouglas Anderson * past it just means schedule ASAP.
1820fb616e3fSDouglas Anderson *
1821fb616e3fSDouglas Anderson * It's _not_ OK, however, if we're more than one frame past.
1822fb616e3fSDouglas Anderson */
1823fb616e3fSDouglas Anderson if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1824fb616e3fSDouglas Anderson /*
1825fb616e3fSDouglas Anderson * OOPS, we missed. That's actually pretty bad since
1826fb616e3fSDouglas Anderson * the hub will be unhappy; try ASAP I guess.
1827fb616e3fSDouglas Anderson */
1828fb616e3fSDouglas Anderson missed = dwc2_frame_num_dec(prev_frame_number,
1829fb616e3fSDouglas Anderson qh->next_active_frame);
1830ced9eee1SDouglas Anderson qh->next_active_frame = frame_number;
1831197ba5f4SPaul Zimmerman }
183274fc4a75SDouglas Anderson
1833fb616e3fSDouglas Anderson return missed;
1834fb616e3fSDouglas Anderson }
1835fb616e3fSDouglas Anderson
1836fb616e3fSDouglas Anderson /**
1837fb616e3fSDouglas Anderson * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1838fb616e3fSDouglas Anderson *
1839fb616e3fSDouglas Anderson * This is called for setting next_active_frame for a periodic transfer for
1840fb616e3fSDouglas Anderson * all cases other than midway through a periodic split. This will also update
1841fb616e3fSDouglas Anderson * start_active_frame.
1842fb616e3fSDouglas Anderson *
1843fb616e3fSDouglas Anderson * Since we _always_ keep start_active_frame as the start of the previous
1844fb616e3fSDouglas Anderson * transfer this is normally pretty easy: we just add our interval to
1845fb616e3fSDouglas Anderson * start_active_frame and we've got our answer.
1846fb616e3fSDouglas Anderson *
1847fb616e3fSDouglas Anderson * The tricks come into play if we miss. In that case we'll look for the next
1848fb616e3fSDouglas Anderson * slot we can fit into.
1849fb616e3fSDouglas Anderson *
1850fb616e3fSDouglas Anderson * @hsotg: The HCD state structure
1851fb616e3fSDouglas Anderson * @qh: QH for the periodic transfer.
1852fb616e3fSDouglas Anderson * @frame_number: The current frame number.
1853fb616e3fSDouglas Anderson *
1854fb616e3fSDouglas Anderson * Return: number missed by (or 0 if we didn't miss).
1855fb616e3fSDouglas Anderson */
dwc2_next_periodic_start(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,u16 frame_number)1856fb616e3fSDouglas Anderson static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1857fb616e3fSDouglas Anderson struct dwc2_qh *qh, u16 frame_number)
1858fb616e3fSDouglas Anderson {
1859fb616e3fSDouglas Anderson int missed = 0;
1860fb616e3fSDouglas Anderson u16 interval = qh->host_interval;
1861fb616e3fSDouglas Anderson u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1862fb616e3fSDouglas Anderson
1863fb616e3fSDouglas Anderson qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1864fb616e3fSDouglas Anderson interval);
1865fb616e3fSDouglas Anderson
1866fb616e3fSDouglas Anderson /*
1867fb616e3fSDouglas Anderson * The dwc2_frame_num_gt() function used below won't work terribly well
1868fb616e3fSDouglas Anderson * with if we just incremented by a really large intervals since the
1869fb616e3fSDouglas Anderson * frame counter only goes to 0x3fff. It's terribly unlikely that we
1870fb616e3fSDouglas Anderson * will have missed in this case anyway. Just go to exit. If we want
1871fb616e3fSDouglas Anderson * to try to do better we'll need to keep track of a bigger counter
1872fb616e3fSDouglas Anderson * somewhere in the driver and handle overflows.
1873fb616e3fSDouglas Anderson */
1874fb616e3fSDouglas Anderson if (interval >= 0x1000)
1875fb616e3fSDouglas Anderson goto exit;
1876fb616e3fSDouglas Anderson
1877fb616e3fSDouglas Anderson /*
1878fb616e3fSDouglas Anderson * Test for misses, which is when it's too late to schedule.
1879fb616e3fSDouglas Anderson *
1880fb616e3fSDouglas Anderson * A few things to note:
1881fb616e3fSDouglas Anderson * - We compare against prev_frame_number since start_active_frame
1882fb616e3fSDouglas Anderson * and next_active_frame are always 1 frame before we want things
1883fb616e3fSDouglas Anderson * to be active and we assume we can still get scheduled in the
1884fb616e3fSDouglas Anderson * current frame number.
18859cf1a601SDouglas Anderson * - It's possible for start_active_frame (now incremented) to be
18869cf1a601SDouglas Anderson * next_active_frame if we got an EO MISS (even_odd miss) which
18879cf1a601SDouglas Anderson * basically means that we detected there wasn't enough time for
18889cf1a601SDouglas Anderson * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
18899cf1a601SDouglas Anderson * at the last second. We want to make sure we don't schedule
18909cf1a601SDouglas Anderson * another transfer for the same frame. My test webcam doesn't seem
18919cf1a601SDouglas Anderson * terribly upset by missing a transfer but really doesn't like when
18929cf1a601SDouglas Anderson * we do two transfers in the same frame.
1893fb616e3fSDouglas Anderson * - Some misses are expected. Specifically, in order to work
1894fb616e3fSDouglas Anderson * perfectly dwc2 really needs quite spectacular interrupt latency
1895fb616e3fSDouglas Anderson * requirements. It needs to be able to handle its interrupts
1896fb616e3fSDouglas Anderson * completely within 125 us of them being asserted. That not only
1897fb616e3fSDouglas Anderson * means that the dwc2 interrupt handler needs to be fast but it
1898fb616e3fSDouglas Anderson * means that nothing else in the system has to block dwc2 for a long
1899fb616e3fSDouglas Anderson * time. We can help with the dwc2 parts of this, but it's hard to
1900fb616e3fSDouglas Anderson * guarantee that a system will have interrupt latency < 125 us, so
1901fb616e3fSDouglas Anderson * we have to be robust to some misses.
1902fb616e3fSDouglas Anderson */
19039cf1a601SDouglas Anderson if (qh->start_active_frame == qh->next_active_frame ||
19049cf1a601SDouglas Anderson dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1905fb616e3fSDouglas Anderson u16 ideal_start = qh->start_active_frame;
19069f9f09b0SDouglas Anderson int periods_in_map;
1907fb616e3fSDouglas Anderson
19089f9f09b0SDouglas Anderson /*
19099f9f09b0SDouglas Anderson * Adjust interval as per gcd with map size.
19109f9f09b0SDouglas Anderson * See pmap_schedule() for more details here.
19119f9f09b0SDouglas Anderson */
19129f9f09b0SDouglas Anderson if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
19139f9f09b0SDouglas Anderson periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
19149f9f09b0SDouglas Anderson else
19159f9f09b0SDouglas Anderson periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
19169f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map);
1917fb616e3fSDouglas Anderson
1918fb616e3fSDouglas Anderson do {
1919fb616e3fSDouglas Anderson qh->start_active_frame = dwc2_frame_num_inc(
1920fb616e3fSDouglas Anderson qh->start_active_frame, interval);
1921fb616e3fSDouglas Anderson } while (dwc2_frame_num_gt(prev_frame_number,
1922fb616e3fSDouglas Anderson qh->start_active_frame));
1923fb616e3fSDouglas Anderson
1924fb616e3fSDouglas Anderson missed = dwc2_frame_num_dec(qh->start_active_frame,
1925fb616e3fSDouglas Anderson ideal_start);
1926fb616e3fSDouglas Anderson }
1927fb616e3fSDouglas Anderson
1928fb616e3fSDouglas Anderson exit:
1929fb616e3fSDouglas Anderson qh->next_active_frame = qh->start_active_frame;
1930fb616e3fSDouglas Anderson
1931fb616e3fSDouglas Anderson return missed;
1932197ba5f4SPaul Zimmerman }
1933197ba5f4SPaul Zimmerman
1934197ba5f4SPaul Zimmerman /*
1935197ba5f4SPaul Zimmerman * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1936197ba5f4SPaul Zimmerman * non-periodic schedule. The QH is added to the inactive non-periodic
1937197ba5f4SPaul Zimmerman * schedule if any QTDs are still attached to the QH.
1938197ba5f4SPaul Zimmerman *
1939197ba5f4SPaul Zimmerman * For periodic QHs, the QH is removed from the periodic queued schedule. If
1940197ba5f4SPaul Zimmerman * there are any QTDs still attached to the QH, the QH is added to either the
1941197ba5f4SPaul Zimmerman * periodic inactive schedule or the periodic ready schedule and its next
1942197ba5f4SPaul Zimmerman * scheduled frame is calculated. The QH is placed in the ready schedule if
1943197ba5f4SPaul Zimmerman * the scheduled frame has been reached already. Otherwise it's placed in the
1944197ba5f4SPaul Zimmerman * inactive schedule. If there are no QTDs attached to the QH, the QH is
1945197ba5f4SPaul Zimmerman * completely removed from the periodic schedule.
1946197ba5f4SPaul Zimmerman */
dwc2_hcd_qh_deactivate(struct dwc2_hsotg * hsotg,struct dwc2_qh * qh,int sched_next_periodic_split)1947197ba5f4SPaul Zimmerman void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1948197ba5f4SPaul Zimmerman int sched_next_periodic_split)
1949197ba5f4SPaul Zimmerman {
1950fb616e3fSDouglas Anderson u16 old_frame = qh->next_active_frame;
1951197ba5f4SPaul Zimmerman u16 frame_number;
1952fb616e3fSDouglas Anderson int missed;
1953197ba5f4SPaul Zimmerman
1954197ba5f4SPaul Zimmerman if (dbg_qh(qh))
1955197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__);
1956197ba5f4SPaul Zimmerman
1957197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) {
1958197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh);
1959197ba5f4SPaul Zimmerman if (!list_empty(&qh->qtd_list))
196038d2b5fbSDouglas Anderson /* Add back to inactive/waiting non-periodic schedule */
1961197ba5f4SPaul Zimmerman dwc2_hcd_qh_add(hsotg, qh);
1962197ba5f4SPaul Zimmerman return;
1963197ba5f4SPaul Zimmerman }
1964197ba5f4SPaul Zimmerman
1965fb616e3fSDouglas Anderson /*
1966fb616e3fSDouglas Anderson * Use the real frame number rather than the cached value as of the
1967fb616e3fSDouglas Anderson * last SOF just to get us a little closer to reality. Note that
1968fb616e3fSDouglas Anderson * means we don't actually know if we've already handled the SOF
1969fb616e3fSDouglas Anderson * interrupt for this frame.
1970fb616e3fSDouglas Anderson */
1971197ba5f4SPaul Zimmerman frame_number = dwc2_hcd_get_frame_number(hsotg);
1972197ba5f4SPaul Zimmerman
1973fb616e3fSDouglas Anderson if (sched_next_periodic_split)
1974fb616e3fSDouglas Anderson missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
1975fb616e3fSDouglas Anderson else
1976fb616e3fSDouglas Anderson missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
1977fb616e3fSDouglas Anderson
1978fb616e3fSDouglas Anderson dwc2_sch_vdbg(hsotg,
1979fb616e3fSDouglas Anderson "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
1980fb616e3fSDouglas Anderson qh, sched_next_periodic_split, frame_number, old_frame,
1981fb616e3fSDouglas Anderson qh->next_active_frame,
1982fb616e3fSDouglas Anderson dwc2_frame_num_dec(qh->next_active_frame, old_frame),
1983fb616e3fSDouglas Anderson missed, missed ? "MISS" : "");
1984197ba5f4SPaul Zimmerman
1985197ba5f4SPaul Zimmerman if (list_empty(&qh->qtd_list)) {
1986197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh);
1987197ba5f4SPaul Zimmerman return;
1988197ba5f4SPaul Zimmerman }
1989fb616e3fSDouglas Anderson
1990197ba5f4SPaul Zimmerman /*
1991197ba5f4SPaul Zimmerman * Remove from periodic_sched_queued and move to
1992197ba5f4SPaul Zimmerman * appropriate queue
1993fb616e3fSDouglas Anderson *
1994fb616e3fSDouglas Anderson * Note: we purposely use the frame_number from the "hsotg" structure
1995fb616e3fSDouglas Anderson * since we know SOF interrupt will handle future frames.
1996197ba5f4SPaul Zimmerman */
1997fb616e3fSDouglas Anderson if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
199894ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry,
199994ef7aeeSDouglas Anderson &hsotg->periodic_sched_ready);
2000197ba5f4SPaul Zimmerman else
200194ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry,
200294ef7aeeSDouglas Anderson &hsotg->periodic_sched_inactive);
2003197ba5f4SPaul Zimmerman }
2004197ba5f4SPaul Zimmerman
2005197ba5f4SPaul Zimmerman /**
2006197ba5f4SPaul Zimmerman * dwc2_hcd_qtd_init() - Initializes a QTD structure
2007197ba5f4SPaul Zimmerman *
2008197ba5f4SPaul Zimmerman * @qtd: The QTD to initialize
2009197ba5f4SPaul Zimmerman * @urb: The associated URB
2010197ba5f4SPaul Zimmerman */
dwc2_hcd_qtd_init(struct dwc2_qtd * qtd,struct dwc2_hcd_urb * urb)2011197ba5f4SPaul Zimmerman void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2012197ba5f4SPaul Zimmerman {
2013197ba5f4SPaul Zimmerman qtd->urb = urb;
2014197ba5f4SPaul Zimmerman if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
2015197ba5f4SPaul Zimmerman USB_ENDPOINT_XFER_CONTROL) {
2016197ba5f4SPaul Zimmerman /*
2017197ba5f4SPaul Zimmerman * The only time the QTD data toggle is used is on the data
2018197ba5f4SPaul Zimmerman * phase of control transfers. This phase always starts with
2019197ba5f4SPaul Zimmerman * DATA1.
2020197ba5f4SPaul Zimmerman */
2021197ba5f4SPaul Zimmerman qtd->data_toggle = DWC2_HC_PID_DATA1;
2022197ba5f4SPaul Zimmerman qtd->control_phase = DWC2_CONTROL_SETUP;
2023197ba5f4SPaul Zimmerman }
2024197ba5f4SPaul Zimmerman
2025197ba5f4SPaul Zimmerman /* Start split */
2026197ba5f4SPaul Zimmerman qtd->complete_split = 0;
2027197ba5f4SPaul Zimmerman qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
2028197ba5f4SPaul Zimmerman qtd->isoc_split_offset = 0;
2029197ba5f4SPaul Zimmerman qtd->in_process = 0;
2030197ba5f4SPaul Zimmerman
2031197ba5f4SPaul Zimmerman /* Store the qtd ptr in the urb to reference the QTD */
2032197ba5f4SPaul Zimmerman urb->qtd = qtd;
2033197ba5f4SPaul Zimmerman }
2034197ba5f4SPaul Zimmerman
2035197ba5f4SPaul Zimmerman /**
2036197ba5f4SPaul Zimmerman * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
203733ad261aSGregory Herrero * Caller must hold driver lock.
2038197ba5f4SPaul Zimmerman *
2039197ba5f4SPaul Zimmerman * @hsotg: The DWC HCD structure
2040197ba5f4SPaul Zimmerman * @qtd: The QTD to add
2041b58e6ceeSMian Yousaf Kaukab * @qh: Queue head to add qtd to
2042197ba5f4SPaul Zimmerman *
2043197ba5f4SPaul Zimmerman * Return: 0 if successful, negative error code otherwise
2044197ba5f4SPaul Zimmerman *
2045b58e6ceeSMian Yousaf Kaukab * If the QH to which the QTD is added is not currently scheduled, it is placed
2046b58e6ceeSMian Yousaf Kaukab * into the proper schedule based on its EP type.
2047197ba5f4SPaul Zimmerman */
dwc2_hcd_qtd_add(struct dwc2_hsotg * hsotg,struct dwc2_qtd * qtd,struct dwc2_qh * qh)2048197ba5f4SPaul Zimmerman int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2049b58e6ceeSMian Yousaf Kaukab struct dwc2_qh *qh)
2050197ba5f4SPaul Zimmerman {
2051197ba5f4SPaul Zimmerman int retval;
2052197ba5f4SPaul Zimmerman
2053b58e6ceeSMian Yousaf Kaukab if (unlikely(!qh)) {
2054b58e6ceeSMian Yousaf Kaukab dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2055b58e6ceeSMian Yousaf Kaukab retval = -EINVAL;
2056b58e6ceeSMian Yousaf Kaukab goto fail;
2057197ba5f4SPaul Zimmerman }
2058197ba5f4SPaul Zimmerman
2059b58e6ceeSMian Yousaf Kaukab retval = dwc2_hcd_qh_add(hsotg, qh);
2060197ba5f4SPaul Zimmerman if (retval)
2061197ba5f4SPaul Zimmerman goto fail;
2062197ba5f4SPaul Zimmerman
2063b58e6ceeSMian Yousaf Kaukab qtd->qh = qh;
2064b58e6ceeSMian Yousaf Kaukab list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2065197ba5f4SPaul Zimmerman
2066197ba5f4SPaul Zimmerman return 0;
2067197ba5f4SPaul Zimmerman fail:
2068197ba5f4SPaul Zimmerman return retval;
2069197ba5f4SPaul Zimmerman }
2070