15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2197ba5f4SPaul Zimmerman /* 3197ba5f4SPaul Zimmerman * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 4197ba5f4SPaul Zimmerman * 5197ba5f4SPaul Zimmerman * Copyright (C) 2004-2013 Synopsys, Inc. 6197ba5f4SPaul Zimmerman * 7197ba5f4SPaul Zimmerman * Redistribution and use in source and binary forms, with or without 8197ba5f4SPaul Zimmerman * modification, are permitted provided that the following conditions 9197ba5f4SPaul Zimmerman * are met: 10197ba5f4SPaul Zimmerman * 1. Redistributions of source code must retain the above copyright 11197ba5f4SPaul Zimmerman * notice, this list of conditions, and the following disclaimer, 12197ba5f4SPaul Zimmerman * without modification. 13197ba5f4SPaul Zimmerman * 2. Redistributions in binary form must reproduce the above copyright 14197ba5f4SPaul Zimmerman * notice, this list of conditions and the following disclaimer in the 15197ba5f4SPaul Zimmerman * documentation and/or other materials provided with the distribution. 16197ba5f4SPaul Zimmerman * 3. The names of the above-listed copyright holders may not be used 17197ba5f4SPaul Zimmerman * to endorse or promote products derived from this software without 18197ba5f4SPaul Zimmerman * specific prior written permission. 19197ba5f4SPaul Zimmerman * 20197ba5f4SPaul Zimmerman * ALTERNATIVELY, this software may be distributed under the terms of the 21197ba5f4SPaul Zimmerman * GNU General Public License ("GPL") as published by the Free Software 22197ba5f4SPaul Zimmerman * Foundation; either version 2 of the License, or (at your option) any 23197ba5f4SPaul Zimmerman * later version. 24197ba5f4SPaul Zimmerman * 25197ba5f4SPaul Zimmerman * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26197ba5f4SPaul Zimmerman * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27197ba5f4SPaul Zimmerman * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28197ba5f4SPaul Zimmerman * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29197ba5f4SPaul Zimmerman * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30197ba5f4SPaul Zimmerman * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31197ba5f4SPaul Zimmerman * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32197ba5f4SPaul Zimmerman * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33197ba5f4SPaul Zimmerman * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34197ba5f4SPaul Zimmerman * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35197ba5f4SPaul Zimmerman * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36197ba5f4SPaul Zimmerman */ 37197ba5f4SPaul Zimmerman 38197ba5f4SPaul Zimmerman /* 39197ba5f4SPaul Zimmerman * This file contains the functions to manage Queue Heads and Queue 40197ba5f4SPaul Zimmerman * Transfer Descriptors for Host mode 41197ba5f4SPaul Zimmerman */ 42fb616e3fSDouglas Anderson #include <linux/gcd.h> 43197ba5f4SPaul Zimmerman #include <linux/kernel.h> 44197ba5f4SPaul Zimmerman #include <linux/module.h> 45197ba5f4SPaul Zimmerman #include <linux/spinlock.h> 46197ba5f4SPaul Zimmerman #include <linux/interrupt.h> 47197ba5f4SPaul Zimmerman #include <linux/dma-mapping.h> 48197ba5f4SPaul Zimmerman #include <linux/io.h> 49197ba5f4SPaul Zimmerman #include <linux/slab.h> 50197ba5f4SPaul Zimmerman #include <linux/usb.h> 51197ba5f4SPaul Zimmerman 52197ba5f4SPaul Zimmerman #include <linux/usb/hcd.h> 53197ba5f4SPaul Zimmerman #include <linux/usb/ch11.h> 54197ba5f4SPaul Zimmerman 55197ba5f4SPaul Zimmerman #include "core.h" 56197ba5f4SPaul Zimmerman #include "hcd.h" 57197ba5f4SPaul Zimmerman 5817dd5b64SDouglas Anderson /* Wait this long before releasing periodic reservation */ 5917dd5b64SDouglas Anderson #define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5)) 6017dd5b64SDouglas Anderson 6138d2b5fbSDouglas Anderson /* If we get a NAK, wait this long before retrying */ 62*310780e8SNathan Chancellor #define DWC2_RETRY_WAIT_DELAY (1 * NSEC_PER_MSEC) 6338d2b5fbSDouglas Anderson 6417dd5b64SDouglas Anderson /** 65b951c6c7SDouglas Anderson * dwc2_periodic_channel_available() - Checks that a channel is available for a 66b951c6c7SDouglas Anderson * periodic transfer 67b951c6c7SDouglas Anderson * 68b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 69b951c6c7SDouglas Anderson * 70b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise 71b951c6c7SDouglas Anderson */ 72b951c6c7SDouglas Anderson static int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 73b951c6c7SDouglas Anderson { 74b951c6c7SDouglas Anderson /* 75b951c6c7SDouglas Anderson * Currently assuming that there is a dedicated host channel for 76b951c6c7SDouglas Anderson * each periodic transaction plus at least one host channel for 77b951c6c7SDouglas Anderson * non-periodic transactions 78b951c6c7SDouglas Anderson */ 79b951c6c7SDouglas Anderson int status; 80b951c6c7SDouglas Anderson int num_channels; 81b951c6c7SDouglas Anderson 82bea8e86cSJohn Youn num_channels = hsotg->params.host_channels; 83ab283202SJohn Youn if ((hsotg->periodic_channels + hsotg->non_periodic_channels < 84ab283202SJohn Youn num_channels) && (hsotg->periodic_channels < num_channels - 1)) { 85b951c6c7SDouglas Anderson status = 0; 86b951c6c7SDouglas Anderson } else { 87b951c6c7SDouglas Anderson dev_dbg(hsotg->dev, 889da51974SJohn Youn "%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", 899da51974SJohn Youn __func__, num_channels, 90b951c6c7SDouglas Anderson hsotg->periodic_channels, hsotg->non_periodic_channels); 91b951c6c7SDouglas Anderson status = -ENOSPC; 92b951c6c7SDouglas Anderson } 93b951c6c7SDouglas Anderson 94b951c6c7SDouglas Anderson return status; 95b951c6c7SDouglas Anderson } 96b951c6c7SDouglas Anderson 97b951c6c7SDouglas Anderson /** 98b951c6c7SDouglas Anderson * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 99b951c6c7SDouglas Anderson * for the specified QH in the periodic schedule 100b951c6c7SDouglas Anderson * 101b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 102b951c6c7SDouglas Anderson * @qh: QH containing periodic bandwidth required 103b951c6c7SDouglas Anderson * 104b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise 105b951c6c7SDouglas Anderson * 106b951c6c7SDouglas Anderson * For simplicity, this calculation assumes that all the transfers in the 107b951c6c7SDouglas Anderson * periodic schedule may occur in the same (micro)frame 108b951c6c7SDouglas Anderson */ 109b951c6c7SDouglas Anderson static int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 110b951c6c7SDouglas Anderson struct dwc2_qh *qh) 111b951c6c7SDouglas Anderson { 112b951c6c7SDouglas Anderson int status; 113b951c6c7SDouglas Anderson s16 max_claimed_usecs; 114b951c6c7SDouglas Anderson 115b951c6c7SDouglas Anderson status = 0; 116b951c6c7SDouglas Anderson 117b951c6c7SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 118b951c6c7SDouglas Anderson /* 119b951c6c7SDouglas Anderson * High speed mode 120b951c6c7SDouglas Anderson * Max periodic usecs is 80% x 125 usec = 100 usec 121b951c6c7SDouglas Anderson */ 122b951c6c7SDouglas Anderson max_claimed_usecs = 100 - qh->host_us; 123b951c6c7SDouglas Anderson } else { 124b951c6c7SDouglas Anderson /* 125b951c6c7SDouglas Anderson * Full speed mode 126b951c6c7SDouglas Anderson * Max periodic usecs is 90% x 1000 usec = 900 usec 127b951c6c7SDouglas Anderson */ 128b951c6c7SDouglas Anderson max_claimed_usecs = 900 - qh->host_us; 129b951c6c7SDouglas Anderson } 130b951c6c7SDouglas Anderson 131b951c6c7SDouglas Anderson if (hsotg->periodic_usecs > max_claimed_usecs) { 132b951c6c7SDouglas Anderson dev_err(hsotg->dev, 133b951c6c7SDouglas Anderson "%s: already claimed usecs %d, required usecs %d\n", 134b951c6c7SDouglas Anderson __func__, hsotg->periodic_usecs, qh->host_us); 135b951c6c7SDouglas Anderson status = -ENOSPC; 136b951c6c7SDouglas Anderson } 137b951c6c7SDouglas Anderson 138b951c6c7SDouglas Anderson return status; 139b951c6c7SDouglas Anderson } 140b951c6c7SDouglas Anderson 141b951c6c7SDouglas Anderson /** 1429f9f09b0SDouglas Anderson * pmap_schedule() - Schedule time in a periodic bitmap (pmap). 1439f9f09b0SDouglas Anderson * 1449f9f09b0SDouglas Anderson * @map: The bitmap representing the schedule; will be updated 1459f9f09b0SDouglas Anderson * upon success. 1469f9f09b0SDouglas Anderson * @bits_per_period: The schedule represents several periods. This is how many 1479f9f09b0SDouglas Anderson * bits are in each period. It's assumed that the beginning 1489f9f09b0SDouglas Anderson * of the schedule will repeat after its end. 1499f9f09b0SDouglas Anderson * @periods_in_map: The number of periods in the schedule. 1509f9f09b0SDouglas Anderson * @num_bits: The number of bits we need per period we want to reserve 1519f9f09b0SDouglas Anderson * in this function call. 1529f9f09b0SDouglas Anderson * @interval: How often we need to be scheduled for the reservation this 1539f9f09b0SDouglas Anderson * time. 1 means every period. 2 means every other period. 1549f9f09b0SDouglas Anderson * ...you get the picture? 1559f9f09b0SDouglas Anderson * @start: The bit number to start at. Normally 0. Must be within 1569f9f09b0SDouglas Anderson * the interval or we return failure right away. 1579f9f09b0SDouglas Anderson * @only_one_period: Normally we'll allow picking a start anywhere within the 1589f9f09b0SDouglas Anderson * first interval, since we can still make all repetition 1599f9f09b0SDouglas Anderson * requirements by doing that. However, if you pass true 1609f9f09b0SDouglas Anderson * here then we'll return failure if we can't fit within 1619f9f09b0SDouglas Anderson * the period that "start" is in. 1629f9f09b0SDouglas Anderson * 1639f9f09b0SDouglas Anderson * The idea here is that we want to schedule time for repeating events that all 1649f9f09b0SDouglas Anderson * want the same resource. The resource is divided into fixed-sized periods 1659f9f09b0SDouglas Anderson * and the events want to repeat every "interval" periods. The schedule 1669f9f09b0SDouglas Anderson * granularity is one bit. 1679f9f09b0SDouglas Anderson * 1689f9f09b0SDouglas Anderson * To keep things "simple", we'll represent our schedule with a bitmap that 1699f9f09b0SDouglas Anderson * contains a fixed number of periods. This gets rid of a lot of complexity 1709f9f09b0SDouglas Anderson * but does mean that we need to handle things specially (and non-ideally) if 1719f9f09b0SDouglas Anderson * the number of the periods in the schedule doesn't match well with the 1729f9f09b0SDouglas Anderson * intervals that we're trying to schedule. 1739f9f09b0SDouglas Anderson * 1749f9f09b0SDouglas Anderson * Here's an explanation of the scheme we'll implement, assuming 8 periods. 1759f9f09b0SDouglas Anderson * - If interval is 1, we need to take up space in each of the 8 1769f9f09b0SDouglas Anderson * periods we're scheduling. Easy. 1779f9f09b0SDouglas Anderson * - If interval is 2, we need to take up space in half of the 1789f9f09b0SDouglas Anderson * periods. Again, easy. 1799f9f09b0SDouglas Anderson * - If interval is 3, we actually need to fall back to interval 1. 1809f9f09b0SDouglas Anderson * Why? Because we might need time in any period. AKA for the 1819f9f09b0SDouglas Anderson * first 8 periods, we'll be in slot 0, 3, 6. Then we'll be 1829f9f09b0SDouglas Anderson * in slot 1, 4, 7. Then we'll be in 2, 5. Then we'll be back to 1839f9f09b0SDouglas Anderson * 0, 3, and 6. Since we could be in any frame we need to reserve 1849f9f09b0SDouglas Anderson * for all of them. Sucks, but that's what you gotta do. Note that 1859f9f09b0SDouglas Anderson * if we were instead scheduling 8 * 3 = 24 we'd do much better, but 1869f9f09b0SDouglas Anderson * then we need more memory and time to do scheduling. 1879f9f09b0SDouglas Anderson * - If interval is 4, easy. 1889f9f09b0SDouglas Anderson * - If interval is 5, we again need interval 1. The schedule will be 1899f9f09b0SDouglas Anderson * 0, 5, 2, 7, 4, 1, 6, 3, 0 1909f9f09b0SDouglas Anderson * - If interval is 6, we need interval 2. 0, 6, 4, 2. 1919f9f09b0SDouglas Anderson * - If interval is 7, we need interval 1. 1929f9f09b0SDouglas Anderson * - If interval is 8, we need interval 8. 1939f9f09b0SDouglas Anderson * 1949f9f09b0SDouglas Anderson * If you do the math, you'll see that we need to pretend that interval is 1959f9f09b0SDouglas Anderson * equal to the greatest_common_divisor(interval, periods_in_map). 1969f9f09b0SDouglas Anderson * 1979f9f09b0SDouglas Anderson * Note that at the moment this function tends to front-pack the schedule. 1989f9f09b0SDouglas Anderson * In some cases that's really non-ideal (it's hard to schedule things that 1999f9f09b0SDouglas Anderson * need to repeat every period). In other cases it's perfect (you can easily 2009f9f09b0SDouglas Anderson * schedule bigger, less often repeating things). 2019f9f09b0SDouglas Anderson * 2029f9f09b0SDouglas Anderson * Here's the algorithm in action (8 periods, 5 bits per period): 2039f9f09b0SDouglas Anderson * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 2049f9f09b0SDouglas Anderson * |*****| ***|*****| ***|*****| ***|*****| ***| OK 3 bits, intv 3 at 2 2059f9f09b0SDouglas Anderson * |*****|* ***|*****| ***|*****|* ***|*****| ***| OK 1 bits, intv 4 at 5 2069f9f09b0SDouglas Anderson * |** |* |** | |** |* |** | | Remv 3 bits, intv 3 at 2 2079f9f09b0SDouglas Anderson * |*** |* |*** | |*** |* |*** | | OK 1 bits, intv 6 at 2 2089f9f09b0SDouglas Anderson * |**** |* * |**** | * |**** |* * |**** | * | OK 1 bits, intv 1 at 3 2099f9f09b0SDouglas Anderson * |**** |**** |**** | *** |**** |**** |**** | *** | OK 2 bits, intv 2 at 6 2109f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 1 at 4 2119f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1 2129f9f09b0SDouglas Anderson * | ***|*****| ***| ****| ***|*****| ***| ****| Remv 2 bits, intv 2 at 0 2139f9f09b0SDouglas Anderson * | ***| ****| ***| ****| ***| ****| ***| ****| Remv 1 bits, intv 4 at 5 2149f9f09b0SDouglas Anderson * | **| ****| **| ****| **| ****| **| ****| Remv 1 bits, intv 6 at 2 2159f9f09b0SDouglas Anderson * | *| ** *| *| ** *| *| ** *| *| ** *| Remv 1 bits, intv 1 at 3 2169f9f09b0SDouglas Anderson * | *| *| *| *| *| *| *| *| Remv 2 bits, intv 2 at 6 2179f9f09b0SDouglas Anderson * | | | | | | | | | Remv 1 bits, intv 1 at 4 2189f9f09b0SDouglas Anderson * |** | |** | |** | |** | | OK 2 bits, intv 2 at 0 2199f9f09b0SDouglas Anderson * |*** | |** | |*** | |** | | OK 1 bits, intv 4 at 2 2209f9f09b0SDouglas Anderson * |*****| |** **| |*****| |** **| | OK 2 bits, intv 2 at 3 2219f9f09b0SDouglas Anderson * |*****|* |** **| |*****|* |** **| | OK 1 bits, intv 4 at 5 2229f9f09b0SDouglas Anderson * |*****|*** |** **| ** |*****|*** |** **| ** | OK 2 bits, intv 2 at 6 2239f9f09b0SDouglas Anderson * |*****|*****|** **| ****|*****|*****|** **| ****| OK 2 bits, intv 2 at 8 2249f9f09b0SDouglas Anderson * |*****|*****|*****| ****|*****|*****|*****| ****| OK 1 bits, intv 4 at 12 2259f9f09b0SDouglas Anderson * 2269f9f09b0SDouglas Anderson * This function is pretty generic and could be easily abstracted if anything 2279f9f09b0SDouglas Anderson * needed similar scheduling. 2289f9f09b0SDouglas Anderson * 2299f9f09b0SDouglas Anderson * Returns either -ENOSPC or a >= 0 start bit which should be passed to the 2309f9f09b0SDouglas Anderson * unschedule routine. The map bitmap will be updated on a non-error result. 231b951c6c7SDouglas Anderson */ 2329f9f09b0SDouglas Anderson static int pmap_schedule(unsigned long *map, int bits_per_period, 2339f9f09b0SDouglas Anderson int periods_in_map, int num_bits, 2349f9f09b0SDouglas Anderson int interval, int start, bool only_one_period) 2359f9f09b0SDouglas Anderson { 2369f9f09b0SDouglas Anderson int interval_bits; 2379f9f09b0SDouglas Anderson int to_reserve; 2389f9f09b0SDouglas Anderson int first_end; 2399f9f09b0SDouglas Anderson int i; 2409f9f09b0SDouglas Anderson 2419f9f09b0SDouglas Anderson if (num_bits > bits_per_period) 2429f9f09b0SDouglas Anderson return -ENOSPC; 2439f9f09b0SDouglas Anderson 2449f9f09b0SDouglas Anderson /* Adjust interval as per description */ 2459f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map); 2469f9f09b0SDouglas Anderson 2479f9f09b0SDouglas Anderson interval_bits = bits_per_period * interval; 2489f9f09b0SDouglas Anderson to_reserve = periods_in_map / interval; 2499f9f09b0SDouglas Anderson 2509f9f09b0SDouglas Anderson /* If start has gotten us past interval then we can't schedule */ 2519f9f09b0SDouglas Anderson if (start >= interval_bits) 2529f9f09b0SDouglas Anderson return -ENOSPC; 2539f9f09b0SDouglas Anderson 2549f9f09b0SDouglas Anderson if (only_one_period) 2559f9f09b0SDouglas Anderson /* Must fit within same period as start; end at begin of next */ 2569f9f09b0SDouglas Anderson first_end = (start / bits_per_period + 1) * bits_per_period; 2579f9f09b0SDouglas Anderson else 2589f9f09b0SDouglas Anderson /* Can fit anywhere in the first interval */ 2599f9f09b0SDouglas Anderson first_end = interval_bits; 2609f9f09b0SDouglas Anderson 2619f9f09b0SDouglas Anderson /* 2629f9f09b0SDouglas Anderson * We'll try to pick the first repetition, then see if that time 2639f9f09b0SDouglas Anderson * is free for each of the subsequent repetitions. If it's not 2649f9f09b0SDouglas Anderson * we'll adjust the start time for the next search of the first 2659f9f09b0SDouglas Anderson * repetition. 2669f9f09b0SDouglas Anderson */ 2679f9f09b0SDouglas Anderson while (start + num_bits <= first_end) { 2689f9f09b0SDouglas Anderson int end; 2699f9f09b0SDouglas Anderson 2709f9f09b0SDouglas Anderson /* Need to stay within this period */ 2719f9f09b0SDouglas Anderson end = (start / bits_per_period + 1) * bits_per_period; 2729f9f09b0SDouglas Anderson 2739f9f09b0SDouglas Anderson /* Look for num_bits us in this microframe starting at start */ 2749f9f09b0SDouglas Anderson start = bitmap_find_next_zero_area(map, end, start, num_bits, 2759f9f09b0SDouglas Anderson 0); 2769f9f09b0SDouglas Anderson 2779f9f09b0SDouglas Anderson /* 2789f9f09b0SDouglas Anderson * We should get start >= end if we fail. We might be 2799f9f09b0SDouglas Anderson * able to check the next microframe depending on the 2809f9f09b0SDouglas Anderson * interval, so continue on (start already updated). 2819f9f09b0SDouglas Anderson */ 2829f9f09b0SDouglas Anderson if (start >= end) { 2839f9f09b0SDouglas Anderson start = end; 2849f9f09b0SDouglas Anderson continue; 2859f9f09b0SDouglas Anderson } 2869f9f09b0SDouglas Anderson 2879f9f09b0SDouglas Anderson /* At this point we have a valid point for first one */ 2889f9f09b0SDouglas Anderson for (i = 1; i < to_reserve; i++) { 2899f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i; 2909f9f09b0SDouglas Anderson int ith_end = end + interval_bits * i; 2919f9f09b0SDouglas Anderson int ret; 2929f9f09b0SDouglas Anderson 2939f9f09b0SDouglas Anderson /* Use this as a dumb "check if bits are 0" */ 2949f9f09b0SDouglas Anderson ret = bitmap_find_next_zero_area( 2959f9f09b0SDouglas Anderson map, ith_start + num_bits, ith_start, num_bits, 2969f9f09b0SDouglas Anderson 0); 2979f9f09b0SDouglas Anderson 2989f9f09b0SDouglas Anderson /* We got the right place, continue checking */ 2999f9f09b0SDouglas Anderson if (ret == ith_start) 3009f9f09b0SDouglas Anderson continue; 3019f9f09b0SDouglas Anderson 3029f9f09b0SDouglas Anderson /* Move start up for next time and exit for loop */ 3039f9f09b0SDouglas Anderson ith_start = bitmap_find_next_zero_area( 3049f9f09b0SDouglas Anderson map, ith_end, ith_start, num_bits, 0); 3059f9f09b0SDouglas Anderson if (ith_start >= ith_end) 3069f9f09b0SDouglas Anderson /* Need a while new period next time */ 3079f9f09b0SDouglas Anderson start = end; 3089f9f09b0SDouglas Anderson else 3099f9f09b0SDouglas Anderson start = ith_start - interval_bits * i; 3109f9f09b0SDouglas Anderson break; 3119f9f09b0SDouglas Anderson } 3129f9f09b0SDouglas Anderson 3139f9f09b0SDouglas Anderson /* If didn't exit the for loop with a break, we have success */ 3149f9f09b0SDouglas Anderson if (i == to_reserve) 3159f9f09b0SDouglas Anderson break; 3169f9f09b0SDouglas Anderson } 3179f9f09b0SDouglas Anderson 3189f9f09b0SDouglas Anderson if (start + num_bits > first_end) 3199f9f09b0SDouglas Anderson return -ENOSPC; 3209f9f09b0SDouglas Anderson 3219f9f09b0SDouglas Anderson for (i = 0; i < to_reserve; i++) { 3229f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i; 3239f9f09b0SDouglas Anderson 3249f9f09b0SDouglas Anderson bitmap_set(map, ith_start, num_bits); 3259f9f09b0SDouglas Anderson } 3269f9f09b0SDouglas Anderson 3279f9f09b0SDouglas Anderson return start; 3289f9f09b0SDouglas Anderson } 3299f9f09b0SDouglas Anderson 3309f9f09b0SDouglas Anderson /** 3319f9f09b0SDouglas Anderson * pmap_unschedule() - Undo work done by pmap_schedule() 3329f9f09b0SDouglas Anderson * 3339f9f09b0SDouglas Anderson * @map: See pmap_schedule(). 3349f9f09b0SDouglas Anderson * @bits_per_period: See pmap_schedule(). 3359f9f09b0SDouglas Anderson * @periods_in_map: See pmap_schedule(). 3369f9f09b0SDouglas Anderson * @num_bits: The number of bits that was passed to schedule. 3379f9f09b0SDouglas Anderson * @interval: The interval that was passed to schedule. 3389f9f09b0SDouglas Anderson * @start: The return value from pmap_schedule(). 3399f9f09b0SDouglas Anderson */ 3409f9f09b0SDouglas Anderson static void pmap_unschedule(unsigned long *map, int bits_per_period, 3419f9f09b0SDouglas Anderson int periods_in_map, int num_bits, 3429f9f09b0SDouglas Anderson int interval, int start) 3439f9f09b0SDouglas Anderson { 3449f9f09b0SDouglas Anderson int interval_bits; 3459f9f09b0SDouglas Anderson int to_release; 3469f9f09b0SDouglas Anderson int i; 3479f9f09b0SDouglas Anderson 3489f9f09b0SDouglas Anderson /* Adjust interval as per description in pmap_schedule() */ 3499f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map); 3509f9f09b0SDouglas Anderson 3519f9f09b0SDouglas Anderson interval_bits = bits_per_period * interval; 3529f9f09b0SDouglas Anderson to_release = periods_in_map / interval; 3539f9f09b0SDouglas Anderson 3549f9f09b0SDouglas Anderson for (i = 0; i < to_release; i++) { 3559f9f09b0SDouglas Anderson int ith_start = start + interval_bits * i; 3569f9f09b0SDouglas Anderson 3579f9f09b0SDouglas Anderson bitmap_clear(map, ith_start, num_bits); 3589f9f09b0SDouglas Anderson } 3599f9f09b0SDouglas Anderson } 3609f9f09b0SDouglas Anderson 3613c220370SVardan Mikayelyan /** 3623c220370SVardan Mikayelyan * dwc2_get_ls_map() - Get the map used for the given qh 3633c220370SVardan Mikayelyan * 3643c220370SVardan Mikayelyan * @hsotg: The HCD state structure for the DWC OTG controller. 3653c220370SVardan Mikayelyan * @qh: QH for the periodic transfer. 3663c220370SVardan Mikayelyan * 3673c220370SVardan Mikayelyan * We'll always get the periodic map out of our TT. Note that even if we're 3683c220370SVardan Mikayelyan * running the host straight in low speed / full speed mode it appears as if 3693c220370SVardan Mikayelyan * a TT is allocated for us, so we'll use it. If that ever changes we can 3703c220370SVardan Mikayelyan * add logic here to get a map out of "hsotg" if !qh->do_split. 3713c220370SVardan Mikayelyan * 3723c220370SVardan Mikayelyan * Returns: the map or NULL if a map couldn't be found. 3733c220370SVardan Mikayelyan */ 3743c220370SVardan Mikayelyan static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg, 3753c220370SVardan Mikayelyan struct dwc2_qh *qh) 3763c220370SVardan Mikayelyan { 3773c220370SVardan Mikayelyan unsigned long *map; 3783c220370SVardan Mikayelyan 3793c220370SVardan Mikayelyan /* Don't expect to be missing a TT and be doing low speed scheduling */ 3803c220370SVardan Mikayelyan if (WARN_ON(!qh->dwc_tt)) 3813c220370SVardan Mikayelyan return NULL; 3823c220370SVardan Mikayelyan 3833c220370SVardan Mikayelyan /* Get the map and adjust if this is a multi_tt hub */ 3843c220370SVardan Mikayelyan map = qh->dwc_tt->periodic_bitmaps; 3853c220370SVardan Mikayelyan if (qh->dwc_tt->usb_tt->multi) 38687606759SWilliam Wu map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1); 3873c220370SVardan Mikayelyan 3883c220370SVardan Mikayelyan return map; 3893c220370SVardan Mikayelyan } 3903c220370SVardan Mikayelyan 3913c220370SVardan Mikayelyan #ifdef DWC2_PRINT_SCHEDULE 3929f9f09b0SDouglas Anderson /* 3939f9f09b0SDouglas Anderson * cat_printf() - A printf() + strcat() helper 3949f9f09b0SDouglas Anderson * 3959f9f09b0SDouglas Anderson * This is useful for concatenating a bunch of strings where each string is 3969f9f09b0SDouglas Anderson * constructed using printf. 3979f9f09b0SDouglas Anderson * 3989f9f09b0SDouglas Anderson * @buf: The destination buffer; will be updated to point after the printed 3999f9f09b0SDouglas Anderson * data. 4009f9f09b0SDouglas Anderson * @size: The number of bytes in the buffer (includes space for '\0'). 4019f9f09b0SDouglas Anderson * @fmt: The format for printf. 4029f9f09b0SDouglas Anderson * @...: The args for printf. 4039f9f09b0SDouglas Anderson */ 404e135ab74SNicolas Iooss static __printf(3, 4) 405e135ab74SNicolas Iooss void cat_printf(char **buf, size_t *size, const char *fmt, ...) 4069f9f09b0SDouglas Anderson { 4079f9f09b0SDouglas Anderson va_list args; 4089f9f09b0SDouglas Anderson int i; 4099f9f09b0SDouglas Anderson 4109f9f09b0SDouglas Anderson if (*size == 0) 4119f9f09b0SDouglas Anderson return; 4129f9f09b0SDouglas Anderson 4139f9f09b0SDouglas Anderson va_start(args, fmt); 4149f9f09b0SDouglas Anderson i = vsnprintf(*buf, *size, fmt, args); 4159f9f09b0SDouglas Anderson va_end(args); 4169f9f09b0SDouglas Anderson 4179f9f09b0SDouglas Anderson if (i >= *size) { 4189f9f09b0SDouglas Anderson (*buf)[*size - 1] = '\0'; 4199f9f09b0SDouglas Anderson *buf += *size; 4209f9f09b0SDouglas Anderson *size = 0; 4219f9f09b0SDouglas Anderson } else { 4229f9f09b0SDouglas Anderson *buf += i; 4239f9f09b0SDouglas Anderson *size -= i; 4249f9f09b0SDouglas Anderson } 4259f9f09b0SDouglas Anderson } 4269f9f09b0SDouglas Anderson 4279f9f09b0SDouglas Anderson /* 4289f9f09b0SDouglas Anderson * pmap_print() - Print the given periodic map 4299f9f09b0SDouglas Anderson * 4309f9f09b0SDouglas Anderson * Will attempt to print out the periodic schedule. 4319f9f09b0SDouglas Anderson * 4329f9f09b0SDouglas Anderson * @map: See pmap_schedule(). 4339f9f09b0SDouglas Anderson * @bits_per_period: See pmap_schedule(). 4349f9f09b0SDouglas Anderson * @periods_in_map: See pmap_schedule(). 4359f9f09b0SDouglas Anderson * @period_name: The name of 1 period, like "uFrame" 4369f9f09b0SDouglas Anderson * @units: The name of the units, like "us". 4379f9f09b0SDouglas Anderson * @print_fn: The function to call for printing. 4389f9f09b0SDouglas Anderson * @print_data: Opaque data to pass to the print function. 4399f9f09b0SDouglas Anderson */ 4409f9f09b0SDouglas Anderson static void pmap_print(unsigned long *map, int bits_per_period, 4419f9f09b0SDouglas Anderson int periods_in_map, const char *period_name, 4429f9f09b0SDouglas Anderson const char *units, 4439f9f09b0SDouglas Anderson void (*print_fn)(const char *str, void *data), 4449f9f09b0SDouglas Anderson void *print_data) 4459f9f09b0SDouglas Anderson { 4469f9f09b0SDouglas Anderson int period; 4479f9f09b0SDouglas Anderson 4489f9f09b0SDouglas Anderson for (period = 0; period < periods_in_map; period++) { 4499f9f09b0SDouglas Anderson char tmp[64]; 4509f9f09b0SDouglas Anderson char *buf = tmp; 4519f9f09b0SDouglas Anderson size_t buf_size = sizeof(tmp); 4529f9f09b0SDouglas Anderson int period_start = period * bits_per_period; 4539f9f09b0SDouglas Anderson int period_end = period_start + bits_per_period; 4549f9f09b0SDouglas Anderson int start = 0; 4559f9f09b0SDouglas Anderson int count = 0; 4569f9f09b0SDouglas Anderson bool printed = false; 4579f9f09b0SDouglas Anderson int i; 4589f9f09b0SDouglas Anderson 4599f9f09b0SDouglas Anderson for (i = period_start; i < period_end + 1; i++) { 4609f9f09b0SDouglas Anderson /* Handle case when ith bit is set */ 4619f9f09b0SDouglas Anderson if (i < period_end && 4629f9f09b0SDouglas Anderson bitmap_find_next_zero_area(map, i + 1, 4639f9f09b0SDouglas Anderson i, 1, 0) != i) { 4649f9f09b0SDouglas Anderson if (count == 0) 4659f9f09b0SDouglas Anderson start = i - period_start; 4669f9f09b0SDouglas Anderson count++; 4679f9f09b0SDouglas Anderson continue; 4689f9f09b0SDouglas Anderson } 4699f9f09b0SDouglas Anderson 4709f9f09b0SDouglas Anderson /* ith bit isn't set; don't care if count == 0 */ 4719f9f09b0SDouglas Anderson if (count == 0) 4729f9f09b0SDouglas Anderson continue; 4739f9f09b0SDouglas Anderson 4749f9f09b0SDouglas Anderson if (!printed) 4759f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, "%s %d: ", 4769f9f09b0SDouglas Anderson period_name, period); 4779f9f09b0SDouglas Anderson else 4789f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, ", "); 4799f9f09b0SDouglas Anderson printed = true; 4809f9f09b0SDouglas Anderson 4819f9f09b0SDouglas Anderson cat_printf(&buf, &buf_size, "%d %s -%3d %s", start, 4829f9f09b0SDouglas Anderson units, start + count - 1, units); 4839f9f09b0SDouglas Anderson count = 0; 4849f9f09b0SDouglas Anderson } 4859f9f09b0SDouglas Anderson 4869f9f09b0SDouglas Anderson if (printed) 4879f9f09b0SDouglas Anderson print_fn(tmp, print_data); 4889f9f09b0SDouglas Anderson } 4899f9f09b0SDouglas Anderson } 4909f9f09b0SDouglas Anderson 4919f9f09b0SDouglas Anderson struct dwc2_qh_print_data { 4929f9f09b0SDouglas Anderson struct dwc2_hsotg *hsotg; 4939f9f09b0SDouglas Anderson struct dwc2_qh *qh; 494b951c6c7SDouglas Anderson }; 495b951c6c7SDouglas Anderson 4969f9f09b0SDouglas Anderson /** 4979f9f09b0SDouglas Anderson * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print() 4989f9f09b0SDouglas Anderson * 4999f9f09b0SDouglas Anderson * @str: The string to print 5009f9f09b0SDouglas Anderson * @data: A pointer to a struct dwc2_qh_print_data 5019f9f09b0SDouglas Anderson */ 5029f9f09b0SDouglas Anderson static void dwc2_qh_print(const char *str, void *data) 503b951c6c7SDouglas Anderson { 5049f9f09b0SDouglas Anderson struct dwc2_qh_print_data *print_data = data; 5059f9f09b0SDouglas Anderson 5069f9f09b0SDouglas Anderson dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str); 5079f9f09b0SDouglas Anderson } 5089f9f09b0SDouglas Anderson 5099f9f09b0SDouglas Anderson /** 5109f9f09b0SDouglas Anderson * dwc2_qh_schedule_print() - Print the periodic schedule 5119f9f09b0SDouglas Anderson * 5129f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 5139f9f09b0SDouglas Anderson * @qh: QH to print. 5149f9f09b0SDouglas Anderson */ 5159f9f09b0SDouglas Anderson static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 5169f9f09b0SDouglas Anderson struct dwc2_qh *qh) 5179f9f09b0SDouglas Anderson { 5189f9f09b0SDouglas Anderson struct dwc2_qh_print_data print_data = { hsotg, qh }; 519b951c6c7SDouglas Anderson int i; 520b951c6c7SDouglas Anderson 5219f9f09b0SDouglas Anderson /* 5229f9f09b0SDouglas Anderson * The printing functions are quite slow and inefficient. 5239f9f09b0SDouglas Anderson * If we don't have tracing turned on, don't run unless the special 5249f9f09b0SDouglas Anderson * define is turned on. 5259f9f09b0SDouglas Anderson */ 5269f9f09b0SDouglas Anderson 5279f9f09b0SDouglas Anderson if (qh->schedule_low_speed) { 5289f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh); 5299f9f09b0SDouglas Anderson 5309f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us", 5319f9f09b0SDouglas Anderson qh, qh->device_us, 5329f9f09b0SDouglas Anderson DWC2_ROUND_US_TO_SLICE(qh->device_us), 5339f9f09b0SDouglas Anderson DWC2_US_PER_SLICE * qh->ls_start_schedule_slice); 5349f9f09b0SDouglas Anderson 5359f9f09b0SDouglas Anderson if (map) { 5369f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, 5379f9f09b0SDouglas Anderson "QH=%p Whole low/full speed map %p now:\n", 5389f9f09b0SDouglas Anderson qh, map); 5399f9f09b0SDouglas Anderson pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 5409f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices", 5419f9f09b0SDouglas Anderson dwc2_qh_print, &print_data); 5429f9f09b0SDouglas Anderson } 543b951c6c7SDouglas Anderson } 544b951c6c7SDouglas Anderson 5459f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++) { 5469f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i; 5479f9f09b0SDouglas Anderson int uframe = trans_time->start_schedule_us / 5489f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME; 5499f9f09b0SDouglas Anderson int rel_us = trans_time->start_schedule_us % 5509f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME; 5519f9f09b0SDouglas Anderson 5529f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, 5539f9f09b0SDouglas Anderson "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n", 5549f9f09b0SDouglas Anderson qh, i, trans_time->duration_us, uframe, rel_us); 5559f9f09b0SDouglas Anderson } 5569f9f09b0SDouglas Anderson if (qh->num_hs_transfers) { 5579f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh); 5589f9f09b0SDouglas Anderson pmap_print(hsotg->hs_periodic_bitmap, 5599f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME, 5609f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us", 5619f9f09b0SDouglas Anderson dwc2_qh_print, &print_data); 5629f9f09b0SDouglas Anderson } 5639f9f09b0SDouglas Anderson } 5643c220370SVardan Mikayelyan #else 5653c220370SVardan Mikayelyan static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg, 5663c220370SVardan Mikayelyan struct dwc2_qh *qh) {}; 5673c220370SVardan Mikayelyan #endif 5689f9f09b0SDouglas Anderson 5699f9f09b0SDouglas Anderson /** 5709f9f09b0SDouglas Anderson * dwc2_ls_pmap_schedule() - Schedule a low speed QH 5719f9f09b0SDouglas Anderson * 5729f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 5739f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 5749f9f09b0SDouglas Anderson * @search_slice: We'll start trying to schedule at the passed slice. 5759f9f09b0SDouglas Anderson * Remember that slices are the units of the low speed 5769f9f09b0SDouglas Anderson * schedule (think 25us or so). 5779f9f09b0SDouglas Anderson * 5789f9f09b0SDouglas Anderson * Wraps pmap_schedule() with the right parameters for low speed scheduling. 5799f9f09b0SDouglas Anderson * 5809f9f09b0SDouglas Anderson * Normally we schedule low speed devices on the map associated with the TT. 5819f9f09b0SDouglas Anderson * 5829f9f09b0SDouglas Anderson * Returns: 0 for success or an error code. 5839f9f09b0SDouglas Anderson */ 5849f9f09b0SDouglas Anderson static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 5859f9f09b0SDouglas Anderson int search_slice) 586b951c6c7SDouglas Anderson { 5879f9f09b0SDouglas Anderson int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 5889f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh); 5899f9f09b0SDouglas Anderson int slice; 5909f9f09b0SDouglas Anderson 5919da51974SJohn Youn if (!map) 5929f9f09b0SDouglas Anderson return -EINVAL; 5939f9f09b0SDouglas Anderson 5949f9f09b0SDouglas Anderson /* 5959f9f09b0SDouglas Anderson * Schedule on the proper low speed map with our low speed scheduling 5969f9f09b0SDouglas Anderson * parameters. Note that we use the "device_interval" here since 5979f9f09b0SDouglas Anderson * we want the low speed interval and the only way we'd be in this 5989f9f09b0SDouglas Anderson * function is if the device is low speed. 5999f9f09b0SDouglas Anderson * 6009f9f09b0SDouglas Anderson * If we happen to be doing low speed and high speed scheduling for the 6019f9f09b0SDouglas Anderson * same transaction (AKA we have a split) we always do low speed first. 6029f9f09b0SDouglas Anderson * That means we can always pass "false" for only_one_period (that 6039f9f09b0SDouglas Anderson * parameters is only useful when we're trying to get one schedule to 6049f9f09b0SDouglas Anderson * match what we already planned in the other schedule). 6059f9f09b0SDouglas Anderson */ 6069f9f09b0SDouglas Anderson slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 6079f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, slices, 6089f9f09b0SDouglas Anderson qh->device_interval, search_slice, false); 6099f9f09b0SDouglas Anderson 6109f9f09b0SDouglas Anderson if (slice < 0) 6119f9f09b0SDouglas Anderson return slice; 6129f9f09b0SDouglas Anderson 6139f9f09b0SDouglas Anderson qh->ls_start_schedule_slice = slice; 6149f9f09b0SDouglas Anderson return 0; 6159f9f09b0SDouglas Anderson } 6169f9f09b0SDouglas Anderson 6179f9f09b0SDouglas Anderson /** 6189f9f09b0SDouglas Anderson * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule() 6199f9f09b0SDouglas Anderson * 6209f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 6219f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 6229f9f09b0SDouglas Anderson */ 6239f9f09b0SDouglas Anderson static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg, 6249f9f09b0SDouglas Anderson struct dwc2_qh *qh) 6259f9f09b0SDouglas Anderson { 6269f9f09b0SDouglas Anderson int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE); 6279f9f09b0SDouglas Anderson unsigned long *map = dwc2_get_ls_map(hsotg, qh); 6289f9f09b0SDouglas Anderson 6299f9f09b0SDouglas Anderson /* Schedule should have failed, so no worries about no error code */ 6309da51974SJohn Youn if (!map) 6319f9f09b0SDouglas Anderson return; 6329f9f09b0SDouglas Anderson 6339f9f09b0SDouglas Anderson pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME, 6349f9f09b0SDouglas Anderson DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval, 6359f9f09b0SDouglas Anderson qh->ls_start_schedule_slice); 6369f9f09b0SDouglas Anderson } 6379f9f09b0SDouglas Anderson 6389f9f09b0SDouglas Anderson /** 6399f9f09b0SDouglas Anderson * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule 6409f9f09b0SDouglas Anderson * 6419f9f09b0SDouglas Anderson * This will schedule something on the main dwc2 schedule. 6429f9f09b0SDouglas Anderson * 6439f9f09b0SDouglas Anderson * We'll start looking in qh->hs_transfers[index].start_schedule_us. We'll 6449f9f09b0SDouglas Anderson * update this with the result upon success. We also use the duration from 6459f9f09b0SDouglas Anderson * the same structure. 6469f9f09b0SDouglas Anderson * 6479f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 6489f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 6499f9f09b0SDouglas Anderson * @only_one_period: If true we will limit ourselves to just looking at 6509f9f09b0SDouglas Anderson * one period (aka one 100us chunk). This is used if we have 6519f9f09b0SDouglas Anderson * already scheduled something on the low speed schedule and 6529f9f09b0SDouglas Anderson * need to find something that matches on the high speed one. 6539f9f09b0SDouglas Anderson * @index: The index into qh->hs_transfers that we're working with. 6549f9f09b0SDouglas Anderson * 6559f9f09b0SDouglas Anderson * Returns: 0 for success or an error code. Upon success the 6569f9f09b0SDouglas Anderson * dwc2_hs_transfer_time specified by "index" will be updated. 6579f9f09b0SDouglas Anderson */ 6589f9f09b0SDouglas Anderson static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 6599f9f09b0SDouglas Anderson bool only_one_period, int index) 6609f9f09b0SDouglas Anderson { 6619f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 6629f9f09b0SDouglas Anderson int us; 6639f9f09b0SDouglas Anderson 6649f9f09b0SDouglas Anderson us = pmap_schedule(hsotg->hs_periodic_bitmap, 6659f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME, 6669f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 6679f9f09b0SDouglas Anderson qh->host_interval, trans_time->start_schedule_us, 6689f9f09b0SDouglas Anderson only_one_period); 6699f9f09b0SDouglas Anderson 6709f9f09b0SDouglas Anderson if (us < 0) 6719f9f09b0SDouglas Anderson return us; 6729f9f09b0SDouglas Anderson 6739f9f09b0SDouglas Anderson trans_time->start_schedule_us = us; 6749f9f09b0SDouglas Anderson return 0; 6759f9f09b0SDouglas Anderson } 6769f9f09b0SDouglas Anderson 6779f9f09b0SDouglas Anderson /** 678a63acbdeSLee Jones * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule() 6799f9f09b0SDouglas Anderson * 6809f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 6819f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 6826fb914d7SGrigor Tovmasyan * @index: Transfer index 6839f9f09b0SDouglas Anderson */ 6849f9f09b0SDouglas Anderson static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg, 6859f9f09b0SDouglas Anderson struct dwc2_qh *qh, int index) 6869f9f09b0SDouglas Anderson { 6879f9f09b0SDouglas Anderson struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index; 6889f9f09b0SDouglas Anderson 6899f9f09b0SDouglas Anderson pmap_unschedule(hsotg->hs_periodic_bitmap, 6909f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME, 6919f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us, 6929f9f09b0SDouglas Anderson qh->host_interval, trans_time->start_schedule_us); 6939f9f09b0SDouglas Anderson } 6949f9f09b0SDouglas Anderson 6959f9f09b0SDouglas Anderson /** 6969f9f09b0SDouglas Anderson * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer. 6979f9f09b0SDouglas Anderson * 6989f9f09b0SDouglas Anderson * This is the most complicated thing in USB. We have to find matching time 6999f9f09b0SDouglas Anderson * in both the global high speed schedule for the port and the low speed 7009f9f09b0SDouglas Anderson * schedule for the TT associated with the given device. 7019f9f09b0SDouglas Anderson * 7029f9f09b0SDouglas Anderson * Being here means that the host must be running in high speed mode and the 7039f9f09b0SDouglas Anderson * device is in low or full speed mode (and behind a hub). 7049f9f09b0SDouglas Anderson * 7059f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 7069f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 7079f9f09b0SDouglas Anderson */ 7089f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg, 7099f9f09b0SDouglas Anderson struct dwc2_qh *qh) 7109f9f09b0SDouglas Anderson { 711babd1839SDouglas Anderson int bytecount = qh->maxp_mult * qh->maxp; 7129f9f09b0SDouglas Anderson int ls_search_slice; 7139f9f09b0SDouglas Anderson int err = 0; 7149f9f09b0SDouglas Anderson int host_interval_in_sched; 7159f9f09b0SDouglas Anderson 7169f9f09b0SDouglas Anderson /* 7179f9f09b0SDouglas Anderson * The interval (how often to repeat) in the actual host schedule. 7189f9f09b0SDouglas Anderson * See pmap_schedule() for gcd() explanation. 7199f9f09b0SDouglas Anderson */ 7209f9f09b0SDouglas Anderson host_interval_in_sched = gcd(qh->host_interval, 7219f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES); 7229f9f09b0SDouglas Anderson 7239f9f09b0SDouglas Anderson /* 7249f9f09b0SDouglas Anderson * We always try to find space in the low speed schedule first, then 7259f9f09b0SDouglas Anderson * try to find high speed time that matches. If we don't, we'll bump 7269f9f09b0SDouglas Anderson * up the place we start searching in the low speed schedule and try 7279f9f09b0SDouglas Anderson * again. To start we'll look right at the beginning of the low speed 7289f9f09b0SDouglas Anderson * schedule. 7299f9f09b0SDouglas Anderson * 7309f9f09b0SDouglas Anderson * Note that this will tend to front-load the high speed schedule. 7319f9f09b0SDouglas Anderson * We may eventually want to try to avoid this by either considering 7329f9f09b0SDouglas Anderson * both schedules together or doing some sort of round robin. 7339f9f09b0SDouglas Anderson */ 7349f9f09b0SDouglas Anderson ls_search_slice = 0; 7359f9f09b0SDouglas Anderson 7369f9f09b0SDouglas Anderson while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) { 7379f9f09b0SDouglas Anderson int start_s_uframe; 7389f9f09b0SDouglas Anderson int ssplit_s_uframe; 7399f9f09b0SDouglas Anderson int second_s_uframe; 7409f9f09b0SDouglas Anderson int rel_uframe; 7419f9f09b0SDouglas Anderson int first_count; 7429f9f09b0SDouglas Anderson int middle_count; 7439f9f09b0SDouglas Anderson int end_count; 7449f9f09b0SDouglas Anderson int first_data_bytes; 7459f9f09b0SDouglas Anderson int other_data_bytes; 746b951c6c7SDouglas Anderson int i; 747b951c6c7SDouglas Anderson 7489f9f09b0SDouglas Anderson if (qh->schedule_low_speed) { 7499f9f09b0SDouglas Anderson err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice); 750b951c6c7SDouglas Anderson 751b951c6c7SDouglas Anderson /* 7529f9f09b0SDouglas Anderson * If we got an error here there's no other magic we 7539f9f09b0SDouglas Anderson * can do, so bail. All the looping above is only 7549f9f09b0SDouglas Anderson * helpful to redo things if we got a low speed slot 7559f9f09b0SDouglas Anderson * and then couldn't find a matching high speed slot. 756b951c6c7SDouglas Anderson */ 7579f9f09b0SDouglas Anderson if (err) 7589f9f09b0SDouglas Anderson return err; 759b951c6c7SDouglas Anderson } else { 7609f9f09b0SDouglas Anderson /* Must be missing the tt structure? Why? */ 7619f9f09b0SDouglas Anderson WARN_ON_ONCE(1); 762b951c6c7SDouglas Anderson } 763b951c6c7SDouglas Anderson 7649f9f09b0SDouglas Anderson /* 7659f9f09b0SDouglas Anderson * This will give us a number 0 - 7 if 7669f9f09b0SDouglas Anderson * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ... 7679f9f09b0SDouglas Anderson */ 7689f9f09b0SDouglas Anderson start_s_uframe = qh->ls_start_schedule_slice / 7699f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME; 7709f9f09b0SDouglas Anderson 7719f9f09b0SDouglas Anderson /* Get a number that's always 0 - 7 */ 7729f9f09b0SDouglas Anderson rel_uframe = (start_s_uframe % 8); 7739f9f09b0SDouglas Anderson 7749f9f09b0SDouglas Anderson /* 7759f9f09b0SDouglas Anderson * If we were going to start in uframe 7 then we would need to 7769f9f09b0SDouglas Anderson * issue a start split in uframe 6, which spec says is not OK. 7779f9f09b0SDouglas Anderson * Move on to the next full frame (assuming there is one). 7789f9f09b0SDouglas Anderson * 7799f9f09b0SDouglas Anderson * See 11.18.4 Host Split Transaction Scheduling Requirements 7809f9f09b0SDouglas Anderson * bullet 1. 7819f9f09b0SDouglas Anderson */ 7829f9f09b0SDouglas Anderson if (rel_uframe == 7) { 7839f9f09b0SDouglas Anderson if (qh->schedule_low_speed) 7849f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh); 7859f9f09b0SDouglas Anderson ls_search_slice = 7869f9f09b0SDouglas Anderson (qh->ls_start_schedule_slice / 7879f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) * 7889f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME; 7899f9f09b0SDouglas Anderson continue; 7909f9f09b0SDouglas Anderson } 7919f9f09b0SDouglas Anderson 7929f9f09b0SDouglas Anderson /* 7939f9f09b0SDouglas Anderson * For ISOC in: 7949f9f09b0SDouglas Anderson * - start split (frame -1) 7959f9f09b0SDouglas Anderson * - complete split w/ data (frame +1) 7969f9f09b0SDouglas Anderson * - complete split w/ data (frame +2) 7979f9f09b0SDouglas Anderson * - ... 7989f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets) 7999f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets+1) 8009f9f09b0SDouglas Anderson * - complete split w/ data (frame +num_data_packets+2, max 8) 8019f9f09b0SDouglas Anderson * ...though if frame was "0" then max is 7... 8029f9f09b0SDouglas Anderson * 8039f9f09b0SDouglas Anderson * For ISOC out we might need to do: 8049f9f09b0SDouglas Anderson * - start split w/ data (frame -1) 8059f9f09b0SDouglas Anderson * - start split w/ data (frame +0) 8069f9f09b0SDouglas Anderson * - ... 8079f9f09b0SDouglas Anderson * - start split w/ data (frame +num_data_packets-2) 8089f9f09b0SDouglas Anderson * 8099f9f09b0SDouglas Anderson * For INTERRUPT in we might need to do: 8109f9f09b0SDouglas Anderson * - start split (frame -1) 8119f9f09b0SDouglas Anderson * - complete split w/ data (frame +1) 8129f9f09b0SDouglas Anderson * - complete split w/ data (frame +2) 8139f9f09b0SDouglas Anderson * - complete split w/ data (frame +3, max 8) 8149f9f09b0SDouglas Anderson * 8159f9f09b0SDouglas Anderson * For INTERRUPT out we might need to do: 8169f9f09b0SDouglas Anderson * - start split w/ data (frame -1) 8179f9f09b0SDouglas Anderson * - complete split (frame +1) 8189f9f09b0SDouglas Anderson * - complete split (frame +2) 8199f9f09b0SDouglas Anderson * - complete split (frame +3, max 8) 8209f9f09b0SDouglas Anderson * 8219f9f09b0SDouglas Anderson * Start adjusting! 8229f9f09b0SDouglas Anderson */ 8239f9f09b0SDouglas Anderson ssplit_s_uframe = (start_s_uframe + 8249f9f09b0SDouglas Anderson host_interval_in_sched - 1) % 8259f9f09b0SDouglas Anderson host_interval_in_sched; 8269f9f09b0SDouglas Anderson if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in) 8279f9f09b0SDouglas Anderson second_s_uframe = start_s_uframe; 8289f9f09b0SDouglas Anderson else 8299f9f09b0SDouglas Anderson second_s_uframe = start_s_uframe + 1; 8309f9f09b0SDouglas Anderson 8319f9f09b0SDouglas Anderson /* First data transfer might not be all 188 bytes. */ 8329f9f09b0SDouglas Anderson first_data_bytes = 188 - 8339f9f09b0SDouglas Anderson DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice % 8349f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME), 8359f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME); 8369f9f09b0SDouglas Anderson if (first_data_bytes > bytecount) 8379f9f09b0SDouglas Anderson first_data_bytes = bytecount; 8389f9f09b0SDouglas Anderson other_data_bytes = bytecount - first_data_bytes; 8399f9f09b0SDouglas Anderson 8409f9f09b0SDouglas Anderson /* 8419f9f09b0SDouglas Anderson * For now, skip OUT xfers where first xfer is partial 8429f9f09b0SDouglas Anderson * 8439f9f09b0SDouglas Anderson * Main dwc2 code assumes: 8449f9f09b0SDouglas Anderson * - INT transfers never get split in two. 8459f9f09b0SDouglas Anderson * - ISOC transfers can always transfer 188 bytes the first 8469f9f09b0SDouglas Anderson * time. 8479f9f09b0SDouglas Anderson * 8489f9f09b0SDouglas Anderson * Until that code is fixed, try again if the first transfer 8499f9f09b0SDouglas Anderson * couldn't transfer everything. 8509f9f09b0SDouglas Anderson * 8519f9f09b0SDouglas Anderson * This code can be removed if/when the rest of dwc2 handles 8529f9f09b0SDouglas Anderson * the above cases. Until it's fixed we just won't be able 8539f9f09b0SDouglas Anderson * to schedule quite as tightly. 8549f9f09b0SDouglas Anderson */ 8559f9f09b0SDouglas Anderson if (!qh->ep_is_in && 8569f9f09b0SDouglas Anderson (first_data_bytes != min_t(int, 188, bytecount))) { 8579f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, 8589f9f09b0SDouglas Anderson "QH=%p avoiding broken 1st xfer (%d, %d)\n", 8599f9f09b0SDouglas Anderson qh, first_data_bytes, bytecount); 8609f9f09b0SDouglas Anderson if (qh->schedule_low_speed) 8619f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh); 8629f9f09b0SDouglas Anderson ls_search_slice = (start_s_uframe + 1) * 8639f9f09b0SDouglas Anderson DWC2_SLICES_PER_UFRAME; 8649f9f09b0SDouglas Anderson continue; 8659f9f09b0SDouglas Anderson } 8669f9f09b0SDouglas Anderson 8679f9f09b0SDouglas Anderson /* Start by assuming transfers for the bytes */ 8689f9f09b0SDouglas Anderson qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188); 8699f9f09b0SDouglas Anderson 8709f9f09b0SDouglas Anderson /* 8719f9f09b0SDouglas Anderson * Everything except ISOC OUT has extra transfers. Rules are 8729f9f09b0SDouglas Anderson * complicated. See 11.18.4 Host Split Transaction Scheduling 8739f9f09b0SDouglas Anderson * Requirements bullet 3. 8749f9f09b0SDouglas Anderson */ 8759f9f09b0SDouglas Anderson if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 8769f9f09b0SDouglas Anderson if (rel_uframe == 6) 8779f9f09b0SDouglas Anderson qh->num_hs_transfers += 2; 8789f9f09b0SDouglas Anderson else 8799f9f09b0SDouglas Anderson qh->num_hs_transfers += 3; 8809f9f09b0SDouglas Anderson 8819f9f09b0SDouglas Anderson if (qh->ep_is_in) { 8829f9f09b0SDouglas Anderson /* 8839f9f09b0SDouglas Anderson * First is start split, middle/end is data. 8849f9f09b0SDouglas Anderson * Allocate full data bytes for all data. 8859f9f09b0SDouglas Anderson */ 8869f9f09b0SDouglas Anderson first_count = 4; 8879f9f09b0SDouglas Anderson middle_count = bytecount; 8889f9f09b0SDouglas Anderson end_count = bytecount; 8899f9f09b0SDouglas Anderson } else { 8909f9f09b0SDouglas Anderson /* 8919f9f09b0SDouglas Anderson * First is data, middle/end is complete. 8929f9f09b0SDouglas Anderson * First transfer and second can have data. 8939f9f09b0SDouglas Anderson * Rest should just have complete split. 8949f9f09b0SDouglas Anderson */ 8959f9f09b0SDouglas Anderson first_count = first_data_bytes; 8969f9f09b0SDouglas Anderson middle_count = max_t(int, 4, other_data_bytes); 8979f9f09b0SDouglas Anderson end_count = 4; 8989f9f09b0SDouglas Anderson } 8999f9f09b0SDouglas Anderson } else { 9009f9f09b0SDouglas Anderson if (qh->ep_is_in) { 9019f9f09b0SDouglas Anderson int last; 9029f9f09b0SDouglas Anderson 9039f9f09b0SDouglas Anderson /* Account for the start split */ 9049f9f09b0SDouglas Anderson qh->num_hs_transfers++; 9059f9f09b0SDouglas Anderson 9069f9f09b0SDouglas Anderson /* Calculate "L" value from spec */ 9079f9f09b0SDouglas Anderson last = rel_uframe + qh->num_hs_transfers + 1; 9089f9f09b0SDouglas Anderson 9099f9f09b0SDouglas Anderson /* Start with basic case */ 9109f9f09b0SDouglas Anderson if (last <= 6) 9119f9f09b0SDouglas Anderson qh->num_hs_transfers += 2; 9129f9f09b0SDouglas Anderson else 9139f9f09b0SDouglas Anderson qh->num_hs_transfers += 1; 9149f9f09b0SDouglas Anderson 9159f9f09b0SDouglas Anderson /* Adjust downwards */ 9169f9f09b0SDouglas Anderson if (last >= 6 && rel_uframe == 0) 9179f9f09b0SDouglas Anderson qh->num_hs_transfers--; 9189f9f09b0SDouglas Anderson 9199f9f09b0SDouglas Anderson /* 1st = start; rest can contain data */ 9209f9f09b0SDouglas Anderson first_count = 4; 9219f9f09b0SDouglas Anderson middle_count = min_t(int, 188, bytecount); 9229f9f09b0SDouglas Anderson end_count = middle_count; 9239f9f09b0SDouglas Anderson } else { 9249f9f09b0SDouglas Anderson /* All contain data, last might be smaller */ 9259f9f09b0SDouglas Anderson first_count = first_data_bytes; 9269f9f09b0SDouglas Anderson middle_count = min_t(int, 188, 9279f9f09b0SDouglas Anderson other_data_bytes); 9289f9f09b0SDouglas Anderson end_count = other_data_bytes % 188; 9299f9f09b0SDouglas Anderson } 9309f9f09b0SDouglas Anderson } 9319f9f09b0SDouglas Anderson 9329f9f09b0SDouglas Anderson /* Assign durations per uFrame */ 9339f9f09b0SDouglas Anderson qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count); 9349f9f09b0SDouglas Anderson for (i = 1; i < qh->num_hs_transfers - 1; i++) 9359f9f09b0SDouglas Anderson qh->hs_transfers[i].duration_us = 9369f9f09b0SDouglas Anderson HS_USECS_ISO(middle_count); 9379f9f09b0SDouglas Anderson if (qh->num_hs_transfers > 1) 9389f9f09b0SDouglas Anderson qh->hs_transfers[qh->num_hs_transfers - 1].duration_us = 9399f9f09b0SDouglas Anderson HS_USECS_ISO(end_count); 9409f9f09b0SDouglas Anderson 9419f9f09b0SDouglas Anderson /* 9429f9f09b0SDouglas Anderson * Assign start us. The call below to dwc2_hs_pmap_schedule() 9439f9f09b0SDouglas Anderson * will start with these numbers but may adjust within the same 9449f9f09b0SDouglas Anderson * microframe. 9459f9f09b0SDouglas Anderson */ 9469f9f09b0SDouglas Anderson qh->hs_transfers[0].start_schedule_us = 9479f9f09b0SDouglas Anderson ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME; 9489f9f09b0SDouglas Anderson for (i = 1; i < qh->num_hs_transfers; i++) 9499f9f09b0SDouglas Anderson qh->hs_transfers[i].start_schedule_us = 9509f9f09b0SDouglas Anderson ((second_s_uframe + i - 1) % 9519f9f09b0SDouglas Anderson DWC2_HS_SCHEDULE_UFRAMES) * 9529f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME; 9539f9f09b0SDouglas Anderson 9549f9f09b0SDouglas Anderson /* Try to schedule with filled in hs_transfers above */ 9559f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++) { 9569f9f09b0SDouglas Anderson err = dwc2_hs_pmap_schedule(hsotg, qh, true, i); 9579f9f09b0SDouglas Anderson if (err) 9589f9f09b0SDouglas Anderson break; 9599f9f09b0SDouglas Anderson } 9609f9f09b0SDouglas Anderson 9619f9f09b0SDouglas Anderson /* If we scheduled all w/out breaking out then we're all good */ 9629f9f09b0SDouglas Anderson if (i == qh->num_hs_transfers) 9639f9f09b0SDouglas Anderson break; 9649f9f09b0SDouglas Anderson 9659f9f09b0SDouglas Anderson for (; i >= 0; i--) 9669f9f09b0SDouglas Anderson dwc2_hs_pmap_unschedule(hsotg, qh, i); 9679f9f09b0SDouglas Anderson 9689f9f09b0SDouglas Anderson if (qh->schedule_low_speed) 9699f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh); 9709f9f09b0SDouglas Anderson 9719f9f09b0SDouglas Anderson /* Try again starting in the next microframe */ 9729f9f09b0SDouglas Anderson ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME; 9739f9f09b0SDouglas Anderson } 9749f9f09b0SDouglas Anderson 9759f9f09b0SDouglas Anderson if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES) 9769f9f09b0SDouglas Anderson return -ENOSPC; 9779f9f09b0SDouglas Anderson 9789f9f09b0SDouglas Anderson return 0; 9799f9f09b0SDouglas Anderson } 9809f9f09b0SDouglas Anderson 9819f9f09b0SDouglas Anderson /** 9829f9f09b0SDouglas Anderson * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer. 9839f9f09b0SDouglas Anderson * 9849f9f09b0SDouglas Anderson * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean 9859f9f09b0SDouglas Anderson * interface. 9869f9f09b0SDouglas Anderson * 9879f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 9889f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 9899f9f09b0SDouglas Anderson */ 9909f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 9919f9f09b0SDouglas Anderson { 9929f9f09b0SDouglas Anderson /* In non-split host and device time are the same */ 9939f9f09b0SDouglas Anderson WARN_ON(qh->host_us != qh->device_us); 9949f9f09b0SDouglas Anderson WARN_ON(qh->host_interval != qh->device_interval); 9959f9f09b0SDouglas Anderson WARN_ON(qh->num_hs_transfers != 1); 9969f9f09b0SDouglas Anderson 9979f9f09b0SDouglas Anderson /* We'll have one transfer; init start to 0 before calling scheduler */ 9989f9f09b0SDouglas Anderson qh->hs_transfers[0].start_schedule_us = 0; 9999f9f09b0SDouglas Anderson qh->hs_transfers[0].duration_us = qh->host_us; 10009f9f09b0SDouglas Anderson 10019f9f09b0SDouglas Anderson return dwc2_hs_pmap_schedule(hsotg, qh, false, 0); 10029f9f09b0SDouglas Anderson } 10039f9f09b0SDouglas Anderson 10049f9f09b0SDouglas Anderson /** 10059f9f09b0SDouglas Anderson * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer. 10069f9f09b0SDouglas Anderson * 10079f9f09b0SDouglas Anderson * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean 10089f9f09b0SDouglas Anderson * interface. 10099f9f09b0SDouglas Anderson * 10109f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 10119f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 10129f9f09b0SDouglas Anderson */ 10139f9f09b0SDouglas Anderson static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 10149f9f09b0SDouglas Anderson { 10159f9f09b0SDouglas Anderson /* In non-split host and device time are the same */ 10169f9f09b0SDouglas Anderson WARN_ON(qh->host_us != qh->device_us); 10179f9f09b0SDouglas Anderson WARN_ON(qh->host_interval != qh->device_interval); 10189f9f09b0SDouglas Anderson WARN_ON(!qh->schedule_low_speed); 10199f9f09b0SDouglas Anderson 10209f9f09b0SDouglas Anderson /* Run on the main low speed schedule (no split = no hub = no TT) */ 10219f9f09b0SDouglas Anderson return dwc2_ls_pmap_schedule(hsotg, qh, 0); 10229f9f09b0SDouglas Anderson } 10239f9f09b0SDouglas Anderson 10249f9f09b0SDouglas Anderson /** 10259f9f09b0SDouglas Anderson * dwc2_uframe_schedule - Schedule a QH for a periodic xfer. 10269f9f09b0SDouglas Anderson * 10279f9f09b0SDouglas Anderson * Calls one of the 3 sub-function depending on what type of transfer this QH 10289f9f09b0SDouglas Anderson * is for. Also adds some printing. 10299f9f09b0SDouglas Anderson * 10309f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 10319f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 10329f9f09b0SDouglas Anderson */ 10339f9f09b0SDouglas Anderson static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1034b951c6c7SDouglas Anderson { 1035b951c6c7SDouglas Anderson int ret; 1036b951c6c7SDouglas Anderson 10379f9f09b0SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH) 10389f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_hs(hsotg, qh); 10399f9f09b0SDouglas Anderson else if (!qh->do_split) 10409f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_ls(hsotg, qh); 10419f9f09b0SDouglas Anderson else 10429f9f09b0SDouglas Anderson ret = dwc2_uframe_schedule_split(hsotg, qh); 10439f9f09b0SDouglas Anderson 10449f9f09b0SDouglas Anderson if (ret) 10459f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret); 10469f9f09b0SDouglas Anderson else 10479f9f09b0SDouglas Anderson dwc2_qh_schedule_print(hsotg, qh); 10489f9f09b0SDouglas Anderson 1049b951c6c7SDouglas Anderson return ret; 1050b951c6c7SDouglas Anderson } 1051b951c6c7SDouglas Anderson 1052b951c6c7SDouglas Anderson /** 10539f9f09b0SDouglas Anderson * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule(). 10549f9f09b0SDouglas Anderson * 10559f9f09b0SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller. 10569f9f09b0SDouglas Anderson * @qh: QH for the periodic transfer. 10579f9f09b0SDouglas Anderson */ 10589f9f09b0SDouglas Anderson static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 10599f9f09b0SDouglas Anderson { 10609f9f09b0SDouglas Anderson int i; 10619f9f09b0SDouglas Anderson 10629f9f09b0SDouglas Anderson for (i = 0; i < qh->num_hs_transfers; i++) 10639f9f09b0SDouglas Anderson dwc2_hs_pmap_unschedule(hsotg, qh, i); 10649f9f09b0SDouglas Anderson 10659f9f09b0SDouglas Anderson if (qh->schedule_low_speed) 10669f9f09b0SDouglas Anderson dwc2_ls_pmap_unschedule(hsotg, qh); 10679f9f09b0SDouglas Anderson 10689f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh); 10699f9f09b0SDouglas Anderson } 10709f9f09b0SDouglas Anderson 10719f9f09b0SDouglas Anderson /** 1072fb616e3fSDouglas Anderson * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled 1073fb616e3fSDouglas Anderson * 1074fb616e3fSDouglas Anderson * Takes a qh that has already been scheduled (which means we know we have the 1075fb616e3fSDouglas Anderson * bandwdith reserved for us) and set the next_active_frame and the 1076fb616e3fSDouglas Anderson * start_active_frame. 1077fb616e3fSDouglas Anderson * 1078fb616e3fSDouglas Anderson * This is expected to be called on qh's that weren't previously actively 1079fb616e3fSDouglas Anderson * running. It just picks the next frame that we can fit into without any 1080fb616e3fSDouglas Anderson * thought about the past. 1081fb616e3fSDouglas Anderson * 1082fb616e3fSDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 1083fb616e3fSDouglas Anderson * @qh: QH for a periodic endpoint 1084fb616e3fSDouglas Anderson * 1085fb616e3fSDouglas Anderson */ 1086fb616e3fSDouglas Anderson static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1087fb616e3fSDouglas Anderson { 1088fb616e3fSDouglas Anderson u16 frame_number; 1089fb616e3fSDouglas Anderson u16 earliest_frame; 1090fb616e3fSDouglas Anderson u16 next_active_frame; 10919f9f09b0SDouglas Anderson u16 relative_frame; 1092fb616e3fSDouglas Anderson u16 interval; 1093fb616e3fSDouglas Anderson 1094fb616e3fSDouglas Anderson /* 1095fb616e3fSDouglas Anderson * Use the real frame number rather than the cached value as of the 1096fb616e3fSDouglas Anderson * last SOF to give us a little extra slop. 1097fb616e3fSDouglas Anderson */ 1098fb616e3fSDouglas Anderson frame_number = dwc2_hcd_get_frame_number(hsotg); 1099fb616e3fSDouglas Anderson 1100fb616e3fSDouglas Anderson /* 1101fb616e3fSDouglas Anderson * We wouldn't want to start any earlier than the next frame just in 1102fb616e3fSDouglas Anderson * case the frame number ticks as we're doing this calculation. 1103fb616e3fSDouglas Anderson * 1104fb616e3fSDouglas Anderson * NOTE: if we could quantify how long till we actually get scheduled 1105fb616e3fSDouglas Anderson * we might be able to avoid the "+ 1" by looking at the upper part of 1106fb616e3fSDouglas Anderson * HFNUM (the FRREM field). For now we'll just use the + 1 though. 1107fb616e3fSDouglas Anderson */ 1108fb616e3fSDouglas Anderson earliest_frame = dwc2_frame_num_inc(frame_number, 1); 1109fb616e3fSDouglas Anderson next_active_frame = earliest_frame; 1110fb616e3fSDouglas Anderson 1111fb616e3fSDouglas Anderson /* Get the "no microframe schduler" out of the way... */ 111295832c00SJohn Youn if (!hsotg->params.uframe_sched) { 1113fb616e3fSDouglas Anderson if (qh->do_split) 1114fb616e3fSDouglas Anderson /* Splits are active at microframe 0 minus 1 */ 1115fb616e3fSDouglas Anderson next_active_frame |= 0x7; 1116fb616e3fSDouglas Anderson goto exit; 1117fb616e3fSDouglas Anderson } 1118fb616e3fSDouglas Anderson 11199f9f09b0SDouglas Anderson if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 11209f9f09b0SDouglas Anderson /* 11219f9f09b0SDouglas Anderson * We're either at high speed or we're doing a split (which 11229f9f09b0SDouglas Anderson * means we're talking high speed to a hub). In any case 11239f9f09b0SDouglas Anderson * the first frame should be based on when the first scheduled 11249f9f09b0SDouglas Anderson * event is. 11259f9f09b0SDouglas Anderson */ 11269f9f09b0SDouglas Anderson WARN_ON(qh->num_hs_transfers < 1); 11279f9f09b0SDouglas Anderson 11289f9f09b0SDouglas Anderson relative_frame = qh->hs_transfers[0].start_schedule_us / 11299f9f09b0SDouglas Anderson DWC2_HS_PERIODIC_US_PER_UFRAME; 11309f9f09b0SDouglas Anderson 11319f9f09b0SDouglas Anderson /* Adjust interval as per high speed schedule */ 11329f9f09b0SDouglas Anderson interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES); 11339f9f09b0SDouglas Anderson 11349f9f09b0SDouglas Anderson } else { 11359f9f09b0SDouglas Anderson /* 11369f9f09b0SDouglas Anderson * Low or full speed directly on dwc2. Just about the same 11379f9f09b0SDouglas Anderson * as high speed but on a different schedule and with slightly 11389f9f09b0SDouglas Anderson * different adjustments. Note that this works because when 11399f9f09b0SDouglas Anderson * the host and device are both low speed then frames in the 11409f9f09b0SDouglas Anderson * controller tick at low speed. 11419f9f09b0SDouglas Anderson */ 11429f9f09b0SDouglas Anderson relative_frame = qh->ls_start_schedule_slice / 11439f9f09b0SDouglas Anderson DWC2_LS_PERIODIC_SLICES_PER_FRAME; 11449f9f09b0SDouglas Anderson interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES); 11459f9f09b0SDouglas Anderson } 11469f9f09b0SDouglas Anderson 11479f9f09b0SDouglas Anderson /* Scheduler messed up if frame is past interval */ 11489f9f09b0SDouglas Anderson WARN_ON(relative_frame >= interval); 1149fb616e3fSDouglas Anderson 1150fb616e3fSDouglas Anderson /* 1151fb616e3fSDouglas Anderson * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've 1152fb616e3fSDouglas Anderson * done the gcd(), so it's safe to move to the beginning of the current 1153fb616e3fSDouglas Anderson * interval like this. 1154fb616e3fSDouglas Anderson * 1155fb616e3fSDouglas Anderson * After this we might be before earliest_frame, but don't worry, 1156fb616e3fSDouglas Anderson * we'll fix it... 1157fb616e3fSDouglas Anderson */ 1158fb616e3fSDouglas Anderson next_active_frame = (next_active_frame / interval) * interval; 1159fb616e3fSDouglas Anderson 1160fb616e3fSDouglas Anderson /* 1161fb616e3fSDouglas Anderson * Actually choose to start at the frame number we've been 1162fb616e3fSDouglas Anderson * scheduled for. 1163fb616e3fSDouglas Anderson */ 1164fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_inc(next_active_frame, 11659f9f09b0SDouglas Anderson relative_frame); 1166fb616e3fSDouglas Anderson 1167fb616e3fSDouglas Anderson /* 1168fb616e3fSDouglas Anderson * We actually need 1 frame before since the next_active_frame is 1169fb616e3fSDouglas Anderson * the frame number we'll be put on the ready list and we won't be on 1170fb616e3fSDouglas Anderson * the bus until 1 frame later. 1171fb616e3fSDouglas Anderson */ 1172fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_dec(next_active_frame, 1); 1173fb616e3fSDouglas Anderson 1174fb616e3fSDouglas Anderson /* 1175fb616e3fSDouglas Anderson * By now we might actually be before the earliest_frame. Let's move 1176fb616e3fSDouglas Anderson * up intervals until we're not. 1177fb616e3fSDouglas Anderson */ 1178fb616e3fSDouglas Anderson while (dwc2_frame_num_gt(earliest_frame, next_active_frame)) 1179fb616e3fSDouglas Anderson next_active_frame = dwc2_frame_num_inc(next_active_frame, 1180fb616e3fSDouglas Anderson interval); 1181fb616e3fSDouglas Anderson 1182fb616e3fSDouglas Anderson exit: 1183fb616e3fSDouglas Anderson qh->next_active_frame = next_active_frame; 1184fb616e3fSDouglas Anderson qh->start_active_frame = next_active_frame; 1185fb616e3fSDouglas Anderson 1186fb616e3fSDouglas Anderson dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n", 1187fb616e3fSDouglas Anderson qh, frame_number, qh->next_active_frame); 1188fb616e3fSDouglas Anderson } 1189fb616e3fSDouglas Anderson 1190fb616e3fSDouglas Anderson /** 11912d3f1398SDouglas Anderson * dwc2_do_reserve() - Make a periodic reservation 11922d3f1398SDouglas Anderson * 11932d3f1398SDouglas Anderson * Try to allocate space in the periodic schedule. Depending on parameters 11942d3f1398SDouglas Anderson * this might use the microframe scheduler or the dumb scheduler. 11952d3f1398SDouglas Anderson * 11962d3f1398SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 11972d3f1398SDouglas Anderson * @qh: QH for the periodic transfer. 11982d3f1398SDouglas Anderson * 11992d3f1398SDouglas Anderson * Returns: 0 upon success; error upon failure. 12002d3f1398SDouglas Anderson */ 12012d3f1398SDouglas Anderson static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 12022d3f1398SDouglas Anderson { 12032d3f1398SDouglas Anderson int status; 12042d3f1398SDouglas Anderson 120595832c00SJohn Youn if (hsotg->params.uframe_sched) { 12069f9f09b0SDouglas Anderson status = dwc2_uframe_schedule(hsotg, qh); 12072d3f1398SDouglas Anderson } else { 12082d3f1398SDouglas Anderson status = dwc2_periodic_channel_available(hsotg); 12092d3f1398SDouglas Anderson if (status) { 12102d3f1398SDouglas Anderson dev_info(hsotg->dev, 12112d3f1398SDouglas Anderson "%s: No host channel available for periodic transfer\n", 12122d3f1398SDouglas Anderson __func__); 12132d3f1398SDouglas Anderson return status; 12142d3f1398SDouglas Anderson } 12152d3f1398SDouglas Anderson 12162d3f1398SDouglas Anderson status = dwc2_check_periodic_bandwidth(hsotg, qh); 12172d3f1398SDouglas Anderson } 12182d3f1398SDouglas Anderson 12192d3f1398SDouglas Anderson if (status) { 12202d3f1398SDouglas Anderson dev_dbg(hsotg->dev, 12212d3f1398SDouglas Anderson "%s: Insufficient periodic bandwidth for periodic transfer\n", 12222d3f1398SDouglas Anderson __func__); 12232d3f1398SDouglas Anderson return status; 12242d3f1398SDouglas Anderson } 12252d3f1398SDouglas Anderson 122695832c00SJohn Youn if (!hsotg->params.uframe_sched) 12272d3f1398SDouglas Anderson /* Reserve periodic channel */ 12282d3f1398SDouglas Anderson hsotg->periodic_channels++; 12292d3f1398SDouglas Anderson 12302d3f1398SDouglas Anderson /* Update claimed usecs per (micro)frame */ 12312d3f1398SDouglas Anderson hsotg->periodic_usecs += qh->host_us; 12322d3f1398SDouglas Anderson 1233fb616e3fSDouglas Anderson dwc2_pick_first_frame(hsotg, qh); 1234fb616e3fSDouglas Anderson 12352d3f1398SDouglas Anderson return 0; 12362d3f1398SDouglas Anderson } 12372d3f1398SDouglas Anderson 12382d3f1398SDouglas Anderson /** 123917dd5b64SDouglas Anderson * dwc2_do_unreserve() - Actually release the periodic reservation 124017dd5b64SDouglas Anderson * 124117dd5b64SDouglas Anderson * This function actually releases the periodic bandwidth that was reserved 124217dd5b64SDouglas Anderson * by the given qh. 124317dd5b64SDouglas Anderson * 124417dd5b64SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 124517dd5b64SDouglas Anderson * @qh: QH for the periodic transfer. 124617dd5b64SDouglas Anderson */ 124717dd5b64SDouglas Anderson static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 124817dd5b64SDouglas Anderson { 124917dd5b64SDouglas Anderson assert_spin_locked(&hsotg->lock); 125017dd5b64SDouglas Anderson 125117dd5b64SDouglas Anderson WARN_ON(!qh->unreserve_pending); 125217dd5b64SDouglas Anderson 125317dd5b64SDouglas Anderson /* No more unreserve pending--we're doing it */ 125417dd5b64SDouglas Anderson qh->unreserve_pending = false; 125517dd5b64SDouglas Anderson 125617dd5b64SDouglas Anderson if (WARN_ON(!list_empty(&qh->qh_list_entry))) 125717dd5b64SDouglas Anderson list_del_init(&qh->qh_list_entry); 125817dd5b64SDouglas Anderson 125917dd5b64SDouglas Anderson /* Update claimed usecs per (micro)frame */ 1260ced9eee1SDouglas Anderson hsotg->periodic_usecs -= qh->host_us; 126117dd5b64SDouglas Anderson 126295832c00SJohn Youn if (hsotg->params.uframe_sched) { 12639f9f09b0SDouglas Anderson dwc2_uframe_unschedule(hsotg, qh); 126417dd5b64SDouglas Anderson } else { 126517dd5b64SDouglas Anderson /* Release periodic channel reservation */ 126617dd5b64SDouglas Anderson hsotg->periodic_channels--; 126717dd5b64SDouglas Anderson } 126817dd5b64SDouglas Anderson } 126917dd5b64SDouglas Anderson 127017dd5b64SDouglas Anderson /** 127117dd5b64SDouglas Anderson * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation 127217dd5b64SDouglas Anderson * 127317dd5b64SDouglas Anderson * According to the kernel doc for usb_submit_urb() (specifically the part about 127417dd5b64SDouglas Anderson * "Reserved Bandwidth Transfers"), we need to keep a reservation active as 127517dd5b64SDouglas Anderson * long as a device driver keeps submitting. Since we're using HCD_BH to give 127617dd5b64SDouglas Anderson * back the URB we need to give the driver a little bit of time before we 127717dd5b64SDouglas Anderson * release the reservation. This worker is called after the appropriate 127817dd5b64SDouglas Anderson * delay. 127917dd5b64SDouglas Anderson * 12806fb914d7SGrigor Tovmasyan * @t: Address to a qh unreserve_work. 128117dd5b64SDouglas Anderson */ 1282e99e88a9SKees Cook static void dwc2_unreserve_timer_fn(struct timer_list *t) 128317dd5b64SDouglas Anderson { 1284e99e88a9SKees Cook struct dwc2_qh *qh = from_timer(qh, t, unreserve_timer); 128517dd5b64SDouglas Anderson struct dwc2_hsotg *hsotg = qh->hsotg; 128617dd5b64SDouglas Anderson unsigned long flags; 128717dd5b64SDouglas Anderson 128817dd5b64SDouglas Anderson /* 128917dd5b64SDouglas Anderson * Wait for the lock, or for us to be scheduled again. We 129017dd5b64SDouglas Anderson * could be scheduled again if: 129117dd5b64SDouglas Anderson * - We started executing but didn't get the lock yet. 129217dd5b64SDouglas Anderson * - A new reservation came in, but cancel didn't take effect 129317dd5b64SDouglas Anderson * because we already started executing. 129417dd5b64SDouglas Anderson * - The timer has been kicked again. 129517dd5b64SDouglas Anderson * In that case cancel and wait for the next call. 129617dd5b64SDouglas Anderson */ 129717dd5b64SDouglas Anderson while (!spin_trylock_irqsave(&hsotg->lock, flags)) { 129817dd5b64SDouglas Anderson if (timer_pending(&qh->unreserve_timer)) 129917dd5b64SDouglas Anderson return; 130017dd5b64SDouglas Anderson } 130117dd5b64SDouglas Anderson 130217dd5b64SDouglas Anderson /* 130317dd5b64SDouglas Anderson * Might be no more unreserve pending if: 130417dd5b64SDouglas Anderson * - We started executing but didn't get the lock yet. 130517dd5b64SDouglas Anderson * - A new reservation came in, but cancel didn't take effect 130617dd5b64SDouglas Anderson * because we already started executing. 130717dd5b64SDouglas Anderson * 130817dd5b64SDouglas Anderson * We can't put this in the loop above because unreserve_pending needs 130917dd5b64SDouglas Anderson * to be accessed under lock, so we can only check it once we got the 131017dd5b64SDouglas Anderson * lock. 131117dd5b64SDouglas Anderson */ 131217dd5b64SDouglas Anderson if (qh->unreserve_pending) 131317dd5b64SDouglas Anderson dwc2_do_unreserve(hsotg, qh); 131417dd5b64SDouglas Anderson 131517dd5b64SDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags); 131617dd5b64SDouglas Anderson } 131717dd5b64SDouglas Anderson 1318197ba5f4SPaul Zimmerman /** 1319b951c6c7SDouglas Anderson * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 1320b951c6c7SDouglas Anderson * host channel is large enough to handle the maximum data transfer in a single 1321b951c6c7SDouglas Anderson * (micro)frame for a periodic transfer 1322b951c6c7SDouglas Anderson * 1323b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 1324b951c6c7SDouglas Anderson * @qh: QH for a periodic endpoint 1325b951c6c7SDouglas Anderson * 1326b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise 1327b951c6c7SDouglas Anderson */ 1328b951c6c7SDouglas Anderson static int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 1329b951c6c7SDouglas Anderson struct dwc2_qh *qh) 1330b951c6c7SDouglas Anderson { 1331b951c6c7SDouglas Anderson u32 max_xfer_size; 1332b951c6c7SDouglas Anderson u32 max_channel_xfer_size; 1333b951c6c7SDouglas Anderson int status = 0; 1334b951c6c7SDouglas Anderson 1335babd1839SDouglas Anderson max_xfer_size = qh->maxp * qh->maxp_mult; 1336bea8e86cSJohn Youn max_channel_xfer_size = hsotg->params.max_transfer_size; 1337b951c6c7SDouglas Anderson 1338b951c6c7SDouglas Anderson if (max_xfer_size > max_channel_xfer_size) { 1339b951c6c7SDouglas Anderson dev_err(hsotg->dev, 1340b951c6c7SDouglas Anderson "%s: Periodic xfer length %d > max xfer length for channel %d\n", 1341b951c6c7SDouglas Anderson __func__, max_xfer_size, max_channel_xfer_size); 1342b951c6c7SDouglas Anderson status = -ENOSPC; 1343b951c6c7SDouglas Anderson } 1344b951c6c7SDouglas Anderson 1345b951c6c7SDouglas Anderson return status; 1346b951c6c7SDouglas Anderson } 1347b951c6c7SDouglas Anderson 1348b951c6c7SDouglas Anderson /** 1349b951c6c7SDouglas Anderson * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 1350b951c6c7SDouglas Anderson * the periodic schedule 1351b951c6c7SDouglas Anderson * 1352b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 1353b951c6c7SDouglas Anderson * @qh: QH for the periodic transfer. The QH should already contain the 1354b951c6c7SDouglas Anderson * scheduling information. 1355b951c6c7SDouglas Anderson * 1356b951c6c7SDouglas Anderson * Return: 0 if successful, negative error code otherwise 1357b951c6c7SDouglas Anderson */ 1358b951c6c7SDouglas Anderson static int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1359b951c6c7SDouglas Anderson { 1360b951c6c7SDouglas Anderson int status; 1361b951c6c7SDouglas Anderson 1362b951c6c7SDouglas Anderson status = dwc2_check_max_xfer_size(hsotg, qh); 1363b951c6c7SDouglas Anderson if (status) { 1364b951c6c7SDouglas Anderson dev_dbg(hsotg->dev, 1365b951c6c7SDouglas Anderson "%s: Channel max transfer size too small for periodic transfer\n", 1366b951c6c7SDouglas Anderson __func__); 1367b951c6c7SDouglas Anderson return status; 1368b951c6c7SDouglas Anderson } 1369b951c6c7SDouglas Anderson 1370b951c6c7SDouglas Anderson /* Cancel pending unreserve; if canceled OK, unreserve was pending */ 1371b951c6c7SDouglas Anderson if (del_timer(&qh->unreserve_timer)) 1372b951c6c7SDouglas Anderson WARN_ON(!qh->unreserve_pending); 1373b951c6c7SDouglas Anderson 1374b951c6c7SDouglas Anderson /* 1375b951c6c7SDouglas Anderson * Only need to reserve if there's not an unreserve pending, since if an 1376b951c6c7SDouglas Anderson * unreserve is pending then by definition our old reservation is still 1377b951c6c7SDouglas Anderson * valid. Unreserve might still be pending even if we didn't cancel if 1378b951c6c7SDouglas Anderson * dwc2_unreserve_timer_fn() already started. Code in the timer handles 1379b951c6c7SDouglas Anderson * that case. 1380b951c6c7SDouglas Anderson */ 1381b951c6c7SDouglas Anderson if (!qh->unreserve_pending) { 13822d3f1398SDouglas Anderson status = dwc2_do_reserve(hsotg, qh); 13832d3f1398SDouglas Anderson if (status) 1384b951c6c7SDouglas Anderson return status; 1385fb616e3fSDouglas Anderson } else { 1386fb616e3fSDouglas Anderson /* 1387fb616e3fSDouglas Anderson * It might have been a while, so make sure that frame_number 1388fb616e3fSDouglas Anderson * is still good. Note: we could also try to use the similar 1389fb616e3fSDouglas Anderson * dwc2_next_periodic_start() but that schedules much more 1390fb616e3fSDouglas Anderson * tightly and we might need to hurry and queue things up. 1391fb616e3fSDouglas Anderson */ 1392fb616e3fSDouglas Anderson if (dwc2_frame_num_le(qh->next_active_frame, 1393fb616e3fSDouglas Anderson hsotg->frame_number)) 1394fb616e3fSDouglas Anderson dwc2_pick_first_frame(hsotg, qh); 1395b951c6c7SDouglas Anderson } 1396b951c6c7SDouglas Anderson 1397b951c6c7SDouglas Anderson qh->unreserve_pending = 0; 1398b951c6c7SDouglas Anderson 139995832c00SJohn Youn if (hsotg->params.dma_desc_enable) 1400b951c6c7SDouglas Anderson /* Don't rely on SOF and start in ready schedule */ 1401b951c6c7SDouglas Anderson list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready); 1402b951c6c7SDouglas Anderson else 1403b951c6c7SDouglas Anderson /* Always start in inactive schedule */ 1404b951c6c7SDouglas Anderson list_add_tail(&qh->qh_list_entry, 1405b951c6c7SDouglas Anderson &hsotg->periodic_sched_inactive); 1406b951c6c7SDouglas Anderson 14072d3f1398SDouglas Anderson return 0; 1408b951c6c7SDouglas Anderson } 1409b951c6c7SDouglas Anderson 1410b951c6c7SDouglas Anderson /** 1411b951c6c7SDouglas Anderson * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 1412b951c6c7SDouglas Anderson * from the periodic schedule 1413b951c6c7SDouglas Anderson * 1414b951c6c7SDouglas Anderson * @hsotg: The HCD state structure for the DWC OTG controller 1415b951c6c7SDouglas Anderson * @qh: QH for the periodic transfer 1416b951c6c7SDouglas Anderson */ 1417b951c6c7SDouglas Anderson static void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 1418b951c6c7SDouglas Anderson struct dwc2_qh *qh) 1419b951c6c7SDouglas Anderson { 1420b951c6c7SDouglas Anderson bool did_modify; 1421b951c6c7SDouglas Anderson 1422b951c6c7SDouglas Anderson assert_spin_locked(&hsotg->lock); 1423b951c6c7SDouglas Anderson 1424b951c6c7SDouglas Anderson /* 1425b951c6c7SDouglas Anderson * Schedule the unreserve to happen in a little bit. Cases here: 1426b951c6c7SDouglas Anderson * - Unreserve worker might be sitting there waiting to grab the lock. 1427b951c6c7SDouglas Anderson * In this case it will notice it's been schedule again and will 1428b951c6c7SDouglas Anderson * quit. 1429b951c6c7SDouglas Anderson * - Unreserve worker might not be scheduled. 1430b951c6c7SDouglas Anderson * 1431b951c6c7SDouglas Anderson * We should never already be scheduled since dwc2_schedule_periodic() 1432b951c6c7SDouglas Anderson * should have canceled the scheduled unreserve timer (hence the 1433b951c6c7SDouglas Anderson * warning on did_modify). 1434b951c6c7SDouglas Anderson * 1435b951c6c7SDouglas Anderson * We add + 1 to the timer to guarantee that at least 1 jiffy has 1436b951c6c7SDouglas Anderson * passed (otherwise if the jiffy counter might tick right after we 1437b951c6c7SDouglas Anderson * read it and we'll get no delay). 1438b951c6c7SDouglas Anderson */ 1439b951c6c7SDouglas Anderson did_modify = mod_timer(&qh->unreserve_timer, 1440b951c6c7SDouglas Anderson jiffies + DWC2_UNRESERVE_DELAY + 1); 1441b951c6c7SDouglas Anderson WARN_ON(did_modify); 1442b951c6c7SDouglas Anderson qh->unreserve_pending = 1; 1443b951c6c7SDouglas Anderson 1444b951c6c7SDouglas Anderson list_del_init(&qh->qh_list_entry); 1445b951c6c7SDouglas Anderson } 1446b951c6c7SDouglas Anderson 1447b951c6c7SDouglas Anderson /** 144838d2b5fbSDouglas Anderson * dwc2_wait_timer_fn() - Timer function to re-queue after waiting 144938d2b5fbSDouglas Anderson * 145038d2b5fbSDouglas Anderson * As per the spec, a NAK indicates that "a function is temporarily unable to 145138d2b5fbSDouglas Anderson * transmit or receive data, but will eventually be able to do so without need 145238d2b5fbSDouglas Anderson * of host intervention". 145338d2b5fbSDouglas Anderson * 145438d2b5fbSDouglas Anderson * That means that when we encounter a NAK we're supposed to retry. 145538d2b5fbSDouglas Anderson * 145638d2b5fbSDouglas Anderson * ...but if we retry right away (from the interrupt handler that saw the NAK) 145738d2b5fbSDouglas Anderson * then we can end up with an interrupt storm (if the other side keeps NAKing 145838d2b5fbSDouglas Anderson * us) because on slow enough CPUs it could take us longer to get out of the 145938d2b5fbSDouglas Anderson * interrupt routine than it takes for the device to send another NAK. That 146038d2b5fbSDouglas Anderson * leads to a constant stream of NAK interrupts and the CPU locks. 146138d2b5fbSDouglas Anderson * 146238d2b5fbSDouglas Anderson * ...so instead of retrying right away in the case of a NAK we'll set a timer 146338d2b5fbSDouglas Anderson * to retry some time later. This function handles that timer and moves the 146438d2b5fbSDouglas Anderson * qh back to the "inactive" list, then queues transactions. 146538d2b5fbSDouglas Anderson * 146638d2b5fbSDouglas Anderson * @t: Pointer to wait_timer in a qh. 14676ed30a7dSTerin Stock * 14686ed30a7dSTerin Stock * Return: HRTIMER_NORESTART to not automatically restart this timer. 146938d2b5fbSDouglas Anderson */ 14706ed30a7dSTerin Stock static enum hrtimer_restart dwc2_wait_timer_fn(struct hrtimer *t) 147138d2b5fbSDouglas Anderson { 14726ed30a7dSTerin Stock struct dwc2_qh *qh = container_of(t, struct dwc2_qh, wait_timer); 147338d2b5fbSDouglas Anderson struct dwc2_hsotg *hsotg = qh->hsotg; 147438d2b5fbSDouglas Anderson unsigned long flags; 147538d2b5fbSDouglas Anderson 147638d2b5fbSDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags); 147738d2b5fbSDouglas Anderson 147838d2b5fbSDouglas Anderson /* 147938d2b5fbSDouglas Anderson * We'll set wait_timer_cancel to true if we want to cancel this 148038d2b5fbSDouglas Anderson * operation in dwc2_hcd_qh_unlink(). 148138d2b5fbSDouglas Anderson */ 148238d2b5fbSDouglas Anderson if (!qh->wait_timer_cancel) { 148338d2b5fbSDouglas Anderson enum dwc2_transaction_type tr_type; 148438d2b5fbSDouglas Anderson 148538d2b5fbSDouglas Anderson qh->want_wait = false; 148638d2b5fbSDouglas Anderson 148738d2b5fbSDouglas Anderson list_move(&qh->qh_list_entry, 148838d2b5fbSDouglas Anderson &hsotg->non_periodic_sched_inactive); 148938d2b5fbSDouglas Anderson 149038d2b5fbSDouglas Anderson tr_type = dwc2_hcd_select_transactions(hsotg); 149138d2b5fbSDouglas Anderson if (tr_type != DWC2_TRANSACTION_NONE) 149238d2b5fbSDouglas Anderson dwc2_hcd_queue_transactions(hsotg, tr_type); 149338d2b5fbSDouglas Anderson } 149438d2b5fbSDouglas Anderson 149538d2b5fbSDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags); 14966ed30a7dSTerin Stock return HRTIMER_NORESTART; 149738d2b5fbSDouglas Anderson } 149838d2b5fbSDouglas Anderson 149938d2b5fbSDouglas Anderson /** 1500197ba5f4SPaul Zimmerman * dwc2_qh_init() - Initializes a QH structure 1501197ba5f4SPaul Zimmerman * 1502197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller 1503197ba5f4SPaul Zimmerman * @qh: The QH to init 1504197ba5f4SPaul Zimmerman * @urb: Holds the information about the device/endpoint needed to initialize 1505197ba5f4SPaul Zimmerman * the QH 15069f9f09b0SDouglas Anderson * @mem_flags: Flags for allocating memory. 1507197ba5f4SPaul Zimmerman */ 1508197ba5f4SPaul Zimmerman static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 15099f9f09b0SDouglas Anderson struct dwc2_hcd_urb *urb, gfp_t mem_flags) 1510197ba5f4SPaul Zimmerman { 15119f9f09b0SDouglas Anderson int dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 15129f9f09b0SDouglas Anderson u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 15139f9f09b0SDouglas Anderson bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); 15149f9f09b0SDouglas Anderson bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); 15159f9f09b0SDouglas Anderson bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); 1516f25c42b8SGevorg Sahakyan u32 hprt = dwc2_readl(hsotg, HPRT0); 15179f9f09b0SDouglas Anderson u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 15189f9f09b0SDouglas Anderson bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && 15199f9f09b0SDouglas Anderson dev_speed != USB_SPEED_HIGH); 1520babd1839SDouglas Anderson int maxp = dwc2_hcd_get_maxp(&urb->pipe_info); 1521babd1839SDouglas Anderson int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info); 1522babd1839SDouglas Anderson int bytecount = maxp_mult * maxp; 1523197ba5f4SPaul Zimmerman char *speed, *type; 1524197ba5f4SPaul Zimmerman 1525197ba5f4SPaul Zimmerman /* Initialize QH */ 152617dd5b64SDouglas Anderson qh->hsotg = hsotg; 1527e99e88a9SKees Cook timer_setup(&qh->unreserve_timer, dwc2_unreserve_timer_fn, 0); 15286ed30a7dSTerin Stock hrtimer_init(&qh->wait_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 15296ed30a7dSTerin Stock qh->wait_timer.function = &dwc2_wait_timer_fn; 15309f9f09b0SDouglas Anderson qh->ep_type = ep_type; 15319f9f09b0SDouglas Anderson qh->ep_is_in = ep_is_in; 1532197ba5f4SPaul Zimmerman 1533197ba5f4SPaul Zimmerman qh->data_toggle = DWC2_HC_PID_DATA0; 15349f9f09b0SDouglas Anderson qh->maxp = maxp; 1535babd1839SDouglas Anderson qh->maxp_mult = maxp_mult; 1536197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&qh->qtd_list); 1537197ba5f4SPaul Zimmerman INIT_LIST_HEAD(&qh->qh_list_entry); 1538197ba5f4SPaul Zimmerman 15399f9f09b0SDouglas Anderson qh->do_split = do_split; 1540197ba5f4SPaul Zimmerman qh->dev_speed = dev_speed; 1541197ba5f4SPaul Zimmerman 15429f9f09b0SDouglas Anderson if (ep_is_int || ep_is_isoc) { 15439f9f09b0SDouglas Anderson /* Compute scheduling parameters once and save them */ 15449f9f09b0SDouglas Anderson int host_speed = do_split ? USB_SPEED_HIGH : dev_speed; 15459f9f09b0SDouglas Anderson struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv, 15469f9f09b0SDouglas Anderson mem_flags, 15479f9f09b0SDouglas Anderson &qh->ttport); 15489f9f09b0SDouglas Anderson int device_ns; 15499f9f09b0SDouglas Anderson 15509f9f09b0SDouglas Anderson qh->dwc_tt = dwc_tt; 15519f9f09b0SDouglas Anderson 15529f9f09b0SDouglas Anderson qh->host_us = NS_TO_US(usb_calc_bus_time(host_speed, ep_is_in, 15539f9f09b0SDouglas Anderson ep_is_isoc, bytecount)); 15549f9f09b0SDouglas Anderson device_ns = usb_calc_bus_time(dev_speed, ep_is_in, 15559f9f09b0SDouglas Anderson ep_is_isoc, bytecount); 15569f9f09b0SDouglas Anderson 15579f9f09b0SDouglas Anderson if (do_split && dwc_tt) 15589f9f09b0SDouglas Anderson device_ns += dwc_tt->usb_tt->think_time; 15599f9f09b0SDouglas Anderson qh->device_us = NS_TO_US(device_ns); 15609f9f09b0SDouglas Anderson 15619f9f09b0SDouglas Anderson qh->device_interval = urb->interval; 15629f9f09b0SDouglas Anderson qh->host_interval = urb->interval * (do_split ? 8 : 1); 15639f9f09b0SDouglas Anderson 15649f9f09b0SDouglas Anderson /* 15659f9f09b0SDouglas Anderson * Schedule low speed if we're running the host in low or 15669f9f09b0SDouglas Anderson * full speed OR if we've got a "TT" to deal with to access this 15679f9f09b0SDouglas Anderson * device. 15689f9f09b0SDouglas Anderson */ 15699f9f09b0SDouglas Anderson qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED || 15709f9f09b0SDouglas Anderson dwc_tt; 15719f9f09b0SDouglas Anderson 15729f9f09b0SDouglas Anderson if (do_split) { 15739f9f09b0SDouglas Anderson /* We won't know num transfers until we schedule */ 15749f9f09b0SDouglas Anderson qh->num_hs_transfers = -1; 15759f9f09b0SDouglas Anderson } else if (dev_speed == USB_SPEED_HIGH) { 15769f9f09b0SDouglas Anderson qh->num_hs_transfers = 1; 15779f9f09b0SDouglas Anderson } else { 15789f9f09b0SDouglas Anderson qh->num_hs_transfers = 0; 15799f9f09b0SDouglas Anderson } 15809f9f09b0SDouglas Anderson 15819f9f09b0SDouglas Anderson /* We'll schedule later when we have something to do */ 15829f9f09b0SDouglas Anderson } 15839f9f09b0SDouglas Anderson 1584197ba5f4SPaul Zimmerman switch (dev_speed) { 1585197ba5f4SPaul Zimmerman case USB_SPEED_LOW: 1586197ba5f4SPaul Zimmerman speed = "low"; 1587197ba5f4SPaul Zimmerman break; 1588197ba5f4SPaul Zimmerman case USB_SPEED_FULL: 1589197ba5f4SPaul Zimmerman speed = "full"; 1590197ba5f4SPaul Zimmerman break; 1591197ba5f4SPaul Zimmerman case USB_SPEED_HIGH: 1592197ba5f4SPaul Zimmerman speed = "high"; 1593197ba5f4SPaul Zimmerman break; 1594197ba5f4SPaul Zimmerman default: 1595197ba5f4SPaul Zimmerman speed = "?"; 1596197ba5f4SPaul Zimmerman break; 1597197ba5f4SPaul Zimmerman } 1598197ba5f4SPaul Zimmerman 1599197ba5f4SPaul Zimmerman switch (qh->ep_type) { 1600197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_ISOC: 1601197ba5f4SPaul Zimmerman type = "isochronous"; 1602197ba5f4SPaul Zimmerman break; 1603197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_INT: 1604197ba5f4SPaul Zimmerman type = "interrupt"; 1605197ba5f4SPaul Zimmerman break; 1606197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_CONTROL: 1607197ba5f4SPaul Zimmerman type = "control"; 1608197ba5f4SPaul Zimmerman break; 1609197ba5f4SPaul Zimmerman case USB_ENDPOINT_XFER_BULK: 1610197ba5f4SPaul Zimmerman type = "bulk"; 1611197ba5f4SPaul Zimmerman break; 1612197ba5f4SPaul Zimmerman default: 1613197ba5f4SPaul Zimmerman type = "?"; 1614197ba5f4SPaul Zimmerman break; 1615197ba5f4SPaul Zimmerman } 1616197ba5f4SPaul Zimmerman 16179f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type, 16189f9f09b0SDouglas Anderson speed, bytecount); 16199f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh, 16209f9f09b0SDouglas Anderson dwc2_hcd_get_dev_addr(&urb->pipe_info), 16219f9f09b0SDouglas Anderson dwc2_hcd_get_ep_num(&urb->pipe_info), 16229f9f09b0SDouglas Anderson ep_is_in ? "IN" : "OUT"); 16239f9f09b0SDouglas Anderson if (ep_is_int || ep_is_isoc) { 16249f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, 16259f9f09b0SDouglas Anderson "QH=%p ...duration: host=%d us, device=%d us\n", 16269f9f09b0SDouglas Anderson qh, qh->host_us, qh->device_us); 16279f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n", 16289f9f09b0SDouglas Anderson qh, qh->host_interval, qh->device_interval); 16299f9f09b0SDouglas Anderson if (qh->schedule_low_speed) 16309f9f09b0SDouglas Anderson dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n", 16319f9f09b0SDouglas Anderson qh, dwc2_get_ls_map(hsotg, qh)); 1632197ba5f4SPaul Zimmerman } 1633197ba5f4SPaul Zimmerman } 1634197ba5f4SPaul Zimmerman 1635197ba5f4SPaul Zimmerman /** 1636197ba5f4SPaul Zimmerman * dwc2_hcd_qh_create() - Allocates and initializes a QH 1637197ba5f4SPaul Zimmerman * 1638197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller 1639197ba5f4SPaul Zimmerman * @urb: Holds the information about the device/endpoint needed 1640197ba5f4SPaul Zimmerman * to initialize the QH 16416fb914d7SGrigor Tovmasyan * @mem_flags: Flags for allocating memory. 1642197ba5f4SPaul Zimmerman * 1643197ba5f4SPaul Zimmerman * Return: Pointer to the newly allocated QH, or NULL on error 1644197ba5f4SPaul Zimmerman */ 1645b58e6ceeSMian Yousaf Kaukab struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 1646197ba5f4SPaul Zimmerman struct dwc2_hcd_urb *urb, 1647197ba5f4SPaul Zimmerman gfp_t mem_flags) 1648197ba5f4SPaul Zimmerman { 1649197ba5f4SPaul Zimmerman struct dwc2_qh *qh; 1650197ba5f4SPaul Zimmerman 1651197ba5f4SPaul Zimmerman if (!urb->priv) 1652197ba5f4SPaul Zimmerman return NULL; 1653197ba5f4SPaul Zimmerman 1654197ba5f4SPaul Zimmerman /* Allocate memory */ 1655197ba5f4SPaul Zimmerman qh = kzalloc(sizeof(*qh), mem_flags); 1656197ba5f4SPaul Zimmerman if (!qh) 1657197ba5f4SPaul Zimmerman return NULL; 1658197ba5f4SPaul Zimmerman 16599f9f09b0SDouglas Anderson dwc2_qh_init(hsotg, qh, urb, mem_flags); 1660197ba5f4SPaul Zimmerman 166195832c00SJohn Youn if (hsotg->params.dma_desc_enable && 1662197ba5f4SPaul Zimmerman dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 1663197ba5f4SPaul Zimmerman dwc2_hcd_qh_free(hsotg, qh); 1664197ba5f4SPaul Zimmerman return NULL; 1665197ba5f4SPaul Zimmerman } 1666197ba5f4SPaul Zimmerman 1667197ba5f4SPaul Zimmerman return qh; 1668197ba5f4SPaul Zimmerman } 1669197ba5f4SPaul Zimmerman 1670197ba5f4SPaul Zimmerman /** 1671197ba5f4SPaul Zimmerman * dwc2_hcd_qh_free() - Frees the QH 1672197ba5f4SPaul Zimmerman * 1673197ba5f4SPaul Zimmerman * @hsotg: HCD instance 1674197ba5f4SPaul Zimmerman * @qh: The QH to free 1675197ba5f4SPaul Zimmerman * 1676197ba5f4SPaul Zimmerman * QH should already be removed from the list. QTD list should already be empty 1677197ba5f4SPaul Zimmerman * if called from URB Dequeue. 1678197ba5f4SPaul Zimmerman * 1679197ba5f4SPaul Zimmerman * Must NOT be called with interrupt disabled or spinlock held 1680197ba5f4SPaul Zimmerman */ 1681197ba5f4SPaul Zimmerman void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1682197ba5f4SPaul Zimmerman { 168317dd5b64SDouglas Anderson /* Make sure any unreserve work is finished. */ 168417dd5b64SDouglas Anderson if (del_timer_sync(&qh->unreserve_timer)) { 168517dd5b64SDouglas Anderson unsigned long flags; 168617dd5b64SDouglas Anderson 168717dd5b64SDouglas Anderson spin_lock_irqsave(&hsotg->lock, flags); 168817dd5b64SDouglas Anderson dwc2_do_unreserve(hsotg, qh); 168917dd5b64SDouglas Anderson spin_unlock_irqrestore(&hsotg->lock, flags); 169017dd5b64SDouglas Anderson } 169138d2b5fbSDouglas Anderson 169238d2b5fbSDouglas Anderson /* 169338d2b5fbSDouglas Anderson * We don't have the lock so we can safely wait until the wait timer 169438d2b5fbSDouglas Anderson * finishes. Of course, at this point in time we'd better have set 169538d2b5fbSDouglas Anderson * wait_timer_active to false so if this timer was still pending it 169638d2b5fbSDouglas Anderson * won't do anything anyway, but we want it to finish before we free 169738d2b5fbSDouglas Anderson * memory. 169838d2b5fbSDouglas Anderson */ 16996ed30a7dSTerin Stock hrtimer_cancel(&qh->wait_timer); 170038d2b5fbSDouglas Anderson 17019f9f09b0SDouglas Anderson dwc2_host_put_tt_info(hsotg, qh->dwc_tt); 170217dd5b64SDouglas Anderson 17033bc04e28SDouglas Anderson if (qh->desc_list) 1704197ba5f4SPaul Zimmerman dwc2_hcd_qh_free_ddma(hsotg, qh); 1705af424a41SWilliam Wu else if (hsotg->unaligned_cache && qh->dw_align_buf) 1706af424a41SWilliam Wu kmem_cache_free(hsotg->unaligned_cache, qh->dw_align_buf); 1707af424a41SWilliam Wu 1708197ba5f4SPaul Zimmerman kfree(qh); 1709197ba5f4SPaul Zimmerman } 1710197ba5f4SPaul Zimmerman 1711197ba5f4SPaul Zimmerman /** 1712197ba5f4SPaul Zimmerman * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 1713197ba5f4SPaul Zimmerman * schedule if it is not already in the schedule. If the QH is already in 1714197ba5f4SPaul Zimmerman * the schedule, no action is taken. 1715197ba5f4SPaul Zimmerman * 1716197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure for the DWC OTG controller 1717197ba5f4SPaul Zimmerman * @qh: The QH to add 1718197ba5f4SPaul Zimmerman * 1719197ba5f4SPaul Zimmerman * Return: 0 if successful, negative error code otherwise 1720197ba5f4SPaul Zimmerman */ 1721197ba5f4SPaul Zimmerman int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1722197ba5f4SPaul Zimmerman { 1723197ba5f4SPaul Zimmerman int status; 1724197ba5f4SPaul Zimmerman u32 intr_mask; 17256ed30a7dSTerin Stock ktime_t delay; 1726197ba5f4SPaul Zimmerman 1727197ba5f4SPaul Zimmerman if (dbg_qh(qh)) 1728197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__); 1729197ba5f4SPaul Zimmerman 1730197ba5f4SPaul Zimmerman if (!list_empty(&qh->qh_list_entry)) 1731197ba5f4SPaul Zimmerman /* QH already in a schedule */ 1732197ba5f4SPaul Zimmerman return 0; 1733197ba5f4SPaul Zimmerman 1734197ba5f4SPaul Zimmerman /* Add the new QH to the appropriate schedule */ 1735197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) { 1736fb616e3fSDouglas Anderson /* Schedule right away */ 1737fb616e3fSDouglas Anderson qh->start_active_frame = hsotg->frame_number; 1738fb616e3fSDouglas Anderson qh->next_active_frame = qh->start_active_frame; 1739fb616e3fSDouglas Anderson 174038d2b5fbSDouglas Anderson if (qh->want_wait) { 174138d2b5fbSDouglas Anderson list_add_tail(&qh->qh_list_entry, 174238d2b5fbSDouglas Anderson &hsotg->non_periodic_sched_waiting); 174338d2b5fbSDouglas Anderson qh->wait_timer_cancel = false; 17446ed30a7dSTerin Stock delay = ktime_set(0, DWC2_RETRY_WAIT_DELAY); 17456ed30a7dSTerin Stock hrtimer_start(&qh->wait_timer, delay, HRTIMER_MODE_REL); 174638d2b5fbSDouglas Anderson } else { 1747197ba5f4SPaul Zimmerman list_add_tail(&qh->qh_list_entry, 1748197ba5f4SPaul Zimmerman &hsotg->non_periodic_sched_inactive); 174938d2b5fbSDouglas Anderson } 1750197ba5f4SPaul Zimmerman return 0; 1751197ba5f4SPaul Zimmerman } 1752197ba5f4SPaul Zimmerman 1753197ba5f4SPaul Zimmerman status = dwc2_schedule_periodic(hsotg, qh); 1754197ba5f4SPaul Zimmerman if (status) 1755197ba5f4SPaul Zimmerman return status; 1756197ba5f4SPaul Zimmerman if (!hsotg->periodic_qh_count) { 1757f25c42b8SGevorg Sahakyan intr_mask = dwc2_readl(hsotg, GINTMSK); 1758197ba5f4SPaul Zimmerman intr_mask |= GINTSTS_SOF; 1759f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, intr_mask, GINTMSK); 1760197ba5f4SPaul Zimmerman } 1761197ba5f4SPaul Zimmerman hsotg->periodic_qh_count++; 1762197ba5f4SPaul Zimmerman 1763197ba5f4SPaul Zimmerman return 0; 1764197ba5f4SPaul Zimmerman } 1765197ba5f4SPaul Zimmerman 1766197ba5f4SPaul Zimmerman /** 1767197ba5f4SPaul Zimmerman * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 1768197ba5f4SPaul Zimmerman * schedule. Memory is not freed. 1769197ba5f4SPaul Zimmerman * 1770197ba5f4SPaul Zimmerman * @hsotg: The HCD state structure 1771197ba5f4SPaul Zimmerman * @qh: QH to remove from schedule 1772197ba5f4SPaul Zimmerman */ 1773197ba5f4SPaul Zimmerman void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 1774197ba5f4SPaul Zimmerman { 1775197ba5f4SPaul Zimmerman u32 intr_mask; 1776197ba5f4SPaul Zimmerman 1777197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__); 1778197ba5f4SPaul Zimmerman 177938d2b5fbSDouglas Anderson /* If the wait_timer is pending, this will stop it from acting */ 178038d2b5fbSDouglas Anderson qh->wait_timer_cancel = true; 178138d2b5fbSDouglas Anderson 1782197ba5f4SPaul Zimmerman if (list_empty(&qh->qh_list_entry)) 1783197ba5f4SPaul Zimmerman /* QH is not in a schedule */ 1784197ba5f4SPaul Zimmerman return; 1785197ba5f4SPaul Zimmerman 1786197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) { 1787197ba5f4SPaul Zimmerman if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry) 1788197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr = 1789197ba5f4SPaul Zimmerman hsotg->non_periodic_qh_ptr->next; 1790197ba5f4SPaul Zimmerman list_del_init(&qh->qh_list_entry); 1791197ba5f4SPaul Zimmerman return; 1792197ba5f4SPaul Zimmerman } 1793197ba5f4SPaul Zimmerman 1794197ba5f4SPaul Zimmerman dwc2_deschedule_periodic(hsotg, qh); 1795197ba5f4SPaul Zimmerman hsotg->periodic_qh_count--; 1796907a4447SSevak Arakelyan if (!hsotg->periodic_qh_count && 179795832c00SJohn Youn !hsotg->params.dma_desc_enable) { 1798f25c42b8SGevorg Sahakyan intr_mask = dwc2_readl(hsotg, GINTMSK); 1799197ba5f4SPaul Zimmerman intr_mask &= ~GINTSTS_SOF; 1800f25c42b8SGevorg Sahakyan dwc2_writel(hsotg, intr_mask, GINTMSK); 1801197ba5f4SPaul Zimmerman } 1802197ba5f4SPaul Zimmerman } 1803197ba5f4SPaul Zimmerman 1804fb616e3fSDouglas Anderson /** 1805fb616e3fSDouglas Anderson * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split. 1806fb616e3fSDouglas Anderson * 1807fb616e3fSDouglas Anderson * This is called for setting next_active_frame for periodic splits for all but 1808fb616e3fSDouglas Anderson * the first packet of the split. Confusing? I thought so... 1809fb616e3fSDouglas Anderson * 1810fb616e3fSDouglas Anderson * Periodic splits are single low/full speed transfers that we end up splitting 1811fb616e3fSDouglas Anderson * up into several high speed transfers. They always fit into one full (1 ms) 1812fb616e3fSDouglas Anderson * frame but might be split over several microframes (125 us each). We to put 1813fb616e3fSDouglas Anderson * each of the parts on a very specific high speed frame. 1814fb616e3fSDouglas Anderson * 1815fb616e3fSDouglas Anderson * This function figures out where the next active uFrame needs to be. 1816fb616e3fSDouglas Anderson * 1817fb616e3fSDouglas Anderson * @hsotg: The HCD state structure 1818fb616e3fSDouglas Anderson * @qh: QH for the periodic transfer. 1819fb616e3fSDouglas Anderson * @frame_number: The current frame number. 1820fb616e3fSDouglas Anderson * 1821fb616e3fSDouglas Anderson * Return: number missed by (or 0 if we didn't miss). 1822197ba5f4SPaul Zimmerman */ 1823fb616e3fSDouglas Anderson static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg, 1824fb616e3fSDouglas Anderson struct dwc2_qh *qh, u16 frame_number) 1825197ba5f4SPaul Zimmerman { 1826ced9eee1SDouglas Anderson u16 old_frame = qh->next_active_frame; 1827fb616e3fSDouglas Anderson u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1828fb616e3fSDouglas Anderson int missed = 0; 1829fb616e3fSDouglas Anderson u16 incr; 1830197ba5f4SPaul Zimmerman 1831197ba5f4SPaul Zimmerman /* 18329f9f09b0SDouglas Anderson * See dwc2_uframe_schedule_split() for split scheduling. 18339f9f09b0SDouglas Anderson * 1834fb616e3fSDouglas Anderson * Basically: increment 1 normally, but 2 right after the start split 1835fb616e3fSDouglas Anderson * (except for ISOC out). 1836197ba5f4SPaul Zimmerman */ 1837fb616e3fSDouglas Anderson if (old_frame == qh->start_active_frame && 1838fb616e3fSDouglas Anderson !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)) 1839fb616e3fSDouglas Anderson incr = 2; 1840fb616e3fSDouglas Anderson else 1841fb616e3fSDouglas Anderson incr = 1; 1842fb616e3fSDouglas Anderson 1843fb616e3fSDouglas Anderson qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr); 1844fb616e3fSDouglas Anderson 1845fb616e3fSDouglas Anderson /* 1846fb616e3fSDouglas Anderson * Note that it's OK for frame_number to be 1 frame past 1847fb616e3fSDouglas Anderson * next_active_frame. Remember that next_active_frame is supposed to 1848fb616e3fSDouglas Anderson * be 1 frame _before_ when we want to be scheduled. If we're 1 frame 1849fb616e3fSDouglas Anderson * past it just means schedule ASAP. 1850fb616e3fSDouglas Anderson * 1851fb616e3fSDouglas Anderson * It's _not_ OK, however, if we're more than one frame past. 1852fb616e3fSDouglas Anderson */ 1853fb616e3fSDouglas Anderson if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) { 1854fb616e3fSDouglas Anderson /* 1855fb616e3fSDouglas Anderson * OOPS, we missed. That's actually pretty bad since 1856fb616e3fSDouglas Anderson * the hub will be unhappy; try ASAP I guess. 1857fb616e3fSDouglas Anderson */ 1858fb616e3fSDouglas Anderson missed = dwc2_frame_num_dec(prev_frame_number, 1859fb616e3fSDouglas Anderson qh->next_active_frame); 1860ced9eee1SDouglas Anderson qh->next_active_frame = frame_number; 1861197ba5f4SPaul Zimmerman } 186274fc4a75SDouglas Anderson 1863fb616e3fSDouglas Anderson return missed; 1864fb616e3fSDouglas Anderson } 1865fb616e3fSDouglas Anderson 1866fb616e3fSDouglas Anderson /** 1867fb616e3fSDouglas Anderson * dwc2_next_periodic_start() - Set next_active_frame for next transfer start 1868fb616e3fSDouglas Anderson * 1869fb616e3fSDouglas Anderson * This is called for setting next_active_frame for a periodic transfer for 1870fb616e3fSDouglas Anderson * all cases other than midway through a periodic split. This will also update 1871fb616e3fSDouglas Anderson * start_active_frame. 1872fb616e3fSDouglas Anderson * 1873fb616e3fSDouglas Anderson * Since we _always_ keep start_active_frame as the start of the previous 1874fb616e3fSDouglas Anderson * transfer this is normally pretty easy: we just add our interval to 1875fb616e3fSDouglas Anderson * start_active_frame and we've got our answer. 1876fb616e3fSDouglas Anderson * 1877fb616e3fSDouglas Anderson * The tricks come into play if we miss. In that case we'll look for the next 1878fb616e3fSDouglas Anderson * slot we can fit into. 1879fb616e3fSDouglas Anderson * 1880fb616e3fSDouglas Anderson * @hsotg: The HCD state structure 1881fb616e3fSDouglas Anderson * @qh: QH for the periodic transfer. 1882fb616e3fSDouglas Anderson * @frame_number: The current frame number. 1883fb616e3fSDouglas Anderson * 1884fb616e3fSDouglas Anderson * Return: number missed by (or 0 if we didn't miss). 1885fb616e3fSDouglas Anderson */ 1886fb616e3fSDouglas Anderson static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg, 1887fb616e3fSDouglas Anderson struct dwc2_qh *qh, u16 frame_number) 1888fb616e3fSDouglas Anderson { 1889fb616e3fSDouglas Anderson int missed = 0; 1890fb616e3fSDouglas Anderson u16 interval = qh->host_interval; 1891fb616e3fSDouglas Anderson u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1); 1892fb616e3fSDouglas Anderson 1893fb616e3fSDouglas Anderson qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame, 1894fb616e3fSDouglas Anderson interval); 1895fb616e3fSDouglas Anderson 1896fb616e3fSDouglas Anderson /* 1897fb616e3fSDouglas Anderson * The dwc2_frame_num_gt() function used below won't work terribly well 1898fb616e3fSDouglas Anderson * with if we just incremented by a really large intervals since the 1899fb616e3fSDouglas Anderson * frame counter only goes to 0x3fff. It's terribly unlikely that we 1900fb616e3fSDouglas Anderson * will have missed in this case anyway. Just go to exit. If we want 1901fb616e3fSDouglas Anderson * to try to do better we'll need to keep track of a bigger counter 1902fb616e3fSDouglas Anderson * somewhere in the driver and handle overflows. 1903fb616e3fSDouglas Anderson */ 1904fb616e3fSDouglas Anderson if (interval >= 0x1000) 1905fb616e3fSDouglas Anderson goto exit; 1906fb616e3fSDouglas Anderson 1907fb616e3fSDouglas Anderson /* 1908fb616e3fSDouglas Anderson * Test for misses, which is when it's too late to schedule. 1909fb616e3fSDouglas Anderson * 1910fb616e3fSDouglas Anderson * A few things to note: 1911fb616e3fSDouglas Anderson * - We compare against prev_frame_number since start_active_frame 1912fb616e3fSDouglas Anderson * and next_active_frame are always 1 frame before we want things 1913fb616e3fSDouglas Anderson * to be active and we assume we can still get scheduled in the 1914fb616e3fSDouglas Anderson * current frame number. 19159cf1a601SDouglas Anderson * - It's possible for start_active_frame (now incremented) to be 19169cf1a601SDouglas Anderson * next_active_frame if we got an EO MISS (even_odd miss) which 19179cf1a601SDouglas Anderson * basically means that we detected there wasn't enough time for 19189cf1a601SDouglas Anderson * the last packet and dwc2_hc_set_even_odd_frame() rescheduled us 19199cf1a601SDouglas Anderson * at the last second. We want to make sure we don't schedule 19209cf1a601SDouglas Anderson * another transfer for the same frame. My test webcam doesn't seem 19219cf1a601SDouglas Anderson * terribly upset by missing a transfer but really doesn't like when 19229cf1a601SDouglas Anderson * we do two transfers in the same frame. 1923fb616e3fSDouglas Anderson * - Some misses are expected. Specifically, in order to work 1924fb616e3fSDouglas Anderson * perfectly dwc2 really needs quite spectacular interrupt latency 1925fb616e3fSDouglas Anderson * requirements. It needs to be able to handle its interrupts 1926fb616e3fSDouglas Anderson * completely within 125 us of them being asserted. That not only 1927fb616e3fSDouglas Anderson * means that the dwc2 interrupt handler needs to be fast but it 1928fb616e3fSDouglas Anderson * means that nothing else in the system has to block dwc2 for a long 1929fb616e3fSDouglas Anderson * time. We can help with the dwc2 parts of this, but it's hard to 1930fb616e3fSDouglas Anderson * guarantee that a system will have interrupt latency < 125 us, so 1931fb616e3fSDouglas Anderson * we have to be robust to some misses. 1932fb616e3fSDouglas Anderson */ 19339cf1a601SDouglas Anderson if (qh->start_active_frame == qh->next_active_frame || 19349cf1a601SDouglas Anderson dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) { 1935fb616e3fSDouglas Anderson u16 ideal_start = qh->start_active_frame; 19369f9f09b0SDouglas Anderson int periods_in_map; 1937fb616e3fSDouglas Anderson 19389f9f09b0SDouglas Anderson /* 19399f9f09b0SDouglas Anderson * Adjust interval as per gcd with map size. 19409f9f09b0SDouglas Anderson * See pmap_schedule() for more details here. 19419f9f09b0SDouglas Anderson */ 19429f9f09b0SDouglas Anderson if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH) 19439f9f09b0SDouglas Anderson periods_in_map = DWC2_HS_SCHEDULE_UFRAMES; 19449f9f09b0SDouglas Anderson else 19459f9f09b0SDouglas Anderson periods_in_map = DWC2_LS_SCHEDULE_FRAMES; 19469f9f09b0SDouglas Anderson interval = gcd(interval, periods_in_map); 1947fb616e3fSDouglas Anderson 1948fb616e3fSDouglas Anderson do { 1949fb616e3fSDouglas Anderson qh->start_active_frame = dwc2_frame_num_inc( 1950fb616e3fSDouglas Anderson qh->start_active_frame, interval); 1951fb616e3fSDouglas Anderson } while (dwc2_frame_num_gt(prev_frame_number, 1952fb616e3fSDouglas Anderson qh->start_active_frame)); 1953fb616e3fSDouglas Anderson 1954fb616e3fSDouglas Anderson missed = dwc2_frame_num_dec(qh->start_active_frame, 1955fb616e3fSDouglas Anderson ideal_start); 1956fb616e3fSDouglas Anderson } 1957fb616e3fSDouglas Anderson 1958fb616e3fSDouglas Anderson exit: 1959fb616e3fSDouglas Anderson qh->next_active_frame = qh->start_active_frame; 1960fb616e3fSDouglas Anderson 1961fb616e3fSDouglas Anderson return missed; 1962197ba5f4SPaul Zimmerman } 1963197ba5f4SPaul Zimmerman 1964197ba5f4SPaul Zimmerman /* 1965197ba5f4SPaul Zimmerman * Deactivates a QH. For non-periodic QHs, removes the QH from the active 1966197ba5f4SPaul Zimmerman * non-periodic schedule. The QH is added to the inactive non-periodic 1967197ba5f4SPaul Zimmerman * schedule if any QTDs are still attached to the QH. 1968197ba5f4SPaul Zimmerman * 1969197ba5f4SPaul Zimmerman * For periodic QHs, the QH is removed from the periodic queued schedule. If 1970197ba5f4SPaul Zimmerman * there are any QTDs still attached to the QH, the QH is added to either the 1971197ba5f4SPaul Zimmerman * periodic inactive schedule or the periodic ready schedule and its next 1972197ba5f4SPaul Zimmerman * scheduled frame is calculated. The QH is placed in the ready schedule if 1973197ba5f4SPaul Zimmerman * the scheduled frame has been reached already. Otherwise it's placed in the 1974197ba5f4SPaul Zimmerman * inactive schedule. If there are no QTDs attached to the QH, the QH is 1975197ba5f4SPaul Zimmerman * completely removed from the periodic schedule. 1976197ba5f4SPaul Zimmerman */ 1977197ba5f4SPaul Zimmerman void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 1978197ba5f4SPaul Zimmerman int sched_next_periodic_split) 1979197ba5f4SPaul Zimmerman { 1980fb616e3fSDouglas Anderson u16 old_frame = qh->next_active_frame; 1981197ba5f4SPaul Zimmerman u16 frame_number; 1982fb616e3fSDouglas Anderson int missed; 1983197ba5f4SPaul Zimmerman 1984197ba5f4SPaul Zimmerman if (dbg_qh(qh)) 1985197ba5f4SPaul Zimmerman dev_vdbg(hsotg->dev, "%s()\n", __func__); 1986197ba5f4SPaul Zimmerman 1987197ba5f4SPaul Zimmerman if (dwc2_qh_is_non_per(qh)) { 1988197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 1989197ba5f4SPaul Zimmerman if (!list_empty(&qh->qtd_list)) 199038d2b5fbSDouglas Anderson /* Add back to inactive/waiting non-periodic schedule */ 1991197ba5f4SPaul Zimmerman dwc2_hcd_qh_add(hsotg, qh); 1992197ba5f4SPaul Zimmerman return; 1993197ba5f4SPaul Zimmerman } 1994197ba5f4SPaul Zimmerman 1995fb616e3fSDouglas Anderson /* 1996fb616e3fSDouglas Anderson * Use the real frame number rather than the cached value as of the 1997fb616e3fSDouglas Anderson * last SOF just to get us a little closer to reality. Note that 1998fb616e3fSDouglas Anderson * means we don't actually know if we've already handled the SOF 1999fb616e3fSDouglas Anderson * interrupt for this frame. 2000fb616e3fSDouglas Anderson */ 2001197ba5f4SPaul Zimmerman frame_number = dwc2_hcd_get_frame_number(hsotg); 2002197ba5f4SPaul Zimmerman 2003fb616e3fSDouglas Anderson if (sched_next_periodic_split) 2004fb616e3fSDouglas Anderson missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number); 2005fb616e3fSDouglas Anderson else 2006fb616e3fSDouglas Anderson missed = dwc2_next_periodic_start(hsotg, qh, frame_number); 2007fb616e3fSDouglas Anderson 2008fb616e3fSDouglas Anderson dwc2_sch_vdbg(hsotg, 2009fb616e3fSDouglas Anderson "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n", 2010fb616e3fSDouglas Anderson qh, sched_next_periodic_split, frame_number, old_frame, 2011fb616e3fSDouglas Anderson qh->next_active_frame, 2012fb616e3fSDouglas Anderson dwc2_frame_num_dec(qh->next_active_frame, old_frame), 2013fb616e3fSDouglas Anderson missed, missed ? "MISS" : ""); 2014197ba5f4SPaul Zimmerman 2015197ba5f4SPaul Zimmerman if (list_empty(&qh->qtd_list)) { 2016197ba5f4SPaul Zimmerman dwc2_hcd_qh_unlink(hsotg, qh); 2017197ba5f4SPaul Zimmerman return; 2018197ba5f4SPaul Zimmerman } 2019fb616e3fSDouglas Anderson 2020197ba5f4SPaul Zimmerman /* 2021197ba5f4SPaul Zimmerman * Remove from periodic_sched_queued and move to 2022197ba5f4SPaul Zimmerman * appropriate queue 2023fb616e3fSDouglas Anderson * 2024fb616e3fSDouglas Anderson * Note: we purposely use the frame_number from the "hsotg" structure 2025fb616e3fSDouglas Anderson * since we know SOF interrupt will handle future frames. 2026197ba5f4SPaul Zimmerman */ 2027fb616e3fSDouglas Anderson if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number)) 202894ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry, 202994ef7aeeSDouglas Anderson &hsotg->periodic_sched_ready); 2030197ba5f4SPaul Zimmerman else 203194ef7aeeSDouglas Anderson list_move_tail(&qh->qh_list_entry, 203294ef7aeeSDouglas Anderson &hsotg->periodic_sched_inactive); 2033197ba5f4SPaul Zimmerman } 2034197ba5f4SPaul Zimmerman 2035197ba5f4SPaul Zimmerman /** 2036197ba5f4SPaul Zimmerman * dwc2_hcd_qtd_init() - Initializes a QTD structure 2037197ba5f4SPaul Zimmerman * 2038197ba5f4SPaul Zimmerman * @qtd: The QTD to initialize 2039197ba5f4SPaul Zimmerman * @urb: The associated URB 2040197ba5f4SPaul Zimmerman */ 2041197ba5f4SPaul Zimmerman void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2042197ba5f4SPaul Zimmerman { 2043197ba5f4SPaul Zimmerman qtd->urb = urb; 2044197ba5f4SPaul Zimmerman if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 2045197ba5f4SPaul Zimmerman USB_ENDPOINT_XFER_CONTROL) { 2046197ba5f4SPaul Zimmerman /* 2047197ba5f4SPaul Zimmerman * The only time the QTD data toggle is used is on the data 2048197ba5f4SPaul Zimmerman * phase of control transfers. This phase always starts with 2049197ba5f4SPaul Zimmerman * DATA1. 2050197ba5f4SPaul Zimmerman */ 2051197ba5f4SPaul Zimmerman qtd->data_toggle = DWC2_HC_PID_DATA1; 2052197ba5f4SPaul Zimmerman qtd->control_phase = DWC2_CONTROL_SETUP; 2053197ba5f4SPaul Zimmerman } 2054197ba5f4SPaul Zimmerman 2055197ba5f4SPaul Zimmerman /* Start split */ 2056197ba5f4SPaul Zimmerman qtd->complete_split = 0; 2057197ba5f4SPaul Zimmerman qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 2058197ba5f4SPaul Zimmerman qtd->isoc_split_offset = 0; 2059197ba5f4SPaul Zimmerman qtd->in_process = 0; 2060197ba5f4SPaul Zimmerman 2061197ba5f4SPaul Zimmerman /* Store the qtd ptr in the urb to reference the QTD */ 2062197ba5f4SPaul Zimmerman urb->qtd = qtd; 2063197ba5f4SPaul Zimmerman } 2064197ba5f4SPaul Zimmerman 2065197ba5f4SPaul Zimmerman /** 2066197ba5f4SPaul Zimmerman * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 206733ad261aSGregory Herrero * Caller must hold driver lock. 2068197ba5f4SPaul Zimmerman * 2069197ba5f4SPaul Zimmerman * @hsotg: The DWC HCD structure 2070197ba5f4SPaul Zimmerman * @qtd: The QTD to add 2071b58e6ceeSMian Yousaf Kaukab * @qh: Queue head to add qtd to 2072197ba5f4SPaul Zimmerman * 2073197ba5f4SPaul Zimmerman * Return: 0 if successful, negative error code otherwise 2074197ba5f4SPaul Zimmerman * 2075b58e6ceeSMian Yousaf Kaukab * If the QH to which the QTD is added is not currently scheduled, it is placed 2076b58e6ceeSMian Yousaf Kaukab * into the proper schedule based on its EP type. 2077197ba5f4SPaul Zimmerman */ 2078197ba5f4SPaul Zimmerman int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2079b58e6ceeSMian Yousaf Kaukab struct dwc2_qh *qh) 2080197ba5f4SPaul Zimmerman { 2081197ba5f4SPaul Zimmerman int retval; 2082197ba5f4SPaul Zimmerman 2083b58e6ceeSMian Yousaf Kaukab if (unlikely(!qh)) { 2084b58e6ceeSMian Yousaf Kaukab dev_err(hsotg->dev, "%s: Invalid QH\n", __func__); 2085b58e6ceeSMian Yousaf Kaukab retval = -EINVAL; 2086b58e6ceeSMian Yousaf Kaukab goto fail; 2087197ba5f4SPaul Zimmerman } 2088197ba5f4SPaul Zimmerman 2089b58e6ceeSMian Yousaf Kaukab retval = dwc2_hcd_qh_add(hsotg, qh); 2090197ba5f4SPaul Zimmerman if (retval) 2091197ba5f4SPaul Zimmerman goto fail; 2092197ba5f4SPaul Zimmerman 2093b58e6ceeSMian Yousaf Kaukab qtd->qh = qh; 2094b58e6ceeSMian Yousaf Kaukab list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list); 2095197ba5f4SPaul Zimmerman 2096197ba5f4SPaul Zimmerman return 0; 2097197ba5f4SPaul Zimmerman fail: 2098197ba5f4SPaul Zimmerman return retval; 2099197ba5f4SPaul Zimmerman } 2100