1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.h - DesignWare HS OTG Controller host-mode declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 #ifndef __DWC2_HCD_H__ 38 #define __DWC2_HCD_H__ 39 40 /* 41 * This file contains the structures, constants, and interfaces for the 42 * Host Contoller Driver (HCD) 43 * 44 * The Host Controller Driver (HCD) is responsible for translating requests 45 * from the USB Driver into the appropriate actions on the DWC_otg controller. 46 * It isolates the USBD from the specifics of the controller by providing an 47 * API to the USBD. 48 */ 49 50 struct dwc2_qh; 51 52 /** 53 * struct dwc2_host_chan - Software host channel descriptor 54 * 55 * @hc_num: Host channel number, used for register address lookup 56 * @dev_addr: Address of the device 57 * @ep_num: Endpoint of the device 58 * @ep_is_in: Endpoint direction 59 * @speed: Device speed. One of the following values: 60 * - USB_SPEED_LOW 61 * - USB_SPEED_FULL 62 * - USB_SPEED_HIGH 63 * @ep_type: Endpoint type. One of the following values: 64 * - USB_ENDPOINT_XFER_CONTROL: 0 65 * - USB_ENDPOINT_XFER_ISOC: 1 66 * - USB_ENDPOINT_XFER_BULK: 2 67 * - USB_ENDPOINT_XFER_INTR: 3 68 * @max_packet: Max packet size in bytes 69 * @data_pid_start: PID for initial transaction. 70 * 0: DATA0 71 * 1: DATA2 72 * 2: DATA1 73 * 3: MDATA (non-Control EP), 74 * SETUP (Control EP) 75 * @multi_count: Number of additional periodic transactions per 76 * (micro)frame 77 * @xfer_buf: Pointer to current transfer buffer position 78 * @xfer_dma: DMA address of xfer_buf 79 * @align_buf: In Buffer DMA mode this will be used if xfer_buf is not 80 * DWORD aligned 81 * @xfer_len: Total number of bytes to transfer 82 * @xfer_count: Number of bytes transferred so far 83 * @start_pkt_count: Packet count at start of transfer 84 * @xfer_started: True if the transfer has been started 85 * @do_ping: True if a PING request should be issued on this channel 86 * @error_state: True if the error count for this transaction is non-zero 87 * @halt_on_queue: True if this channel should be halted the next time a 88 * request is queued for the channel. This is necessary in 89 * slave mode if no request queue space is available when 90 * an attempt is made to halt the channel. 91 * @halt_pending: True if the host channel has been halted, but the core 92 * is not finished flushing queued requests 93 * @do_split: Enable split for the channel 94 * @complete_split: Enable complete split 95 * @hub_addr: Address of high speed hub for the split 96 * @hub_port: Port of the low/full speed device for the split 97 * @xact_pos: Split transaction position. One of the following values: 98 * - DWC2_HCSPLT_XACTPOS_MID 99 * - DWC2_HCSPLT_XACTPOS_BEGIN 100 * - DWC2_HCSPLT_XACTPOS_END 101 * - DWC2_HCSPLT_XACTPOS_ALL 102 * @requests: Number of requests issued for this channel since it was 103 * assigned to the current transfer (not counting PINGs) 104 * @schinfo: Scheduling micro-frame bitmap 105 * @ntd: Number of transfer descriptors for the transfer 106 * @halt_status: Reason for halting the host channel 107 * @hcint: Contents of the HCINT register when the interrupt came 108 * @qh: QH for the transfer being processed by this channel 109 * @hc_list_entry: For linking to list of host channels 110 * @desc_list_addr: Current QH's descriptor list DMA address 111 * @desc_list_sz: Current QH's descriptor list size 112 * @split_order_list_entry: List entry for keeping track of the order of splits 113 * 114 * This structure represents the state of a single host channel when acting in 115 * host mode. It contains the data items needed to transfer packets to an 116 * endpoint via a host channel. 117 */ 118 struct dwc2_host_chan { 119 u8 hc_num; 120 121 unsigned dev_addr:7; 122 unsigned ep_num:4; 123 unsigned ep_is_in:1; 124 unsigned speed:4; 125 unsigned ep_type:2; 126 unsigned max_packet:11; 127 unsigned data_pid_start:2; 128 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 129 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 130 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 131 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 132 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 133 134 unsigned multi_count:2; 135 136 u8 *xfer_buf; 137 dma_addr_t xfer_dma; 138 dma_addr_t align_buf; 139 u32 xfer_len; 140 u32 xfer_count; 141 u16 start_pkt_count; 142 u8 xfer_started; 143 u8 do_ping; 144 u8 error_state; 145 u8 halt_on_queue; 146 u8 halt_pending; 147 u8 do_split; 148 u8 complete_split; 149 u8 hub_addr; 150 u8 hub_port; 151 u8 xact_pos; 152 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 153 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 154 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 155 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 156 157 u8 requests; 158 u8 schinfo; 159 u16 ntd; 160 enum dwc2_halt_status halt_status; 161 u32 hcint; 162 struct dwc2_qh *qh; 163 struct list_head hc_list_entry; 164 dma_addr_t desc_list_addr; 165 u32 desc_list_sz; 166 struct list_head split_order_list_entry; 167 }; 168 169 struct dwc2_hcd_pipe_info { 170 u8 dev_addr; 171 u8 ep_num; 172 u8 pipe_type; 173 u8 pipe_dir; 174 u16 mps; 175 }; 176 177 struct dwc2_hcd_iso_packet_desc { 178 u32 offset; 179 u32 length; 180 u32 actual_length; 181 u32 status; 182 }; 183 184 struct dwc2_qtd; 185 186 struct dwc2_hcd_urb { 187 void *priv; 188 struct dwc2_qtd *qtd; 189 void *buf; 190 dma_addr_t dma; 191 void *setup_packet; 192 dma_addr_t setup_dma; 193 u32 length; 194 u32 actual_length; 195 u32 status; 196 u32 error_count; 197 u32 packet_count; 198 u32 flags; 199 u16 interval; 200 struct dwc2_hcd_pipe_info pipe_info; 201 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 202 }; 203 204 /* Phases for control transfers */ 205 enum dwc2_control_phase { 206 DWC2_CONTROL_SETUP, 207 DWC2_CONTROL_DATA, 208 DWC2_CONTROL_STATUS, 209 }; 210 211 /* Transaction types */ 212 enum dwc2_transaction_type { 213 DWC2_TRANSACTION_NONE, 214 DWC2_TRANSACTION_PERIODIC, 215 DWC2_TRANSACTION_NON_PERIODIC, 216 DWC2_TRANSACTION_ALL, 217 }; 218 219 /* The number of elements per LS bitmap (per port on multi_tt) */ 220 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ 221 BITS_PER_LONG) 222 223 /** 224 * struct dwc2_tt - dwc2 data associated with a usb_tt 225 * 226 * @refcount: Number of Queue Heads (QHs) holding a reference. 227 * @usb_tt: Pointer back to the official usb_tt. 228 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted 229 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP 230 * elements (so sizeof(long) times that in bytes). 231 * 232 * This structure is stored in the hcpriv of the official usb_tt. 233 */ 234 struct dwc2_tt { 235 int refcount; 236 struct usb_tt *usb_tt; 237 unsigned long periodic_bitmaps[]; 238 }; 239 240 /** 241 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. 242 * 243 * @start_schedule_us: The start time on the main bus schedule. Note that 244 * the main bus schedule is tightly packed and this 245 * time should be interpreted as tightly packed (so 246 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us 247 * instead of 125 us). 248 * @duration_us: How long this transfer goes. 249 */ 250 251 struct dwc2_hs_transfer_time { 252 u32 start_schedule_us; 253 u16 duration_us; 254 }; 255 256 /** 257 * struct dwc2_qh - Software queue head structure 258 * 259 * @hsotg: The HCD state structure for the DWC OTG controller 260 * @ep_type: Endpoint type. One of the following values: 261 * - USB_ENDPOINT_XFER_CONTROL 262 * - USB_ENDPOINT_XFER_BULK 263 * - USB_ENDPOINT_XFER_INT 264 * - USB_ENDPOINT_XFER_ISOC 265 * @ep_is_in: Endpoint direction 266 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 267 * @dev_speed: Device speed. One of the following values: 268 * - USB_SPEED_LOW 269 * - USB_SPEED_FULL 270 * - USB_SPEED_HIGH 271 * @data_toggle: Determines the PID of the next data packet for 272 * non-controltransfers. Ignored for control transfers. 273 * One of the following values: 274 * - DWC2_HC_PID_DATA0 275 * - DWC2_HC_PID_DATA1 276 * @ping_state: Ping state 277 * @do_split: Full/low speed endpoint on high-speed hub requires split 278 * @td_first: Index of first activated isochronous transfer descriptor 279 * @td_last: Index of last activated isochronous transfer descriptor 280 * @host_us: Bandwidth in microseconds per transfer as seen by host 281 * @device_us: Bandwidth in microseconds per transfer as seen by device 282 * @host_interval: Interval between transfers as seen by the host. If 283 * the host is high speed and the device is low speed this 284 * will be 8 times device interval. 285 * @device_interval: Interval between transfers as seen by the device. 286 * interval. 287 * @next_active_frame: (Micro)frame _before_ we next need to put something on 288 * the bus. We'll move the qh to active here. If the 289 * host is in high speed mode this will be a uframe. If 290 * the host is in low speed mode this will be a full frame. 291 * @start_active_frame: If we are partway through a split transfer, this will be 292 * what next_active_frame was when we started. Otherwise 293 * it should always be the same as next_active_frame. 294 * @num_hs_transfers: Number of transfers in hs_transfers. 295 * Normally this is 1 but can be more than one for splits. 296 * Always >= 1 unless the host is in low/full speed mode. 297 * @hs_transfers: Transfers that are scheduled as seen by the high speed 298 * bus. Not used if host is in low or full speed mode (but 299 * note that it IS USED if the device is low or full speed 300 * as long as the HOST is in high speed mode). 301 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus 302 * schedule that's being used by this device. This 303 * will be on the periodic_bitmap in a 304 * "struct dwc2_tt". Not used if this device is high 305 * speed. Note that this is in "schedule slice" which 306 * is tightly packed. 307 * @ntd: Actual number of transfer descriptors in a list 308 * @dw_align_buf: Used instead of original buffer if its physical address 309 * is not dword-aligned 310 * @dw_align_buf_dma: DMA address for dw_align_buf 311 * @qtd_list: List of QTDs for this QH 312 * @channel: Host channel currently processing transfers for this QH 313 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 314 * schedule 315 * @desc_list: List of transfer descriptors 316 * @desc_list_dma: Physical address of desc_list 317 * @desc_list_sz: Size of descriptors list 318 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 319 * descriptor and indicates original XferSize value for the 320 * descriptor 321 * @unreserve_timer: Timer for releasing periodic reservation. 322 * @wait_timer: Timer used to wait before re-queuing. 323 * @dwc_tt: Pointer to our tt info (or NULL if no tt). 324 * @ttport: Port number within our tt. 325 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 326 * @unreserve_pending: True if we planned to unreserve but haven't yet. 327 * @schedule_low_speed: True if we have a low/full speed component (either the 328 * host is in low/full speed mode or do_split). 329 * @want_wait: We should wait before re-queuing; only matters for non- 330 * periodic transfers and is ignored for periodic ones. 331 * @wait_timer_cancel: Set to true to cancel the wait_timer. 332 * 333 * @tt_buffer_dirty: True if EP's TT buffer is not clean. 334 * A Queue Head (QH) holds the static characteristics of an endpoint and 335 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 336 * be entered in either the non-periodic or periodic schedule. 337 */ 338 struct dwc2_qh { 339 struct dwc2_hsotg *hsotg; 340 u8 ep_type; 341 u8 ep_is_in; 342 u16 maxp; 343 u8 dev_speed; 344 u8 data_toggle; 345 u8 ping_state; 346 u8 do_split; 347 u8 td_first; 348 u8 td_last; 349 u16 host_us; 350 u16 device_us; 351 u16 host_interval; 352 u16 device_interval; 353 u16 next_active_frame; 354 u16 start_active_frame; 355 s16 num_hs_transfers; 356 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; 357 u32 ls_start_schedule_slice; 358 u16 ntd; 359 u8 *dw_align_buf; 360 dma_addr_t dw_align_buf_dma; 361 struct list_head qtd_list; 362 struct dwc2_host_chan *channel; 363 struct list_head qh_list_entry; 364 struct dwc2_dma_desc *desc_list; 365 dma_addr_t desc_list_dma; 366 u32 desc_list_sz; 367 u32 *n_bytes; 368 struct timer_list unreserve_timer; 369 struct timer_list wait_timer; 370 struct dwc2_tt *dwc_tt; 371 int ttport; 372 unsigned tt_buffer_dirty:1; 373 unsigned unreserve_pending:1; 374 unsigned schedule_low_speed:1; 375 unsigned want_wait:1; 376 unsigned wait_timer_cancel:1; 377 }; 378 379 /** 380 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 381 * 382 * @control_phase: Current phase for control transfers (Setup, Data, or 383 * Status) 384 * @in_process: Indicates if this QTD is currently processed by HW 385 * @data_toggle: Determines the PID of the next data packet for the 386 * data phase of control transfers. Ignored for other 387 * transfer types. One of the following values: 388 * - DWC2_HC_PID_DATA0 389 * - DWC2_HC_PID_DATA1 390 * @complete_split: Keeps track of the current split type for FS/LS 391 * endpoints on a HS Hub 392 * @isoc_split_pos: Position of the ISOC split in full/low speed 393 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 394 * transfer. A frame descriptor describes the buffer 395 * position and length of the data to be transferred in the 396 * next scheduled (micro)frame of an isochronous transfer. 397 * It also holds status for that transaction. The frame 398 * index starts at 0. 399 * @isoc_split_offset: Position of the ISOC split in the buffer for the 400 * current frame 401 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 402 * @error_count: Holds the number of bus errors that have occurred for 403 * a transaction within this transfer 404 * @n_desc: Number of DMA descriptors for this QTD 405 * @isoc_frame_index_last: Last activated frame (packet) index, used in 406 * descriptor DMA mode only 407 * @num_naks: Number of NAKs received on this QTD. 408 * @urb: URB for this transfer 409 * @qh: Queue head for this QTD 410 * @qtd_list_entry: For linking to the QH's list of QTDs 411 * @isoc_td_first: Index of first activated isochronous transfer 412 * descriptor in Descriptor DMA mode 413 * @isoc_td_last: Index of last activated isochronous transfer 414 * descriptor in Descriptor DMA mode 415 * 416 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 417 * interrupt, or isochronous transfer. A single QTD is created for each URB 418 * (of one of these types) submitted to the HCD. The transfer associated with 419 * a QTD may require one or multiple transactions. 420 * 421 * A QTD is linked to a Queue Head, which is entered in either the 422 * non-periodic or periodic schedule for execution. When a QTD is chosen for 423 * execution, some or all of its transactions may be executed. After 424 * execution, the state of the QTD is updated. The QTD may be retired if all 425 * its transactions are complete or if an error occurred. Otherwise, it 426 * remains in the schedule so more transactions can be executed later. 427 */ 428 struct dwc2_qtd { 429 enum dwc2_control_phase control_phase; 430 u8 in_process; 431 u8 data_toggle; 432 u8 complete_split; 433 u8 isoc_split_pos; 434 u16 isoc_frame_index; 435 u16 isoc_split_offset; 436 u16 isoc_td_last; 437 u16 isoc_td_first; 438 u32 ssplit_out_xfer_count; 439 u8 error_count; 440 u8 n_desc; 441 u16 isoc_frame_index_last; 442 u16 num_naks; 443 struct dwc2_hcd_urb *urb; 444 struct dwc2_qh *qh; 445 struct list_head qtd_list_entry; 446 }; 447 448 #ifdef DEBUG 449 struct hc_xfer_info { 450 struct dwc2_hsotg *hsotg; 451 struct dwc2_host_chan *chan; 452 }; 453 #endif 454 455 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 456 457 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 458 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 459 { 460 return (struct usb_hcd *)hsotg->priv; 461 } 462 463 /* 464 * Inline used to disable one channel interrupt. Channel interrupts are 465 * disabled when the channel is halted or released by the interrupt handler. 466 * There is no need to handle further interrupts of that type until the 467 * channel is re-assigned. In fact, subsequent handling may cause crashes 468 * because the channel structures are cleaned up when the channel is released. 469 */ 470 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 471 { 472 u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum)); 473 474 mask &= ~intr; 475 dwc2_writel(hsotg, mask, HCINTMSK(chnum)); 476 } 477 478 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 479 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 480 enum dwc2_halt_status halt_status); 481 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 482 struct dwc2_host_chan *chan); 483 484 /* 485 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 486 * are read as 1, they won't clear when written back. 487 */ 488 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 489 { 490 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 491 492 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 493 return hprt0; 494 } 495 496 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 497 { 498 return pipe->ep_num; 499 } 500 501 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 502 { 503 return pipe->pipe_type; 504 } 505 506 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 507 { 508 return pipe->mps; 509 } 510 511 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 512 { 513 return pipe->dev_addr; 514 } 515 516 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 517 { 518 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 519 } 520 521 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 522 { 523 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 524 } 525 526 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 527 { 528 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 529 } 530 531 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 532 { 533 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 534 } 535 536 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 537 { 538 return pipe->pipe_dir == USB_DIR_IN; 539 } 540 541 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 542 { 543 return !dwc2_hcd_is_pipe_in(pipe); 544 } 545 546 int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 547 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 548 549 /* Transaction Execution Functions */ 550 enum dwc2_transaction_type dwc2_hcd_select_transactions( 551 struct dwc2_hsotg *hsotg); 552 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 553 enum dwc2_transaction_type tr_type); 554 555 /* Schedule Queue Functions */ 556 /* Implemented in hcd_queue.c */ 557 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 558 struct dwc2_hcd_urb *urb, 559 gfp_t mem_flags); 560 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 561 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 562 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 563 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 564 int sched_csplit); 565 566 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 567 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 568 struct dwc2_qh *qh); 569 570 /* Unlinks and frees a QTD */ 571 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 572 struct dwc2_qtd *qtd, 573 struct dwc2_qh *qh) 574 { 575 list_del(&qtd->qtd_list_entry); 576 kfree(qtd); 577 qtd = NULL; 578 } 579 580 /* Descriptor DMA support functions */ 581 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 582 struct dwc2_qh *qh); 583 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 584 struct dwc2_host_chan *chan, int chnum, 585 enum dwc2_halt_status halt_status); 586 587 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 588 gfp_t mem_flags); 589 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 590 591 /* Check if QH is non-periodic */ 592 #define dwc2_qh_is_non_per(_qh_ptr_) \ 593 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 594 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 595 596 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 597 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 598 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 599 static inline bool dbg_urb(struct urb *urb) { return true; } 600 static inline bool dbg_perio(void) { return true; } 601 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 602 static inline bool dbg_hc(struct dwc2_host_chan *hc) 603 { 604 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 605 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 606 } 607 608 static inline bool dbg_qh(struct dwc2_qh *qh) 609 { 610 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 611 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 612 } 613 614 static inline bool dbg_urb(struct urb *urb) 615 { 616 return usb_pipetype(urb->pipe) == PIPE_BULK || 617 usb_pipetype(urb->pipe) == PIPE_CONTROL; 618 } 619 620 static inline bool dbg_perio(void) { return false; } 621 #endif 622 623 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 624 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 625 626 /* Packet size for any kind of endpoint descriptor */ 627 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 628 629 /* 630 * Returns true if frame1 index is greater than frame2 index. The comparison 631 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 632 * frame number when the max index frame number is reached. 633 */ 634 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 635 { 636 u16 diff = fr_idx1 - fr_idx2; 637 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 638 639 return diff && !sign; 640 } 641 642 /* 643 * Returns true if frame1 is less than or equal to frame2. The comparison is 644 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 645 * frame number when the max frame number is reached. 646 */ 647 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 648 { 649 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 650 } 651 652 /* 653 * Returns true if frame1 is greater than frame2. The comparison is done 654 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 655 * number when the max frame number is reached. 656 */ 657 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 658 { 659 return (frame1 != frame2) && 660 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 661 } 662 663 /* 664 * Increments frame by the amount specified by inc. The addition is done 665 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 666 */ 667 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 668 { 669 return (frame + inc) & HFNUM_MAX_FRNUM; 670 } 671 672 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 673 { 674 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 675 } 676 677 static inline u16 dwc2_full_frame_num(u16 frame) 678 { 679 return (frame & HFNUM_MAX_FRNUM) >> 3; 680 } 681 682 static inline u16 dwc2_micro_frame_num(u16 frame) 683 { 684 return frame & 0x7; 685 } 686 687 /* 688 * Returns the Core Interrupt Status register contents, ANDed with the Core 689 * Interrupt Mask register contents 690 */ 691 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 692 { 693 return dwc2_readl(hsotg, GINTSTS) & 694 dwc2_readl(hsotg, GINTMSK); 695 } 696 697 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 698 { 699 return dwc2_urb->status; 700 } 701 702 static inline u32 dwc2_hcd_urb_get_actual_length( 703 struct dwc2_hcd_urb *dwc2_urb) 704 { 705 return dwc2_urb->actual_length; 706 } 707 708 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 709 { 710 return dwc2_urb->error_count; 711 } 712 713 static inline void dwc2_hcd_urb_set_iso_desc_params( 714 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 715 u32 length) 716 { 717 dwc2_urb->iso_descs[desc_num].offset = offset; 718 dwc2_urb->iso_descs[desc_num].length = length; 719 } 720 721 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 722 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 723 { 724 return dwc2_urb->iso_descs[desc_num].status; 725 } 726 727 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 728 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 729 { 730 return dwc2_urb->iso_descs[desc_num].actual_length; 731 } 732 733 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 734 struct usb_host_endpoint *ep) 735 { 736 struct dwc2_qh *qh = ep->hcpriv; 737 738 if (qh && !list_empty(&qh->qh_list_entry)) 739 return 1; 740 741 return 0; 742 } 743 744 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 745 struct usb_host_endpoint *ep) 746 { 747 struct dwc2_qh *qh = ep->hcpriv; 748 749 if (!qh) { 750 WARN_ON(1); 751 return 0; 752 } 753 754 return qh->host_us; 755 } 756 757 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 758 struct dwc2_host_chan *chan, int chnum, 759 struct dwc2_qtd *qtd); 760 761 /* HCD Core API */ 762 763 /** 764 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 765 * 766 * @hsotg: The DWC2 HCD 767 * 768 * Returns IRQ_HANDLED if interrupt is handled 769 * Return IRQ_NONE if interrupt is not handled 770 */ 771 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 772 773 /** 774 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 775 * 776 * @hsotg: The DWC2 HCD 777 */ 778 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 779 780 /** 781 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 782 * and 0 otherwise 783 * 784 * @hsotg: The DWC2 HCD 785 */ 786 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 787 788 /** 789 * dwc2_hcd_dump_state() - Dumps hsotg state 790 * 791 * @hsotg: The DWC2 HCD 792 * 793 * NOTE: This function will be removed once the peripheral controller code 794 * is integrated and the driver is stable 795 */ 796 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 797 798 /* URB interface */ 799 800 /* Transfer flags */ 801 #define URB_GIVEBACK_ASAP 0x1 802 #define URB_SEND_ZERO_PACKET 0x2 803 804 /* Host driver callbacks */ 805 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 806 void *context, gfp_t mem_flags, 807 int *ttport); 808 809 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 810 struct dwc2_tt *dwc_tt); 811 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 812 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 813 int status); 814 815 #endif /* __DWC2_HCD_H__ */ 816