xref: /openbmc/linux/drivers/usb/dwc2/hcd.h (revision f21e49be)
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /*
3  * hcd.h - DesignWare HS OTG Controller host-mode declarations
4  *
5  * Copyright (C) 2004-2013 Synopsys, Inc.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The names of the above-listed copyright holders may not be used
17  *    to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * ALTERNATIVELY, this software may be distributed under the terms of the
21  * GNU General Public License ("GPL") as published by the Free Software
22  * Foundation; either version 2 of the License, or (at your option) any
23  * later version.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 #ifndef __DWC2_HCD_H__
38 #define __DWC2_HCD_H__
39 
40 /*
41  * This file contains the structures, constants, and interfaces for the
42  * Host Contoller Driver (HCD)
43  *
44  * The Host Controller Driver (HCD) is responsible for translating requests
45  * from the USB Driver into the appropriate actions on the DWC_otg controller.
46  * It isolates the USBD from the specifics of the controller by providing an
47  * API to the USBD.
48  */
49 
50 struct dwc2_qh;
51 
52 /**
53  * struct dwc2_host_chan - Software host channel descriptor
54  *
55  * @hc_num:             Host channel number, used for register address lookup
56  * @dev_addr:           Address of the device
57  * @ep_num:             Endpoint of the device
58  * @ep_is_in:           Endpoint direction
59  * @speed:              Device speed. One of the following values:
60  *                       - USB_SPEED_LOW
61  *                       - USB_SPEED_FULL
62  *                       - USB_SPEED_HIGH
63  * @ep_type:            Endpoint type. One of the following values:
64  *                       - USB_ENDPOINT_XFER_CONTROL: 0
65  *                       - USB_ENDPOINT_XFER_ISOC:    1
66  *                       - USB_ENDPOINT_XFER_BULK:    2
67  *                       - USB_ENDPOINT_XFER_INTR:    3
68  * @max_packet:         Max packet size in bytes
69  * @data_pid_start:     PID for initial transaction.
70  *                       0: DATA0
71  *                       1: DATA2
72  *                       2: DATA1
73  *                       3: MDATA (non-Control EP),
74  *                          SETUP (Control EP)
75  * @multi_count:        Number of additional periodic transactions per
76  *                      (micro)frame
77  * @xfer_buf:           Pointer to current transfer buffer position
78  * @xfer_dma:           DMA address of xfer_buf
79  * @align_buf:          In Buffer DMA mode this will be used if xfer_buf is not
80  *                      DWORD aligned
81  * @xfer_len:           Total number of bytes to transfer
82  * @xfer_count:         Number of bytes transferred so far
83  * @start_pkt_count:    Packet count at start of transfer
84  * @xfer_started:       True if the transfer has been started
85  * @do_ping:            True if a PING request should be issued on this channel
86  * @error_state:        True if the error count for this transaction is non-zero
87  * @halt_on_queue:      True if this channel should be halted the next time a
88  *                      request is queued for the channel. This is necessary in
89  *                      slave mode if no request queue space is available when
90  *                      an attempt is made to halt the channel.
91  * @halt_pending:       True if the host channel has been halted, but the core
92  *                      is not finished flushing queued requests
93  * @do_split:           Enable split for the channel
94  * @complete_split:     Enable complete split
95  * @hub_addr:           Address of high speed hub for the split
96  * @hub_port:           Port of the low/full speed device for the split
97  * @xact_pos:           Split transaction position. One of the following values:
98  *                       - DWC2_HCSPLT_XACTPOS_MID
99  *                       - DWC2_HCSPLT_XACTPOS_BEGIN
100  *                       - DWC2_HCSPLT_XACTPOS_END
101  *                       - DWC2_HCSPLT_XACTPOS_ALL
102  * @requests:           Number of requests issued for this channel since it was
103  *                      assigned to the current transfer (not counting PINGs)
104  * @schinfo:            Scheduling micro-frame bitmap
105  * @ntd:                Number of transfer descriptors for the transfer
106  * @halt_status:        Reason for halting the host channel
107  * @hcint:               Contents of the HCINT register when the interrupt came
108  * @qh:                 QH for the transfer being processed by this channel
109  * @hc_list_entry:      For linking to list of host channels
110  * @desc_list_addr:     Current QH's descriptor list DMA address
111  * @desc_list_sz:       Current QH's descriptor list size
112  * @split_order_list_entry: List entry for keeping track of the order of splits
113  *
114  * This structure represents the state of a single host channel when acting in
115  * host mode. It contains the data items needed to transfer packets to an
116  * endpoint via a host channel.
117  */
118 struct dwc2_host_chan {
119 	u8 hc_num;
120 
121 	unsigned dev_addr:7;
122 	unsigned ep_num:4;
123 	unsigned ep_is_in:1;
124 	unsigned speed:4;
125 	unsigned ep_type:2;
126 	unsigned max_packet:11;
127 	unsigned data_pid_start:2;
128 #define DWC2_HC_PID_DATA0	TSIZ_SC_MC_PID_DATA0
129 #define DWC2_HC_PID_DATA2	TSIZ_SC_MC_PID_DATA2
130 #define DWC2_HC_PID_DATA1	TSIZ_SC_MC_PID_DATA1
131 #define DWC2_HC_PID_MDATA	TSIZ_SC_MC_PID_MDATA
132 #define DWC2_HC_PID_SETUP	TSIZ_SC_MC_PID_SETUP
133 
134 	unsigned multi_count:2;
135 
136 	u8 *xfer_buf;
137 	dma_addr_t xfer_dma;
138 	dma_addr_t align_buf;
139 	u32 xfer_len;
140 	u32 xfer_count;
141 	u16 start_pkt_count;
142 	u8 xfer_started;
143 	u8 do_ping;
144 	u8 error_state;
145 	u8 halt_on_queue;
146 	u8 halt_pending;
147 	u8 do_split;
148 	u8 complete_split;
149 	u8 hub_addr;
150 	u8 hub_port;
151 	u8 xact_pos;
152 #define DWC2_HCSPLT_XACTPOS_MID	HCSPLT_XACTPOS_MID
153 #define DWC2_HCSPLT_XACTPOS_END	HCSPLT_XACTPOS_END
154 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN
155 #define DWC2_HCSPLT_XACTPOS_ALL	HCSPLT_XACTPOS_ALL
156 
157 	u8 requests;
158 	u8 schinfo;
159 	u16 ntd;
160 	enum dwc2_halt_status halt_status;
161 	u32 hcint;
162 	struct dwc2_qh *qh;
163 	struct list_head hc_list_entry;
164 	dma_addr_t desc_list_addr;
165 	u32 desc_list_sz;
166 	struct list_head split_order_list_entry;
167 };
168 
169 struct dwc2_hcd_pipe_info {
170 	u8 dev_addr;
171 	u8 ep_num;
172 	u8 pipe_type;
173 	u8 pipe_dir;
174 	u16 maxp;
175 	u16 maxp_mult;
176 };
177 
178 struct dwc2_hcd_iso_packet_desc {
179 	u32 offset;
180 	u32 length;
181 	u32 actual_length;
182 	u32 status;
183 };
184 
185 struct dwc2_qtd;
186 
187 struct dwc2_hcd_urb {
188 	void *priv;
189 	struct dwc2_qtd *qtd;
190 	void *buf;
191 	dma_addr_t dma;
192 	void *setup_packet;
193 	dma_addr_t setup_dma;
194 	u32 length;
195 	u32 actual_length;
196 	u32 status;
197 	u32 error_count;
198 	u32 packet_count;
199 	u32 flags;
200 	u16 interval;
201 	struct dwc2_hcd_pipe_info pipe_info;
202 	struct dwc2_hcd_iso_packet_desc iso_descs[];
203 };
204 
205 /* Phases for control transfers */
206 enum dwc2_control_phase {
207 	DWC2_CONTROL_SETUP,
208 	DWC2_CONTROL_DATA,
209 	DWC2_CONTROL_STATUS,
210 };
211 
212 /* Transaction types */
213 enum dwc2_transaction_type {
214 	DWC2_TRANSACTION_NONE,
215 	DWC2_TRANSACTION_PERIODIC,
216 	DWC2_TRANSACTION_NON_PERIODIC,
217 	DWC2_TRANSACTION_ALL,
218 };
219 
220 /* The number of elements per LS bitmap (per port on multi_tt) */
221 #define DWC2_ELEMENTS_PER_LS_BITMAP	DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \
222 						     BITS_PER_LONG)
223 
224 /**
225  * struct dwc2_tt - dwc2 data associated with a usb_tt
226  *
227  * @refcount:           Number of Queue Heads (QHs) holding a reference.
228  * @usb_tt:             Pointer back to the official usb_tt.
229  * @periodic_bitmaps:   Bitmap for which parts of the 1ms frame are accounted
230  *                      for already.  Each is DWC2_ELEMENTS_PER_LS_BITMAP
231  *			elements (so sizeof(long) times that in bytes).
232  *
233  * This structure is stored in the hcpriv of the official usb_tt.
234  */
235 struct dwc2_tt {
236 	int refcount;
237 	struct usb_tt *usb_tt;
238 	unsigned long periodic_bitmaps[];
239 };
240 
241 /**
242  * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus.
243  *
244  * @start_schedule_us:  The start time on the main bus schedule.  Note that
245  *                         the main bus schedule is tightly packed and this
246  *			   time should be interpreted as tightly packed (so
247  *			   uFrame 0 starts at 0 us, uFrame 1 starts at 100 us
248  *			   instead of 125 us).
249  * @duration_us:           How long this transfer goes.
250  */
251 
252 struct dwc2_hs_transfer_time {
253 	u32 start_schedule_us;
254 	u16 duration_us;
255 };
256 
257 /**
258  * struct dwc2_qh - Software queue head structure
259  *
260  * @hsotg:              The HCD state structure for the DWC OTG controller
261  * @ep_type:            Endpoint type. One of the following values:
262  *                       - USB_ENDPOINT_XFER_CONTROL
263  *                       - USB_ENDPOINT_XFER_BULK
264  *                       - USB_ENDPOINT_XFER_INT
265  *                       - USB_ENDPOINT_XFER_ISOC
266  * @ep_is_in:           Endpoint direction
267  * @maxp:               Value from wMaxPacketSize field of Endpoint Descriptor
268  * @maxp_mult:          Multiplier for maxp
269  * @dev_speed:          Device speed. One of the following values:
270  *                       - USB_SPEED_LOW
271  *                       - USB_SPEED_FULL
272  *                       - USB_SPEED_HIGH
273  * @data_toggle:        Determines the PID of the next data packet for
274  *                      non-controltransfers. Ignored for control transfers.
275  *                      One of the following values:
276  *                       - DWC2_HC_PID_DATA0
277  *                       - DWC2_HC_PID_DATA1
278  * @ping_state:         Ping state
279  * @do_split:           Full/low speed endpoint on high-speed hub requires split
280  * @td_first:           Index of first activated isochronous transfer descriptor
281  * @td_last:            Index of last activated isochronous transfer descriptor
282  * @host_us:            Bandwidth in microseconds per transfer as seen by host
283  * @device_us:          Bandwidth in microseconds per transfer as seen by device
284  * @host_interval:      Interval between transfers as seen by the host.  If
285  *                      the host is high speed and the device is low speed this
286  *                      will be 8 times device interval.
287  * @device_interval:    Interval between transfers as seen by the device.
288  *                      interval.
289  * @next_active_frame:  (Micro)frame _before_ we next need to put something on
290  *                      the bus.  We'll move the qh to active here.  If the
291  *                      host is in high speed mode this will be a uframe.  If
292  *                      the host is in low speed mode this will be a full frame.
293  * @start_active_frame: If we are partway through a split transfer, this will be
294  *			what next_active_frame was when we started.  Otherwise
295  *			it should always be the same as next_active_frame.
296  * @num_hs_transfers:   Number of transfers in hs_transfers.
297  *                      Normally this is 1 but can be more than one for splits.
298  *                      Always >= 1 unless the host is in low/full speed mode.
299  * @hs_transfers:       Transfers that are scheduled as seen by the high speed
300  *                      bus.  Not used if host is in low or full speed mode (but
301  *                      note that it IS USED if the device is low or full speed
302  *                      as long as the HOST is in high speed mode).
303  * @ls_start_schedule_slice: Start time (in slices) on the low speed bus
304  *                           schedule that's being used by this device.  This
305  *			     will be on the periodic_bitmap in a
306  *                           "struct dwc2_tt".  Not used if this device is high
307  *                           speed.  Note that this is in "schedule slice" which
308  *                           is tightly packed.
309  * @ntd:                Actual number of transfer descriptors in a list
310  * @dw_align_buf:       Used instead of original buffer if its physical address
311  *                      is not dword-aligned
312  * @dw_align_buf_dma:   DMA address for dw_align_buf
313  * @qtd_list:           List of QTDs for this QH
314  * @channel:            Host channel currently processing transfers for this QH
315  * @qh_list_entry:      Entry for QH in either the periodic or non-periodic
316  *                      schedule
317  * @desc_list:          List of transfer descriptors
318  * @desc_list_dma:      Physical address of desc_list
319  * @desc_list_sz:       Size of descriptors list
320  * @n_bytes:            Xfer Bytes array. Each element corresponds to a transfer
321  *                      descriptor and indicates original XferSize value for the
322  *                      descriptor
323  * @unreserve_timer:    Timer for releasing periodic reservation.
324  * @wait_timer:         Timer used to wait before re-queuing.
325  * @dwc_tt:            Pointer to our tt info (or NULL if no tt).
326  * @ttport:             Port number within our tt.
327  * @tt_buffer_dirty     True if clear_tt_buffer_complete is pending
328  * @unreserve_pending:  True if we planned to unreserve but haven't yet.
329  * @schedule_low_speed: True if we have a low/full speed component (either the
330  *			host is in low/full speed mode or do_split).
331  * @want_wait:          We should wait before re-queuing; only matters for non-
332  *                      periodic transfers and is ignored for periodic ones.
333  * @wait_timer_cancel:  Set to true to cancel the wait_timer.
334  *
335  * @tt_buffer_dirty:	True if EP's TT buffer is not clean.
336  * A Queue Head (QH) holds the static characteristics of an endpoint and
337  * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
338  * be entered in either the non-periodic or periodic schedule.
339  */
340 struct dwc2_qh {
341 	struct dwc2_hsotg *hsotg;
342 	u8 ep_type;
343 	u8 ep_is_in;
344 	u16 maxp;
345 	u16 maxp_mult;
346 	u8 dev_speed;
347 	u8 data_toggle;
348 	u8 ping_state;
349 	u8 do_split;
350 	u8 td_first;
351 	u8 td_last;
352 	u16 host_us;
353 	u16 device_us;
354 	u16 host_interval;
355 	u16 device_interval;
356 	u16 next_active_frame;
357 	u16 start_active_frame;
358 	s16 num_hs_transfers;
359 	struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES];
360 	u32 ls_start_schedule_slice;
361 	u16 ntd;
362 	u8 *dw_align_buf;
363 	dma_addr_t dw_align_buf_dma;
364 	struct list_head qtd_list;
365 	struct dwc2_host_chan *channel;
366 	struct list_head qh_list_entry;
367 	struct dwc2_dma_desc *desc_list;
368 	dma_addr_t desc_list_dma;
369 	u32 desc_list_sz;
370 	u32 *n_bytes;
371 	struct timer_list unreserve_timer;
372 	struct hrtimer wait_timer;
373 	struct dwc2_tt *dwc_tt;
374 	int ttport;
375 	unsigned tt_buffer_dirty:1;
376 	unsigned unreserve_pending:1;
377 	unsigned schedule_low_speed:1;
378 	unsigned want_wait:1;
379 	unsigned wait_timer_cancel:1;
380 };
381 
382 /**
383  * struct dwc2_qtd - Software queue transfer descriptor (QTD)
384  *
385  * @control_phase:      Current phase for control transfers (Setup, Data, or
386  *                      Status)
387  * @in_process:         Indicates if this QTD is currently processed by HW
388  * @data_toggle:        Determines the PID of the next data packet for the
389  *                      data phase of control transfers. Ignored for other
390  *                      transfer types. One of the following values:
391  *                       - DWC2_HC_PID_DATA0
392  *                       - DWC2_HC_PID_DATA1
393  * @complete_split:     Keeps track of the current split type for FS/LS
394  *                      endpoints on a HS Hub
395  * @isoc_split_pos:     Position of the ISOC split in full/low speed
396  * @isoc_frame_index:   Index of the next frame descriptor for an isochronous
397  *                      transfer. A frame descriptor describes the buffer
398  *                      position and length of the data to be transferred in the
399  *                      next scheduled (micro)frame of an isochronous transfer.
400  *                      It also holds status for that transaction. The frame
401  *                      index starts at 0.
402  * @isoc_split_offset:  Position of the ISOC split in the buffer for the
403  *                      current frame
404  * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT
405  * @error_count:        Holds the number of bus errors that have occurred for
406  *                      a transaction within this transfer
407  * @n_desc:             Number of DMA descriptors for this QTD
408  * @isoc_frame_index_last: Last activated frame (packet) index, used in
409  *                      descriptor DMA mode only
410  * @num_naks:           Number of NAKs received on this QTD.
411  * @urb:                URB for this transfer
412  * @qh:                 Queue head for this QTD
413  * @qtd_list_entry:     For linking to the QH's list of QTDs
414  * @isoc_td_first:	Index of first activated isochronous transfer
415  *			descriptor in Descriptor DMA mode
416  * @isoc_td_last:	Index of last activated isochronous transfer
417  *			descriptor in Descriptor DMA mode
418  *
419  * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
420  * interrupt, or isochronous transfer. A single QTD is created for each URB
421  * (of one of these types) submitted to the HCD. The transfer associated with
422  * a QTD may require one or multiple transactions.
423  *
424  * A QTD is linked to a Queue Head, which is entered in either the
425  * non-periodic or periodic schedule for execution. When a QTD is chosen for
426  * execution, some or all of its transactions may be executed. After
427  * execution, the state of the QTD is updated. The QTD may be retired if all
428  * its transactions are complete or if an error occurred. Otherwise, it
429  * remains in the schedule so more transactions can be executed later.
430  */
431 struct dwc2_qtd {
432 	enum dwc2_control_phase control_phase;
433 	u8 in_process;
434 	u8 data_toggle;
435 	u8 complete_split;
436 	u8 isoc_split_pos;
437 	u16 isoc_frame_index;
438 	u16 isoc_split_offset;
439 	u16 isoc_td_last;
440 	u16 isoc_td_first;
441 	u32 ssplit_out_xfer_count;
442 	u8 error_count;
443 	u8 n_desc;
444 	u16 isoc_frame_index_last;
445 	u16 num_naks;
446 	struct dwc2_hcd_urb *urb;
447 	struct dwc2_qh *qh;
448 	struct list_head qtd_list_entry;
449 };
450 
451 #ifdef DEBUG
452 struct hc_xfer_info {
453 	struct dwc2_hsotg *hsotg;
454 	struct dwc2_host_chan *chan;
455 };
456 #endif
457 
458 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
459 
460 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */
461 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg)
462 {
463 	return (struct usb_hcd *)hsotg->priv;
464 }
465 
466 /*
467  * Inline used to disable one channel interrupt. Channel interrupts are
468  * disabled when the channel is halted or released by the interrupt handler.
469  * There is no need to handle further interrupts of that type until the
470  * channel is re-assigned. In fact, subsequent handling may cause crashes
471  * because the channel structures are cleaned up when the channel is released.
472  */
473 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr)
474 {
475 	u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum));
476 
477 	mask &= ~intr;
478 	dwc2_writel(hsotg, mask, HCINTMSK(chnum));
479 }
480 
481 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
482 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
483 		  enum dwc2_halt_status halt_status);
484 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
485 				 struct dwc2_host_chan *chan);
486 
487 /*
488  * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they
489  * are read as 1, they won't clear when written back.
490  */
491 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg)
492 {
493 	u32 hprt0 = dwc2_readl(hsotg, HPRT0);
494 
495 	hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG);
496 	return hprt0;
497 }
498 
499 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe)
500 {
501 	return pipe->ep_num;
502 }
503 
504 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe)
505 {
506 	return pipe->pipe_type;
507 }
508 
509 static inline u16 dwc2_hcd_get_maxp(struct dwc2_hcd_pipe_info *pipe)
510 {
511 	return pipe->maxp;
512 }
513 
514 static inline u16 dwc2_hcd_get_maxp_mult(struct dwc2_hcd_pipe_info *pipe)
515 {
516 	return pipe->maxp_mult;
517 }
518 
519 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe)
520 {
521 	return pipe->dev_addr;
522 }
523 
524 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe)
525 {
526 	return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC;
527 }
528 
529 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe)
530 {
531 	return pipe->pipe_type == USB_ENDPOINT_XFER_INT;
532 }
533 
534 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe)
535 {
536 	return pipe->pipe_type == USB_ENDPOINT_XFER_BULK;
537 }
538 
539 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe)
540 {
541 	return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL;
542 }
543 
544 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe)
545 {
546 	return pipe->pipe_dir == USB_DIR_IN;
547 }
548 
549 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe)
550 {
551 	return !dwc2_hcd_is_pipe_in(pipe);
552 }
553 
554 int dwc2_hcd_init(struct dwc2_hsotg *hsotg);
555 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg);
556 
557 /* Transaction Execution Functions */
558 enum dwc2_transaction_type dwc2_hcd_select_transactions(
559 						struct dwc2_hsotg *hsotg);
560 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
561 				 enum dwc2_transaction_type tr_type);
562 
563 /* Schedule Queue Functions */
564 /* Implemented in hcd_queue.c */
565 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
566 				   struct dwc2_hcd_urb *urb,
567 					  gfp_t mem_flags);
568 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
569 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
570 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
571 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
572 			    int sched_csplit);
573 
574 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb);
575 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
576 		     struct dwc2_qh *qh);
577 
578 /* Unlinks and frees a QTD */
579 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg,
580 						struct dwc2_qtd *qtd,
581 						struct dwc2_qh *qh)
582 {
583 	list_del(&qtd->qtd_list_entry);
584 	kfree(qtd);
585 }
586 
587 /* Descriptor DMA support functions */
588 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg,
589 			      struct dwc2_qh *qh);
590 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg,
591 				 struct dwc2_host_chan *chan, int chnum,
592 					enum dwc2_halt_status halt_status);
593 
594 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
595 			  gfp_t mem_flags);
596 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh);
597 
598 /* Check if QH is non-periodic */
599 #define dwc2_qh_is_non_per(_qh_ptr_) \
600 	((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \
601 	 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL)
602 
603 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC
604 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; }
605 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; }
606 static inline bool dbg_urb(struct urb *urb) { return true; }
607 static inline bool dbg_perio(void) { return true; }
608 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */
609 static inline bool dbg_hc(struct dwc2_host_chan *hc)
610 {
611 	return hc->ep_type == USB_ENDPOINT_XFER_BULK ||
612 	       hc->ep_type == USB_ENDPOINT_XFER_CONTROL;
613 }
614 
615 static inline bool dbg_qh(struct dwc2_qh *qh)
616 {
617 	return qh->ep_type == USB_ENDPOINT_XFER_BULK ||
618 	       qh->ep_type == USB_ENDPOINT_XFER_CONTROL;
619 }
620 
621 static inline bool dbg_urb(struct urb *urb)
622 {
623 	return usb_pipetype(urb->pipe) == PIPE_BULK ||
624 	       usb_pipetype(urb->pipe) == PIPE_CONTROL;
625 }
626 
627 static inline bool dbg_perio(void) { return false; }
628 #endif
629 
630 /*
631  * Returns true if frame1 index is greater than frame2 index. The comparison
632  * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the
633  * frame number when the max index frame number is reached.
634  */
635 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2)
636 {
637 	u16 diff = fr_idx1 - fr_idx2;
638 	u16 sign = diff & (FRLISTEN_64_SIZE >> 1);
639 
640 	return diff && !sign;
641 }
642 
643 /*
644  * Returns true if frame1 is less than or equal to frame2. The comparison is
645  * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the
646  * frame number when the max frame number is reached.
647  */
648 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2)
649 {
650 	return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1);
651 }
652 
653 /*
654  * Returns true if frame1 is greater than frame2. The comparison is done
655  * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
656  * number when the max frame number is reached.
657  */
658 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2)
659 {
660 	return (frame1 != frame2) &&
661 	       ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1);
662 }
663 
664 /*
665  * Increments frame by the amount specified by inc. The addition is done
666  * modulo HFNUM_MAX_FRNUM. Returns the incremented value.
667  */
668 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc)
669 {
670 	return (frame + inc) & HFNUM_MAX_FRNUM;
671 }
672 
673 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec)
674 {
675 	return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM;
676 }
677 
678 static inline u16 dwc2_full_frame_num(u16 frame)
679 {
680 	return (frame & HFNUM_MAX_FRNUM) >> 3;
681 }
682 
683 static inline u16 dwc2_micro_frame_num(u16 frame)
684 {
685 	return frame & 0x7;
686 }
687 
688 /*
689  * Returns the Core Interrupt Status register contents, ANDed with the Core
690  * Interrupt Mask register contents
691  */
692 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg)
693 {
694 	return dwc2_readl(hsotg, GINTSTS) &
695 	       dwc2_readl(hsotg, GINTMSK);
696 }
697 
698 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb)
699 {
700 	return dwc2_urb->status;
701 }
702 
703 static inline u32 dwc2_hcd_urb_get_actual_length(
704 		struct dwc2_hcd_urb *dwc2_urb)
705 {
706 	return dwc2_urb->actual_length;
707 }
708 
709 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb)
710 {
711 	return dwc2_urb->error_count;
712 }
713 
714 static inline void dwc2_hcd_urb_set_iso_desc_params(
715 		struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset,
716 		u32 length)
717 {
718 	dwc2_urb->iso_descs[desc_num].offset = offset;
719 	dwc2_urb->iso_descs[desc_num].length = length;
720 }
721 
722 static inline u32 dwc2_hcd_urb_get_iso_desc_status(
723 		struct dwc2_hcd_urb *dwc2_urb, int desc_num)
724 {
725 	return dwc2_urb->iso_descs[desc_num].status;
726 }
727 
728 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length(
729 		struct dwc2_hcd_urb *dwc2_urb, int desc_num)
730 {
731 	return dwc2_urb->iso_descs[desc_num].actual_length;
732 }
733 
734 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg,
735 						  struct usb_host_endpoint *ep)
736 {
737 	struct dwc2_qh *qh = ep->hcpriv;
738 
739 	if (qh && !list_empty(&qh->qh_list_entry))
740 		return 1;
741 
742 	return 0;
743 }
744 
745 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg,
746 					    struct usb_host_endpoint *ep)
747 {
748 	struct dwc2_qh *qh = ep->hcpriv;
749 
750 	if (!qh) {
751 		WARN_ON(1);
752 		return 0;
753 	}
754 
755 	return qh->host_us;
756 }
757 
758 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
759 			       struct dwc2_host_chan *chan, int chnum,
760 				      struct dwc2_qtd *qtd);
761 
762 /* HCD Core API */
763 
764 /**
765  * dwc2_handle_hcd_intr() - Called on every hardware interrupt
766  *
767  * @hsotg: The DWC2 HCD
768  *
769  * Returns IRQ_HANDLED if interrupt is handled
770  * Return IRQ_NONE if interrupt is not handled
771  */
772 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg);
773 
774 /**
775  * dwc2_hcd_stop() - Halts the DWC_otg host mode operation
776  *
777  * @hsotg: The DWC2 HCD
778  */
779 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg);
780 
781 /**
782  * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host,
783  * and 0 otherwise
784  *
785  * @hsotg: The DWC2 HCD
786  */
787 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg);
788 
789 /**
790  * dwc2_hcd_dump_state() - Dumps hsotg state
791  *
792  * @hsotg: The DWC2 HCD
793  *
794  * NOTE: This function will be removed once the peripheral controller code
795  * is integrated and the driver is stable
796  */
797 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg);
798 
799 /* URB interface */
800 
801 /* Transfer flags */
802 #define URB_GIVEBACK_ASAP	0x1
803 #define URB_SEND_ZERO_PACKET	0x2
804 
805 /* Host driver callbacks */
806 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg,
807 				      void *context, gfp_t mem_flags,
808 				      int *ttport);
809 
810 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg,
811 			   struct dwc2_tt *dwc_tt);
812 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context);
813 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
814 			int status);
815 
816 #endif /* __DWC2_HCD_H__ */
817