1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.h - DesignWare HS OTG Controller host-mode declarations 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 #ifndef __DWC2_HCD_H__ 38 #define __DWC2_HCD_H__ 39 40 /* 41 * This file contains the structures, constants, and interfaces for the 42 * Host Contoller Driver (HCD) 43 * 44 * The Host Controller Driver (HCD) is responsible for translating requests 45 * from the USB Driver into the appropriate actions on the DWC_otg controller. 46 * It isolates the USBD from the specifics of the controller by providing an 47 * API to the USBD. 48 */ 49 50 struct dwc2_qh; 51 52 /** 53 * struct dwc2_host_chan - Software host channel descriptor 54 * 55 * @hc_num: Host channel number, used for register address lookup 56 * @dev_addr: Address of the device 57 * @ep_num: Endpoint of the device 58 * @ep_is_in: Endpoint direction 59 * @speed: Device speed. One of the following values: 60 * - USB_SPEED_LOW 61 * - USB_SPEED_FULL 62 * - USB_SPEED_HIGH 63 * @ep_type: Endpoint type. One of the following values: 64 * - USB_ENDPOINT_XFER_CONTROL: 0 65 * - USB_ENDPOINT_XFER_ISOC: 1 66 * - USB_ENDPOINT_XFER_BULK: 2 67 * - USB_ENDPOINT_XFER_INTR: 3 68 * @max_packet: Max packet size in bytes 69 * @data_pid_start: PID for initial transaction. 70 * 0: DATA0 71 * 1: DATA2 72 * 2: DATA1 73 * 3: MDATA (non-Control EP), 74 * SETUP (Control EP) 75 * @multi_count: Number of additional periodic transactions per 76 * (micro)frame 77 * @xfer_buf: Pointer to current transfer buffer position 78 * @xfer_dma: DMA address of xfer_buf 79 * @xfer_len: Total number of bytes to transfer 80 * @xfer_count: Number of bytes transferred so far 81 * @start_pkt_count: Packet count at start of transfer 82 * @xfer_started: True if the transfer has been started 83 * @do_ping: True if a PING request should be issued on this channel 84 * @error_state: True if the error count for this transaction is non-zero 85 * @halt_on_queue: True if this channel should be halted the next time a 86 * request is queued for the channel. This is necessary in 87 * slave mode if no request queue space is available when 88 * an attempt is made to halt the channel. 89 * @halt_pending: True if the host channel has been halted, but the core 90 * is not finished flushing queued requests 91 * @do_split: Enable split for the channel 92 * @complete_split: Enable complete split 93 * @hub_addr: Address of high speed hub for the split 94 * @hub_port: Port of the low/full speed device for the split 95 * @xact_pos: Split transaction position. One of the following values: 96 * - DWC2_HCSPLT_XACTPOS_MID 97 * - DWC2_HCSPLT_XACTPOS_BEGIN 98 * - DWC2_HCSPLT_XACTPOS_END 99 * - DWC2_HCSPLT_XACTPOS_ALL 100 * @requests: Number of requests issued for this channel since it was 101 * assigned to the current transfer (not counting PINGs) 102 * @schinfo: Scheduling micro-frame bitmap 103 * @ntd: Number of transfer descriptors for the transfer 104 * @halt_status: Reason for halting the host channel 105 * @hcint: Contents of the HCINT register when the interrupt came 106 * @qh: QH for the transfer being processed by this channel 107 * @hc_list_entry: For linking to list of host channels 108 * @desc_list_addr: Current QH's descriptor list DMA address 109 * @desc_list_sz: Current QH's descriptor list size 110 * @split_order_list_entry: List entry for keeping track of the order of splits 111 * 112 * This structure represents the state of a single host channel when acting in 113 * host mode. It contains the data items needed to transfer packets to an 114 * endpoint via a host channel. 115 */ 116 struct dwc2_host_chan { 117 u8 hc_num; 118 119 unsigned dev_addr:7; 120 unsigned ep_num:4; 121 unsigned ep_is_in:1; 122 unsigned speed:4; 123 unsigned ep_type:2; 124 unsigned max_packet:11; 125 unsigned data_pid_start:2; 126 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 127 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 128 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 129 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 130 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 131 132 unsigned multi_count:2; 133 134 u8 *xfer_buf; 135 dma_addr_t xfer_dma; 136 u32 xfer_len; 137 u32 xfer_count; 138 u16 start_pkt_count; 139 u8 xfer_started; 140 u8 do_ping; 141 u8 error_state; 142 u8 halt_on_queue; 143 u8 halt_pending; 144 u8 do_split; 145 u8 complete_split; 146 u8 hub_addr; 147 u8 hub_port; 148 u8 xact_pos; 149 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 150 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 151 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 152 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 153 154 u8 requests; 155 u8 schinfo; 156 u16 ntd; 157 enum dwc2_halt_status halt_status; 158 u32 hcint; 159 struct dwc2_qh *qh; 160 struct list_head hc_list_entry; 161 dma_addr_t desc_list_addr; 162 u32 desc_list_sz; 163 struct list_head split_order_list_entry; 164 }; 165 166 struct dwc2_hcd_pipe_info { 167 u8 dev_addr; 168 u8 ep_num; 169 u8 pipe_type; 170 u8 pipe_dir; 171 u16 mps; 172 }; 173 174 struct dwc2_hcd_iso_packet_desc { 175 u32 offset; 176 u32 length; 177 u32 actual_length; 178 u32 status; 179 }; 180 181 struct dwc2_qtd; 182 183 struct dwc2_hcd_urb { 184 void *priv; 185 struct dwc2_qtd *qtd; 186 void *buf; 187 dma_addr_t dma; 188 void *setup_packet; 189 dma_addr_t setup_dma; 190 u32 length; 191 u32 actual_length; 192 u32 status; 193 u32 error_count; 194 u32 packet_count; 195 u32 flags; 196 u16 interval; 197 struct dwc2_hcd_pipe_info pipe_info; 198 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 199 }; 200 201 /* Phases for control transfers */ 202 enum dwc2_control_phase { 203 DWC2_CONTROL_SETUP, 204 DWC2_CONTROL_DATA, 205 DWC2_CONTROL_STATUS, 206 }; 207 208 /* Transaction types */ 209 enum dwc2_transaction_type { 210 DWC2_TRANSACTION_NONE, 211 DWC2_TRANSACTION_PERIODIC, 212 DWC2_TRANSACTION_NON_PERIODIC, 213 DWC2_TRANSACTION_ALL, 214 }; 215 216 /* The number of elements per LS bitmap (per port on multi_tt) */ 217 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ 218 BITS_PER_LONG) 219 220 /** 221 * struct dwc2_tt - dwc2 data associated with a usb_tt 222 * 223 * @refcount: Number of Queue Heads (QHs) holding a reference. 224 * @usb_tt: Pointer back to the official usb_tt. 225 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted 226 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP 227 * elements (so sizeof(long) times that in bytes). 228 * 229 * This structure is stored in the hcpriv of the official usb_tt. 230 */ 231 struct dwc2_tt { 232 int refcount; 233 struct usb_tt *usb_tt; 234 unsigned long periodic_bitmaps[]; 235 }; 236 237 /** 238 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. 239 * 240 * @start_schedule_us: The start time on the main bus schedule. Note that 241 * the main bus schedule is tightly packed and this 242 * time should be interpreted as tightly packed (so 243 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us 244 * instead of 125 us). 245 * @duration_us: How long this transfer goes. 246 */ 247 248 struct dwc2_hs_transfer_time { 249 u32 start_schedule_us; 250 u16 duration_us; 251 }; 252 253 /** 254 * struct dwc2_qh - Software queue head structure 255 * 256 * @hsotg: The HCD state structure for the DWC OTG controller 257 * @ep_type: Endpoint type. One of the following values: 258 * - USB_ENDPOINT_XFER_CONTROL 259 * - USB_ENDPOINT_XFER_BULK 260 * - USB_ENDPOINT_XFER_INT 261 * - USB_ENDPOINT_XFER_ISOC 262 * @ep_is_in: Endpoint direction 263 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 264 * @dev_speed: Device speed. One of the following values: 265 * - USB_SPEED_LOW 266 * - USB_SPEED_FULL 267 * - USB_SPEED_HIGH 268 * @data_toggle: Determines the PID of the next data packet for 269 * non-controltransfers. Ignored for control transfers. 270 * One of the following values: 271 * - DWC2_HC_PID_DATA0 272 * - DWC2_HC_PID_DATA1 273 * @ping_state: Ping state 274 * @do_split: Full/low speed endpoint on high-speed hub requires split 275 * @td_first: Index of first activated isochronous transfer descriptor 276 * @td_last: Index of last activated isochronous transfer descriptor 277 * @host_us: Bandwidth in microseconds per transfer as seen by host 278 * @device_us: Bandwidth in microseconds per transfer as seen by device 279 * @host_interval: Interval between transfers as seen by the host. If 280 * the host is high speed and the device is low speed this 281 * will be 8 times device interval. 282 * @device_interval: Interval between transfers as seen by the device. 283 * interval. 284 * @next_active_frame: (Micro)frame _before_ we next need to put something on 285 * the bus. We'll move the qh to active here. If the 286 * host is in high speed mode this will be a uframe. If 287 * the host is in low speed mode this will be a full frame. 288 * @start_active_frame: If we are partway through a split transfer, this will be 289 * what next_active_frame was when we started. Otherwise 290 * it should always be the same as next_active_frame. 291 * @num_hs_transfers: Number of transfers in hs_transfers. 292 * Normally this is 1 but can be more than one for splits. 293 * Always >= 1 unless the host is in low/full speed mode. 294 * @hs_transfers: Transfers that are scheduled as seen by the high speed 295 * bus. Not used if host is in low or full speed mode (but 296 * note that it IS USED if the device is low or full speed 297 * as long as the HOST is in high speed mode). 298 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus 299 * schedule that's being used by this device. This 300 * will be on the periodic_bitmap in a 301 * "struct dwc2_tt". Not used if this device is high 302 * speed. Note that this is in "schedule slice" which 303 * is tightly packed. 304 * @ntd: Actual number of transfer descriptors in a list 305 * @qtd_list: List of QTDs for this QH 306 * @channel: Host channel currently processing transfers for this QH 307 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 308 * schedule 309 * @desc_list: List of transfer descriptors 310 * @desc_list_dma: Physical address of desc_list 311 * @desc_list_sz: Size of descriptors list 312 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 313 * descriptor and indicates original XferSize value for the 314 * descriptor 315 * @unreserve_timer: Timer for releasing periodic reservation. 316 * @wait_timer: Timer used to wait before re-queuing. 317 * @dwc_tt: Pointer to our tt info (or NULL if no tt). 318 * @ttport: Port number within our tt. 319 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 320 * @unreserve_pending: True if we planned to unreserve but haven't yet. 321 * @schedule_low_speed: True if we have a low/full speed component (either the 322 * host is in low/full speed mode or do_split). 323 * @want_wait: We should wait before re-queuing; only matters for non- 324 * periodic transfers and is ignored for periodic ones. 325 * @wait_timer_cancel: Set to true to cancel the wait_timer. 326 * 327 * @tt_buffer_dirty: True if EP's TT buffer is not clean. 328 * A Queue Head (QH) holds the static characteristics of an endpoint and 329 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 330 * be entered in either the non-periodic or periodic schedule. 331 */ 332 struct dwc2_qh { 333 struct dwc2_hsotg *hsotg; 334 u8 ep_type; 335 u8 ep_is_in; 336 u16 maxp; 337 u8 dev_speed; 338 u8 data_toggle; 339 u8 ping_state; 340 u8 do_split; 341 u8 td_first; 342 u8 td_last; 343 u16 host_us; 344 u16 device_us; 345 u16 host_interval; 346 u16 device_interval; 347 u16 next_active_frame; 348 u16 start_active_frame; 349 s16 num_hs_transfers; 350 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; 351 u32 ls_start_schedule_slice; 352 u16 ntd; 353 struct list_head qtd_list; 354 struct dwc2_host_chan *channel; 355 struct list_head qh_list_entry; 356 struct dwc2_dma_desc *desc_list; 357 dma_addr_t desc_list_dma; 358 u32 desc_list_sz; 359 u32 *n_bytes; 360 struct timer_list unreserve_timer; 361 struct timer_list wait_timer; 362 struct dwc2_tt *dwc_tt; 363 int ttport; 364 unsigned tt_buffer_dirty:1; 365 unsigned unreserve_pending:1; 366 unsigned schedule_low_speed:1; 367 unsigned want_wait:1; 368 unsigned wait_timer_cancel:1; 369 }; 370 371 /** 372 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 373 * 374 * @control_phase: Current phase for control transfers (Setup, Data, or 375 * Status) 376 * @in_process: Indicates if this QTD is currently processed by HW 377 * @data_toggle: Determines the PID of the next data packet for the 378 * data phase of control transfers. Ignored for other 379 * transfer types. One of the following values: 380 * - DWC2_HC_PID_DATA0 381 * - DWC2_HC_PID_DATA1 382 * @complete_split: Keeps track of the current split type for FS/LS 383 * endpoints on a HS Hub 384 * @isoc_split_pos: Position of the ISOC split in full/low speed 385 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 386 * transfer. A frame descriptor describes the buffer 387 * position and length of the data to be transferred in the 388 * next scheduled (micro)frame of an isochronous transfer. 389 * It also holds status for that transaction. The frame 390 * index starts at 0. 391 * @isoc_split_offset: Position of the ISOC split in the buffer for the 392 * current frame 393 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 394 * @error_count: Holds the number of bus errors that have occurred for 395 * a transaction within this transfer 396 * @n_desc: Number of DMA descriptors for this QTD 397 * @isoc_frame_index_last: Last activated frame (packet) index, used in 398 * descriptor DMA mode only 399 * @num_naks: Number of NAKs received on this QTD. 400 * @urb: URB for this transfer 401 * @qh: Queue head for this QTD 402 * @qtd_list_entry: For linking to the QH's list of QTDs 403 * @isoc_td_first: Index of first activated isochronous transfer 404 * descriptor in Descriptor DMA mode 405 * @isoc_td_last: Index of last activated isochronous transfer 406 * descriptor in Descriptor DMA mode 407 * 408 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 409 * interrupt, or isochronous transfer. A single QTD is created for each URB 410 * (of one of these types) submitted to the HCD. The transfer associated with 411 * a QTD may require one or multiple transactions. 412 * 413 * A QTD is linked to a Queue Head, which is entered in either the 414 * non-periodic or periodic schedule for execution. When a QTD is chosen for 415 * execution, some or all of its transactions may be executed. After 416 * execution, the state of the QTD is updated. The QTD may be retired if all 417 * its transactions are complete or if an error occurred. Otherwise, it 418 * remains in the schedule so more transactions can be executed later. 419 */ 420 struct dwc2_qtd { 421 enum dwc2_control_phase control_phase; 422 u8 in_process; 423 u8 data_toggle; 424 u8 complete_split; 425 u8 isoc_split_pos; 426 u16 isoc_frame_index; 427 u16 isoc_split_offset; 428 u16 isoc_td_last; 429 u16 isoc_td_first; 430 u32 ssplit_out_xfer_count; 431 u8 error_count; 432 u8 n_desc; 433 u16 isoc_frame_index_last; 434 u16 num_naks; 435 struct dwc2_hcd_urb *urb; 436 struct dwc2_qh *qh; 437 struct list_head qtd_list_entry; 438 }; 439 440 #ifdef DEBUG 441 struct hc_xfer_info { 442 struct dwc2_hsotg *hsotg; 443 struct dwc2_host_chan *chan; 444 }; 445 #endif 446 447 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 448 449 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 450 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 451 { 452 return (struct usb_hcd *)hsotg->priv; 453 } 454 455 /* 456 * Inline used to disable one channel interrupt. Channel interrupts are 457 * disabled when the channel is halted or released by the interrupt handler. 458 * There is no need to handle further interrupts of that type until the 459 * channel is re-assigned. In fact, subsequent handling may cause crashes 460 * because the channel structures are cleaned up when the channel is released. 461 */ 462 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 463 { 464 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 465 466 mask &= ~intr; 467 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 468 } 469 470 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 471 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 472 enum dwc2_halt_status halt_status); 473 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 474 struct dwc2_host_chan *chan); 475 476 /* 477 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 478 * are read as 1, they won't clear when written back. 479 */ 480 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 481 { 482 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 483 484 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 485 return hprt0; 486 } 487 488 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 489 { 490 return pipe->ep_num; 491 } 492 493 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 494 { 495 return pipe->pipe_type; 496 } 497 498 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 499 { 500 return pipe->mps; 501 } 502 503 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 504 { 505 return pipe->dev_addr; 506 } 507 508 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 509 { 510 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 511 } 512 513 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 514 { 515 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 516 } 517 518 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 519 { 520 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 521 } 522 523 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 524 { 525 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 526 } 527 528 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 529 { 530 return pipe->pipe_dir == USB_DIR_IN; 531 } 532 533 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 534 { 535 return !dwc2_hcd_is_pipe_in(pipe); 536 } 537 538 int dwc2_hcd_init(struct dwc2_hsotg *hsotg); 539 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 540 541 /* Transaction Execution Functions */ 542 enum dwc2_transaction_type dwc2_hcd_select_transactions( 543 struct dwc2_hsotg *hsotg); 544 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 545 enum dwc2_transaction_type tr_type); 546 547 /* Schedule Queue Functions */ 548 /* Implemented in hcd_queue.c */ 549 struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 550 struct dwc2_hcd_urb *urb, 551 gfp_t mem_flags); 552 void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 553 int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 554 void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 555 void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 556 int sched_csplit); 557 558 void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 559 int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 560 struct dwc2_qh *qh); 561 562 /* Unlinks and frees a QTD */ 563 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 564 struct dwc2_qtd *qtd, 565 struct dwc2_qh *qh) 566 { 567 list_del(&qtd->qtd_list_entry); 568 kfree(qtd); 569 qtd = NULL; 570 } 571 572 /* Descriptor DMA support functions */ 573 void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 574 struct dwc2_qh *qh); 575 void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 576 struct dwc2_host_chan *chan, int chnum, 577 enum dwc2_halt_status halt_status); 578 579 int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 580 gfp_t mem_flags); 581 void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 582 583 /* Check if QH is non-periodic */ 584 #define dwc2_qh_is_non_per(_qh_ptr_) \ 585 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 586 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 587 588 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 589 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 590 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 591 static inline bool dbg_urb(struct urb *urb) { return true; } 592 static inline bool dbg_perio(void) { return true; } 593 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 594 static inline bool dbg_hc(struct dwc2_host_chan *hc) 595 { 596 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 597 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 598 } 599 600 static inline bool dbg_qh(struct dwc2_qh *qh) 601 { 602 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 603 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 604 } 605 606 static inline bool dbg_urb(struct urb *urb) 607 { 608 return usb_pipetype(urb->pipe) == PIPE_BULK || 609 usb_pipetype(urb->pipe) == PIPE_CONTROL; 610 } 611 612 static inline bool dbg_perio(void) { return false; } 613 #endif 614 615 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 616 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 617 618 /* Packet size for any kind of endpoint descriptor */ 619 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 620 621 /* 622 * Returns true if frame1 index is greater than frame2 index. The comparison 623 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 624 * frame number when the max index frame number is reached. 625 */ 626 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 627 { 628 u16 diff = fr_idx1 - fr_idx2; 629 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 630 631 return diff && !sign; 632 } 633 634 /* 635 * Returns true if frame1 is less than or equal to frame2. The comparison is 636 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 637 * frame number when the max frame number is reached. 638 */ 639 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 640 { 641 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 642 } 643 644 /* 645 * Returns true if frame1 is greater than frame2. The comparison is done 646 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 647 * number when the max frame number is reached. 648 */ 649 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 650 { 651 return (frame1 != frame2) && 652 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 653 } 654 655 /* 656 * Increments frame by the amount specified by inc. The addition is done 657 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 658 */ 659 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 660 { 661 return (frame + inc) & HFNUM_MAX_FRNUM; 662 } 663 664 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 665 { 666 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 667 } 668 669 static inline u16 dwc2_full_frame_num(u16 frame) 670 { 671 return (frame & HFNUM_MAX_FRNUM) >> 3; 672 } 673 674 static inline u16 dwc2_micro_frame_num(u16 frame) 675 { 676 return frame & 0x7; 677 } 678 679 /* 680 * Returns the Core Interrupt Status register contents, ANDed with the Core 681 * Interrupt Mask register contents 682 */ 683 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 684 { 685 return dwc2_readl(hsotg->regs + GINTSTS) & 686 dwc2_readl(hsotg->regs + GINTMSK); 687 } 688 689 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 690 { 691 return dwc2_urb->status; 692 } 693 694 static inline u32 dwc2_hcd_urb_get_actual_length( 695 struct dwc2_hcd_urb *dwc2_urb) 696 { 697 return dwc2_urb->actual_length; 698 } 699 700 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 701 { 702 return dwc2_urb->error_count; 703 } 704 705 static inline void dwc2_hcd_urb_set_iso_desc_params( 706 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 707 u32 length) 708 { 709 dwc2_urb->iso_descs[desc_num].offset = offset; 710 dwc2_urb->iso_descs[desc_num].length = length; 711 } 712 713 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 714 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 715 { 716 return dwc2_urb->iso_descs[desc_num].status; 717 } 718 719 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 720 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 721 { 722 return dwc2_urb->iso_descs[desc_num].actual_length; 723 } 724 725 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 726 struct usb_host_endpoint *ep) 727 { 728 struct dwc2_qh *qh = ep->hcpriv; 729 730 if (qh && !list_empty(&qh->qh_list_entry)) 731 return 1; 732 733 return 0; 734 } 735 736 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 737 struct usb_host_endpoint *ep) 738 { 739 struct dwc2_qh *qh = ep->hcpriv; 740 741 if (!qh) { 742 WARN_ON(1); 743 return 0; 744 } 745 746 return qh->host_us; 747 } 748 749 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 750 struct dwc2_host_chan *chan, int chnum, 751 struct dwc2_qtd *qtd); 752 753 /* HCD Core API */ 754 755 /** 756 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 757 * 758 * @hsotg: The DWC2 HCD 759 * 760 * Returns IRQ_HANDLED if interrupt is handled 761 * Return IRQ_NONE if interrupt is not handled 762 */ 763 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 764 765 /** 766 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 767 * 768 * @hsotg: The DWC2 HCD 769 */ 770 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 771 772 /** 773 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 774 * and 0 otherwise 775 * 776 * @hsotg: The DWC2 HCD 777 */ 778 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 779 780 /** 781 * dwc2_hcd_dump_state() - Dumps hsotg state 782 * 783 * @hsotg: The DWC2 HCD 784 * 785 * NOTE: This function will be removed once the peripheral controller code 786 * is integrated and the driver is stable 787 */ 788 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 789 790 /* URB interface */ 791 792 /* Transfer flags */ 793 #define URB_GIVEBACK_ASAP 0x1 794 #define URB_SEND_ZERO_PACKET 0x2 795 796 /* Host driver callbacks */ 797 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 798 void *context, gfp_t mem_flags, 799 int *ttport); 800 801 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 802 struct dwc2_tt *dwc_tt); 803 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 804 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 805 int status); 806 807 #endif /* __DWC2_HCD_H__ */ 808