1 /* 2 * hcd.h - DesignWare HS OTG Controller host-mode declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 #ifndef __DWC2_HCD_H__ 37 #define __DWC2_HCD_H__ 38 39 /* 40 * This file contains the structures, constants, and interfaces for the 41 * Host Contoller Driver (HCD) 42 * 43 * The Host Controller Driver (HCD) is responsible for translating requests 44 * from the USB Driver into the appropriate actions on the DWC_otg controller. 45 * It isolates the USBD from the specifics of the controller by providing an 46 * API to the USBD. 47 */ 48 49 struct dwc2_qh; 50 51 /** 52 * struct dwc2_host_chan - Software host channel descriptor 53 * 54 * @hc_num: Host channel number, used for register address lookup 55 * @dev_addr: Address of the device 56 * @ep_num: Endpoint of the device 57 * @ep_is_in: Endpoint direction 58 * @speed: Device speed. One of the following values: 59 * - USB_SPEED_LOW 60 * - USB_SPEED_FULL 61 * - USB_SPEED_HIGH 62 * @ep_type: Endpoint type. One of the following values: 63 * - USB_ENDPOINT_XFER_CONTROL: 0 64 * - USB_ENDPOINT_XFER_ISOC: 1 65 * - USB_ENDPOINT_XFER_BULK: 2 66 * - USB_ENDPOINT_XFER_INTR: 3 67 * @max_packet: Max packet size in bytes 68 * @data_pid_start: PID for initial transaction. 69 * 0: DATA0 70 * 1: DATA2 71 * 2: DATA1 72 * 3: MDATA (non-Control EP), 73 * SETUP (Control EP) 74 * @multi_count: Number of additional periodic transactions per 75 * (micro)frame 76 * @xfer_buf: Pointer to current transfer buffer position 77 * @xfer_dma: DMA address of xfer_buf 78 * @xfer_len: Total number of bytes to transfer 79 * @xfer_count: Number of bytes transferred so far 80 * @start_pkt_count: Packet count at start of transfer 81 * @xfer_started: True if the transfer has been started 82 * @ping: True if a PING request should be issued on this channel 83 * @error_state: True if the error count for this transaction is non-zero 84 * @halt_on_queue: True if this channel should be halted the next time a 85 * request is queued for the channel. This is necessary in 86 * slave mode if no request queue space is available when 87 * an attempt is made to halt the channel. 88 * @halt_pending: True if the host channel has been halted, but the core 89 * is not finished flushing queued requests 90 * @do_split: Enable split for the channel 91 * @complete_split: Enable complete split 92 * @hub_addr: Address of high speed hub for the split 93 * @hub_port: Port of the low/full speed device for the split 94 * @xact_pos: Split transaction position. One of the following values: 95 * - DWC2_HCSPLT_XACTPOS_MID 96 * - DWC2_HCSPLT_XACTPOS_BEGIN 97 * - DWC2_HCSPLT_XACTPOS_END 98 * - DWC2_HCSPLT_XACTPOS_ALL 99 * @requests: Number of requests issued for this channel since it was 100 * assigned to the current transfer (not counting PINGs) 101 * @schinfo: Scheduling micro-frame bitmap 102 * @ntd: Number of transfer descriptors for the transfer 103 * @halt_status: Reason for halting the host channel 104 * @hcint Contents of the HCINT register when the interrupt came 105 * @qh: QH for the transfer being processed by this channel 106 * @hc_list_entry: For linking to list of host channels 107 * @desc_list_addr: Current QH's descriptor list DMA address 108 * @desc_list_sz: Current QH's descriptor list size 109 * @split_order_list_entry: List entry for keeping track of the order of splits 110 * 111 * This structure represents the state of a single host channel when acting in 112 * host mode. It contains the data items needed to transfer packets to an 113 * endpoint via a host channel. 114 */ 115 struct dwc2_host_chan { 116 u8 hc_num; 117 118 unsigned dev_addr:7; 119 unsigned ep_num:4; 120 unsigned ep_is_in:1; 121 unsigned speed:4; 122 unsigned ep_type:2; 123 unsigned max_packet:11; 124 unsigned data_pid_start:2; 125 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 126 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 127 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 128 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 129 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 130 131 unsigned multi_count:2; 132 133 u8 *xfer_buf; 134 dma_addr_t xfer_dma; 135 u32 xfer_len; 136 u32 xfer_count; 137 u16 start_pkt_count; 138 u8 xfer_started; 139 u8 do_ping; 140 u8 error_state; 141 u8 halt_on_queue; 142 u8 halt_pending; 143 u8 do_split; 144 u8 complete_split; 145 u8 hub_addr; 146 u8 hub_port; 147 u8 xact_pos; 148 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 149 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 150 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 151 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 152 153 u8 requests; 154 u8 schinfo; 155 u16 ntd; 156 enum dwc2_halt_status halt_status; 157 u32 hcint; 158 struct dwc2_qh *qh; 159 struct list_head hc_list_entry; 160 dma_addr_t desc_list_addr; 161 u32 desc_list_sz; 162 struct list_head split_order_list_entry; 163 }; 164 165 struct dwc2_hcd_pipe_info { 166 u8 dev_addr; 167 u8 ep_num; 168 u8 pipe_type; 169 u8 pipe_dir; 170 u16 mps; 171 }; 172 173 struct dwc2_hcd_iso_packet_desc { 174 u32 offset; 175 u32 length; 176 u32 actual_length; 177 u32 status; 178 }; 179 180 struct dwc2_qtd; 181 182 struct dwc2_hcd_urb { 183 void *priv; 184 struct dwc2_qtd *qtd; 185 void *buf; 186 dma_addr_t dma; 187 void *setup_packet; 188 dma_addr_t setup_dma; 189 u32 length; 190 u32 actual_length; 191 u32 status; 192 u32 error_count; 193 u32 packet_count; 194 u32 flags; 195 u16 interval; 196 struct dwc2_hcd_pipe_info pipe_info; 197 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 198 }; 199 200 /* Phases for control transfers */ 201 enum dwc2_control_phase { 202 DWC2_CONTROL_SETUP, 203 DWC2_CONTROL_DATA, 204 DWC2_CONTROL_STATUS, 205 }; 206 207 /* Transaction types */ 208 enum dwc2_transaction_type { 209 DWC2_TRANSACTION_NONE, 210 DWC2_TRANSACTION_PERIODIC, 211 DWC2_TRANSACTION_NON_PERIODIC, 212 DWC2_TRANSACTION_ALL, 213 }; 214 215 /* The number of elements per LS bitmap (per port on multi_tt) */ 216 #define DWC2_ELEMENTS_PER_LS_BITMAP DIV_ROUND_UP(DWC2_LS_SCHEDULE_SLICES, \ 217 BITS_PER_LONG) 218 219 /** 220 * struct dwc2_tt - dwc2 data associated with a usb_tt 221 * 222 * @refcount: Number of Queue Heads (QHs) holding a reference. 223 * @usb_tt: Pointer back to the official usb_tt. 224 * @periodic_bitmaps: Bitmap for which parts of the 1ms frame are accounted 225 * for already. Each is DWC2_ELEMENTS_PER_LS_BITMAP 226 * elements (so sizeof(long) times that in bytes). 227 * 228 * This structure is stored in the hcpriv of the official usb_tt. 229 */ 230 struct dwc2_tt { 231 int refcount; 232 struct usb_tt *usb_tt; 233 unsigned long periodic_bitmaps[]; 234 }; 235 236 /** 237 * struct dwc2_hs_transfer_time - Info about a transfer on the high speed bus. 238 * 239 * @start_schedule_usecs: The start time on the main bus schedule. Note that 240 * the main bus schedule is tightly packed and this 241 * time should be interpreted as tightly packed (so 242 * uFrame 0 starts at 0 us, uFrame 1 starts at 100 us 243 * instead of 125 us). 244 * @duration_us: How long this transfer goes. 245 */ 246 247 struct dwc2_hs_transfer_time { 248 u32 start_schedule_us; 249 u16 duration_us; 250 }; 251 252 /** 253 * struct dwc2_qh - Software queue head structure 254 * 255 * @hsotg: The HCD state structure for the DWC OTG controller 256 * @ep_type: Endpoint type. One of the following values: 257 * - USB_ENDPOINT_XFER_CONTROL 258 * - USB_ENDPOINT_XFER_BULK 259 * - USB_ENDPOINT_XFER_INT 260 * - USB_ENDPOINT_XFER_ISOC 261 * @ep_is_in: Endpoint direction 262 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 263 * @dev_speed: Device speed. One of the following values: 264 * - USB_SPEED_LOW 265 * - USB_SPEED_FULL 266 * - USB_SPEED_HIGH 267 * @data_toggle: Determines the PID of the next data packet for 268 * non-controltransfers. Ignored for control transfers. 269 * One of the following values: 270 * - DWC2_HC_PID_DATA0 271 * - DWC2_HC_PID_DATA1 272 * @ping_state: Ping state 273 * @do_split: Full/low speed endpoint on high-speed hub requires split 274 * @td_first: Index of first activated isochronous transfer descriptor 275 * @td_last: Index of last activated isochronous transfer descriptor 276 * @host_us: Bandwidth in microseconds per transfer as seen by host 277 * @device_us: Bandwidth in microseconds per transfer as seen by device 278 * @host_interval: Interval between transfers as seen by the host. If 279 * the host is high speed and the device is low speed this 280 * will be 8 times device interval. 281 * @device_interval: Interval between transfers as seen by the device. 282 * interval. 283 * @next_active_frame: (Micro)frame _before_ we next need to put something on 284 * the bus. We'll move the qh to active here. If the 285 * host is in high speed mode this will be a uframe. If 286 * the host is in low speed mode this will be a full frame. 287 * @start_active_frame: If we are partway through a split transfer, this will be 288 * what next_active_frame was when we started. Otherwise 289 * it should always be the same as next_active_frame. 290 * @num_hs_transfers: Number of transfers in hs_transfers. 291 * Normally this is 1 but can be more than one for splits. 292 * Always >= 1 unless the host is in low/full speed mode. 293 * @hs_transfers: Transfers that are scheduled as seen by the high speed 294 * bus. Not used if host is in low or full speed mode (but 295 * note that it IS USED if the device is low or full speed 296 * as long as the HOST is in high speed mode). 297 * @ls_start_schedule_slice: Start time (in slices) on the low speed bus 298 * schedule that's being used by this device. This 299 * will be on the periodic_bitmap in a 300 * "struct dwc2_tt". Not used if this device is high 301 * speed. Note that this is in "schedule slice" which 302 * is tightly packed. 303 * @ls_duration_us: Duration on the low speed bus schedule. 304 * @ntd: Actual number of transfer descriptors in a list 305 * @qtd_list: List of QTDs for this QH 306 * @channel: Host channel currently processing transfers for this QH 307 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 308 * schedule 309 * @desc_list: List of transfer descriptors 310 * @desc_list_dma: Physical address of desc_list 311 * @desc_list_sz: Size of descriptors list 312 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 313 * descriptor and indicates original XferSize value for the 314 * descriptor 315 * @unreserve_timer: Timer for releasing periodic reservation. 316 * @dwc2_tt: Pointer to our tt info (or NULL if no tt). 317 * @ttport: Port number within our tt. 318 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 319 * @unreserve_pending: True if we planned to unreserve but haven't yet. 320 * @schedule_low_speed: True if we have a low/full speed component (either the 321 * host is in low/full speed mode or do_split). 322 * 323 * A Queue Head (QH) holds the static characteristics of an endpoint and 324 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 325 * be entered in either the non-periodic or periodic schedule. 326 */ 327 struct dwc2_qh { 328 struct dwc2_hsotg *hsotg; 329 u8 ep_type; 330 u8 ep_is_in; 331 u16 maxp; 332 u8 dev_speed; 333 u8 data_toggle; 334 u8 ping_state; 335 u8 do_split; 336 u8 td_first; 337 u8 td_last; 338 u16 host_us; 339 u16 device_us; 340 u16 host_interval; 341 u16 device_interval; 342 u16 next_active_frame; 343 u16 start_active_frame; 344 s16 num_hs_transfers; 345 struct dwc2_hs_transfer_time hs_transfers[DWC2_HS_SCHEDULE_UFRAMES]; 346 u32 ls_start_schedule_slice; 347 u16 ntd; 348 struct list_head qtd_list; 349 struct dwc2_host_chan *channel; 350 struct list_head qh_list_entry; 351 struct dwc2_hcd_dma_desc *desc_list; 352 dma_addr_t desc_list_dma; 353 u32 desc_list_sz; 354 u32 *n_bytes; 355 struct timer_list unreserve_timer; 356 struct dwc2_tt *dwc_tt; 357 int ttport; 358 unsigned tt_buffer_dirty:1; 359 unsigned unreserve_pending:1; 360 unsigned schedule_low_speed:1; 361 }; 362 363 /** 364 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 365 * 366 * @control_phase: Current phase for control transfers (Setup, Data, or 367 * Status) 368 * @in_process: Indicates if this QTD is currently processed by HW 369 * @data_toggle: Determines the PID of the next data packet for the 370 * data phase of control transfers. Ignored for other 371 * transfer types. One of the following values: 372 * - DWC2_HC_PID_DATA0 373 * - DWC2_HC_PID_DATA1 374 * @complete_split: Keeps track of the current split type for FS/LS 375 * endpoints on a HS Hub 376 * @isoc_split_pos: Position of the ISOC split in full/low speed 377 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 378 * transfer. A frame descriptor describes the buffer 379 * position and length of the data to be transferred in the 380 * next scheduled (micro)frame of an isochronous transfer. 381 * It also holds status for that transaction. The frame 382 * index starts at 0. 383 * @isoc_split_offset: Position of the ISOC split in the buffer for the 384 * current frame 385 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 386 * @error_count: Holds the number of bus errors that have occurred for 387 * a transaction within this transfer 388 * @n_desc: Number of DMA descriptors for this QTD 389 * @isoc_frame_index_last: Last activated frame (packet) index, used in 390 * descriptor DMA mode only 391 * @urb: URB for this transfer 392 * @qh: Queue head for this QTD 393 * @qtd_list_entry: For linking to the QH's list of QTDs 394 * 395 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 396 * interrupt, or isochronous transfer. A single QTD is created for each URB 397 * (of one of these types) submitted to the HCD. The transfer associated with 398 * a QTD may require one or multiple transactions. 399 * 400 * A QTD is linked to a Queue Head, which is entered in either the 401 * non-periodic or periodic schedule for execution. When a QTD is chosen for 402 * execution, some or all of its transactions may be executed. After 403 * execution, the state of the QTD is updated. The QTD may be retired if all 404 * its transactions are complete or if an error occurred. Otherwise, it 405 * remains in the schedule so more transactions can be executed later. 406 */ 407 struct dwc2_qtd { 408 enum dwc2_control_phase control_phase; 409 u8 in_process; 410 u8 data_toggle; 411 u8 complete_split; 412 u8 isoc_split_pos; 413 u16 isoc_frame_index; 414 u16 isoc_split_offset; 415 u16 isoc_td_last; 416 u16 isoc_td_first; 417 u32 ssplit_out_xfer_count; 418 u8 error_count; 419 u8 n_desc; 420 u16 isoc_frame_index_last; 421 struct dwc2_hcd_urb *urb; 422 struct dwc2_qh *qh; 423 struct list_head qtd_list_entry; 424 }; 425 426 #ifdef DEBUG 427 struct hc_xfer_info { 428 struct dwc2_hsotg *hsotg; 429 struct dwc2_host_chan *chan; 430 }; 431 #endif 432 433 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg); 434 435 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 436 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 437 { 438 return (struct usb_hcd *)hsotg->priv; 439 } 440 441 /* 442 * Inline used to disable one channel interrupt. Channel interrupts are 443 * disabled when the channel is halted or released by the interrupt handler. 444 * There is no need to handle further interrupts of that type until the 445 * channel is re-assigned. In fact, subsequent handling may cause crashes 446 * because the channel structures are cleaned up when the channel is released. 447 */ 448 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 449 { 450 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 451 452 mask &= ~intr; 453 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 454 } 455 456 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); 457 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 458 enum dwc2_halt_status halt_status); 459 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 460 struct dwc2_host_chan *chan); 461 462 /* 463 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 464 * are read as 1, they won't clear when written back. 465 */ 466 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 467 { 468 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 469 470 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 471 return hprt0; 472 } 473 474 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 475 { 476 return pipe->ep_num; 477 } 478 479 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 480 { 481 return pipe->pipe_type; 482 } 483 484 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 485 { 486 return pipe->mps; 487 } 488 489 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 490 { 491 return pipe->dev_addr; 492 } 493 494 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 495 { 496 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 497 } 498 499 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 500 { 501 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 502 } 503 504 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 505 { 506 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 507 } 508 509 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 510 { 511 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 512 } 513 514 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 515 { 516 return pipe->pipe_dir == USB_DIR_IN; 517 } 518 519 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 520 { 521 return !dwc2_hcd_is_pipe_in(pipe); 522 } 523 524 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq); 525 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 526 527 /* Transaction Execution Functions */ 528 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 529 struct dwc2_hsotg *hsotg); 530 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 531 enum dwc2_transaction_type tr_type); 532 533 /* Schedule Queue Functions */ 534 /* Implemented in hcd_queue.c */ 535 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 536 struct dwc2_hcd_urb *urb, 537 gfp_t mem_flags); 538 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 539 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 540 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 541 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 542 int sched_csplit); 543 544 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 545 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 546 struct dwc2_qh *qh); 547 548 /* Unlinks and frees a QTD */ 549 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 550 struct dwc2_qtd *qtd, 551 struct dwc2_qh *qh) 552 { 553 list_del(&qtd->qtd_list_entry); 554 kfree(qtd); 555 qtd = NULL; 556 } 557 558 /* Descriptor DMA support functions */ 559 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 560 struct dwc2_qh *qh); 561 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 562 struct dwc2_host_chan *chan, int chnum, 563 enum dwc2_halt_status halt_status); 564 565 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 566 gfp_t mem_flags); 567 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 568 569 /* Check if QH is non-periodic */ 570 #define dwc2_qh_is_non_per(_qh_ptr_) \ 571 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 572 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 573 574 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 575 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 576 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 577 static inline bool dbg_urb(struct urb *urb) { return true; } 578 static inline bool dbg_perio(void) { return true; } 579 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 580 static inline bool dbg_hc(struct dwc2_host_chan *hc) 581 { 582 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 583 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 584 } 585 586 static inline bool dbg_qh(struct dwc2_qh *qh) 587 { 588 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 589 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 590 } 591 592 static inline bool dbg_urb(struct urb *urb) 593 { 594 return usb_pipetype(urb->pipe) == PIPE_BULK || 595 usb_pipetype(urb->pipe) == PIPE_CONTROL; 596 } 597 598 static inline bool dbg_perio(void) { return false; } 599 #endif 600 601 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 602 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 603 604 /* Packet size for any kind of endpoint descriptor */ 605 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 606 607 /* 608 * Returns true if frame1 index is greater than frame2 index. The comparison 609 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 610 * frame number when the max index frame number is reached. 611 */ 612 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 613 { 614 u16 diff = fr_idx1 - fr_idx2; 615 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 616 617 return diff && !sign; 618 } 619 620 /* 621 * Returns true if frame1 is less than or equal to frame2. The comparison is 622 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 623 * frame number when the max frame number is reached. 624 */ 625 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 626 { 627 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 628 } 629 630 /* 631 * Returns true if frame1 is greater than frame2. The comparison is done 632 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 633 * number when the max frame number is reached. 634 */ 635 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 636 { 637 return (frame1 != frame2) && 638 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 639 } 640 641 /* 642 * Increments frame by the amount specified by inc. The addition is done 643 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 644 */ 645 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 646 { 647 return (frame + inc) & HFNUM_MAX_FRNUM; 648 } 649 650 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 651 { 652 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 653 } 654 655 static inline u16 dwc2_full_frame_num(u16 frame) 656 { 657 return (frame & HFNUM_MAX_FRNUM) >> 3; 658 } 659 660 static inline u16 dwc2_micro_frame_num(u16 frame) 661 { 662 return frame & 0x7; 663 } 664 665 /* 666 * Returns the Core Interrupt Status register contents, ANDed with the Core 667 * Interrupt Mask register contents 668 */ 669 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 670 { 671 return dwc2_readl(hsotg->regs + GINTSTS) & 672 dwc2_readl(hsotg->regs + GINTMSK); 673 } 674 675 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 676 { 677 return dwc2_urb->status; 678 } 679 680 static inline u32 dwc2_hcd_urb_get_actual_length( 681 struct dwc2_hcd_urb *dwc2_urb) 682 { 683 return dwc2_urb->actual_length; 684 } 685 686 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 687 { 688 return dwc2_urb->error_count; 689 } 690 691 static inline void dwc2_hcd_urb_set_iso_desc_params( 692 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 693 u32 length) 694 { 695 dwc2_urb->iso_descs[desc_num].offset = offset; 696 dwc2_urb->iso_descs[desc_num].length = length; 697 } 698 699 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 700 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 701 { 702 return dwc2_urb->iso_descs[desc_num].status; 703 } 704 705 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 706 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 707 { 708 return dwc2_urb->iso_descs[desc_num].actual_length; 709 } 710 711 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 712 struct usb_host_endpoint *ep) 713 { 714 struct dwc2_qh *qh = ep->hcpriv; 715 716 if (qh && !list_empty(&qh->qh_list_entry)) 717 return 1; 718 719 return 0; 720 } 721 722 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 723 struct usb_host_endpoint *ep) 724 { 725 struct dwc2_qh *qh = ep->hcpriv; 726 727 if (!qh) { 728 WARN_ON(1); 729 return 0; 730 } 731 732 return qh->host_us; 733 } 734 735 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 736 struct dwc2_host_chan *chan, int chnum, 737 struct dwc2_qtd *qtd); 738 739 /* HCD Core API */ 740 741 /** 742 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 743 * 744 * @hsotg: The DWC2 HCD 745 * 746 * Returns IRQ_HANDLED if interrupt is handled 747 * Return IRQ_NONE if interrupt is not handled 748 */ 749 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 750 751 /** 752 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 753 * 754 * @hsotg: The DWC2 HCD 755 */ 756 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 757 758 /** 759 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 760 * and 0 otherwise 761 * 762 * @hsotg: The DWC2 HCD 763 */ 764 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 765 766 /** 767 * dwc2_hcd_dump_state() - Dumps hsotg state 768 * 769 * @hsotg: The DWC2 HCD 770 * 771 * NOTE: This function will be removed once the peripheral controller code 772 * is integrated and the driver is stable 773 */ 774 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 775 776 /** 777 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 778 * 779 * @hsotg: The DWC2 HCD 780 * 781 * This can be used to determine average interrupt latency. Frame remaining is 782 * also shown for start transfer and two additional sample points. 783 * 784 * NOTE: This function will be removed once the peripheral controller code 785 * is integrated and the driver is stable 786 */ 787 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 788 789 /* URB interface */ 790 791 /* Transfer flags */ 792 #define URB_GIVEBACK_ASAP 0x1 793 #define URB_SEND_ZERO_PACKET 0x2 794 795 /* Host driver callbacks */ 796 797 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 798 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 799 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 800 int *hub_addr, int *hub_port); 801 extern struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, 802 void *context, gfp_t mem_flags, 803 int *ttport); 804 805 extern void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, 806 struct dwc2_tt *dwc_tt); 807 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 808 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 809 int status); 810 811 #ifdef DEBUG 812 /* 813 * Macro to sample the remaining PHY clocks left in the current frame. This 814 * may be used during debugging to determine the average time it takes to 815 * execute sections of code. There are two possible sample points, "a" and 816 * "b", so the _letter_ argument must be one of these values. 817 * 818 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 819 * example, "cat /sys/devices/lm0/hcd_frrem". 820 */ 821 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 822 do { \ 823 struct hfnum_data _hfnum_; \ 824 struct dwc2_qtd *_qtd_; \ 825 \ 826 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 827 qtd_list_entry); \ 828 if (usb_pipeint(_qtd_->urb->pipe) && \ 829 (_qh_)->start_active_frame != 0 && !_qtd_->complete_split) { \ 830 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ 831 switch (_hfnum_.b.frnum & 0x7) { \ 832 case 7: \ 833 (_hcd_)->hfnum_7_samples_##_letter_++; \ 834 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 835 _hfnum_.b.frrem; \ 836 break; \ 837 case 0: \ 838 (_hcd_)->hfnum_0_samples_##_letter_++; \ 839 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 840 _hfnum_.b.frrem; \ 841 break; \ 842 default: \ 843 (_hcd_)->hfnum_other_samples_##_letter_++; \ 844 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 845 _hfnum_.b.frrem; \ 846 break; \ 847 } \ 848 } \ 849 } while (0) 850 #else 851 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 852 #endif 853 854 #endif /* __DWC2_HCD_H__ */ 855