1 /* 2 * hcd.h - DesignWare HS OTG Controller host-mode declarations 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 #ifndef __DWC2_HCD_H__ 37 #define __DWC2_HCD_H__ 38 39 /* 40 * This file contains the structures, constants, and interfaces for the 41 * Host Contoller Driver (HCD) 42 * 43 * The Host Controller Driver (HCD) is responsible for translating requests 44 * from the USB Driver into the appropriate actions on the DWC_otg controller. 45 * It isolates the USBD from the specifics of the controller by providing an 46 * API to the USBD. 47 */ 48 49 struct dwc2_qh; 50 51 /** 52 * struct dwc2_host_chan - Software host channel descriptor 53 * 54 * @hc_num: Host channel number, used for register address lookup 55 * @dev_addr: Address of the device 56 * @ep_num: Endpoint of the device 57 * @ep_is_in: Endpoint direction 58 * @speed: Device speed. One of the following values: 59 * - USB_SPEED_LOW 60 * - USB_SPEED_FULL 61 * - USB_SPEED_HIGH 62 * @ep_type: Endpoint type. One of the following values: 63 * - USB_ENDPOINT_XFER_CONTROL: 0 64 * - USB_ENDPOINT_XFER_ISOC: 1 65 * - USB_ENDPOINT_XFER_BULK: 2 66 * - USB_ENDPOINT_XFER_INTR: 3 67 * @max_packet: Max packet size in bytes 68 * @data_pid_start: PID for initial transaction. 69 * 0: DATA0 70 * 1: DATA2 71 * 2: DATA1 72 * 3: MDATA (non-Control EP), 73 * SETUP (Control EP) 74 * @multi_count: Number of additional periodic transactions per 75 * (micro)frame 76 * @xfer_buf: Pointer to current transfer buffer position 77 * @xfer_dma: DMA address of xfer_buf 78 * @xfer_len: Total number of bytes to transfer 79 * @xfer_count: Number of bytes transferred so far 80 * @start_pkt_count: Packet count at start of transfer 81 * @xfer_started: True if the transfer has been started 82 * @ping: True if a PING request should be issued on this channel 83 * @error_state: True if the error count for this transaction is non-zero 84 * @halt_on_queue: True if this channel should be halted the next time a 85 * request is queued for the channel. This is necessary in 86 * slave mode if no request queue space is available when 87 * an attempt is made to halt the channel. 88 * @halt_pending: True if the host channel has been halted, but the core 89 * is not finished flushing queued requests 90 * @do_split: Enable split for the channel 91 * @complete_split: Enable complete split 92 * @hub_addr: Address of high speed hub for the split 93 * @hub_port: Port of the low/full speed device for the split 94 * @xact_pos: Split transaction position. One of the following values: 95 * - DWC2_HCSPLT_XACTPOS_MID 96 * - DWC2_HCSPLT_XACTPOS_BEGIN 97 * - DWC2_HCSPLT_XACTPOS_END 98 * - DWC2_HCSPLT_XACTPOS_ALL 99 * @requests: Number of requests issued for this channel since it was 100 * assigned to the current transfer (not counting PINGs) 101 * @schinfo: Scheduling micro-frame bitmap 102 * @ntd: Number of transfer descriptors for the transfer 103 * @halt_status: Reason for halting the host channel 104 * @hcint Contents of the HCINT register when the interrupt came 105 * @qh: QH for the transfer being processed by this channel 106 * @hc_list_entry: For linking to list of host channels 107 * @desc_list_addr: Current QH's descriptor list DMA address 108 * @desc_list_sz: Current QH's descriptor list size 109 * @split_order_list_entry: List entry for keeping track of the order of splits 110 * 111 * This structure represents the state of a single host channel when acting in 112 * host mode. It contains the data items needed to transfer packets to an 113 * endpoint via a host channel. 114 */ 115 struct dwc2_host_chan { 116 u8 hc_num; 117 118 unsigned dev_addr:7; 119 unsigned ep_num:4; 120 unsigned ep_is_in:1; 121 unsigned speed:4; 122 unsigned ep_type:2; 123 unsigned max_packet:11; 124 unsigned data_pid_start:2; 125 #define DWC2_HC_PID_DATA0 TSIZ_SC_MC_PID_DATA0 126 #define DWC2_HC_PID_DATA2 TSIZ_SC_MC_PID_DATA2 127 #define DWC2_HC_PID_DATA1 TSIZ_SC_MC_PID_DATA1 128 #define DWC2_HC_PID_MDATA TSIZ_SC_MC_PID_MDATA 129 #define DWC2_HC_PID_SETUP TSIZ_SC_MC_PID_SETUP 130 131 unsigned multi_count:2; 132 133 u8 *xfer_buf; 134 dma_addr_t xfer_dma; 135 u32 xfer_len; 136 u32 xfer_count; 137 u16 start_pkt_count; 138 u8 xfer_started; 139 u8 do_ping; 140 u8 error_state; 141 u8 halt_on_queue; 142 u8 halt_pending; 143 u8 do_split; 144 u8 complete_split; 145 u8 hub_addr; 146 u8 hub_port; 147 u8 xact_pos; 148 #define DWC2_HCSPLT_XACTPOS_MID HCSPLT_XACTPOS_MID 149 #define DWC2_HCSPLT_XACTPOS_END HCSPLT_XACTPOS_END 150 #define DWC2_HCSPLT_XACTPOS_BEGIN HCSPLT_XACTPOS_BEGIN 151 #define DWC2_HCSPLT_XACTPOS_ALL HCSPLT_XACTPOS_ALL 152 153 u8 requests; 154 u8 schinfo; 155 u16 ntd; 156 enum dwc2_halt_status halt_status; 157 u32 hcint; 158 struct dwc2_qh *qh; 159 struct list_head hc_list_entry; 160 dma_addr_t desc_list_addr; 161 u32 desc_list_sz; 162 struct list_head split_order_list_entry; 163 }; 164 165 struct dwc2_hcd_pipe_info { 166 u8 dev_addr; 167 u8 ep_num; 168 u8 pipe_type; 169 u8 pipe_dir; 170 u16 mps; 171 }; 172 173 struct dwc2_hcd_iso_packet_desc { 174 u32 offset; 175 u32 length; 176 u32 actual_length; 177 u32 status; 178 }; 179 180 struct dwc2_qtd; 181 182 struct dwc2_hcd_urb { 183 void *priv; 184 struct dwc2_qtd *qtd; 185 void *buf; 186 dma_addr_t dma; 187 void *setup_packet; 188 dma_addr_t setup_dma; 189 u32 length; 190 u32 actual_length; 191 u32 status; 192 u32 error_count; 193 u32 packet_count; 194 u32 flags; 195 u16 interval; 196 struct dwc2_hcd_pipe_info pipe_info; 197 struct dwc2_hcd_iso_packet_desc iso_descs[0]; 198 }; 199 200 /* Phases for control transfers */ 201 enum dwc2_control_phase { 202 DWC2_CONTROL_SETUP, 203 DWC2_CONTROL_DATA, 204 DWC2_CONTROL_STATUS, 205 }; 206 207 /* Transaction types */ 208 enum dwc2_transaction_type { 209 DWC2_TRANSACTION_NONE, 210 DWC2_TRANSACTION_PERIODIC, 211 DWC2_TRANSACTION_NON_PERIODIC, 212 DWC2_TRANSACTION_ALL, 213 }; 214 215 /** 216 * struct dwc2_qh - Software queue head structure 217 * 218 * @hsotg: The HCD state structure for the DWC OTG controller 219 * @ep_type: Endpoint type. One of the following values: 220 * - USB_ENDPOINT_XFER_CONTROL 221 * - USB_ENDPOINT_XFER_BULK 222 * - USB_ENDPOINT_XFER_INT 223 * - USB_ENDPOINT_XFER_ISOC 224 * @ep_is_in: Endpoint direction 225 * @maxp: Value from wMaxPacketSize field of Endpoint Descriptor 226 * @dev_speed: Device speed. One of the following values: 227 * - USB_SPEED_LOW 228 * - USB_SPEED_FULL 229 * - USB_SPEED_HIGH 230 * @data_toggle: Determines the PID of the next data packet for 231 * non-controltransfers. Ignored for control transfers. 232 * One of the following values: 233 * - DWC2_HC_PID_DATA0 234 * - DWC2_HC_PID_DATA1 235 * @ping_state: Ping state 236 * @do_split: Full/low speed endpoint on high-speed hub requires split 237 * @td_first: Index of first activated isochronous transfer descriptor 238 * @td_last: Index of last activated isochronous transfer descriptor 239 * @usecs: Bandwidth in microseconds per (micro)frame 240 * @interval: Interval between transfers in (micro)frames 241 * @sched_frame: (Micro)frame to initialize a periodic transfer. 242 * The transfer executes in the following (micro)frame. 243 * @frame_usecs: Internal variable used by the microframe scheduler 244 * @start_split_frame: (Micro)frame at which last start split was initialized 245 * @ntd: Actual number of transfer descriptors in a list 246 * @qtd_list: List of QTDs for this QH 247 * @channel: Host channel currently processing transfers for this QH 248 * @qh_list_entry: Entry for QH in either the periodic or non-periodic 249 * schedule 250 * @desc_list: List of transfer descriptors 251 * @desc_list_dma: Physical address of desc_list 252 * @desc_list_sz: Size of descriptors list 253 * @n_bytes: Xfer Bytes array. Each element corresponds to a transfer 254 * descriptor and indicates original XferSize value for the 255 * descriptor 256 * @unreserve_timer: Timer for releasing periodic reservation. 257 * @tt_buffer_dirty True if clear_tt_buffer_complete is pending 258 * @unreserve_pending: True if we planned to unreserve but haven't yet. 259 * 260 * A Queue Head (QH) holds the static characteristics of an endpoint and 261 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 262 * be entered in either the non-periodic or periodic schedule. 263 */ 264 struct dwc2_qh { 265 struct dwc2_hsotg *hsotg; 266 u8 ep_type; 267 u8 ep_is_in; 268 u16 maxp; 269 u8 dev_speed; 270 u8 data_toggle; 271 u8 ping_state; 272 u8 do_split; 273 u8 td_first; 274 u8 td_last; 275 u16 usecs; 276 u16 interval; 277 u16 sched_frame; 278 u16 frame_usecs[8]; 279 u16 start_split_frame; 280 u16 ntd; 281 struct list_head qtd_list; 282 struct dwc2_host_chan *channel; 283 struct list_head qh_list_entry; 284 struct dwc2_hcd_dma_desc *desc_list; 285 dma_addr_t desc_list_dma; 286 u32 desc_list_sz; 287 u32 *n_bytes; 288 struct timer_list unreserve_timer; 289 unsigned tt_buffer_dirty:1; 290 unsigned unreserve_pending:1; 291 }; 292 293 /** 294 * struct dwc2_qtd - Software queue transfer descriptor (QTD) 295 * 296 * @control_phase: Current phase for control transfers (Setup, Data, or 297 * Status) 298 * @in_process: Indicates if this QTD is currently processed by HW 299 * @data_toggle: Determines the PID of the next data packet for the 300 * data phase of control transfers. Ignored for other 301 * transfer types. One of the following values: 302 * - DWC2_HC_PID_DATA0 303 * - DWC2_HC_PID_DATA1 304 * @complete_split: Keeps track of the current split type for FS/LS 305 * endpoints on a HS Hub 306 * @isoc_split_pos: Position of the ISOC split in full/low speed 307 * @isoc_frame_index: Index of the next frame descriptor for an isochronous 308 * transfer. A frame descriptor describes the buffer 309 * position and length of the data to be transferred in the 310 * next scheduled (micro)frame of an isochronous transfer. 311 * It also holds status for that transaction. The frame 312 * index starts at 0. 313 * @isoc_split_offset: Position of the ISOC split in the buffer for the 314 * current frame 315 * @ssplit_out_xfer_count: How many bytes transferred during SSPLIT OUT 316 * @error_count: Holds the number of bus errors that have occurred for 317 * a transaction within this transfer 318 * @n_desc: Number of DMA descriptors for this QTD 319 * @isoc_frame_index_last: Last activated frame (packet) index, used in 320 * descriptor DMA mode only 321 * @urb: URB for this transfer 322 * @qh: Queue head for this QTD 323 * @qtd_list_entry: For linking to the QH's list of QTDs 324 * 325 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 326 * interrupt, or isochronous transfer. A single QTD is created for each URB 327 * (of one of these types) submitted to the HCD. The transfer associated with 328 * a QTD may require one or multiple transactions. 329 * 330 * A QTD is linked to a Queue Head, which is entered in either the 331 * non-periodic or periodic schedule for execution. When a QTD is chosen for 332 * execution, some or all of its transactions may be executed. After 333 * execution, the state of the QTD is updated. The QTD may be retired if all 334 * its transactions are complete or if an error occurred. Otherwise, it 335 * remains in the schedule so more transactions can be executed later. 336 */ 337 struct dwc2_qtd { 338 enum dwc2_control_phase control_phase; 339 u8 in_process; 340 u8 data_toggle; 341 u8 complete_split; 342 u8 isoc_split_pos; 343 u16 isoc_frame_index; 344 u16 isoc_split_offset; 345 u16 isoc_td_last; 346 u16 isoc_td_first; 347 u32 ssplit_out_xfer_count; 348 u8 error_count; 349 u8 n_desc; 350 u16 isoc_frame_index_last; 351 struct dwc2_hcd_urb *urb; 352 struct dwc2_qh *qh; 353 struct list_head qtd_list_entry; 354 }; 355 356 #ifdef DEBUG 357 struct hc_xfer_info { 358 struct dwc2_hsotg *hsotg; 359 struct dwc2_host_chan *chan; 360 }; 361 #endif 362 363 /* Gets the struct usb_hcd that contains a struct dwc2_hsotg */ 364 static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) 365 { 366 return (struct usb_hcd *)hsotg->priv; 367 } 368 369 /* 370 * Inline used to disable one channel interrupt. Channel interrupts are 371 * disabled when the channel is halted or released by the interrupt handler. 372 * There is no need to handle further interrupts of that type until the 373 * channel is re-assigned. In fact, subsequent handling may cause crashes 374 * because the channel structures are cleaned up when the channel is released. 375 */ 376 static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) 377 { 378 u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); 379 380 mask &= ~intr; 381 dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); 382 } 383 384 /* 385 * Reads HPRT0 in preparation to modify. It keeps the WC bits 0 so that if they 386 * are read as 1, they won't clear when written back. 387 */ 388 static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) 389 { 390 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 391 392 hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); 393 return hprt0; 394 } 395 396 static inline u8 dwc2_hcd_get_ep_num(struct dwc2_hcd_pipe_info *pipe) 397 { 398 return pipe->ep_num; 399 } 400 401 static inline u8 dwc2_hcd_get_pipe_type(struct dwc2_hcd_pipe_info *pipe) 402 { 403 return pipe->pipe_type; 404 } 405 406 static inline u16 dwc2_hcd_get_mps(struct dwc2_hcd_pipe_info *pipe) 407 { 408 return pipe->mps; 409 } 410 411 static inline u8 dwc2_hcd_get_dev_addr(struct dwc2_hcd_pipe_info *pipe) 412 { 413 return pipe->dev_addr; 414 } 415 416 static inline u8 dwc2_hcd_is_pipe_isoc(struct dwc2_hcd_pipe_info *pipe) 417 { 418 return pipe->pipe_type == USB_ENDPOINT_XFER_ISOC; 419 } 420 421 static inline u8 dwc2_hcd_is_pipe_int(struct dwc2_hcd_pipe_info *pipe) 422 { 423 return pipe->pipe_type == USB_ENDPOINT_XFER_INT; 424 } 425 426 static inline u8 dwc2_hcd_is_pipe_bulk(struct dwc2_hcd_pipe_info *pipe) 427 { 428 return pipe->pipe_type == USB_ENDPOINT_XFER_BULK; 429 } 430 431 static inline u8 dwc2_hcd_is_pipe_control(struct dwc2_hcd_pipe_info *pipe) 432 { 433 return pipe->pipe_type == USB_ENDPOINT_XFER_CONTROL; 434 } 435 436 static inline u8 dwc2_hcd_is_pipe_in(struct dwc2_hcd_pipe_info *pipe) 437 { 438 return pipe->pipe_dir == USB_DIR_IN; 439 } 440 441 static inline u8 dwc2_hcd_is_pipe_out(struct dwc2_hcd_pipe_info *pipe) 442 { 443 return !dwc2_hcd_is_pipe_in(pipe); 444 } 445 446 extern int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq); 447 extern void dwc2_hcd_remove(struct dwc2_hsotg *hsotg); 448 449 /* Transaction Execution Functions */ 450 extern enum dwc2_transaction_type dwc2_hcd_select_transactions( 451 struct dwc2_hsotg *hsotg); 452 extern void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 453 enum dwc2_transaction_type tr_type); 454 455 /* Schedule Queue Functions */ 456 /* Implemented in hcd_queue.c */ 457 extern void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg); 458 extern struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 459 struct dwc2_hcd_urb *urb, 460 gfp_t mem_flags); 461 extern void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 462 extern int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 463 extern void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 464 extern void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 465 int sched_csplit); 466 467 extern void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb); 468 extern int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 469 struct dwc2_qh *qh); 470 471 /* Unlinks and frees a QTD */ 472 static inline void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 473 struct dwc2_qtd *qtd, 474 struct dwc2_qh *qh) 475 { 476 list_del(&qtd->qtd_list_entry); 477 kfree(qtd); 478 } 479 480 /* Descriptor DMA support functions */ 481 extern void dwc2_hcd_start_xfer_ddma(struct dwc2_hsotg *hsotg, 482 struct dwc2_qh *qh); 483 extern void dwc2_hcd_complete_xfer_ddma(struct dwc2_hsotg *hsotg, 484 struct dwc2_host_chan *chan, int chnum, 485 enum dwc2_halt_status halt_status); 486 487 extern int dwc2_hcd_qh_init_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 488 gfp_t mem_flags); 489 extern void dwc2_hcd_qh_free_ddma(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh); 490 491 /* Check if QH is non-periodic */ 492 #define dwc2_qh_is_non_per(_qh_ptr_) \ 493 ((_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_BULK || \ 494 (_qh_ptr_)->ep_type == USB_ENDPOINT_XFER_CONTROL) 495 496 #ifdef CONFIG_USB_DWC2_DEBUG_PERIODIC 497 static inline bool dbg_hc(struct dwc2_host_chan *hc) { return true; } 498 static inline bool dbg_qh(struct dwc2_qh *qh) { return true; } 499 static inline bool dbg_urb(struct urb *urb) { return true; } 500 static inline bool dbg_perio(void) { return true; } 501 #else /* !CONFIG_USB_DWC2_DEBUG_PERIODIC */ 502 static inline bool dbg_hc(struct dwc2_host_chan *hc) 503 { 504 return hc->ep_type == USB_ENDPOINT_XFER_BULK || 505 hc->ep_type == USB_ENDPOINT_XFER_CONTROL; 506 } 507 508 static inline bool dbg_qh(struct dwc2_qh *qh) 509 { 510 return qh->ep_type == USB_ENDPOINT_XFER_BULK || 511 qh->ep_type == USB_ENDPOINT_XFER_CONTROL; 512 } 513 514 static inline bool dbg_urb(struct urb *urb) 515 { 516 return usb_pipetype(urb->pipe) == PIPE_BULK || 517 usb_pipetype(urb->pipe) == PIPE_CONTROL; 518 } 519 520 static inline bool dbg_perio(void) { return false; } 521 #endif 522 523 /* High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 524 #define dwc2_hb_mult(wmaxpacketsize) (1 + (((wmaxpacketsize) >> 11) & 0x03)) 525 526 /* Packet size for any kind of endpoint descriptor */ 527 #define dwc2_max_packet(wmaxpacketsize) ((wmaxpacketsize) & 0x07ff) 528 529 /* 530 * Returns true if frame1 index is greater than frame2 index. The comparison 531 * is done modulo FRLISTEN_64_SIZE. This accounts for the rollover of the 532 * frame number when the max index frame number is reached. 533 */ 534 static inline bool dwc2_frame_idx_num_gt(u16 fr_idx1, u16 fr_idx2) 535 { 536 u16 diff = fr_idx1 - fr_idx2; 537 u16 sign = diff & (FRLISTEN_64_SIZE >> 1); 538 539 return diff && !sign; 540 } 541 542 /* 543 * Returns true if frame1 is less than or equal to frame2. The comparison is 544 * done modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the 545 * frame number when the max frame number is reached. 546 */ 547 static inline int dwc2_frame_num_le(u16 frame1, u16 frame2) 548 { 549 return ((frame2 - frame1) & HFNUM_MAX_FRNUM) <= (HFNUM_MAX_FRNUM >> 1); 550 } 551 552 /* 553 * Returns true if frame1 is greater than frame2. The comparison is done 554 * modulo HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 555 * number when the max frame number is reached. 556 */ 557 static inline int dwc2_frame_num_gt(u16 frame1, u16 frame2) 558 { 559 return (frame1 != frame2) && 560 ((frame1 - frame2) & HFNUM_MAX_FRNUM) < (HFNUM_MAX_FRNUM >> 1); 561 } 562 563 /* 564 * Increments frame by the amount specified by inc. The addition is done 565 * modulo HFNUM_MAX_FRNUM. Returns the incremented value. 566 */ 567 static inline u16 dwc2_frame_num_inc(u16 frame, u16 inc) 568 { 569 return (frame + inc) & HFNUM_MAX_FRNUM; 570 } 571 572 static inline u16 dwc2_frame_num_dec(u16 frame, u16 dec) 573 { 574 return (frame + HFNUM_MAX_FRNUM + 1 - dec) & HFNUM_MAX_FRNUM; 575 } 576 577 static inline u16 dwc2_full_frame_num(u16 frame) 578 { 579 return (frame & HFNUM_MAX_FRNUM) >> 3; 580 } 581 582 static inline u16 dwc2_micro_frame_num(u16 frame) 583 { 584 return frame & 0x7; 585 } 586 587 /* 588 * Returns the Core Interrupt Status register contents, ANDed with the Core 589 * Interrupt Mask register contents 590 */ 591 static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) 592 { 593 return dwc2_readl(hsotg->regs + GINTSTS) & 594 dwc2_readl(hsotg->regs + GINTMSK); 595 } 596 597 static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) 598 { 599 return dwc2_urb->status; 600 } 601 602 static inline u32 dwc2_hcd_urb_get_actual_length( 603 struct dwc2_hcd_urb *dwc2_urb) 604 { 605 return dwc2_urb->actual_length; 606 } 607 608 static inline u32 dwc2_hcd_urb_get_error_count(struct dwc2_hcd_urb *dwc2_urb) 609 { 610 return dwc2_urb->error_count; 611 } 612 613 static inline void dwc2_hcd_urb_set_iso_desc_params( 614 struct dwc2_hcd_urb *dwc2_urb, int desc_num, u32 offset, 615 u32 length) 616 { 617 dwc2_urb->iso_descs[desc_num].offset = offset; 618 dwc2_urb->iso_descs[desc_num].length = length; 619 } 620 621 static inline u32 dwc2_hcd_urb_get_iso_desc_status( 622 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 623 { 624 return dwc2_urb->iso_descs[desc_num].status; 625 } 626 627 static inline u32 dwc2_hcd_urb_get_iso_desc_actual_length( 628 struct dwc2_hcd_urb *dwc2_urb, int desc_num) 629 { 630 return dwc2_urb->iso_descs[desc_num].actual_length; 631 } 632 633 static inline int dwc2_hcd_is_bandwidth_allocated(struct dwc2_hsotg *hsotg, 634 struct usb_host_endpoint *ep) 635 { 636 struct dwc2_qh *qh = ep->hcpriv; 637 638 if (qh && !list_empty(&qh->qh_list_entry)) 639 return 1; 640 641 return 0; 642 } 643 644 static inline u16 dwc2_hcd_get_ep_bandwidth(struct dwc2_hsotg *hsotg, 645 struct usb_host_endpoint *ep) 646 { 647 struct dwc2_qh *qh = ep->hcpriv; 648 649 if (!qh) { 650 WARN_ON(1); 651 return 0; 652 } 653 654 return qh->usecs; 655 } 656 657 extern void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, 658 struct dwc2_host_chan *chan, int chnum, 659 struct dwc2_qtd *qtd); 660 661 /* HCD Core API */ 662 663 /** 664 * dwc2_handle_hcd_intr() - Called on every hardware interrupt 665 * 666 * @hsotg: The DWC2 HCD 667 * 668 * Returns IRQ_HANDLED if interrupt is handled 669 * Return IRQ_NONE if interrupt is not handled 670 */ 671 extern irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg); 672 673 /** 674 * dwc2_hcd_stop() - Halts the DWC_otg host mode operation 675 * 676 * @hsotg: The DWC2 HCD 677 */ 678 extern void dwc2_hcd_stop(struct dwc2_hsotg *hsotg); 679 680 /** 681 * dwc2_hcd_is_b_host() - Returns 1 if core currently is acting as B host, 682 * and 0 otherwise 683 * 684 * @hsotg: The DWC2 HCD 685 */ 686 extern int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg); 687 688 /** 689 * dwc2_hcd_dump_state() - Dumps hsotg state 690 * 691 * @hsotg: The DWC2 HCD 692 * 693 * NOTE: This function will be removed once the peripheral controller code 694 * is integrated and the driver is stable 695 */ 696 extern void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg); 697 698 /** 699 * dwc2_hcd_dump_frrem() - Dumps the average frame remaining at SOF 700 * 701 * @hsotg: The DWC2 HCD 702 * 703 * This can be used to determine average interrupt latency. Frame remaining is 704 * also shown for start transfer and two additional sample points. 705 * 706 * NOTE: This function will be removed once the peripheral controller code 707 * is integrated and the driver is stable 708 */ 709 extern void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg); 710 711 /* URB interface */ 712 713 /* Transfer flags */ 714 #define URB_GIVEBACK_ASAP 0x1 715 #define URB_SEND_ZERO_PACKET 0x2 716 717 /* Host driver callbacks */ 718 719 extern void dwc2_host_start(struct dwc2_hsotg *hsotg); 720 extern void dwc2_host_disconnect(struct dwc2_hsotg *hsotg); 721 extern void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 722 int *hub_addr, int *hub_port); 723 extern int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context); 724 extern void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 725 int status); 726 727 #ifdef DEBUG 728 /* 729 * Macro to sample the remaining PHY clocks left in the current frame. This 730 * may be used during debugging to determine the average time it takes to 731 * execute sections of code. There are two possible sample points, "a" and 732 * "b", so the _letter_ argument must be one of these values. 733 * 734 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 735 * example, "cat /sys/devices/lm0/hcd_frrem". 736 */ 737 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) \ 738 do { \ 739 struct hfnum_data _hfnum_; \ 740 struct dwc2_qtd *_qtd_; \ 741 \ 742 _qtd_ = list_entry((_qh_)->qtd_list.next, struct dwc2_qtd, \ 743 qtd_list_entry); \ 744 if (usb_pipeint(_qtd_->urb->pipe) && \ 745 (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ 746 _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ 747 switch (_hfnum_.b.frnum & 0x7) { \ 748 case 7: \ 749 (_hcd_)->hfnum_7_samples_##_letter_++; \ 750 (_hcd_)->hfnum_7_frrem_accum_##_letter_ += \ 751 _hfnum_.b.frrem; \ 752 break; \ 753 case 0: \ 754 (_hcd_)->hfnum_0_samples_##_letter_++; \ 755 (_hcd_)->hfnum_0_frrem_accum_##_letter_ += \ 756 _hfnum_.b.frrem; \ 757 break; \ 758 default: \ 759 (_hcd_)->hfnum_other_samples_##_letter_++; \ 760 (_hcd_)->hfnum_other_frrem_accum_##_letter_ += \ 761 _hfnum_.b.frrem; \ 762 break; \ 763 } \ 764 } \ 765 } while (0) 766 #else 767 #define dwc2_sample_frrem(_hcd_, _qh_, _letter_) do {} while (0) 768 #endif 769 770 #endif /* __DWC2_HCD_H__ */ 771