1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 if (qh->channel && qh->channel->qh == qh) 168 qh->channel->qh = NULL; 169 170 spin_unlock_irqrestore(&hsotg->lock, flags); 171 dwc2_hcd_qh_free(hsotg, qh); 172 spin_lock_irqsave(&hsotg->lock, flags); 173 } 174 175 spin_unlock_irqrestore(&hsotg->lock, flags); 176 } 177 178 /* 179 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 180 * and periodic schedules. The QTD associated with each URB is removed from 181 * the schedule and freed. This function may be called when a disconnect is 182 * detected or when the HCD is being stopped. 183 * 184 * Must be called with interrupt disabled and spinlock held 185 */ 186 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 187 { 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 191 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 192 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 193 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 194 } 195 196 /** 197 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 198 * 199 * @hsotg: Pointer to struct dwc2_hsotg 200 */ 201 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 202 { 203 u32 hprt0; 204 205 if (hsotg->op_state == OTG_STATE_B_HOST) { 206 /* 207 * Reset the port. During a HNP mode switch the reset 208 * needs to occur within 1ms and have a duration of at 209 * least 50ms. 210 */ 211 hprt0 = dwc2_read_hprt0(hsotg); 212 hprt0 |= HPRT0_RST; 213 dwc2_writel(hprt0, hsotg->regs + HPRT0); 214 } 215 216 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 217 msecs_to_jiffies(50)); 218 } 219 220 /* Must be called with interrupt disabled and spinlock held */ 221 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 222 { 223 int num_channels = hsotg->core_params->host_channels; 224 struct dwc2_host_chan *channel; 225 u32 hcchar; 226 int i; 227 228 if (hsotg->core_params->dma_enable <= 0) { 229 /* Flush out any channel requests in slave mode */ 230 for (i = 0; i < num_channels; i++) { 231 channel = hsotg->hc_ptr_array[i]; 232 if (!list_empty(&channel->hc_list_entry)) 233 continue; 234 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 235 if (hcchar & HCCHAR_CHENA) { 236 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 237 hcchar |= HCCHAR_CHDIS; 238 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 239 } 240 } 241 } 242 243 for (i = 0; i < num_channels; i++) { 244 channel = hsotg->hc_ptr_array[i]; 245 if (!list_empty(&channel->hc_list_entry)) 246 continue; 247 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 248 if (hcchar & HCCHAR_CHENA) { 249 /* Halt the channel */ 250 hcchar |= HCCHAR_CHDIS; 251 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 252 } 253 254 dwc2_hc_cleanup(hsotg, channel); 255 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 256 /* 257 * Added for Descriptor DMA to prevent channel double cleanup in 258 * release_channel_ddma(), which is called from ep_disable when 259 * device disconnects 260 */ 261 channel->qh = NULL; 262 } 263 /* All channels have been freed, mark them available */ 264 if (hsotg->core_params->uframe_sched > 0) { 265 hsotg->available_host_channels = 266 hsotg->core_params->host_channels; 267 } else { 268 hsotg->non_periodic_channels = 0; 269 hsotg->periodic_channels = 0; 270 } 271 } 272 273 /** 274 * dwc2_hcd_connect() - Handles connect of the HCD 275 * 276 * @hsotg: Pointer to struct dwc2_hsotg 277 * 278 * Must be called with interrupt disabled and spinlock held 279 */ 280 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 281 { 282 if (hsotg->lx_state != DWC2_L0) 283 usb_hcd_resume_root_hub(hsotg->priv); 284 285 hsotg->flags.b.port_connect_status_change = 1; 286 hsotg->flags.b.port_connect_status = 1; 287 } 288 289 /** 290 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 291 * 292 * @hsotg: Pointer to struct dwc2_hsotg 293 * @force: If true, we won't try to reconnect even if we see device connected. 294 * 295 * Must be called with interrupt disabled and spinlock held 296 */ 297 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 298 { 299 u32 intr; 300 u32 hprt0; 301 302 /* Set status flags for the hub driver */ 303 hsotg->flags.b.port_connect_status_change = 1; 304 hsotg->flags.b.port_connect_status = 0; 305 306 /* 307 * Shutdown any transfers in process by clearing the Tx FIFO Empty 308 * interrupt mask and status bits and disabling subsequent host 309 * channel interrupts. 310 */ 311 intr = dwc2_readl(hsotg->regs + GINTMSK); 312 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 313 dwc2_writel(intr, hsotg->regs + GINTMSK); 314 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 315 dwc2_writel(intr, hsotg->regs + GINTSTS); 316 317 /* 318 * Turn off the vbus power only if the core has transitioned to device 319 * mode. If still in host mode, need to keep power on to detect a 320 * reconnection. 321 */ 322 if (dwc2_is_device_mode(hsotg)) { 323 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 324 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 325 dwc2_writel(0, hsotg->regs + HPRT0); 326 } 327 328 dwc2_disable_host_interrupts(hsotg); 329 } 330 331 /* Respond with an error status to all URBs in the schedule */ 332 dwc2_kill_all_urbs(hsotg); 333 334 if (dwc2_is_host_mode(hsotg)) 335 /* Clean up any host channels that were in use */ 336 dwc2_hcd_cleanup_channels(hsotg); 337 338 dwc2_host_disconnect(hsotg); 339 340 /* 341 * Add an extra check here to see if we're actually connected but 342 * we don't have a detection interrupt pending. This can happen if: 343 * 1. hardware sees connect 344 * 2. hardware sees disconnect 345 * 3. hardware sees connect 346 * 4. dwc2_port_intr() - clears connect interrupt 347 * 5. dwc2_handle_common_intr() - calls here 348 * 349 * Without the extra check here we will end calling disconnect 350 * and won't get any future interrupts to handle the connect. 351 */ 352 if (!force) { 353 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 354 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 355 dwc2_hcd_connect(hsotg); 356 } 357 } 358 359 /** 360 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 361 * 362 * @hsotg: Pointer to struct dwc2_hsotg 363 */ 364 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 365 { 366 if (hsotg->bus_suspended) { 367 hsotg->flags.b.port_suspend_change = 1; 368 usb_hcd_resume_root_hub(hsotg->priv); 369 } 370 371 if (hsotg->lx_state == DWC2_L1) 372 hsotg->flags.b.port_l1_change = 1; 373 } 374 375 /** 376 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 377 * 378 * @hsotg: Pointer to struct dwc2_hsotg 379 * 380 * Must be called with interrupt disabled and spinlock held 381 */ 382 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 383 { 384 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 385 386 /* 387 * The root hub should be disconnected before this function is called. 388 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 389 * and the QH lists (via ..._hcd_endpoint_disable). 390 */ 391 392 /* Turn off all host-specific interrupts */ 393 dwc2_disable_host_interrupts(hsotg); 394 395 /* Turn off the vbus power */ 396 dev_dbg(hsotg->dev, "PortPower off\n"); 397 dwc2_writel(0, hsotg->regs + HPRT0); 398 } 399 400 /* Caller must hold driver lock */ 401 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 402 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 403 struct dwc2_qtd *qtd) 404 { 405 u32 intr_mask; 406 int retval; 407 int dev_speed; 408 409 if (!hsotg->flags.b.port_connect_status) { 410 /* No longer connected */ 411 dev_err(hsotg->dev, "Not connected\n"); 412 return -ENODEV; 413 } 414 415 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 416 417 /* Some configurations cannot support LS traffic on a FS root port */ 418 if ((dev_speed == USB_SPEED_LOW) && 419 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 420 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 421 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 422 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 423 424 if (prtspd == HPRT0_SPD_FULL_SPEED) 425 return -ENODEV; 426 } 427 428 if (!qtd) 429 return -EINVAL; 430 431 dwc2_hcd_qtd_init(qtd, urb); 432 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 433 if (retval) { 434 dev_err(hsotg->dev, 435 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 436 retval); 437 return retval; 438 } 439 440 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 441 if (!(intr_mask & GINTSTS_SOF)) { 442 enum dwc2_transaction_type tr_type; 443 444 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 445 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 446 /* 447 * Do not schedule SG transactions until qtd has 448 * URB_GIVEBACK_ASAP set 449 */ 450 return 0; 451 452 tr_type = dwc2_hcd_select_transactions(hsotg); 453 if (tr_type != DWC2_TRANSACTION_NONE) 454 dwc2_hcd_queue_transactions(hsotg, tr_type); 455 } 456 457 return 0; 458 } 459 460 /* Must be called with interrupt disabled and spinlock held */ 461 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 462 struct dwc2_hcd_urb *urb) 463 { 464 struct dwc2_qh *qh; 465 struct dwc2_qtd *urb_qtd; 466 467 urb_qtd = urb->qtd; 468 if (!urb_qtd) { 469 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 470 return -EINVAL; 471 } 472 473 qh = urb_qtd->qh; 474 if (!qh) { 475 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 476 return -EINVAL; 477 } 478 479 urb->priv = NULL; 480 481 if (urb_qtd->in_process && qh->channel) { 482 dwc2_dump_channel_info(hsotg, qh->channel); 483 484 /* The QTD is in process (it has been assigned to a channel) */ 485 if (hsotg->flags.b.port_connect_status) 486 /* 487 * If still connected (i.e. in host mode), halt the 488 * channel so it can be used for other transfers. If 489 * no longer connected, the host registers can't be 490 * written to halt the channel since the core is in 491 * device mode. 492 */ 493 dwc2_hc_halt(hsotg, qh->channel, 494 DWC2_HC_XFER_URB_DEQUEUE); 495 } 496 497 /* 498 * Free the QTD and clean up the associated QH. Leave the QH in the 499 * schedule if it has any remaining QTDs. 500 */ 501 if (hsotg->core_params->dma_desc_enable <= 0) { 502 u8 in_process = urb_qtd->in_process; 503 504 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 505 if (in_process) { 506 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 507 qh->channel = NULL; 508 } else if (list_empty(&qh->qtd_list)) { 509 dwc2_hcd_qh_unlink(hsotg, qh); 510 } 511 } else { 512 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 513 } 514 515 return 0; 516 } 517 518 /* Must NOT be called with interrupt disabled or spinlock held */ 519 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 520 struct usb_host_endpoint *ep, int retry) 521 { 522 struct dwc2_qtd *qtd, *qtd_tmp; 523 struct dwc2_qh *qh; 524 unsigned long flags; 525 int rc; 526 527 spin_lock_irqsave(&hsotg->lock, flags); 528 529 qh = ep->hcpriv; 530 if (!qh) { 531 rc = -EINVAL; 532 goto err; 533 } 534 535 while (!list_empty(&qh->qtd_list) && retry--) { 536 if (retry == 0) { 537 dev_err(hsotg->dev, 538 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 539 rc = -EBUSY; 540 goto err; 541 } 542 543 spin_unlock_irqrestore(&hsotg->lock, flags); 544 usleep_range(20000, 40000); 545 spin_lock_irqsave(&hsotg->lock, flags); 546 qh = ep->hcpriv; 547 if (!qh) { 548 rc = -EINVAL; 549 goto err; 550 } 551 } 552 553 dwc2_hcd_qh_unlink(hsotg, qh); 554 555 /* Free each QTD in the QH's QTD list */ 556 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 557 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 558 559 ep->hcpriv = NULL; 560 561 if (qh->channel && qh->channel->qh == qh) 562 qh->channel->qh = NULL; 563 564 spin_unlock_irqrestore(&hsotg->lock, flags); 565 566 dwc2_hcd_qh_free(hsotg, qh); 567 568 return 0; 569 570 err: 571 ep->hcpriv = NULL; 572 spin_unlock_irqrestore(&hsotg->lock, flags); 573 574 return rc; 575 } 576 577 /* Must be called with interrupt disabled and spinlock held */ 578 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 579 struct usb_host_endpoint *ep) 580 { 581 struct dwc2_qh *qh = ep->hcpriv; 582 583 if (!qh) 584 return -EINVAL; 585 586 qh->data_toggle = DWC2_HC_PID_DATA0; 587 588 return 0; 589 } 590 591 /* 592 * Initializes dynamic portions of the DWC_otg HCD state 593 * 594 * Must be called with interrupt disabled and spinlock held 595 */ 596 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 597 { 598 struct dwc2_host_chan *chan, *chan_tmp; 599 int num_channels; 600 int i; 601 602 hsotg->flags.d32 = 0; 603 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 604 605 if (hsotg->core_params->uframe_sched > 0) { 606 hsotg->available_host_channels = 607 hsotg->core_params->host_channels; 608 } else { 609 hsotg->non_periodic_channels = 0; 610 hsotg->periodic_channels = 0; 611 } 612 613 /* 614 * Put all channels in the free channel list and clean up channel 615 * states 616 */ 617 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 618 hc_list_entry) 619 list_del_init(&chan->hc_list_entry); 620 621 num_channels = hsotg->core_params->host_channels; 622 for (i = 0; i < num_channels; i++) { 623 chan = hsotg->hc_ptr_array[i]; 624 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 625 dwc2_hc_cleanup(hsotg, chan); 626 } 627 628 /* Initialize the DWC core for host mode operation */ 629 dwc2_core_host_init(hsotg); 630 } 631 632 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 633 struct dwc2_host_chan *chan, 634 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 635 { 636 int hub_addr, hub_port; 637 638 chan->do_split = 1; 639 chan->xact_pos = qtd->isoc_split_pos; 640 chan->complete_split = qtd->complete_split; 641 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 642 chan->hub_addr = (u8)hub_addr; 643 chan->hub_port = (u8)hub_port; 644 } 645 646 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 647 struct dwc2_host_chan *chan, 648 struct dwc2_qtd *qtd) 649 { 650 struct dwc2_hcd_urb *urb = qtd->urb; 651 struct dwc2_hcd_iso_packet_desc *frame_desc; 652 653 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 654 case USB_ENDPOINT_XFER_CONTROL: 655 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 656 657 switch (qtd->control_phase) { 658 case DWC2_CONTROL_SETUP: 659 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 660 chan->do_ping = 0; 661 chan->ep_is_in = 0; 662 chan->data_pid_start = DWC2_HC_PID_SETUP; 663 if (hsotg->core_params->dma_enable > 0) 664 chan->xfer_dma = urb->setup_dma; 665 else 666 chan->xfer_buf = urb->setup_packet; 667 chan->xfer_len = 8; 668 break; 669 670 case DWC2_CONTROL_DATA: 671 dev_vdbg(hsotg->dev, " Control data transaction\n"); 672 chan->data_pid_start = qtd->data_toggle; 673 break; 674 675 case DWC2_CONTROL_STATUS: 676 /* 677 * Direction is opposite of data direction or IN if no 678 * data 679 */ 680 dev_vdbg(hsotg->dev, " Control status transaction\n"); 681 if (urb->length == 0) 682 chan->ep_is_in = 1; 683 else 684 chan->ep_is_in = 685 dwc2_hcd_is_pipe_out(&urb->pipe_info); 686 if (chan->ep_is_in) 687 chan->do_ping = 0; 688 chan->data_pid_start = DWC2_HC_PID_DATA1; 689 chan->xfer_len = 0; 690 if (hsotg->core_params->dma_enable > 0) 691 chan->xfer_dma = hsotg->status_buf_dma; 692 else 693 chan->xfer_buf = hsotg->status_buf; 694 break; 695 } 696 break; 697 698 case USB_ENDPOINT_XFER_BULK: 699 chan->ep_type = USB_ENDPOINT_XFER_BULK; 700 break; 701 702 case USB_ENDPOINT_XFER_INT: 703 chan->ep_type = USB_ENDPOINT_XFER_INT; 704 break; 705 706 case USB_ENDPOINT_XFER_ISOC: 707 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 708 if (hsotg->core_params->dma_desc_enable > 0) 709 break; 710 711 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 712 frame_desc->status = 0; 713 714 if (hsotg->core_params->dma_enable > 0) { 715 chan->xfer_dma = urb->dma; 716 chan->xfer_dma += frame_desc->offset + 717 qtd->isoc_split_offset; 718 } else { 719 chan->xfer_buf = urb->buf; 720 chan->xfer_buf += frame_desc->offset + 721 qtd->isoc_split_offset; 722 } 723 724 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 725 726 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 727 if (chan->xfer_len <= 188) 728 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 729 else 730 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 731 } 732 break; 733 } 734 } 735 736 #define DWC2_USB_DMA_ALIGN 4 737 738 struct dma_aligned_buffer { 739 void *kmalloc_ptr; 740 void *old_xfer_buffer; 741 u8 data[0]; 742 }; 743 744 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 745 { 746 struct dma_aligned_buffer *temp; 747 748 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 749 return; 750 751 temp = container_of(urb->transfer_buffer, 752 struct dma_aligned_buffer, data); 753 754 if (usb_urb_dir_in(urb)) 755 memcpy(temp->old_xfer_buffer, temp->data, 756 urb->transfer_buffer_length); 757 urb->transfer_buffer = temp->old_xfer_buffer; 758 kfree(temp->kmalloc_ptr); 759 760 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 761 } 762 763 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 764 { 765 struct dma_aligned_buffer *temp, *kmalloc_ptr; 766 size_t kmalloc_size; 767 768 if (urb->num_sgs || urb->sg || 769 urb->transfer_buffer_length == 0 || 770 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 771 return 0; 772 773 /* Allocate a buffer with enough padding for alignment */ 774 kmalloc_size = urb->transfer_buffer_length + 775 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 776 777 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 778 if (!kmalloc_ptr) 779 return -ENOMEM; 780 781 /* Position our struct dma_aligned_buffer such that data is aligned */ 782 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 783 temp->kmalloc_ptr = kmalloc_ptr; 784 temp->old_xfer_buffer = urb->transfer_buffer; 785 if (usb_urb_dir_out(urb)) 786 memcpy(temp->data, urb->transfer_buffer, 787 urb->transfer_buffer_length); 788 urb->transfer_buffer = temp->data; 789 790 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 791 792 return 0; 793 } 794 795 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 796 gfp_t mem_flags) 797 { 798 int ret; 799 800 /* We assume setup_dma is always aligned; warn if not */ 801 WARN_ON_ONCE(urb->setup_dma && 802 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 803 804 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 805 if (ret) 806 return ret; 807 808 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 809 if (ret) 810 dwc2_free_dma_aligned_buffer(urb); 811 812 return ret; 813 } 814 815 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 816 { 817 usb_hcd_unmap_urb_for_dma(hcd, urb); 818 dwc2_free_dma_aligned_buffer(urb); 819 } 820 821 /** 822 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 823 * channel and initializes the host channel to perform the transactions. The 824 * host channel is removed from the free list. 825 * 826 * @hsotg: The HCD state structure 827 * @qh: Transactions from the first QTD for this QH are selected and assigned 828 * to a free host channel 829 */ 830 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 831 { 832 struct dwc2_host_chan *chan; 833 struct dwc2_hcd_urb *urb; 834 struct dwc2_qtd *qtd; 835 836 if (dbg_qh(qh)) 837 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 838 839 if (list_empty(&qh->qtd_list)) { 840 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 841 return -ENOMEM; 842 } 843 844 if (list_empty(&hsotg->free_hc_list)) { 845 dev_dbg(hsotg->dev, "No free channel to assign\n"); 846 return -ENOMEM; 847 } 848 849 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 850 hc_list_entry); 851 852 /* Remove host channel from free list */ 853 list_del_init(&chan->hc_list_entry); 854 855 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 856 urb = qtd->urb; 857 qh->channel = chan; 858 qtd->in_process = 1; 859 860 /* 861 * Use usb_pipedevice to determine device address. This address is 862 * 0 before the SET_ADDRESS command and the correct address afterward. 863 */ 864 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 865 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 866 chan->speed = qh->dev_speed; 867 chan->max_packet = dwc2_max_packet(qh->maxp); 868 869 chan->xfer_started = 0; 870 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 871 chan->error_state = (qtd->error_count > 0); 872 chan->halt_on_queue = 0; 873 chan->halt_pending = 0; 874 chan->requests = 0; 875 876 /* 877 * The following values may be modified in the transfer type section 878 * below. The xfer_len value may be reduced when the transfer is 879 * started to accommodate the max widths of the XferSize and PktCnt 880 * fields in the HCTSIZn register. 881 */ 882 883 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 884 if (chan->ep_is_in) 885 chan->do_ping = 0; 886 else 887 chan->do_ping = qh->ping_state; 888 889 chan->data_pid_start = qh->data_toggle; 890 chan->multi_count = 1; 891 892 if (urb->actual_length > urb->length && 893 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 894 urb->actual_length = urb->length; 895 896 if (hsotg->core_params->dma_enable > 0) 897 chan->xfer_dma = urb->dma + urb->actual_length; 898 else 899 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 900 901 chan->xfer_len = urb->length - urb->actual_length; 902 chan->xfer_count = 0; 903 904 /* Set the split attributes if required */ 905 if (qh->do_split) 906 dwc2_hc_init_split(hsotg, chan, qtd, urb); 907 else 908 chan->do_split = 0; 909 910 /* Set the transfer attributes */ 911 dwc2_hc_init_xfer(hsotg, chan, qtd); 912 913 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 914 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 915 /* 916 * This value may be modified when the transfer is started 917 * to reflect the actual transfer length 918 */ 919 chan->multi_count = dwc2_hb_mult(qh->maxp); 920 921 if (hsotg->core_params->dma_desc_enable > 0) { 922 chan->desc_list_addr = qh->desc_list_dma; 923 chan->desc_list_sz = qh->desc_list_sz; 924 } 925 926 dwc2_hc_init(hsotg, chan); 927 chan->qh = qh; 928 929 return 0; 930 } 931 932 /** 933 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 934 * schedule and assigns them to available host channels. Called from the HCD 935 * interrupt handler functions. 936 * 937 * @hsotg: The HCD state structure 938 * 939 * Return: The types of new transactions that were assigned to host channels 940 */ 941 enum dwc2_transaction_type dwc2_hcd_select_transactions( 942 struct dwc2_hsotg *hsotg) 943 { 944 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 945 struct list_head *qh_ptr; 946 struct dwc2_qh *qh; 947 int num_channels; 948 949 #ifdef DWC2_DEBUG_SOF 950 dev_vdbg(hsotg->dev, " Select Transactions\n"); 951 #endif 952 953 /* Process entries in the periodic ready list */ 954 qh_ptr = hsotg->periodic_sched_ready.next; 955 while (qh_ptr != &hsotg->periodic_sched_ready) { 956 if (list_empty(&hsotg->free_hc_list)) 957 break; 958 if (hsotg->core_params->uframe_sched > 0) { 959 if (hsotg->available_host_channels <= 1) 960 break; 961 hsotg->available_host_channels--; 962 } 963 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 964 if (dwc2_assign_and_init_hc(hsotg, qh)) 965 break; 966 967 /* 968 * Move the QH from the periodic ready schedule to the 969 * periodic assigned schedule 970 */ 971 qh_ptr = qh_ptr->next; 972 list_move_tail(&qh->qh_list_entry, 973 &hsotg->periodic_sched_assigned); 974 ret_val = DWC2_TRANSACTION_PERIODIC; 975 } 976 977 /* 978 * Process entries in the inactive portion of the non-periodic 979 * schedule. Some free host channels may not be used if they are 980 * reserved for periodic transfers. 981 */ 982 num_channels = hsotg->core_params->host_channels; 983 qh_ptr = hsotg->non_periodic_sched_inactive.next; 984 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 985 if (hsotg->core_params->uframe_sched <= 0 && 986 hsotg->non_periodic_channels >= num_channels - 987 hsotg->periodic_channels) 988 break; 989 if (list_empty(&hsotg->free_hc_list)) 990 break; 991 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 992 if (hsotg->core_params->uframe_sched > 0) { 993 if (hsotg->available_host_channels < 1) 994 break; 995 hsotg->available_host_channels--; 996 } 997 998 if (dwc2_assign_and_init_hc(hsotg, qh)) 999 break; 1000 1001 /* 1002 * Move the QH from the non-periodic inactive schedule to the 1003 * non-periodic active schedule 1004 */ 1005 qh_ptr = qh_ptr->next; 1006 list_move_tail(&qh->qh_list_entry, 1007 &hsotg->non_periodic_sched_active); 1008 1009 if (ret_val == DWC2_TRANSACTION_NONE) 1010 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 1011 else 1012 ret_val = DWC2_TRANSACTION_ALL; 1013 1014 if (hsotg->core_params->uframe_sched <= 0) 1015 hsotg->non_periodic_channels++; 1016 } 1017 1018 return ret_val; 1019 } 1020 1021 /** 1022 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 1023 * a host channel associated with either a periodic or non-periodic transfer 1024 * 1025 * @hsotg: The HCD state structure 1026 * @chan: Host channel descriptor associated with either a periodic or 1027 * non-periodic transfer 1028 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 1029 * for periodic transfers or the non-periodic Tx FIFO 1030 * for non-periodic transfers 1031 * 1032 * Return: 1 if a request is queued and more requests may be needed to 1033 * complete the transfer, 0 if no more requests are required for this 1034 * transfer, -1 if there is insufficient space in the Tx FIFO 1035 * 1036 * This function assumes that there is space available in the appropriate 1037 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1038 * it checks whether space is available in the appropriate Tx FIFO. 1039 * 1040 * Must be called with interrupt disabled and spinlock held 1041 */ 1042 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1043 struct dwc2_host_chan *chan, 1044 u16 fifo_dwords_avail) 1045 { 1046 int retval = 0; 1047 1048 if (chan->do_split) 1049 /* Put ourselves on the list to keep order straight */ 1050 list_move_tail(&chan->split_order_list_entry, 1051 &hsotg->split_order); 1052 1053 if (hsotg->core_params->dma_enable > 0) { 1054 if (hsotg->core_params->dma_desc_enable > 0) { 1055 if (!chan->xfer_started || 1056 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1057 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1058 chan->qh->ping_state = 0; 1059 } 1060 } else if (!chan->xfer_started) { 1061 dwc2_hc_start_transfer(hsotg, chan); 1062 chan->qh->ping_state = 0; 1063 } 1064 } else if (chan->halt_pending) { 1065 /* Don't queue a request if the channel has been halted */ 1066 } else if (chan->halt_on_queue) { 1067 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1068 } else if (chan->do_ping) { 1069 if (!chan->xfer_started) 1070 dwc2_hc_start_transfer(hsotg, chan); 1071 } else if (!chan->ep_is_in || 1072 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1073 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1074 if (!chan->xfer_started) { 1075 dwc2_hc_start_transfer(hsotg, chan); 1076 retval = 1; 1077 } else { 1078 retval = dwc2_hc_continue_transfer(hsotg, chan); 1079 } 1080 } else { 1081 retval = -1; 1082 } 1083 } else { 1084 if (!chan->xfer_started) { 1085 dwc2_hc_start_transfer(hsotg, chan); 1086 retval = 1; 1087 } else { 1088 retval = dwc2_hc_continue_transfer(hsotg, chan); 1089 } 1090 } 1091 1092 return retval; 1093 } 1094 1095 /* 1096 * Processes periodic channels for the next frame and queues transactions for 1097 * these channels to the DWC_otg controller. After queueing transactions, the 1098 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1099 * to queue as Periodic Tx FIFO or request queue space becomes available. 1100 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1101 * 1102 * Must be called with interrupt disabled and spinlock held 1103 */ 1104 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1105 { 1106 struct list_head *qh_ptr; 1107 struct dwc2_qh *qh; 1108 u32 tx_status; 1109 u32 fspcavail; 1110 u32 gintmsk; 1111 int status; 1112 bool no_queue_space = false; 1113 bool no_fifo_space = false; 1114 u32 qspcavail; 1115 1116 /* If empty list then just adjust interrupt enables */ 1117 if (list_empty(&hsotg->periodic_sched_assigned)) 1118 goto exit; 1119 1120 if (dbg_perio()) 1121 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1122 1123 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1124 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1125 TXSTS_QSPCAVAIL_SHIFT; 1126 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1127 TXSTS_FSPCAVAIL_SHIFT; 1128 1129 if (dbg_perio()) { 1130 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1131 qspcavail); 1132 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1133 fspcavail); 1134 } 1135 1136 qh_ptr = hsotg->periodic_sched_assigned.next; 1137 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1138 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1139 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1140 TXSTS_QSPCAVAIL_SHIFT; 1141 if (qspcavail == 0) { 1142 no_queue_space = 1; 1143 break; 1144 } 1145 1146 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1147 if (!qh->channel) { 1148 qh_ptr = qh_ptr->next; 1149 continue; 1150 } 1151 1152 /* Make sure EP's TT buffer is clean before queueing qtds */ 1153 if (qh->tt_buffer_dirty) { 1154 qh_ptr = qh_ptr->next; 1155 continue; 1156 } 1157 1158 /* 1159 * Set a flag if we're queuing high-bandwidth in slave mode. 1160 * The flag prevents any halts to get into the request queue in 1161 * the middle of multiple high-bandwidth packets getting queued. 1162 */ 1163 if (hsotg->core_params->dma_enable <= 0 && 1164 qh->channel->multi_count > 1) 1165 hsotg->queuing_high_bandwidth = 1; 1166 1167 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1168 TXSTS_FSPCAVAIL_SHIFT; 1169 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1170 if (status < 0) { 1171 no_fifo_space = 1; 1172 break; 1173 } 1174 1175 /* 1176 * In Slave mode, stay on the current transfer until there is 1177 * nothing more to do or the high-bandwidth request count is 1178 * reached. In DMA mode, only need to queue one request. The 1179 * controller automatically handles multiple packets for 1180 * high-bandwidth transfers. 1181 */ 1182 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1183 qh->channel->requests == qh->channel->multi_count) { 1184 qh_ptr = qh_ptr->next; 1185 /* 1186 * Move the QH from the periodic assigned schedule to 1187 * the periodic queued schedule 1188 */ 1189 list_move_tail(&qh->qh_list_entry, 1190 &hsotg->periodic_sched_queued); 1191 1192 /* done queuing high bandwidth */ 1193 hsotg->queuing_high_bandwidth = 0; 1194 } 1195 } 1196 1197 exit: 1198 if (no_queue_space || no_fifo_space || 1199 (hsotg->core_params->dma_enable <= 0 && 1200 !list_empty(&hsotg->periodic_sched_assigned))) { 1201 /* 1202 * May need to queue more transactions as the request 1203 * queue or Tx FIFO empties. Enable the periodic Tx 1204 * FIFO empty interrupt. (Always use the half-empty 1205 * level to ensure that new requests are loaded as 1206 * soon as possible.) 1207 */ 1208 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1209 if (!(gintmsk & GINTSTS_PTXFEMP)) { 1210 gintmsk |= GINTSTS_PTXFEMP; 1211 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1212 } 1213 } else { 1214 /* 1215 * Disable the Tx FIFO empty interrupt since there are 1216 * no more transactions that need to be queued right 1217 * now. This function is called from interrupt 1218 * handlers to queue more transactions as transfer 1219 * states change. 1220 */ 1221 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1222 if (gintmsk & GINTSTS_PTXFEMP) { 1223 gintmsk &= ~GINTSTS_PTXFEMP; 1224 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1225 } 1226 } 1227 } 1228 1229 /* 1230 * Processes active non-periodic channels and queues transactions for these 1231 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1232 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1233 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1234 * FIFO Empty interrupt is disabled. 1235 * 1236 * Must be called with interrupt disabled and spinlock held 1237 */ 1238 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1239 { 1240 struct list_head *orig_qh_ptr; 1241 struct dwc2_qh *qh; 1242 u32 tx_status; 1243 u32 qspcavail; 1244 u32 fspcavail; 1245 u32 gintmsk; 1246 int status; 1247 int no_queue_space = 0; 1248 int no_fifo_space = 0; 1249 int more_to_do = 0; 1250 1251 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1252 1253 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1254 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1255 TXSTS_QSPCAVAIL_SHIFT; 1256 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1257 TXSTS_FSPCAVAIL_SHIFT; 1258 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1259 qspcavail); 1260 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1261 fspcavail); 1262 1263 /* 1264 * Keep track of the starting point. Skip over the start-of-list 1265 * entry. 1266 */ 1267 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1268 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1269 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1270 1271 /* 1272 * Process once through the active list or until no more space is 1273 * available in the request queue or the Tx FIFO 1274 */ 1275 do { 1276 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1277 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1278 TXSTS_QSPCAVAIL_SHIFT; 1279 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1280 no_queue_space = 1; 1281 break; 1282 } 1283 1284 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1285 qh_list_entry); 1286 if (!qh->channel) 1287 goto next; 1288 1289 /* Make sure EP's TT buffer is clean before queueing qtds */ 1290 if (qh->tt_buffer_dirty) 1291 goto next; 1292 1293 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1294 TXSTS_FSPCAVAIL_SHIFT; 1295 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1296 1297 if (status > 0) { 1298 more_to_do = 1; 1299 } else if (status < 0) { 1300 no_fifo_space = 1; 1301 break; 1302 } 1303 next: 1304 /* Advance to next QH, skipping start-of-list entry */ 1305 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1306 if (hsotg->non_periodic_qh_ptr == 1307 &hsotg->non_periodic_sched_active) 1308 hsotg->non_periodic_qh_ptr = 1309 hsotg->non_periodic_qh_ptr->next; 1310 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1311 1312 if (hsotg->core_params->dma_enable <= 0) { 1313 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1314 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1315 TXSTS_QSPCAVAIL_SHIFT; 1316 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1317 TXSTS_FSPCAVAIL_SHIFT; 1318 dev_vdbg(hsotg->dev, 1319 " NP Tx Req Queue Space Avail (after queue): %d\n", 1320 qspcavail); 1321 dev_vdbg(hsotg->dev, 1322 " NP Tx FIFO Space Avail (after queue): %d\n", 1323 fspcavail); 1324 1325 if (more_to_do || no_queue_space || no_fifo_space) { 1326 /* 1327 * May need to queue more transactions as the request 1328 * queue or Tx FIFO empties. Enable the non-periodic 1329 * Tx FIFO empty interrupt. (Always use the half-empty 1330 * level to ensure that new requests are loaded as 1331 * soon as possible.) 1332 */ 1333 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1334 gintmsk |= GINTSTS_NPTXFEMP; 1335 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1336 } else { 1337 /* 1338 * Disable the Tx FIFO empty interrupt since there are 1339 * no more transactions that need to be queued right 1340 * now. This function is called from interrupt 1341 * handlers to queue more transactions as transfer 1342 * states change. 1343 */ 1344 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1345 gintmsk &= ~GINTSTS_NPTXFEMP; 1346 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1347 } 1348 } 1349 } 1350 1351 /** 1352 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1353 * and queues transactions for these channels to the DWC_otg controller. Called 1354 * from the HCD interrupt handler functions. 1355 * 1356 * @hsotg: The HCD state structure 1357 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1358 * or both) 1359 * 1360 * Must be called with interrupt disabled and spinlock held 1361 */ 1362 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1363 enum dwc2_transaction_type tr_type) 1364 { 1365 #ifdef DWC2_DEBUG_SOF 1366 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1367 #endif 1368 /* Process host channels associated with periodic transfers */ 1369 if (tr_type == DWC2_TRANSACTION_PERIODIC || 1370 tr_type == DWC2_TRANSACTION_ALL) 1371 dwc2_process_periodic_channels(hsotg); 1372 1373 /* Process host channels associated with non-periodic transfers */ 1374 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1375 tr_type == DWC2_TRANSACTION_ALL) { 1376 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1377 dwc2_process_non_periodic_channels(hsotg); 1378 } else { 1379 /* 1380 * Ensure NP Tx FIFO empty interrupt is disabled when 1381 * there are no non-periodic transfers to process 1382 */ 1383 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1384 1385 gintmsk &= ~GINTSTS_NPTXFEMP; 1386 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1387 } 1388 } 1389 } 1390 1391 static void dwc2_conn_id_status_change(struct work_struct *work) 1392 { 1393 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1394 wf_otg); 1395 u32 count = 0; 1396 u32 gotgctl; 1397 unsigned long flags; 1398 1399 dev_dbg(hsotg->dev, "%s()\n", __func__); 1400 1401 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1402 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1403 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1404 !!(gotgctl & GOTGCTL_CONID_B)); 1405 1406 /* B-Device connector (Device Mode) */ 1407 if (gotgctl & GOTGCTL_CONID_B) { 1408 /* Wait for switch to device mode */ 1409 dev_dbg(hsotg->dev, "connId B\n"); 1410 while (!dwc2_is_device_mode(hsotg)) { 1411 dev_info(hsotg->dev, 1412 "Waiting for Peripheral Mode, Mode=%s\n", 1413 dwc2_is_host_mode(hsotg) ? "Host" : 1414 "Peripheral"); 1415 usleep_range(20000, 40000); 1416 if (++count > 250) 1417 break; 1418 } 1419 if (count > 250) 1420 dev_err(hsotg->dev, 1421 "Connection id status change timed out\n"); 1422 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1423 dwc2_core_init(hsotg, false); 1424 dwc2_enable_global_interrupts(hsotg); 1425 spin_lock_irqsave(&hsotg->lock, flags); 1426 dwc2_hsotg_core_init_disconnected(hsotg, false); 1427 spin_unlock_irqrestore(&hsotg->lock, flags); 1428 dwc2_hsotg_core_connect(hsotg); 1429 } else { 1430 /* A-Device connector (Host Mode) */ 1431 dev_dbg(hsotg->dev, "connId A\n"); 1432 while (!dwc2_is_host_mode(hsotg)) { 1433 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1434 dwc2_is_host_mode(hsotg) ? 1435 "Host" : "Peripheral"); 1436 usleep_range(20000, 40000); 1437 if (++count > 250) 1438 break; 1439 } 1440 if (count > 250) 1441 dev_err(hsotg->dev, 1442 "Connection id status change timed out\n"); 1443 hsotg->op_state = OTG_STATE_A_HOST; 1444 1445 /* Initialize the Core for Host mode */ 1446 dwc2_core_init(hsotg, false); 1447 dwc2_enable_global_interrupts(hsotg); 1448 dwc2_hcd_start(hsotg); 1449 } 1450 } 1451 1452 static void dwc2_wakeup_detected(unsigned long data) 1453 { 1454 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1455 u32 hprt0; 1456 1457 dev_dbg(hsotg->dev, "%s()\n", __func__); 1458 1459 /* 1460 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1461 * so that OPT tests pass with all PHYs.) 1462 */ 1463 hprt0 = dwc2_read_hprt0(hsotg); 1464 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1465 hprt0 &= ~HPRT0_RES; 1466 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1467 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1468 dwc2_readl(hsotg->regs + HPRT0)); 1469 1470 dwc2_hcd_rem_wakeup(hsotg); 1471 hsotg->bus_suspended = 0; 1472 1473 /* Change to L0 state */ 1474 hsotg->lx_state = DWC2_L0; 1475 } 1476 1477 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1478 { 1479 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1480 1481 return hcd->self.b_hnp_enable; 1482 } 1483 1484 /* Must NOT be called with interrupt disabled or spinlock held */ 1485 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1486 { 1487 unsigned long flags; 1488 u32 hprt0; 1489 u32 pcgctl; 1490 u32 gotgctl; 1491 1492 dev_dbg(hsotg->dev, "%s()\n", __func__); 1493 1494 spin_lock_irqsave(&hsotg->lock, flags); 1495 1496 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1497 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1498 gotgctl |= GOTGCTL_HSTSETHNPEN; 1499 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 1500 hsotg->op_state = OTG_STATE_A_SUSPEND; 1501 } 1502 1503 hprt0 = dwc2_read_hprt0(hsotg); 1504 hprt0 |= HPRT0_SUSP; 1505 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1506 1507 hsotg->bus_suspended = 1; 1508 1509 /* 1510 * If hibernation is supported, Phy clock will be suspended 1511 * after registers are backuped. 1512 */ 1513 if (!hsotg->core_params->hibernation) { 1514 /* Suspend the Phy Clock */ 1515 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1516 pcgctl |= PCGCTL_STOPPCLK; 1517 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1518 udelay(10); 1519 } 1520 1521 /* For HNP the bus must be suspended for at least 200ms */ 1522 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1523 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1524 pcgctl &= ~PCGCTL_STOPPCLK; 1525 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1526 1527 spin_unlock_irqrestore(&hsotg->lock, flags); 1528 1529 usleep_range(200000, 250000); 1530 } else { 1531 spin_unlock_irqrestore(&hsotg->lock, flags); 1532 } 1533 } 1534 1535 /* Must NOT be called with interrupt disabled or spinlock held */ 1536 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1537 { 1538 unsigned long flags; 1539 u32 hprt0; 1540 u32 pcgctl; 1541 1542 spin_lock_irqsave(&hsotg->lock, flags); 1543 1544 /* 1545 * If hibernation is supported, Phy clock is already resumed 1546 * after registers restore. 1547 */ 1548 if (!hsotg->core_params->hibernation) { 1549 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1550 pcgctl &= ~PCGCTL_STOPPCLK; 1551 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1552 spin_unlock_irqrestore(&hsotg->lock, flags); 1553 usleep_range(20000, 40000); 1554 spin_lock_irqsave(&hsotg->lock, flags); 1555 } 1556 1557 hprt0 = dwc2_read_hprt0(hsotg); 1558 hprt0 |= HPRT0_RES; 1559 hprt0 &= ~HPRT0_SUSP; 1560 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1561 spin_unlock_irqrestore(&hsotg->lock, flags); 1562 1563 msleep(USB_RESUME_TIMEOUT); 1564 1565 spin_lock_irqsave(&hsotg->lock, flags); 1566 hprt0 = dwc2_read_hprt0(hsotg); 1567 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1568 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1569 hsotg->bus_suspended = 0; 1570 spin_unlock_irqrestore(&hsotg->lock, flags); 1571 } 1572 1573 /* Handles hub class-specific requests */ 1574 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1575 u16 wvalue, u16 windex, char *buf, u16 wlength) 1576 { 1577 struct usb_hub_descriptor *hub_desc; 1578 int retval = 0; 1579 u32 hprt0; 1580 u32 port_status; 1581 u32 speed; 1582 u32 pcgctl; 1583 1584 switch (typereq) { 1585 case ClearHubFeature: 1586 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1587 1588 switch (wvalue) { 1589 case C_HUB_LOCAL_POWER: 1590 case C_HUB_OVER_CURRENT: 1591 /* Nothing required here */ 1592 break; 1593 1594 default: 1595 retval = -EINVAL; 1596 dev_err(hsotg->dev, 1597 "ClearHubFeature request %1xh unknown\n", 1598 wvalue); 1599 } 1600 break; 1601 1602 case ClearPortFeature: 1603 if (wvalue != USB_PORT_FEAT_L1) 1604 if (!windex || windex > 1) 1605 goto error; 1606 switch (wvalue) { 1607 case USB_PORT_FEAT_ENABLE: 1608 dev_dbg(hsotg->dev, 1609 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1610 hprt0 = dwc2_read_hprt0(hsotg); 1611 hprt0 |= HPRT0_ENA; 1612 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1613 break; 1614 1615 case USB_PORT_FEAT_SUSPEND: 1616 dev_dbg(hsotg->dev, 1617 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1618 1619 if (hsotg->bus_suspended) 1620 dwc2_port_resume(hsotg); 1621 break; 1622 1623 case USB_PORT_FEAT_POWER: 1624 dev_dbg(hsotg->dev, 1625 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1626 hprt0 = dwc2_read_hprt0(hsotg); 1627 hprt0 &= ~HPRT0_PWR; 1628 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1629 break; 1630 1631 case USB_PORT_FEAT_INDICATOR: 1632 dev_dbg(hsotg->dev, 1633 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1634 /* Port indicator not supported */ 1635 break; 1636 1637 case USB_PORT_FEAT_C_CONNECTION: 1638 /* 1639 * Clears driver's internal Connect Status Change flag 1640 */ 1641 dev_dbg(hsotg->dev, 1642 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1643 hsotg->flags.b.port_connect_status_change = 0; 1644 break; 1645 1646 case USB_PORT_FEAT_C_RESET: 1647 /* Clears driver's internal Port Reset Change flag */ 1648 dev_dbg(hsotg->dev, 1649 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1650 hsotg->flags.b.port_reset_change = 0; 1651 break; 1652 1653 case USB_PORT_FEAT_C_ENABLE: 1654 /* 1655 * Clears the driver's internal Port Enable/Disable 1656 * Change flag 1657 */ 1658 dev_dbg(hsotg->dev, 1659 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1660 hsotg->flags.b.port_enable_change = 0; 1661 break; 1662 1663 case USB_PORT_FEAT_C_SUSPEND: 1664 /* 1665 * Clears the driver's internal Port Suspend Change 1666 * flag, which is set when resume signaling on the host 1667 * port is complete 1668 */ 1669 dev_dbg(hsotg->dev, 1670 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1671 hsotg->flags.b.port_suspend_change = 0; 1672 break; 1673 1674 case USB_PORT_FEAT_C_PORT_L1: 1675 dev_dbg(hsotg->dev, 1676 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1677 hsotg->flags.b.port_l1_change = 0; 1678 break; 1679 1680 case USB_PORT_FEAT_C_OVER_CURRENT: 1681 dev_dbg(hsotg->dev, 1682 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1683 hsotg->flags.b.port_over_current_change = 0; 1684 break; 1685 1686 default: 1687 retval = -EINVAL; 1688 dev_err(hsotg->dev, 1689 "ClearPortFeature request %1xh unknown or unsupported\n", 1690 wvalue); 1691 } 1692 break; 1693 1694 case GetHubDescriptor: 1695 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1696 hub_desc = (struct usb_hub_descriptor *)buf; 1697 hub_desc->bDescLength = 9; 1698 hub_desc->bDescriptorType = USB_DT_HUB; 1699 hub_desc->bNbrPorts = 1; 1700 hub_desc->wHubCharacteristics = 1701 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1702 HUB_CHAR_INDV_PORT_OCPM); 1703 hub_desc->bPwrOn2PwrGood = 1; 1704 hub_desc->bHubContrCurrent = 0; 1705 hub_desc->u.hs.DeviceRemovable[0] = 0; 1706 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1707 break; 1708 1709 case GetHubStatus: 1710 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1711 memset(buf, 0, 4); 1712 break; 1713 1714 case GetPortStatus: 1715 dev_vdbg(hsotg->dev, 1716 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1717 hsotg->flags.d32); 1718 if (!windex || windex > 1) 1719 goto error; 1720 1721 port_status = 0; 1722 if (hsotg->flags.b.port_connect_status_change) 1723 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1724 if (hsotg->flags.b.port_enable_change) 1725 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1726 if (hsotg->flags.b.port_suspend_change) 1727 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1728 if (hsotg->flags.b.port_l1_change) 1729 port_status |= USB_PORT_STAT_C_L1 << 16; 1730 if (hsotg->flags.b.port_reset_change) 1731 port_status |= USB_PORT_STAT_C_RESET << 16; 1732 if (hsotg->flags.b.port_over_current_change) { 1733 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1734 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1735 } 1736 1737 if (!hsotg->flags.b.port_connect_status) { 1738 /* 1739 * The port is disconnected, which means the core is 1740 * either in device mode or it soon will be. Just 1741 * return 0's for the remainder of the port status 1742 * since the port register can't be read if the core 1743 * is in device mode. 1744 */ 1745 *(__le32 *)buf = cpu_to_le32(port_status); 1746 break; 1747 } 1748 1749 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1750 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1751 1752 if (hprt0 & HPRT0_CONNSTS) 1753 port_status |= USB_PORT_STAT_CONNECTION; 1754 if (hprt0 & HPRT0_ENA) 1755 port_status |= USB_PORT_STAT_ENABLE; 1756 if (hprt0 & HPRT0_SUSP) 1757 port_status |= USB_PORT_STAT_SUSPEND; 1758 if (hprt0 & HPRT0_OVRCURRACT) 1759 port_status |= USB_PORT_STAT_OVERCURRENT; 1760 if (hprt0 & HPRT0_RST) 1761 port_status |= USB_PORT_STAT_RESET; 1762 if (hprt0 & HPRT0_PWR) 1763 port_status |= USB_PORT_STAT_POWER; 1764 1765 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1766 if (speed == HPRT0_SPD_HIGH_SPEED) 1767 port_status |= USB_PORT_STAT_HIGH_SPEED; 1768 else if (speed == HPRT0_SPD_LOW_SPEED) 1769 port_status |= USB_PORT_STAT_LOW_SPEED; 1770 1771 if (hprt0 & HPRT0_TSTCTL_MASK) 1772 port_status |= USB_PORT_STAT_TEST; 1773 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1774 1775 if (hsotg->core_params->dma_desc_fs_enable) { 1776 /* 1777 * Enable descriptor DMA only if a full speed 1778 * device is connected. 1779 */ 1780 if (hsotg->new_connection && 1781 ((port_status & 1782 (USB_PORT_STAT_CONNECTION | 1783 USB_PORT_STAT_HIGH_SPEED | 1784 USB_PORT_STAT_LOW_SPEED)) == 1785 USB_PORT_STAT_CONNECTION)) { 1786 u32 hcfg; 1787 1788 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 1789 hsotg->core_params->dma_desc_enable = 1; 1790 hcfg = dwc2_readl(hsotg->regs + HCFG); 1791 hcfg |= HCFG_DESCDMA; 1792 dwc2_writel(hcfg, hsotg->regs + HCFG); 1793 hsotg->new_connection = false; 1794 } 1795 } 1796 1797 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1798 *(__le32 *)buf = cpu_to_le32(port_status); 1799 break; 1800 1801 case SetHubFeature: 1802 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1803 /* No HUB features supported */ 1804 break; 1805 1806 case SetPortFeature: 1807 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1808 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1809 goto error; 1810 1811 if (!hsotg->flags.b.port_connect_status) { 1812 /* 1813 * The port is disconnected, which means the core is 1814 * either in device mode or it soon will be. Just 1815 * return without doing anything since the port 1816 * register can't be written if the core is in device 1817 * mode. 1818 */ 1819 break; 1820 } 1821 1822 switch (wvalue) { 1823 case USB_PORT_FEAT_SUSPEND: 1824 dev_dbg(hsotg->dev, 1825 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1826 if (windex != hsotg->otg_port) 1827 goto error; 1828 dwc2_port_suspend(hsotg, windex); 1829 break; 1830 1831 case USB_PORT_FEAT_POWER: 1832 dev_dbg(hsotg->dev, 1833 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1834 hprt0 = dwc2_read_hprt0(hsotg); 1835 hprt0 |= HPRT0_PWR; 1836 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1837 break; 1838 1839 case USB_PORT_FEAT_RESET: 1840 hprt0 = dwc2_read_hprt0(hsotg); 1841 dev_dbg(hsotg->dev, 1842 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1843 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1844 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1845 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1846 /* ??? Original driver does this */ 1847 dwc2_writel(0, hsotg->regs + PCGCTL); 1848 1849 hprt0 = dwc2_read_hprt0(hsotg); 1850 /* Clear suspend bit if resetting from suspend state */ 1851 hprt0 &= ~HPRT0_SUSP; 1852 1853 /* 1854 * When B-Host the Port reset bit is set in the Start 1855 * HCD Callback function, so that the reset is started 1856 * within 1ms of the HNP success interrupt 1857 */ 1858 if (!dwc2_hcd_is_b_host(hsotg)) { 1859 hprt0 |= HPRT0_PWR | HPRT0_RST; 1860 dev_dbg(hsotg->dev, 1861 "In host mode, hprt0=%08x\n", hprt0); 1862 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1863 } 1864 1865 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1866 usleep_range(50000, 70000); 1867 hprt0 &= ~HPRT0_RST; 1868 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1869 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1870 break; 1871 1872 case USB_PORT_FEAT_INDICATOR: 1873 dev_dbg(hsotg->dev, 1874 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1875 /* Not supported */ 1876 break; 1877 1878 case USB_PORT_FEAT_TEST: 1879 hprt0 = dwc2_read_hprt0(hsotg); 1880 dev_dbg(hsotg->dev, 1881 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1882 hprt0 &= ~HPRT0_TSTCTL_MASK; 1883 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1884 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1885 break; 1886 1887 default: 1888 retval = -EINVAL; 1889 dev_err(hsotg->dev, 1890 "SetPortFeature %1xh unknown or unsupported\n", 1891 wvalue); 1892 break; 1893 } 1894 break; 1895 1896 default: 1897 error: 1898 retval = -EINVAL; 1899 dev_dbg(hsotg->dev, 1900 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1901 typereq, windex, wvalue); 1902 break; 1903 } 1904 1905 return retval; 1906 } 1907 1908 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1909 { 1910 int retval; 1911 1912 if (port != 1) 1913 return -EINVAL; 1914 1915 retval = (hsotg->flags.b.port_connect_status_change || 1916 hsotg->flags.b.port_reset_change || 1917 hsotg->flags.b.port_enable_change || 1918 hsotg->flags.b.port_suspend_change || 1919 hsotg->flags.b.port_over_current_change); 1920 1921 if (retval) { 1922 dev_dbg(hsotg->dev, 1923 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1924 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1925 hsotg->flags.b.port_connect_status_change); 1926 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1927 hsotg->flags.b.port_reset_change); 1928 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1929 hsotg->flags.b.port_enable_change); 1930 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1931 hsotg->flags.b.port_suspend_change); 1932 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1933 hsotg->flags.b.port_over_current_change); 1934 } 1935 1936 return retval; 1937 } 1938 1939 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1940 { 1941 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1942 1943 #ifdef DWC2_DEBUG_SOF 1944 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1945 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1946 #endif 1947 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1948 } 1949 1950 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 1951 { 1952 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 1953 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 1954 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1955 unsigned int us_per_frame; 1956 unsigned int frame_number; 1957 unsigned int remaining; 1958 unsigned int interval; 1959 unsigned int phy_clks; 1960 1961 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 1962 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 1963 1964 /* Extract fields */ 1965 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1966 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 1967 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 1968 1969 /* 1970 * Number of phy clocks since the last tick of the frame number after 1971 * "us" has passed. 1972 */ 1973 phy_clks = (interval - remaining) + 1974 DIV_ROUND_UP(interval * us, us_per_frame); 1975 1976 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 1977 } 1978 1979 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1980 { 1981 return hsotg->op_state == OTG_STATE_B_HOST; 1982 } 1983 1984 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1985 int iso_desc_count, 1986 gfp_t mem_flags) 1987 { 1988 struct dwc2_hcd_urb *urb; 1989 u32 size = sizeof(*urb) + iso_desc_count * 1990 sizeof(struct dwc2_hcd_iso_packet_desc); 1991 1992 urb = kzalloc(size, mem_flags); 1993 if (urb) 1994 urb->packet_count = iso_desc_count; 1995 return urb; 1996 } 1997 1998 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1999 struct dwc2_hcd_urb *urb, u8 dev_addr, 2000 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 2001 { 2002 if (dbg_perio() || 2003 ep_type == USB_ENDPOINT_XFER_BULK || 2004 ep_type == USB_ENDPOINT_XFER_CONTROL) 2005 dev_vdbg(hsotg->dev, 2006 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 2007 dev_addr, ep_num, ep_dir, ep_type, mps); 2008 urb->pipe_info.dev_addr = dev_addr; 2009 urb->pipe_info.ep_num = ep_num; 2010 urb->pipe_info.pipe_type = ep_type; 2011 urb->pipe_info.pipe_dir = ep_dir; 2012 urb->pipe_info.mps = mps; 2013 } 2014 2015 /* 2016 * NOTE: This function will be removed once the peripheral controller code 2017 * is integrated and the driver is stable 2018 */ 2019 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 2020 { 2021 #ifdef DEBUG 2022 struct dwc2_host_chan *chan; 2023 struct dwc2_hcd_urb *urb; 2024 struct dwc2_qtd *qtd; 2025 int num_channels; 2026 u32 np_tx_status; 2027 u32 p_tx_status; 2028 int i; 2029 2030 num_channels = hsotg->core_params->host_channels; 2031 dev_dbg(hsotg->dev, "\n"); 2032 dev_dbg(hsotg->dev, 2033 "************************************************************\n"); 2034 dev_dbg(hsotg->dev, "HCD State:\n"); 2035 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 2036 2037 for (i = 0; i < num_channels; i++) { 2038 chan = hsotg->hc_ptr_array[i]; 2039 dev_dbg(hsotg->dev, " Channel %d:\n", i); 2040 dev_dbg(hsotg->dev, 2041 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 2042 chan->dev_addr, chan->ep_num, chan->ep_is_in); 2043 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 2044 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 2045 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 2046 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 2047 chan->data_pid_start); 2048 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 2049 dev_dbg(hsotg->dev, " xfer_started: %d\n", 2050 chan->xfer_started); 2051 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 2052 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 2053 (unsigned long)chan->xfer_dma); 2054 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 2055 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 2056 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 2057 chan->halt_on_queue); 2058 dev_dbg(hsotg->dev, " halt_pending: %d\n", 2059 chan->halt_pending); 2060 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 2061 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 2062 dev_dbg(hsotg->dev, " complete_split: %d\n", 2063 chan->complete_split); 2064 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 2065 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 2066 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 2067 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 2068 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 2069 2070 if (chan->xfer_started) { 2071 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 2072 2073 hfnum = dwc2_readl(hsotg->regs + HFNUM); 2074 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2075 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 2076 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 2077 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 2078 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 2079 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 2080 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 2081 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 2082 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 2083 } 2084 2085 if (!(chan->xfer_started && chan->qh)) 2086 continue; 2087 2088 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2089 if (!qtd->in_process) 2090 break; 2091 urb = qtd->urb; 2092 dev_dbg(hsotg->dev, " URB Info:\n"); 2093 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2094 qtd, urb); 2095 if (urb) { 2096 dev_dbg(hsotg->dev, 2097 " Dev: %d, EP: %d %s\n", 2098 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2099 dwc2_hcd_get_ep_num(&urb->pipe_info), 2100 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2101 "IN" : "OUT"); 2102 dev_dbg(hsotg->dev, 2103 " Max packet size: %d\n", 2104 dwc2_hcd_get_mps(&urb->pipe_info)); 2105 dev_dbg(hsotg->dev, 2106 " transfer_buffer: %p\n", 2107 urb->buf); 2108 dev_dbg(hsotg->dev, 2109 " transfer_dma: %08lx\n", 2110 (unsigned long)urb->dma); 2111 dev_dbg(hsotg->dev, 2112 " transfer_buffer_length: %d\n", 2113 urb->length); 2114 dev_dbg(hsotg->dev, " actual_length: %d\n", 2115 urb->actual_length); 2116 } 2117 } 2118 } 2119 2120 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2121 hsotg->non_periodic_channels); 2122 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2123 hsotg->periodic_channels); 2124 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2125 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 2126 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2127 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2128 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2129 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2130 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2131 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2132 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2133 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2134 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2135 dwc2_hcd_dump_frrem(hsotg); 2136 dwc2_dump_global_registers(hsotg); 2137 dwc2_dump_host_registers(hsotg); 2138 dev_dbg(hsotg->dev, 2139 "************************************************************\n"); 2140 dev_dbg(hsotg->dev, "\n"); 2141 #endif 2142 } 2143 2144 /* 2145 * NOTE: This function will be removed once the peripheral controller code 2146 * is integrated and the driver is stable 2147 */ 2148 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2149 { 2150 #ifdef DWC2_DUMP_FRREM 2151 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2152 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2153 hsotg->frrem_samples, hsotg->frrem_accum, 2154 hsotg->frrem_samples > 0 ? 2155 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2156 dev_dbg(hsotg->dev, "\n"); 2157 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2158 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2159 hsotg->hfnum_7_samples, 2160 hsotg->hfnum_7_frrem_accum, 2161 hsotg->hfnum_7_samples > 0 ? 2162 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2163 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2164 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2165 hsotg->hfnum_0_samples, 2166 hsotg->hfnum_0_frrem_accum, 2167 hsotg->hfnum_0_samples > 0 ? 2168 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2169 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2170 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2171 hsotg->hfnum_other_samples, 2172 hsotg->hfnum_other_frrem_accum, 2173 hsotg->hfnum_other_samples > 0 ? 2174 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2175 0); 2176 dev_dbg(hsotg->dev, "\n"); 2177 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2178 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2179 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2180 hsotg->hfnum_7_samples_a > 0 ? 2181 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2182 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2183 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2184 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2185 hsotg->hfnum_0_samples_a > 0 ? 2186 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2187 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2188 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2189 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2190 hsotg->hfnum_other_samples_a > 0 ? 2191 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2192 : 0); 2193 dev_dbg(hsotg->dev, "\n"); 2194 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2195 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2196 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2197 hsotg->hfnum_7_samples_b > 0 ? 2198 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2199 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2200 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2201 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2202 (hsotg->hfnum_0_samples_b > 0) ? 2203 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2204 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2205 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2206 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2207 (hsotg->hfnum_other_samples_b > 0) ? 2208 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2209 : 0); 2210 #endif 2211 } 2212 2213 struct wrapper_priv_data { 2214 struct dwc2_hsotg *hsotg; 2215 }; 2216 2217 /* Gets the dwc2_hsotg from a usb_hcd */ 2218 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2219 { 2220 struct wrapper_priv_data *p; 2221 2222 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2223 return p->hsotg; 2224 } 2225 2226 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2227 2228 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2229 { 2230 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2231 2232 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2233 _dwc2_hcd_start(hcd); 2234 } 2235 2236 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2237 { 2238 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2239 2240 hcd->self.is_b_host = 0; 2241 } 2242 2243 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2244 int *hub_port) 2245 { 2246 struct urb *urb = context; 2247 2248 if (urb->dev->tt) 2249 *hub_addr = urb->dev->tt->hub->devnum; 2250 else 2251 *hub_addr = 0; 2252 *hub_port = urb->dev->ttport; 2253 } 2254 2255 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2256 { 2257 struct urb *urb = context; 2258 2259 return urb->dev->speed; 2260 } 2261 2262 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2263 struct urb *urb) 2264 { 2265 struct usb_bus *bus = hcd_to_bus(hcd); 2266 2267 if (urb->interval) 2268 bus->bandwidth_allocated += bw / urb->interval; 2269 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2270 bus->bandwidth_isoc_reqs++; 2271 else 2272 bus->bandwidth_int_reqs++; 2273 } 2274 2275 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2276 struct urb *urb) 2277 { 2278 struct usb_bus *bus = hcd_to_bus(hcd); 2279 2280 if (urb->interval) 2281 bus->bandwidth_allocated -= bw / urb->interval; 2282 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2283 bus->bandwidth_isoc_reqs--; 2284 else 2285 bus->bandwidth_int_reqs--; 2286 } 2287 2288 /* 2289 * Sets the final status of an URB and returns it to the upper layer. Any 2290 * required cleanup of the URB is performed. 2291 * 2292 * Must be called with interrupt disabled and spinlock held 2293 */ 2294 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2295 int status) 2296 { 2297 struct urb *urb; 2298 int i; 2299 2300 if (!qtd) { 2301 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2302 return; 2303 } 2304 2305 if (!qtd->urb) { 2306 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2307 return; 2308 } 2309 2310 urb = qtd->urb->priv; 2311 if (!urb) { 2312 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2313 return; 2314 } 2315 2316 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2317 2318 if (dbg_urb(urb)) 2319 dev_vdbg(hsotg->dev, 2320 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2321 __func__, urb, usb_pipedevice(urb->pipe), 2322 usb_pipeendpoint(urb->pipe), 2323 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2324 urb->actual_length); 2325 2326 2327 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2328 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2329 for (i = 0; i < urb->number_of_packets; ++i) { 2330 urb->iso_frame_desc[i].actual_length = 2331 dwc2_hcd_urb_get_iso_desc_actual_length( 2332 qtd->urb, i); 2333 urb->iso_frame_desc[i].status = 2334 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2335 } 2336 } 2337 2338 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2339 for (i = 0; i < urb->number_of_packets; i++) 2340 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2341 i, urb->iso_frame_desc[i].status); 2342 } 2343 2344 urb->status = status; 2345 if (!status) { 2346 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2347 urb->actual_length < urb->transfer_buffer_length) 2348 urb->status = -EREMOTEIO; 2349 } 2350 2351 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2352 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2353 struct usb_host_endpoint *ep = urb->ep; 2354 2355 if (ep) 2356 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2357 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2358 urb); 2359 } 2360 2361 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2362 urb->hcpriv = NULL; 2363 kfree(qtd->urb); 2364 qtd->urb = NULL; 2365 2366 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2367 } 2368 2369 /* 2370 * Work queue function for starting the HCD when A-Cable is connected 2371 */ 2372 static void dwc2_hcd_start_func(struct work_struct *work) 2373 { 2374 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2375 start_work.work); 2376 2377 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2378 dwc2_host_start(hsotg); 2379 } 2380 2381 /* 2382 * Reset work queue function 2383 */ 2384 static void dwc2_hcd_reset_func(struct work_struct *work) 2385 { 2386 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2387 reset_work.work); 2388 unsigned long flags; 2389 u32 hprt0; 2390 2391 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2392 2393 spin_lock_irqsave(&hsotg->lock, flags); 2394 2395 hprt0 = dwc2_read_hprt0(hsotg); 2396 hprt0 &= ~HPRT0_RST; 2397 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2398 hsotg->flags.b.port_reset_change = 1; 2399 2400 spin_unlock_irqrestore(&hsotg->lock, flags); 2401 } 2402 2403 /* 2404 * ========================================================================= 2405 * Linux HC Driver Functions 2406 * ========================================================================= 2407 */ 2408 2409 /* 2410 * Initializes the DWC_otg controller and its root hub and prepares it for host 2411 * mode operation. Activates the root port. Returns 0 on success and a negative 2412 * error code on failure. 2413 */ 2414 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2415 { 2416 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2417 struct usb_bus *bus = hcd_to_bus(hcd); 2418 unsigned long flags; 2419 2420 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2421 2422 spin_lock_irqsave(&hsotg->lock, flags); 2423 hsotg->lx_state = DWC2_L0; 2424 hcd->state = HC_STATE_RUNNING; 2425 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2426 2427 if (dwc2_is_device_mode(hsotg)) { 2428 spin_unlock_irqrestore(&hsotg->lock, flags); 2429 return 0; /* why 0 ?? */ 2430 } 2431 2432 dwc2_hcd_reinit(hsotg); 2433 2434 /* Initialize and connect root hub if one is not already attached */ 2435 if (bus->root_hub) { 2436 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2437 /* Inform the HUB driver to resume */ 2438 usb_hcd_resume_root_hub(hcd); 2439 } 2440 2441 spin_unlock_irqrestore(&hsotg->lock, flags); 2442 return 0; 2443 } 2444 2445 /* 2446 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2447 * stopped. 2448 */ 2449 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2450 { 2451 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2452 unsigned long flags; 2453 2454 /* Turn off all host-specific interrupts */ 2455 dwc2_disable_host_interrupts(hsotg); 2456 2457 /* Wait for interrupt processing to finish */ 2458 synchronize_irq(hcd->irq); 2459 2460 spin_lock_irqsave(&hsotg->lock, flags); 2461 /* Ensure hcd is disconnected */ 2462 dwc2_hcd_disconnect(hsotg, true); 2463 dwc2_hcd_stop(hsotg); 2464 hsotg->lx_state = DWC2_L3; 2465 hcd->state = HC_STATE_HALT; 2466 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2467 spin_unlock_irqrestore(&hsotg->lock, flags); 2468 2469 usleep_range(1000, 3000); 2470 } 2471 2472 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2473 { 2474 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2475 unsigned long flags; 2476 int ret = 0; 2477 u32 hprt0; 2478 2479 spin_lock_irqsave(&hsotg->lock, flags); 2480 2481 if (hsotg->lx_state != DWC2_L0) 2482 goto unlock; 2483 2484 if (!HCD_HW_ACCESSIBLE(hcd)) 2485 goto unlock; 2486 2487 if (!hsotg->core_params->hibernation) 2488 goto skip_power_saving; 2489 2490 /* 2491 * Drive USB suspend and disable port Power 2492 * if usb bus is not suspended. 2493 */ 2494 if (!hsotg->bus_suspended) { 2495 hprt0 = dwc2_read_hprt0(hsotg); 2496 hprt0 |= HPRT0_SUSP; 2497 hprt0 &= ~HPRT0_PWR; 2498 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2499 } 2500 2501 /* Enter hibernation */ 2502 ret = dwc2_enter_hibernation(hsotg); 2503 if (ret) { 2504 if (ret != -ENOTSUPP) 2505 dev_err(hsotg->dev, 2506 "enter hibernation failed\n"); 2507 goto skip_power_saving; 2508 } 2509 2510 /* Ask phy to be suspended */ 2511 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2512 spin_unlock_irqrestore(&hsotg->lock, flags); 2513 usb_phy_set_suspend(hsotg->uphy, true); 2514 spin_lock_irqsave(&hsotg->lock, flags); 2515 } 2516 2517 /* After entering hibernation, hardware is no more accessible */ 2518 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2519 2520 skip_power_saving: 2521 hsotg->lx_state = DWC2_L2; 2522 unlock: 2523 spin_unlock_irqrestore(&hsotg->lock, flags); 2524 2525 return ret; 2526 } 2527 2528 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2529 { 2530 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2531 unsigned long flags; 2532 int ret = 0; 2533 2534 spin_lock_irqsave(&hsotg->lock, flags); 2535 2536 if (hsotg->lx_state != DWC2_L2) 2537 goto unlock; 2538 2539 if (!hsotg->core_params->hibernation) { 2540 hsotg->lx_state = DWC2_L0; 2541 goto unlock; 2542 } 2543 2544 /* 2545 * Set HW accessible bit before powering on the controller 2546 * since an interrupt may rise. 2547 */ 2548 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2549 2550 /* 2551 * Enable power if not already done. 2552 * This must not be spinlocked since duration 2553 * of this call is unknown. 2554 */ 2555 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2556 spin_unlock_irqrestore(&hsotg->lock, flags); 2557 usb_phy_set_suspend(hsotg->uphy, false); 2558 spin_lock_irqsave(&hsotg->lock, flags); 2559 } 2560 2561 /* Exit hibernation */ 2562 ret = dwc2_exit_hibernation(hsotg, true); 2563 if (ret && (ret != -ENOTSUPP)) 2564 dev_err(hsotg->dev, "exit hibernation failed\n"); 2565 2566 hsotg->lx_state = DWC2_L0; 2567 2568 spin_unlock_irqrestore(&hsotg->lock, flags); 2569 2570 if (hsotg->bus_suspended) { 2571 spin_lock_irqsave(&hsotg->lock, flags); 2572 hsotg->flags.b.port_suspend_change = 1; 2573 spin_unlock_irqrestore(&hsotg->lock, flags); 2574 dwc2_port_resume(hsotg); 2575 } else { 2576 /* Wait for controller to correctly update D+/D- level */ 2577 usleep_range(3000, 5000); 2578 2579 /* 2580 * Clear Port Enable and Port Status changes. 2581 * Enable Port Power. 2582 */ 2583 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 2584 HPRT0_ENACHG, hsotg->regs + HPRT0); 2585 /* Wait for controller to detect Port Connect */ 2586 usleep_range(5000, 7000); 2587 } 2588 2589 return ret; 2590 unlock: 2591 spin_unlock_irqrestore(&hsotg->lock, flags); 2592 2593 return ret; 2594 } 2595 2596 /* Returns the current frame number */ 2597 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2598 { 2599 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2600 2601 return dwc2_hcd_get_frame_number(hsotg); 2602 } 2603 2604 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2605 char *fn_name) 2606 { 2607 #ifdef VERBOSE_DEBUG 2608 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2609 char *pipetype; 2610 char *speed; 2611 2612 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2613 dev_vdbg(hsotg->dev, " Device address: %d\n", 2614 usb_pipedevice(urb->pipe)); 2615 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2616 usb_pipeendpoint(urb->pipe), 2617 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2618 2619 switch (usb_pipetype(urb->pipe)) { 2620 case PIPE_CONTROL: 2621 pipetype = "CONTROL"; 2622 break; 2623 case PIPE_BULK: 2624 pipetype = "BULK"; 2625 break; 2626 case PIPE_INTERRUPT: 2627 pipetype = "INTERRUPT"; 2628 break; 2629 case PIPE_ISOCHRONOUS: 2630 pipetype = "ISOCHRONOUS"; 2631 break; 2632 default: 2633 pipetype = "UNKNOWN"; 2634 break; 2635 } 2636 2637 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2638 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2639 "IN" : "OUT"); 2640 2641 switch (urb->dev->speed) { 2642 case USB_SPEED_HIGH: 2643 speed = "HIGH"; 2644 break; 2645 case USB_SPEED_FULL: 2646 speed = "FULL"; 2647 break; 2648 case USB_SPEED_LOW: 2649 speed = "LOW"; 2650 break; 2651 default: 2652 speed = "UNKNOWN"; 2653 break; 2654 } 2655 2656 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2657 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2658 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2659 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2660 urb->transfer_buffer_length); 2661 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2662 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2663 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2664 urb->setup_packet, (unsigned long)urb->setup_dma); 2665 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2666 2667 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2668 int i; 2669 2670 for (i = 0; i < urb->number_of_packets; i++) { 2671 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2672 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2673 urb->iso_frame_desc[i].offset, 2674 urb->iso_frame_desc[i].length); 2675 } 2676 } 2677 #endif 2678 } 2679 2680 /* 2681 * Starts processing a USB transfer request specified by a USB Request Block 2682 * (URB). mem_flags indicates the type of memory allocation to use while 2683 * processing this URB. 2684 */ 2685 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2686 gfp_t mem_flags) 2687 { 2688 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2689 struct usb_host_endpoint *ep = urb->ep; 2690 struct dwc2_hcd_urb *dwc2_urb; 2691 int i; 2692 int retval; 2693 int alloc_bandwidth = 0; 2694 u8 ep_type = 0; 2695 u32 tflags = 0; 2696 void *buf; 2697 unsigned long flags; 2698 struct dwc2_qh *qh; 2699 bool qh_allocated = false; 2700 struct dwc2_qtd *qtd; 2701 2702 if (dbg_urb(urb)) { 2703 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2704 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2705 } 2706 2707 if (ep == NULL) 2708 return -EINVAL; 2709 2710 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2711 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2712 spin_lock_irqsave(&hsotg->lock, flags); 2713 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2714 alloc_bandwidth = 1; 2715 spin_unlock_irqrestore(&hsotg->lock, flags); 2716 } 2717 2718 switch (usb_pipetype(urb->pipe)) { 2719 case PIPE_CONTROL: 2720 ep_type = USB_ENDPOINT_XFER_CONTROL; 2721 break; 2722 case PIPE_ISOCHRONOUS: 2723 ep_type = USB_ENDPOINT_XFER_ISOC; 2724 break; 2725 case PIPE_BULK: 2726 ep_type = USB_ENDPOINT_XFER_BULK; 2727 break; 2728 case PIPE_INTERRUPT: 2729 ep_type = USB_ENDPOINT_XFER_INT; 2730 break; 2731 default: 2732 dev_warn(hsotg->dev, "Wrong ep type\n"); 2733 } 2734 2735 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2736 mem_flags); 2737 if (!dwc2_urb) 2738 return -ENOMEM; 2739 2740 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2741 usb_pipeendpoint(urb->pipe), ep_type, 2742 usb_pipein(urb->pipe), 2743 usb_maxpacket(urb->dev, urb->pipe, 2744 !(usb_pipein(urb->pipe)))); 2745 2746 buf = urb->transfer_buffer; 2747 2748 if (hcd->self.uses_dma) { 2749 if (!buf && (urb->transfer_dma & 3)) { 2750 dev_err(hsotg->dev, 2751 "%s: unaligned transfer with no transfer_buffer", 2752 __func__); 2753 retval = -EINVAL; 2754 goto fail0; 2755 } 2756 } 2757 2758 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2759 tflags |= URB_GIVEBACK_ASAP; 2760 if (urb->transfer_flags & URB_ZERO_PACKET) 2761 tflags |= URB_SEND_ZERO_PACKET; 2762 2763 dwc2_urb->priv = urb; 2764 dwc2_urb->buf = buf; 2765 dwc2_urb->dma = urb->transfer_dma; 2766 dwc2_urb->length = urb->transfer_buffer_length; 2767 dwc2_urb->setup_packet = urb->setup_packet; 2768 dwc2_urb->setup_dma = urb->setup_dma; 2769 dwc2_urb->flags = tflags; 2770 dwc2_urb->interval = urb->interval; 2771 dwc2_urb->status = -EINPROGRESS; 2772 2773 for (i = 0; i < urb->number_of_packets; ++i) 2774 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2775 urb->iso_frame_desc[i].offset, 2776 urb->iso_frame_desc[i].length); 2777 2778 urb->hcpriv = dwc2_urb; 2779 qh = (struct dwc2_qh *) ep->hcpriv; 2780 /* Create QH for the endpoint if it doesn't exist */ 2781 if (!qh) { 2782 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2783 if (!qh) { 2784 retval = -ENOMEM; 2785 goto fail0; 2786 } 2787 ep->hcpriv = qh; 2788 qh_allocated = true; 2789 } 2790 2791 qtd = kzalloc(sizeof(*qtd), mem_flags); 2792 if (!qtd) { 2793 retval = -ENOMEM; 2794 goto fail1; 2795 } 2796 2797 spin_lock_irqsave(&hsotg->lock, flags); 2798 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2799 if (retval) 2800 goto fail2; 2801 2802 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2803 if (retval) 2804 goto fail3; 2805 2806 if (alloc_bandwidth) { 2807 dwc2_allocate_bus_bandwidth(hcd, 2808 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2809 urb); 2810 } 2811 2812 spin_unlock_irqrestore(&hsotg->lock, flags); 2813 2814 return 0; 2815 2816 fail3: 2817 dwc2_urb->priv = NULL; 2818 usb_hcd_unlink_urb_from_ep(hcd, urb); 2819 if (qh_allocated && qh->channel && qh->channel->qh == qh) 2820 qh->channel->qh = NULL; 2821 fail2: 2822 spin_unlock_irqrestore(&hsotg->lock, flags); 2823 urb->hcpriv = NULL; 2824 kfree(qtd); 2825 fail1: 2826 if (qh_allocated) { 2827 struct dwc2_qtd *qtd2, *qtd2_tmp; 2828 2829 ep->hcpriv = NULL; 2830 dwc2_hcd_qh_unlink(hsotg, qh); 2831 /* Free each QTD in the QH's QTD list */ 2832 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2833 qtd_list_entry) 2834 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2835 dwc2_hcd_qh_free(hsotg, qh); 2836 } 2837 fail0: 2838 kfree(dwc2_urb); 2839 2840 return retval; 2841 } 2842 2843 /* 2844 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2845 */ 2846 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2847 int status) 2848 { 2849 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2850 int rc; 2851 unsigned long flags; 2852 2853 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2854 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2855 2856 spin_lock_irqsave(&hsotg->lock, flags); 2857 2858 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2859 if (rc) 2860 goto out; 2861 2862 if (!urb->hcpriv) { 2863 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2864 goto out; 2865 } 2866 2867 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2868 2869 usb_hcd_unlink_urb_from_ep(hcd, urb); 2870 2871 kfree(urb->hcpriv); 2872 urb->hcpriv = NULL; 2873 2874 /* Higher layer software sets URB status */ 2875 spin_unlock(&hsotg->lock); 2876 usb_hcd_giveback_urb(hcd, urb, status); 2877 spin_lock(&hsotg->lock); 2878 2879 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2880 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2881 out: 2882 spin_unlock_irqrestore(&hsotg->lock, flags); 2883 2884 return rc; 2885 } 2886 2887 /* 2888 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2889 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2890 * must already be dequeued. 2891 */ 2892 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2893 struct usb_host_endpoint *ep) 2894 { 2895 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2896 2897 dev_dbg(hsotg->dev, 2898 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2899 ep->desc.bEndpointAddress, ep->hcpriv); 2900 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2901 } 2902 2903 /* 2904 * Resets endpoint specific parameter values, in current version used to reset 2905 * the data toggle (as a WA). This function can be called from usb_clear_halt 2906 * routine. 2907 */ 2908 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2909 struct usb_host_endpoint *ep) 2910 { 2911 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2912 unsigned long flags; 2913 2914 dev_dbg(hsotg->dev, 2915 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2916 ep->desc.bEndpointAddress); 2917 2918 spin_lock_irqsave(&hsotg->lock, flags); 2919 dwc2_hcd_endpoint_reset(hsotg, ep); 2920 spin_unlock_irqrestore(&hsotg->lock, flags); 2921 } 2922 2923 /* 2924 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2925 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2926 * interrupt. 2927 * 2928 * This function is called by the USB core when an interrupt occurs 2929 */ 2930 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2931 { 2932 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2933 2934 return dwc2_handle_hcd_intr(hsotg); 2935 } 2936 2937 /* 2938 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2939 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2940 * is the status change indicator for the single root port. Returns 1 if either 2941 * change indicator is 1, otherwise returns 0. 2942 */ 2943 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2944 { 2945 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2946 2947 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2948 return buf[0] != 0; 2949 } 2950 2951 /* Handles hub class-specific requests */ 2952 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2953 u16 windex, char *buf, u16 wlength) 2954 { 2955 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2956 wvalue, windex, buf, wlength); 2957 return retval; 2958 } 2959 2960 /* Handles hub TT buffer clear completions */ 2961 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2962 struct usb_host_endpoint *ep) 2963 { 2964 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2965 struct dwc2_qh *qh; 2966 unsigned long flags; 2967 2968 qh = ep->hcpriv; 2969 if (!qh) 2970 return; 2971 2972 spin_lock_irqsave(&hsotg->lock, flags); 2973 qh->tt_buffer_dirty = 0; 2974 2975 if (hsotg->flags.b.port_connect_status) 2976 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2977 2978 spin_unlock_irqrestore(&hsotg->lock, flags); 2979 } 2980 2981 static struct hc_driver dwc2_hc_driver = { 2982 .description = "dwc2_hsotg", 2983 .product_desc = "DWC OTG Controller", 2984 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2985 2986 .irq = _dwc2_hcd_irq, 2987 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 2988 2989 .start = _dwc2_hcd_start, 2990 .stop = _dwc2_hcd_stop, 2991 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2992 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2993 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2994 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2995 .get_frame_number = _dwc2_hcd_get_frame_number, 2996 2997 .hub_status_data = _dwc2_hcd_hub_status_data, 2998 .hub_control = _dwc2_hcd_hub_control, 2999 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 3000 3001 .bus_suspend = _dwc2_hcd_suspend, 3002 .bus_resume = _dwc2_hcd_resume, 3003 3004 .map_urb_for_dma = dwc2_map_urb_for_dma, 3005 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 3006 }; 3007 3008 /* 3009 * Frees secondary storage associated with the dwc2_hsotg structure contained 3010 * in the struct usb_hcd field 3011 */ 3012 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 3013 { 3014 u32 ahbcfg; 3015 u32 dctl; 3016 int i; 3017 3018 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 3019 3020 /* Free memory for QH/QTD lists */ 3021 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 3022 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 3023 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 3024 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 3025 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 3026 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 3027 3028 /* Free memory for the host channels */ 3029 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 3030 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 3031 3032 if (chan != NULL) { 3033 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 3034 i, chan); 3035 hsotg->hc_ptr_array[i] = NULL; 3036 kfree(chan); 3037 } 3038 } 3039 3040 if (hsotg->core_params->dma_enable > 0) { 3041 if (hsotg->status_buf) { 3042 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 3043 hsotg->status_buf, 3044 hsotg->status_buf_dma); 3045 hsotg->status_buf = NULL; 3046 } 3047 } else { 3048 kfree(hsotg->status_buf); 3049 hsotg->status_buf = NULL; 3050 } 3051 3052 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 3053 3054 /* Disable all interrupts */ 3055 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 3056 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 3057 dwc2_writel(0, hsotg->regs + GINTMSK); 3058 3059 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 3060 dctl = dwc2_readl(hsotg->regs + DCTL); 3061 dctl |= DCTL_SFTDISCON; 3062 dwc2_writel(dctl, hsotg->regs + DCTL); 3063 } 3064 3065 if (hsotg->wq_otg) { 3066 if (!cancel_work_sync(&hsotg->wf_otg)) 3067 flush_workqueue(hsotg->wq_otg); 3068 destroy_workqueue(hsotg->wq_otg); 3069 } 3070 3071 del_timer(&hsotg->wkp_timer); 3072 } 3073 3074 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 3075 { 3076 /* Turn off all host-specific interrupts */ 3077 dwc2_disable_host_interrupts(hsotg); 3078 3079 dwc2_hcd_free(hsotg); 3080 } 3081 3082 /* 3083 * Initializes the HCD. This function allocates memory for and initializes the 3084 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 3085 * USB bus with the core and calls the hc_driver->start() function. It returns 3086 * a negative error on failure. 3087 */ 3088 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 3089 { 3090 struct usb_hcd *hcd; 3091 struct dwc2_host_chan *channel; 3092 u32 hcfg; 3093 int i, num_channels; 3094 int retval; 3095 3096 if (usb_disabled()) 3097 return -ENODEV; 3098 3099 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 3100 3101 retval = -ENOMEM; 3102 3103 hcfg = dwc2_readl(hsotg->regs + HCFG); 3104 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 3105 3106 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3107 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 3108 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3109 if (!hsotg->frame_num_array) 3110 goto error1; 3111 hsotg->last_frame_num_array = kzalloc( 3112 sizeof(*hsotg->last_frame_num_array) * 3113 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3114 if (!hsotg->last_frame_num_array) 3115 goto error1; 3116 #endif 3117 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 3118 3119 /* Check if the bus driver or platform code has setup a dma_mask */ 3120 if (hsotg->core_params->dma_enable > 0 && 3121 hsotg->dev->dma_mask == NULL) { 3122 dev_warn(hsotg->dev, 3123 "dma_mask not set, disabling DMA\n"); 3124 hsotg->core_params->dma_enable = 0; 3125 hsotg->core_params->dma_desc_enable = 0; 3126 } 3127 3128 /* Set device flags indicating whether the HCD supports DMA */ 3129 if (hsotg->core_params->dma_enable > 0) { 3130 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3131 dev_warn(hsotg->dev, "can't set DMA mask\n"); 3132 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3133 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 3134 } 3135 3136 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 3137 if (!hcd) 3138 goto error1; 3139 3140 if (hsotg->core_params->dma_enable <= 0) 3141 hcd->self.uses_dma = 0; 3142 3143 hcd->has_tt = 1; 3144 3145 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 3146 hsotg->priv = hcd; 3147 3148 /* 3149 * Disable the global interrupt until all the interrupt handlers are 3150 * installed 3151 */ 3152 dwc2_disable_global_interrupts(hsotg); 3153 3154 /* Initialize the DWC_otg core, and select the Phy type */ 3155 retval = dwc2_core_init(hsotg, true); 3156 if (retval) 3157 goto error2; 3158 3159 /* Create new workqueue and init work */ 3160 retval = -ENOMEM; 3161 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 3162 if (!hsotg->wq_otg) { 3163 dev_err(hsotg->dev, "Failed to create workqueue\n"); 3164 goto error2; 3165 } 3166 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 3167 3168 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 3169 (unsigned long)hsotg); 3170 3171 /* Initialize the non-periodic schedule */ 3172 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 3173 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 3174 3175 /* Initialize the periodic schedule */ 3176 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 3177 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 3178 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 3179 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 3180 3181 INIT_LIST_HEAD(&hsotg->split_order); 3182 3183 /* 3184 * Create a host channel descriptor for each host channel implemented 3185 * in the controller. Initialize the channel descriptor array. 3186 */ 3187 INIT_LIST_HEAD(&hsotg->free_hc_list); 3188 num_channels = hsotg->core_params->host_channels; 3189 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 3190 3191 for (i = 0; i < num_channels; i++) { 3192 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 3193 if (channel == NULL) 3194 goto error3; 3195 channel->hc_num = i; 3196 INIT_LIST_HEAD(&channel->split_order_list_entry); 3197 hsotg->hc_ptr_array[i] = channel; 3198 } 3199 3200 if (hsotg->core_params->uframe_sched > 0) 3201 dwc2_hcd_init_usecs(hsotg); 3202 3203 /* Initialize hsotg start work */ 3204 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 3205 3206 /* Initialize port reset work */ 3207 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 3208 3209 /* 3210 * Allocate space for storing data on status transactions. Normally no 3211 * data is sent, but this space acts as a bit bucket. This must be 3212 * done after usb_add_hcd since that function allocates the DMA buffer 3213 * pool. 3214 */ 3215 if (hsotg->core_params->dma_enable > 0) 3216 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 3217 DWC2_HCD_STATUS_BUF_SIZE, 3218 &hsotg->status_buf_dma, GFP_KERNEL); 3219 else 3220 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 3221 GFP_KERNEL); 3222 3223 if (!hsotg->status_buf) 3224 goto error3; 3225 3226 /* 3227 * Create kmem caches to handle descriptor buffers in descriptor 3228 * DMA mode. 3229 * Alignment must be set to 512 bytes. 3230 */ 3231 if (hsotg->core_params->dma_desc_enable || 3232 hsotg->core_params->dma_desc_fs_enable) { 3233 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 3234 sizeof(struct dwc2_hcd_dma_desc) * 3235 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 3236 NULL); 3237 if (!hsotg->desc_gen_cache) { 3238 dev_err(hsotg->dev, 3239 "unable to create dwc2 generic desc cache\n"); 3240 3241 /* 3242 * Disable descriptor dma mode since it will not be 3243 * usable. 3244 */ 3245 hsotg->core_params->dma_desc_enable = 0; 3246 hsotg->core_params->dma_desc_fs_enable = 0; 3247 } 3248 3249 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 3250 sizeof(struct dwc2_hcd_dma_desc) * 3251 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 3252 if (!hsotg->desc_hsisoc_cache) { 3253 dev_err(hsotg->dev, 3254 "unable to create dwc2 hs isoc desc cache\n"); 3255 3256 kmem_cache_destroy(hsotg->desc_gen_cache); 3257 3258 /* 3259 * Disable descriptor dma mode since it will not be 3260 * usable. 3261 */ 3262 hsotg->core_params->dma_desc_enable = 0; 3263 hsotg->core_params->dma_desc_fs_enable = 0; 3264 } 3265 } 3266 3267 hsotg->otg_port = 1; 3268 hsotg->frame_list = NULL; 3269 hsotg->frame_list_dma = 0; 3270 hsotg->periodic_qh_count = 0; 3271 3272 /* Initiate lx_state to L3 disconnected state */ 3273 hsotg->lx_state = DWC2_L3; 3274 3275 hcd->self.otg_port = hsotg->otg_port; 3276 3277 /* Don't support SG list at this point */ 3278 hcd->self.sg_tablesize = 0; 3279 3280 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3281 otg_set_host(hsotg->uphy->otg, &hcd->self); 3282 3283 /* 3284 * Finish generic HCD initialization and start the HCD. This function 3285 * allocates the DMA buffer pool, registers the USB bus, requests the 3286 * IRQ line, and calls hcd_start method. 3287 */ 3288 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3289 if (retval < 0) 3290 goto error4; 3291 3292 device_wakeup_enable(hcd->self.controller); 3293 3294 dwc2_hcd_dump_state(hsotg); 3295 3296 dwc2_enable_global_interrupts(hsotg); 3297 3298 return 0; 3299 3300 error4: 3301 kmem_cache_destroy(hsotg->desc_gen_cache); 3302 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 3303 error3: 3304 dwc2_hcd_release(hsotg); 3305 error2: 3306 usb_put_hcd(hcd); 3307 error1: 3308 kfree(hsotg->core_params); 3309 3310 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3311 kfree(hsotg->last_frame_num_array); 3312 kfree(hsotg->frame_num_array); 3313 #endif 3314 3315 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3316 return retval; 3317 } 3318 3319 /* 3320 * Removes the HCD. 3321 * Frees memory and resources associated with the HCD and deregisters the bus. 3322 */ 3323 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3324 { 3325 struct usb_hcd *hcd; 3326 3327 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3328 3329 hcd = dwc2_hsotg_to_hcd(hsotg); 3330 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3331 3332 if (!hcd) { 3333 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3334 __func__); 3335 return; 3336 } 3337 3338 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3339 otg_set_host(hsotg->uphy->otg, NULL); 3340 3341 usb_remove_hcd(hcd); 3342 hsotg->priv = NULL; 3343 3344 kmem_cache_destroy(hsotg->desc_gen_cache); 3345 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 3346 3347 dwc2_hcd_release(hsotg); 3348 usb_put_hcd(hcd); 3349 3350 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3351 kfree(hsotg->last_frame_num_array); 3352 kfree(hsotg->frame_num_array); 3353 #endif 3354 } 3355