1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /* 58 * ========================================================================= 59 * Host Core Layer Functions 60 * ========================================================================= 61 */ 62 63 /** 64 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 65 * used in both device and host modes 66 * 67 * @hsotg: Programming view of the DWC_otg controller 68 */ 69 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 70 { 71 u32 intmsk; 72 73 /* Clear any pending OTG Interrupts */ 74 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 75 76 /* Clear any pending interrupts */ 77 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 78 79 /* Enable the interrupts in the GINTMSK */ 80 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 81 82 if (hsotg->core_params->dma_enable <= 0) 83 intmsk |= GINTSTS_RXFLVL; 84 if (hsotg->core_params->external_id_pin_ctl <= 0) 85 intmsk |= GINTSTS_CONIDSTSCHNG; 86 87 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 88 GINTSTS_SESSREQINT; 89 90 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 91 } 92 93 /* 94 * Initializes the FSLSPClkSel field of the HCFG register depending on the 95 * PHY type 96 */ 97 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 98 { 99 u32 hcfg, val; 100 101 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 102 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 103 hsotg->core_params->ulpi_fs_ls > 0) || 104 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 105 /* Full speed PHY */ 106 val = HCFG_FSLSPCLKSEL_48_MHZ; 107 } else { 108 /* High speed PHY running at full speed or high speed */ 109 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 110 } 111 112 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 113 hcfg = dwc2_readl(hsotg->regs + HCFG); 114 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 115 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 116 dwc2_writel(hcfg, hsotg->regs + HCFG); 117 } 118 119 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 120 { 121 u32 usbcfg, i2cctl; 122 int retval = 0; 123 124 /* 125 * core_init() is now called on every switch so only call the 126 * following for the first time through 127 */ 128 if (select_phy) { 129 dev_dbg(hsotg->dev, "FS PHY selected\n"); 130 131 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 132 if (!(usbcfg & GUSBCFG_PHYSEL)) { 133 usbcfg |= GUSBCFG_PHYSEL; 134 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 135 136 /* Reset after a PHY select */ 137 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 138 139 if (retval) { 140 dev_err(hsotg->dev, 141 "%s: Reset failed, aborting", __func__); 142 return retval; 143 } 144 } 145 } 146 147 /* 148 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 149 * do this on HNP Dev/Host mode switches (done in dev_init and 150 * host_init). 151 */ 152 if (dwc2_is_host_mode(hsotg)) 153 dwc2_init_fs_ls_pclk_sel(hsotg); 154 155 if (hsotg->core_params->i2c_enable > 0) { 156 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 157 158 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 159 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 160 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 161 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 162 163 /* Program GI2CCTL.I2CEn */ 164 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 165 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 166 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 167 i2cctl &= ~GI2CCTL_I2CEN; 168 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 169 i2cctl |= GI2CCTL_I2CEN; 170 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 171 } 172 173 return retval; 174 } 175 176 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 177 { 178 u32 usbcfg, usbcfg_old; 179 int retval = 0; 180 181 if (!select_phy) 182 return 0; 183 184 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 185 usbcfg_old = usbcfg; 186 187 /* 188 * HS PHY parameters. These parameters are preserved during soft reset 189 * so only program the first time. Do a soft reset immediately after 190 * setting phyif. 191 */ 192 switch (hsotg->core_params->phy_type) { 193 case DWC2_PHY_TYPE_PARAM_ULPI: 194 /* ULPI interface */ 195 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 196 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 197 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 198 if (hsotg->core_params->phy_ulpi_ddr > 0) 199 usbcfg |= GUSBCFG_DDRSEL; 200 break; 201 case DWC2_PHY_TYPE_PARAM_UTMI: 202 /* UTMI+ interface */ 203 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 204 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 205 if (hsotg->core_params->phy_utmi_width == 16) 206 usbcfg |= GUSBCFG_PHYIF16; 207 break; 208 default: 209 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 210 break; 211 } 212 213 if (usbcfg != usbcfg_old) { 214 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 215 216 /* Reset after setting the PHY parameters */ 217 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 218 if (retval) { 219 dev_err(hsotg->dev, 220 "%s: Reset failed, aborting", __func__); 221 return retval; 222 } 223 } 224 225 return retval; 226 } 227 228 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 229 { 230 u32 usbcfg; 231 int retval = 0; 232 233 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL && 234 hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) { 235 /* If FS mode with FS PHY */ 236 retval = dwc2_fs_phy_init(hsotg, select_phy); 237 if (retval) 238 return retval; 239 } else { 240 /* High speed PHY */ 241 retval = dwc2_hs_phy_init(hsotg, select_phy); 242 if (retval) 243 return retval; 244 } 245 246 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 247 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 248 hsotg->core_params->ulpi_fs_ls > 0) { 249 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 250 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 251 usbcfg |= GUSBCFG_ULPI_FS_LS; 252 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 253 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 254 } else { 255 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 256 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 257 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 258 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 259 } 260 261 return retval; 262 } 263 264 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 265 { 266 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 267 268 switch (hsotg->hw_params.arch) { 269 case GHWCFG2_EXT_DMA_ARCH: 270 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 271 return -EINVAL; 272 273 case GHWCFG2_INT_DMA_ARCH: 274 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 275 if (hsotg->core_params->ahbcfg != -1) { 276 ahbcfg &= GAHBCFG_CTRL_MASK; 277 ahbcfg |= hsotg->core_params->ahbcfg & 278 ~GAHBCFG_CTRL_MASK; 279 } 280 break; 281 282 case GHWCFG2_SLAVE_ONLY_ARCH: 283 default: 284 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 285 break; 286 } 287 288 dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n", 289 hsotg->core_params->dma_enable, 290 hsotg->core_params->dma_desc_enable); 291 292 if (hsotg->core_params->dma_enable > 0) { 293 if (hsotg->core_params->dma_desc_enable > 0) 294 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 295 else 296 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 297 } else { 298 dev_dbg(hsotg->dev, "Using Slave mode\n"); 299 hsotg->core_params->dma_desc_enable = 0; 300 } 301 302 if (hsotg->core_params->dma_enable > 0) 303 ahbcfg |= GAHBCFG_DMA_EN; 304 305 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 306 307 return 0; 308 } 309 310 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 311 { 312 u32 usbcfg; 313 314 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 315 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 316 317 switch (hsotg->hw_params.op_mode) { 318 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 319 if (hsotg->core_params->otg_cap == 320 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 321 usbcfg |= GUSBCFG_HNPCAP; 322 if (hsotg->core_params->otg_cap != 323 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 324 usbcfg |= GUSBCFG_SRPCAP; 325 break; 326 327 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 328 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 329 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 330 if (hsotg->core_params->otg_cap != 331 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 332 usbcfg |= GUSBCFG_SRPCAP; 333 break; 334 335 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 336 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 337 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 338 default: 339 break; 340 } 341 342 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 343 } 344 345 /** 346 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 347 * 348 * @hsotg: Programming view of DWC_otg controller 349 */ 350 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 351 { 352 u32 intmsk; 353 354 dev_dbg(hsotg->dev, "%s()\n", __func__); 355 356 /* Disable all interrupts */ 357 dwc2_writel(0, hsotg->regs + GINTMSK); 358 dwc2_writel(0, hsotg->regs + HAINTMSK); 359 360 /* Enable the common interrupts */ 361 dwc2_enable_common_interrupts(hsotg); 362 363 /* Enable host mode interrupts without disturbing common interrupts */ 364 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 365 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 366 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 367 } 368 369 /** 370 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 371 * 372 * @hsotg: Programming view of DWC_otg controller 373 */ 374 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 375 { 376 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 377 378 /* Disable host mode interrupts without disturbing common interrupts */ 379 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 380 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 381 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 382 } 383 384 /* 385 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 386 * For system that have a total fifo depth that is smaller than the default 387 * RX + TX fifo size. 388 * 389 * @hsotg: Programming view of DWC_otg controller 390 */ 391 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 392 { 393 struct dwc2_core_params *params = hsotg->core_params; 394 struct dwc2_hw_params *hw = &hsotg->hw_params; 395 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 396 397 total_fifo_size = hw->total_fifo_size; 398 rxfsiz = params->host_rx_fifo_size; 399 nptxfsiz = params->host_nperio_tx_fifo_size; 400 ptxfsiz = params->host_perio_tx_fifo_size; 401 402 /* 403 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 404 * allocation with support for high bandwidth endpoints. Synopsys 405 * defines MPS(Max Packet size) for a periodic EP=1024, and for 406 * non-periodic as 512. 407 */ 408 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 409 /* 410 * For Buffer DMA mode/Scatter Gather DMA mode 411 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 412 * with n = number of host channel. 413 * 2 * ((1024/4) + 2) = 516 414 */ 415 rxfsiz = 516 + hw->host_channels; 416 417 /* 418 * min non-periodic tx fifo depth 419 * 2 * (largest non-periodic USB packet used / 4) 420 * 2 * (512/4) = 256 421 */ 422 nptxfsiz = 256; 423 424 /* 425 * min periodic tx fifo depth 426 * (largest packet size*MC)/4 427 * (1024 * 3)/4 = 768 428 */ 429 ptxfsiz = 768; 430 431 params->host_rx_fifo_size = rxfsiz; 432 params->host_nperio_tx_fifo_size = nptxfsiz; 433 params->host_perio_tx_fifo_size = ptxfsiz; 434 } 435 436 /* 437 * If the summation of RX, NPTX and PTX fifo sizes is still 438 * bigger than the total_fifo_size, then we have a problem. 439 * 440 * We won't be able to allocate as many endpoints. Right now, 441 * we're just printing an error message, but ideally this FIFO 442 * allocation algorithm would be improved in the future. 443 * 444 * FIXME improve this FIFO allocation algorithm. 445 */ 446 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 447 dev_err(hsotg->dev, "invalid fifo sizes\n"); 448 } 449 450 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 451 { 452 struct dwc2_core_params *params = hsotg->core_params; 453 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 454 455 if (!params->enable_dynamic_fifo) 456 return; 457 458 dwc2_calculate_dynamic_fifo(hsotg); 459 460 /* Rx FIFO */ 461 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 462 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 463 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 464 grxfsiz |= params->host_rx_fifo_size << 465 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 466 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 467 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 468 dwc2_readl(hsotg->regs + GRXFSIZ)); 469 470 /* Non-periodic Tx FIFO */ 471 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 472 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 473 nptxfsiz = params->host_nperio_tx_fifo_size << 474 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 475 nptxfsiz |= params->host_rx_fifo_size << 476 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 477 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 478 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 479 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 480 481 /* Periodic Tx FIFO */ 482 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 483 dwc2_readl(hsotg->regs + HPTXFSIZ)); 484 hptxfsiz = params->host_perio_tx_fifo_size << 485 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 486 hptxfsiz |= (params->host_rx_fifo_size + 487 params->host_nperio_tx_fifo_size) << 488 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 489 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 490 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 491 dwc2_readl(hsotg->regs + HPTXFSIZ)); 492 493 if (hsotg->core_params->en_multiple_tx_fifo > 0 && 494 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 495 /* 496 * Global DFIFOCFG calculation for Host mode - 497 * include RxFIFO, NPTXFIFO and HPTXFIFO 498 */ 499 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 500 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 501 dfifocfg |= (params->host_rx_fifo_size + 502 params->host_nperio_tx_fifo_size + 503 params->host_perio_tx_fifo_size) << 504 GDFIFOCFG_EPINFOBASE_SHIFT & 505 GDFIFOCFG_EPINFOBASE_MASK; 506 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 507 } 508 } 509 510 /** 511 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 512 * the HFIR register according to PHY type and speed 513 * 514 * @hsotg: Programming view of DWC_otg controller 515 * 516 * NOTE: The caller can modify the value of the HFIR register only after the 517 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 518 * has been set 519 */ 520 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 521 { 522 u32 usbcfg; 523 u32 hprt0; 524 int clock = 60; /* default value */ 525 526 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 527 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 528 529 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 530 !(usbcfg & GUSBCFG_PHYIF16)) 531 clock = 60; 532 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 533 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 534 clock = 48; 535 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 536 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 537 clock = 30; 538 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 539 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 540 clock = 60; 541 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 542 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 543 clock = 48; 544 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 545 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 546 clock = 48; 547 if ((usbcfg & GUSBCFG_PHYSEL) && 548 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 549 clock = 48; 550 551 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 552 /* High speed case */ 553 return 125 * clock - 1; 554 555 /* FS/LS case */ 556 return 1000 * clock - 1; 557 } 558 559 /** 560 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 561 * buffer 562 * 563 * @core_if: Programming view of DWC_otg controller 564 * @dest: Destination buffer for the packet 565 * @bytes: Number of bytes to copy to the destination 566 */ 567 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 568 { 569 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 570 u32 *data_buf = (u32 *)dest; 571 int word_count = (bytes + 3) / 4; 572 int i; 573 574 /* 575 * Todo: Account for the case where dest is not dword aligned. This 576 * requires reading data from the FIFO into a u32 temp buffer, then 577 * moving it into the data buffer. 578 */ 579 580 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 581 582 for (i = 0; i < word_count; i++, data_buf++) 583 *data_buf = dwc2_readl(fifo); 584 } 585 586 /** 587 * dwc2_dump_channel_info() - Prints the state of a host channel 588 * 589 * @hsotg: Programming view of DWC_otg controller 590 * @chan: Pointer to the channel to dump 591 * 592 * Must be called with interrupt disabled and spinlock held 593 * 594 * NOTE: This function will be removed once the peripheral controller code 595 * is integrated and the driver is stable 596 */ 597 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 598 struct dwc2_host_chan *chan) 599 { 600 #ifdef VERBOSE_DEBUG 601 int num_channels = hsotg->core_params->host_channels; 602 struct dwc2_qh *qh; 603 u32 hcchar; 604 u32 hcsplt; 605 u32 hctsiz; 606 u32 hc_dma; 607 int i; 608 609 if (!chan) 610 return; 611 612 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 613 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 614 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 615 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 616 617 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 618 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 619 hcchar, hcsplt); 620 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 621 hctsiz, hc_dma); 622 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 623 chan->dev_addr, chan->ep_num, chan->ep_is_in); 624 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 625 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 626 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 627 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 628 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 629 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 630 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 631 (unsigned long)chan->xfer_dma); 632 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 633 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 634 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 635 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 636 qh_list_entry) 637 dev_dbg(hsotg->dev, " %p\n", qh); 638 dev_dbg(hsotg->dev, " NP active sched:\n"); 639 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 640 qh_list_entry) 641 dev_dbg(hsotg->dev, " %p\n", qh); 642 dev_dbg(hsotg->dev, " Channels:\n"); 643 for (i = 0; i < num_channels; i++) { 644 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 645 646 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 647 } 648 #endif /* VERBOSE_DEBUG */ 649 } 650 651 /* 652 * ========================================================================= 653 * Low Level Host Channel Access Functions 654 * ========================================================================= 655 */ 656 657 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 658 struct dwc2_host_chan *chan) 659 { 660 u32 hcintmsk = HCINTMSK_CHHLTD; 661 662 switch (chan->ep_type) { 663 case USB_ENDPOINT_XFER_CONTROL: 664 case USB_ENDPOINT_XFER_BULK: 665 dev_vdbg(hsotg->dev, "control/bulk\n"); 666 hcintmsk |= HCINTMSK_XFERCOMPL; 667 hcintmsk |= HCINTMSK_STALL; 668 hcintmsk |= HCINTMSK_XACTERR; 669 hcintmsk |= HCINTMSK_DATATGLERR; 670 if (chan->ep_is_in) { 671 hcintmsk |= HCINTMSK_BBLERR; 672 } else { 673 hcintmsk |= HCINTMSK_NAK; 674 hcintmsk |= HCINTMSK_NYET; 675 if (chan->do_ping) 676 hcintmsk |= HCINTMSK_ACK; 677 } 678 679 if (chan->do_split) { 680 hcintmsk |= HCINTMSK_NAK; 681 if (chan->complete_split) 682 hcintmsk |= HCINTMSK_NYET; 683 else 684 hcintmsk |= HCINTMSK_ACK; 685 } 686 687 if (chan->error_state) 688 hcintmsk |= HCINTMSK_ACK; 689 break; 690 691 case USB_ENDPOINT_XFER_INT: 692 if (dbg_perio()) 693 dev_vdbg(hsotg->dev, "intr\n"); 694 hcintmsk |= HCINTMSK_XFERCOMPL; 695 hcintmsk |= HCINTMSK_NAK; 696 hcintmsk |= HCINTMSK_STALL; 697 hcintmsk |= HCINTMSK_XACTERR; 698 hcintmsk |= HCINTMSK_DATATGLERR; 699 hcintmsk |= HCINTMSK_FRMOVRUN; 700 701 if (chan->ep_is_in) 702 hcintmsk |= HCINTMSK_BBLERR; 703 if (chan->error_state) 704 hcintmsk |= HCINTMSK_ACK; 705 if (chan->do_split) { 706 if (chan->complete_split) 707 hcintmsk |= HCINTMSK_NYET; 708 else 709 hcintmsk |= HCINTMSK_ACK; 710 } 711 break; 712 713 case USB_ENDPOINT_XFER_ISOC: 714 if (dbg_perio()) 715 dev_vdbg(hsotg->dev, "isoc\n"); 716 hcintmsk |= HCINTMSK_XFERCOMPL; 717 hcintmsk |= HCINTMSK_FRMOVRUN; 718 hcintmsk |= HCINTMSK_ACK; 719 720 if (chan->ep_is_in) { 721 hcintmsk |= HCINTMSK_XACTERR; 722 hcintmsk |= HCINTMSK_BBLERR; 723 } 724 break; 725 default: 726 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 727 break; 728 } 729 730 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 731 if (dbg_hc(chan)) 732 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 733 } 734 735 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 736 struct dwc2_host_chan *chan) 737 { 738 u32 hcintmsk = HCINTMSK_CHHLTD; 739 740 /* 741 * For Descriptor DMA mode core halts the channel on AHB error. 742 * Interrupt is not required. 743 */ 744 if (hsotg->core_params->dma_desc_enable <= 0) { 745 if (dbg_hc(chan)) 746 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 747 hcintmsk |= HCINTMSK_AHBERR; 748 } else { 749 if (dbg_hc(chan)) 750 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 751 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 752 hcintmsk |= HCINTMSK_XFERCOMPL; 753 } 754 755 if (chan->error_state && !chan->do_split && 756 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 757 if (dbg_hc(chan)) 758 dev_vdbg(hsotg->dev, "setting ACK\n"); 759 hcintmsk |= HCINTMSK_ACK; 760 if (chan->ep_is_in) { 761 hcintmsk |= HCINTMSK_DATATGLERR; 762 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 763 hcintmsk |= HCINTMSK_NAK; 764 } 765 } 766 767 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 768 if (dbg_hc(chan)) 769 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 770 } 771 772 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 773 struct dwc2_host_chan *chan) 774 { 775 u32 intmsk; 776 777 if (hsotg->core_params->dma_enable > 0) { 778 if (dbg_hc(chan)) 779 dev_vdbg(hsotg->dev, "DMA enabled\n"); 780 dwc2_hc_enable_dma_ints(hsotg, chan); 781 } else { 782 if (dbg_hc(chan)) 783 dev_vdbg(hsotg->dev, "DMA disabled\n"); 784 dwc2_hc_enable_slave_ints(hsotg, chan); 785 } 786 787 /* Enable the top level host channel interrupt */ 788 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 789 intmsk |= 1 << chan->hc_num; 790 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 791 if (dbg_hc(chan)) 792 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 793 794 /* Make sure host channel interrupts are enabled */ 795 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 796 intmsk |= GINTSTS_HCHINT; 797 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 798 if (dbg_hc(chan)) 799 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 800 } 801 802 /** 803 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 804 * a specific endpoint 805 * 806 * @hsotg: Programming view of DWC_otg controller 807 * @chan: Information needed to initialize the host channel 808 * 809 * The HCCHARn register is set up with the characteristics specified in chan. 810 * Host channel interrupts that may need to be serviced while this transfer is 811 * in progress are enabled. 812 */ 813 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 814 { 815 u8 hc_num = chan->hc_num; 816 u32 hcintmsk; 817 u32 hcchar; 818 u32 hcsplt = 0; 819 820 if (dbg_hc(chan)) 821 dev_vdbg(hsotg->dev, "%s()\n", __func__); 822 823 /* Clear old interrupt conditions for this host channel */ 824 hcintmsk = 0xffffffff; 825 hcintmsk &= ~HCINTMSK_RESERVED14_31; 826 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 827 828 /* Enable channel interrupts required for this transfer */ 829 dwc2_hc_enable_ints(hsotg, chan); 830 831 /* 832 * Program the HCCHARn register with the endpoint characteristics for 833 * the current transfer 834 */ 835 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 836 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 837 if (chan->ep_is_in) 838 hcchar |= HCCHAR_EPDIR; 839 if (chan->speed == USB_SPEED_LOW) 840 hcchar |= HCCHAR_LSPDDEV; 841 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 842 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 843 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 844 if (dbg_hc(chan)) { 845 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 846 hc_num, hcchar); 847 848 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 849 __func__, hc_num); 850 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 851 chan->dev_addr); 852 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 853 chan->ep_num); 854 dev_vdbg(hsotg->dev, " Is In: %d\n", 855 chan->ep_is_in); 856 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 857 chan->speed == USB_SPEED_LOW); 858 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 859 chan->ep_type); 860 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 861 chan->max_packet); 862 } 863 864 /* Program the HCSPLT register for SPLITs */ 865 if (chan->do_split) { 866 if (dbg_hc(chan)) 867 dev_vdbg(hsotg->dev, 868 "Programming HC %d with split --> %s\n", 869 hc_num, 870 chan->complete_split ? "CSPLIT" : "SSPLIT"); 871 if (chan->complete_split) 872 hcsplt |= HCSPLT_COMPSPLT; 873 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 874 HCSPLT_XACTPOS_MASK; 875 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 876 HCSPLT_HUBADDR_MASK; 877 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 878 HCSPLT_PRTADDR_MASK; 879 if (dbg_hc(chan)) { 880 dev_vdbg(hsotg->dev, " comp split %d\n", 881 chan->complete_split); 882 dev_vdbg(hsotg->dev, " xact pos %d\n", 883 chan->xact_pos); 884 dev_vdbg(hsotg->dev, " hub addr %d\n", 885 chan->hub_addr); 886 dev_vdbg(hsotg->dev, " hub port %d\n", 887 chan->hub_port); 888 dev_vdbg(hsotg->dev, " is_in %d\n", 889 chan->ep_is_in); 890 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 891 chan->max_packet); 892 dev_vdbg(hsotg->dev, " xferlen %d\n", 893 chan->xfer_len); 894 } 895 } 896 897 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 898 } 899 900 /** 901 * dwc2_hc_halt() - Attempts to halt a host channel 902 * 903 * @hsotg: Controller register interface 904 * @chan: Host channel to halt 905 * @halt_status: Reason for halting the channel 906 * 907 * This function should only be called in Slave mode or to abort a transfer in 908 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 909 * controller halts the channel when the transfer is complete or a condition 910 * occurs that requires application intervention. 911 * 912 * In slave mode, checks for a free request queue entry, then sets the Channel 913 * Enable and Channel Disable bits of the Host Channel Characteristics 914 * register of the specified channel to intiate the halt. If there is no free 915 * request queue entry, sets only the Channel Disable bit of the HCCHARn 916 * register to flush requests for this channel. In the latter case, sets a 917 * flag to indicate that the host channel needs to be halted when a request 918 * queue slot is open. 919 * 920 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 921 * HCCHARn register. The controller ensures there is space in the request 922 * queue before submitting the halt request. 923 * 924 * Some time may elapse before the core flushes any posted requests for this 925 * host channel and halts. The Channel Halted interrupt handler completes the 926 * deactivation of the host channel. 927 */ 928 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 929 enum dwc2_halt_status halt_status) 930 { 931 u32 nptxsts, hptxsts, hcchar; 932 933 if (dbg_hc(chan)) 934 dev_vdbg(hsotg->dev, "%s()\n", __func__); 935 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 936 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 937 938 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 939 halt_status == DWC2_HC_XFER_AHB_ERR) { 940 /* 941 * Disable all channel interrupts except Ch Halted. The QTD 942 * and QH state associated with this transfer has been cleared 943 * (in the case of URB_DEQUEUE), so the channel needs to be 944 * shut down carefully to prevent crashes. 945 */ 946 u32 hcintmsk = HCINTMSK_CHHLTD; 947 948 dev_vdbg(hsotg->dev, "dequeue/error\n"); 949 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 950 951 /* 952 * Make sure no other interrupts besides halt are currently 953 * pending. Handling another interrupt could cause a crash due 954 * to the QTD and QH state. 955 */ 956 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 957 958 /* 959 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 960 * even if the channel was already halted for some other 961 * reason 962 */ 963 chan->halt_status = halt_status; 964 965 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 966 if (!(hcchar & HCCHAR_CHENA)) { 967 /* 968 * The channel is either already halted or it hasn't 969 * started yet. In DMA mode, the transfer may halt if 970 * it finishes normally or a condition occurs that 971 * requires driver intervention. Don't want to halt 972 * the channel again. In either Slave or DMA mode, 973 * it's possible that the transfer has been assigned 974 * to a channel, but not started yet when an URB is 975 * dequeued. Don't want to halt a channel that hasn't 976 * started yet. 977 */ 978 return; 979 } 980 } 981 if (chan->halt_pending) { 982 /* 983 * A halt has already been issued for this channel. This might 984 * happen when a transfer is aborted by a higher level in 985 * the stack. 986 */ 987 dev_vdbg(hsotg->dev, 988 "*** %s: Channel %d, chan->halt_pending already set ***\n", 989 __func__, chan->hc_num); 990 return; 991 } 992 993 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 994 995 /* No need to set the bit in DDMA for disabling the channel */ 996 /* TODO check it everywhere channel is disabled */ 997 if (hsotg->core_params->dma_desc_enable <= 0) { 998 if (dbg_hc(chan)) 999 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1000 hcchar |= HCCHAR_CHENA; 1001 } else { 1002 if (dbg_hc(chan)) 1003 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1004 } 1005 hcchar |= HCCHAR_CHDIS; 1006 1007 if (hsotg->core_params->dma_enable <= 0) { 1008 if (dbg_hc(chan)) 1009 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1010 hcchar |= HCCHAR_CHENA; 1011 1012 /* Check for space in the request queue to issue the halt */ 1013 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1014 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1015 dev_vdbg(hsotg->dev, "control/bulk\n"); 1016 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1017 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1018 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1019 hcchar &= ~HCCHAR_CHENA; 1020 } 1021 } else { 1022 if (dbg_perio()) 1023 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1024 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1025 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1026 hsotg->queuing_high_bandwidth) { 1027 if (dbg_perio()) 1028 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1029 hcchar &= ~HCCHAR_CHENA; 1030 } 1031 } 1032 } else { 1033 if (dbg_hc(chan)) 1034 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1035 } 1036 1037 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1038 chan->halt_status = halt_status; 1039 1040 if (hcchar & HCCHAR_CHENA) { 1041 if (dbg_hc(chan)) 1042 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1043 chan->halt_pending = 1; 1044 chan->halt_on_queue = 0; 1045 } else { 1046 if (dbg_hc(chan)) 1047 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1048 chan->halt_on_queue = 1; 1049 } 1050 1051 if (dbg_hc(chan)) { 1052 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1053 chan->hc_num); 1054 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1055 hcchar); 1056 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1057 chan->halt_pending); 1058 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1059 chan->halt_on_queue); 1060 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1061 chan->halt_status); 1062 } 1063 } 1064 1065 /** 1066 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1067 * 1068 * @hsotg: Programming view of DWC_otg controller 1069 * @chan: Identifies the host channel to clean up 1070 * 1071 * This function is normally called after a transfer is done and the host 1072 * channel is being released 1073 */ 1074 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1075 { 1076 u32 hcintmsk; 1077 1078 chan->xfer_started = 0; 1079 1080 list_del_init(&chan->split_order_list_entry); 1081 1082 /* 1083 * Clear channel interrupt enables and any unhandled channel interrupt 1084 * conditions 1085 */ 1086 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1087 hcintmsk = 0xffffffff; 1088 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1089 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1090 } 1091 1092 /** 1093 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1094 * which frame a periodic transfer should occur 1095 * 1096 * @hsotg: Programming view of DWC_otg controller 1097 * @chan: Identifies the host channel to set up and its properties 1098 * @hcchar: Current value of the HCCHAR register for the specified host channel 1099 * 1100 * This function has no effect on non-periodic transfers 1101 */ 1102 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1103 struct dwc2_host_chan *chan, u32 *hcchar) 1104 { 1105 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1106 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1107 int host_speed; 1108 int xfer_ns; 1109 int xfer_us; 1110 int bytes_in_fifo; 1111 u16 fifo_space; 1112 u16 frame_number; 1113 u16 wire_frame; 1114 1115 /* 1116 * Try to figure out if we're an even or odd frame. If we set 1117 * even and the current frame number is even the the transfer 1118 * will happen immediately. Similar if both are odd. If one is 1119 * even and the other is odd then the transfer will happen when 1120 * the frame number ticks. 1121 * 1122 * There's a bit of a balancing act to get this right. 1123 * Sometimes we may want to send data in the current frame (AK 1124 * right away). We might want to do this if the frame number 1125 * _just_ ticked, but we might also want to do this in order 1126 * to continue a split transaction that happened late in a 1127 * microframe (so we didn't know to queue the next transfer 1128 * until the frame number had ticked). The problem is that we 1129 * need a lot of knowledge to know if there's actually still 1130 * time to send things or if it would be better to wait until 1131 * the next frame. 1132 * 1133 * We can look at how much time is left in the current frame 1134 * and make a guess about whether we'll have time to transfer. 1135 * We'll do that. 1136 */ 1137 1138 /* Get speed host is running at */ 1139 host_speed = (chan->speed != USB_SPEED_HIGH && 1140 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1141 1142 /* See how many bytes are in the periodic FIFO right now */ 1143 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1144 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1145 bytes_in_fifo = sizeof(u32) * 1146 (hsotg->core_params->host_perio_tx_fifo_size - 1147 fifo_space); 1148 1149 /* 1150 * Roughly estimate bus time for everything in the periodic 1151 * queue + our new transfer. This is "rough" because we're 1152 * using a function that makes takes into account IN/OUT 1153 * and INT/ISO and we're just slamming in one value for all 1154 * transfers. This should be an over-estimate and that should 1155 * be OK, but we can probably tighten it. 1156 */ 1157 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1158 chan->xfer_len + bytes_in_fifo); 1159 xfer_us = NS_TO_US(xfer_ns); 1160 1161 /* See what frame number we'll be at by the time we finish */ 1162 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1163 1164 /* This is when we were scheduled to be on the wire */ 1165 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1166 1167 /* 1168 * If we'd finish _after_ the frame we're scheduled in then 1169 * it's hopeless. Just schedule right away and hope for the 1170 * best. Note that it _might_ be wise to call back into the 1171 * scheduler to pick a better frame, but this is better than 1172 * nothing. 1173 */ 1174 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1175 dwc2_sch_vdbg(hsotg, 1176 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1177 chan->qh, wire_frame, frame_number, 1178 dwc2_frame_num_dec(frame_number, 1179 wire_frame)); 1180 wire_frame = frame_number; 1181 1182 /* 1183 * We picked a different frame number; communicate this 1184 * back to the scheduler so it doesn't try to schedule 1185 * another in the same frame. 1186 * 1187 * Remember that next_active_frame is 1 before the wire 1188 * frame. 1189 */ 1190 chan->qh->next_active_frame = 1191 dwc2_frame_num_dec(frame_number, 1); 1192 } 1193 1194 if (wire_frame & 1) 1195 *hcchar |= HCCHAR_ODDFRM; 1196 else 1197 *hcchar &= ~HCCHAR_ODDFRM; 1198 } 1199 } 1200 1201 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1202 { 1203 /* Set up the initial PID for the transfer */ 1204 if (chan->speed == USB_SPEED_HIGH) { 1205 if (chan->ep_is_in) { 1206 if (chan->multi_count == 1) 1207 chan->data_pid_start = DWC2_HC_PID_DATA0; 1208 else if (chan->multi_count == 2) 1209 chan->data_pid_start = DWC2_HC_PID_DATA1; 1210 else 1211 chan->data_pid_start = DWC2_HC_PID_DATA2; 1212 } else { 1213 if (chan->multi_count == 1) 1214 chan->data_pid_start = DWC2_HC_PID_DATA0; 1215 else 1216 chan->data_pid_start = DWC2_HC_PID_MDATA; 1217 } 1218 } else { 1219 chan->data_pid_start = DWC2_HC_PID_DATA0; 1220 } 1221 } 1222 1223 /** 1224 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1225 * the Host Channel 1226 * 1227 * @hsotg: Programming view of DWC_otg controller 1228 * @chan: Information needed to initialize the host channel 1229 * 1230 * This function should only be called in Slave mode. For a channel associated 1231 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1232 * associated with a periodic EP, the periodic Tx FIFO is written. 1233 * 1234 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1235 * the number of bytes written to the Tx FIFO. 1236 */ 1237 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1238 struct dwc2_host_chan *chan) 1239 { 1240 u32 i; 1241 u32 remaining_count; 1242 u32 byte_count; 1243 u32 dword_count; 1244 u32 __iomem *data_fifo; 1245 u32 *data_buf = (u32 *)chan->xfer_buf; 1246 1247 if (dbg_hc(chan)) 1248 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1249 1250 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1251 1252 remaining_count = chan->xfer_len - chan->xfer_count; 1253 if (remaining_count > chan->max_packet) 1254 byte_count = chan->max_packet; 1255 else 1256 byte_count = remaining_count; 1257 1258 dword_count = (byte_count + 3) / 4; 1259 1260 if (((unsigned long)data_buf & 0x3) == 0) { 1261 /* xfer_buf is DWORD aligned */ 1262 for (i = 0; i < dword_count; i++, data_buf++) 1263 dwc2_writel(*data_buf, data_fifo); 1264 } else { 1265 /* xfer_buf is not DWORD aligned */ 1266 for (i = 0; i < dword_count; i++, data_buf++) { 1267 u32 data = data_buf[0] | data_buf[1] << 8 | 1268 data_buf[2] << 16 | data_buf[3] << 24; 1269 dwc2_writel(data, data_fifo); 1270 } 1271 } 1272 1273 chan->xfer_count += byte_count; 1274 chan->xfer_buf += byte_count; 1275 } 1276 1277 /** 1278 * dwc2_hc_do_ping() - Starts a PING transfer 1279 * 1280 * @hsotg: Programming view of DWC_otg controller 1281 * @chan: Information needed to initialize the host channel 1282 * 1283 * This function should only be called in Slave mode. The Do Ping bit is set in 1284 * the HCTSIZ register, then the channel is enabled. 1285 */ 1286 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1287 struct dwc2_host_chan *chan) 1288 { 1289 u32 hcchar; 1290 u32 hctsiz; 1291 1292 if (dbg_hc(chan)) 1293 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1294 chan->hc_num); 1295 1296 hctsiz = TSIZ_DOPNG; 1297 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1298 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1299 1300 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1301 hcchar |= HCCHAR_CHENA; 1302 hcchar &= ~HCCHAR_CHDIS; 1303 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1304 } 1305 1306 /** 1307 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1308 * channel and starts the transfer 1309 * 1310 * @hsotg: Programming view of DWC_otg controller 1311 * @chan: Information needed to initialize the host channel. The xfer_len value 1312 * may be reduced to accommodate the max widths of the XferSize and 1313 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1314 * changed to reflect the final xfer_len value. 1315 * 1316 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1317 * the caller must ensure that there is sufficient space in the request queue 1318 * and Tx Data FIFO. 1319 * 1320 * For an OUT transfer in Slave mode, it loads a data packet into the 1321 * appropriate FIFO. If necessary, additional data packets are loaded in the 1322 * Host ISR. 1323 * 1324 * For an IN transfer in Slave mode, a data packet is requested. The data 1325 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1326 * additional data packets are requested in the Host ISR. 1327 * 1328 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1329 * register along with a packet count of 1 and the channel is enabled. This 1330 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1331 * simply set to 0 since no data transfer occurs in this case. 1332 * 1333 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1334 * all the information required to perform the subsequent data transfer. In 1335 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1336 * controller performs the entire PING protocol, then starts the data 1337 * transfer. 1338 */ 1339 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1340 struct dwc2_host_chan *chan) 1341 { 1342 u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size; 1343 u16 max_hc_pkt_count = hsotg->core_params->max_packet_count; 1344 u32 hcchar; 1345 u32 hctsiz = 0; 1346 u16 num_packets; 1347 u32 ec_mc; 1348 1349 if (dbg_hc(chan)) 1350 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1351 1352 if (chan->do_ping) { 1353 if (hsotg->core_params->dma_enable <= 0) { 1354 if (dbg_hc(chan)) 1355 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1356 dwc2_hc_do_ping(hsotg, chan); 1357 chan->xfer_started = 1; 1358 return; 1359 } 1360 1361 if (dbg_hc(chan)) 1362 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1363 1364 hctsiz |= TSIZ_DOPNG; 1365 } 1366 1367 if (chan->do_split) { 1368 if (dbg_hc(chan)) 1369 dev_vdbg(hsotg->dev, "split\n"); 1370 num_packets = 1; 1371 1372 if (chan->complete_split && !chan->ep_is_in) 1373 /* 1374 * For CSPLIT OUT Transfer, set the size to 0 so the 1375 * core doesn't expect any data written to the FIFO 1376 */ 1377 chan->xfer_len = 0; 1378 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1379 chan->xfer_len = chan->max_packet; 1380 else if (!chan->ep_is_in && chan->xfer_len > 188) 1381 chan->xfer_len = 188; 1382 1383 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1384 TSIZ_XFERSIZE_MASK; 1385 1386 /* For split set ec_mc for immediate retries */ 1387 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1388 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1389 ec_mc = 3; 1390 else 1391 ec_mc = 1; 1392 } else { 1393 if (dbg_hc(chan)) 1394 dev_vdbg(hsotg->dev, "no split\n"); 1395 /* 1396 * Ensure that the transfer length and packet count will fit 1397 * in the widths allocated for them in the HCTSIZn register 1398 */ 1399 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1400 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1401 /* 1402 * Make sure the transfer size is no larger than one 1403 * (micro)frame's worth of data. (A check was done 1404 * when the periodic transfer was accepted to ensure 1405 * that a (micro)frame's worth of data can be 1406 * programmed into a channel.) 1407 */ 1408 u32 max_periodic_len = 1409 chan->multi_count * chan->max_packet; 1410 1411 if (chan->xfer_len > max_periodic_len) 1412 chan->xfer_len = max_periodic_len; 1413 } else if (chan->xfer_len > max_hc_xfer_size) { 1414 /* 1415 * Make sure that xfer_len is a multiple of max packet 1416 * size 1417 */ 1418 chan->xfer_len = 1419 max_hc_xfer_size - chan->max_packet + 1; 1420 } 1421 1422 if (chan->xfer_len > 0) { 1423 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1424 chan->max_packet; 1425 if (num_packets > max_hc_pkt_count) { 1426 num_packets = max_hc_pkt_count; 1427 chan->xfer_len = num_packets * chan->max_packet; 1428 } 1429 } else { 1430 /* Need 1 packet for transfer length of 0 */ 1431 num_packets = 1; 1432 } 1433 1434 if (chan->ep_is_in) 1435 /* 1436 * Always program an integral # of max packets for IN 1437 * transfers 1438 */ 1439 chan->xfer_len = num_packets * chan->max_packet; 1440 1441 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1442 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1443 /* 1444 * Make sure that the multi_count field matches the 1445 * actual transfer length 1446 */ 1447 chan->multi_count = num_packets; 1448 1449 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1450 dwc2_set_pid_isoc(chan); 1451 1452 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1453 TSIZ_XFERSIZE_MASK; 1454 1455 /* The ec_mc gets the multi_count for non-split */ 1456 ec_mc = chan->multi_count; 1457 } 1458 1459 chan->start_pkt_count = num_packets; 1460 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1461 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1462 TSIZ_SC_MC_PID_MASK; 1463 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1464 if (dbg_hc(chan)) { 1465 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1466 hctsiz, chan->hc_num); 1467 1468 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1469 chan->hc_num); 1470 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1471 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1472 TSIZ_XFERSIZE_SHIFT); 1473 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1474 (hctsiz & TSIZ_PKTCNT_MASK) >> 1475 TSIZ_PKTCNT_SHIFT); 1476 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1477 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1478 TSIZ_SC_MC_PID_SHIFT); 1479 } 1480 1481 if (hsotg->core_params->dma_enable > 0) { 1482 dwc2_writel((u32)chan->xfer_dma, 1483 hsotg->regs + HCDMA(chan->hc_num)); 1484 if (dbg_hc(chan)) 1485 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1486 (unsigned long)chan->xfer_dma, chan->hc_num); 1487 } 1488 1489 /* Start the split */ 1490 if (chan->do_split) { 1491 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1492 1493 hcsplt |= HCSPLT_SPLTENA; 1494 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1495 } 1496 1497 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1498 hcchar &= ~HCCHAR_MULTICNT_MASK; 1499 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1500 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1501 1502 if (hcchar & HCCHAR_CHDIS) 1503 dev_warn(hsotg->dev, 1504 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1505 __func__, chan->hc_num, hcchar); 1506 1507 /* Set host channel enable after all other setup is complete */ 1508 hcchar |= HCCHAR_CHENA; 1509 hcchar &= ~HCCHAR_CHDIS; 1510 1511 if (dbg_hc(chan)) 1512 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1513 (hcchar & HCCHAR_MULTICNT_MASK) >> 1514 HCCHAR_MULTICNT_SHIFT); 1515 1516 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1517 if (dbg_hc(chan)) 1518 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1519 chan->hc_num); 1520 1521 chan->xfer_started = 1; 1522 chan->requests++; 1523 1524 if (hsotg->core_params->dma_enable <= 0 && 1525 !chan->ep_is_in && chan->xfer_len > 0) 1526 /* Load OUT packet into the appropriate Tx FIFO */ 1527 dwc2_hc_write_packet(hsotg, chan); 1528 } 1529 1530 /** 1531 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1532 * host channel and starts the transfer in Descriptor DMA mode 1533 * 1534 * @hsotg: Programming view of DWC_otg controller 1535 * @chan: Information needed to initialize the host channel 1536 * 1537 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1538 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1539 * with micro-frame bitmap. 1540 * 1541 * Initializes HCDMA register with descriptor list address and CTD value then 1542 * starts the transfer via enabling the channel. 1543 */ 1544 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1545 struct dwc2_host_chan *chan) 1546 { 1547 u32 hcchar; 1548 u32 hctsiz = 0; 1549 1550 if (chan->do_ping) 1551 hctsiz |= TSIZ_DOPNG; 1552 1553 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1554 dwc2_set_pid_isoc(chan); 1555 1556 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1557 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1558 TSIZ_SC_MC_PID_MASK; 1559 1560 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1561 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1562 1563 /* Non-zero only for high-speed interrupt endpoints */ 1564 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1565 1566 if (dbg_hc(chan)) { 1567 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1568 chan->hc_num); 1569 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1570 chan->data_pid_start); 1571 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1572 } 1573 1574 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1575 1576 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1577 chan->desc_list_sz, DMA_TO_DEVICE); 1578 1579 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1580 1581 if (dbg_hc(chan)) 1582 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1583 &chan->desc_list_addr, chan->hc_num); 1584 1585 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1586 hcchar &= ~HCCHAR_MULTICNT_MASK; 1587 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1588 HCCHAR_MULTICNT_MASK; 1589 1590 if (hcchar & HCCHAR_CHDIS) 1591 dev_warn(hsotg->dev, 1592 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1593 __func__, chan->hc_num, hcchar); 1594 1595 /* Set host channel enable after all other setup is complete */ 1596 hcchar |= HCCHAR_CHENA; 1597 hcchar &= ~HCCHAR_CHDIS; 1598 1599 if (dbg_hc(chan)) 1600 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1601 (hcchar & HCCHAR_MULTICNT_MASK) >> 1602 HCCHAR_MULTICNT_SHIFT); 1603 1604 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1605 if (dbg_hc(chan)) 1606 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1607 chan->hc_num); 1608 1609 chan->xfer_started = 1; 1610 chan->requests++; 1611 } 1612 1613 /** 1614 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1615 * a previous call to dwc2_hc_start_transfer() 1616 * 1617 * @hsotg: Programming view of DWC_otg controller 1618 * @chan: Information needed to initialize the host channel 1619 * 1620 * The caller must ensure there is sufficient space in the request queue and Tx 1621 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1622 * the controller acts autonomously to complete transfers programmed to a host 1623 * channel. 1624 * 1625 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1626 * if there is any data remaining to be queued. For an IN transfer, another 1627 * data packet is always requested. For the SETUP phase of a control transfer, 1628 * this function does nothing. 1629 * 1630 * Return: 1 if a new request is queued, 0 if no more requests are required 1631 * for this transfer 1632 */ 1633 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1634 struct dwc2_host_chan *chan) 1635 { 1636 if (dbg_hc(chan)) 1637 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1638 chan->hc_num); 1639 1640 if (chan->do_split) 1641 /* SPLITs always queue just once per channel */ 1642 return 0; 1643 1644 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1645 /* SETUPs are queued only once since they can't be NAK'd */ 1646 return 0; 1647 1648 if (chan->ep_is_in) { 1649 /* 1650 * Always queue another request for other IN transfers. If 1651 * back-to-back INs are issued and NAKs are received for both, 1652 * the driver may still be processing the first NAK when the 1653 * second NAK is received. When the interrupt handler clears 1654 * the NAK interrupt for the first NAK, the second NAK will 1655 * not be seen. So we can't depend on the NAK interrupt 1656 * handler to requeue a NAK'd request. Instead, IN requests 1657 * are issued each time this function is called. When the 1658 * transfer completes, the extra requests for the channel will 1659 * be flushed. 1660 */ 1661 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1662 1663 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1664 hcchar |= HCCHAR_CHENA; 1665 hcchar &= ~HCCHAR_CHDIS; 1666 if (dbg_hc(chan)) 1667 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1668 hcchar); 1669 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1670 chan->requests++; 1671 return 1; 1672 } 1673 1674 /* OUT transfers */ 1675 1676 if (chan->xfer_count < chan->xfer_len) { 1677 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1678 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1679 u32 hcchar = dwc2_readl(hsotg->regs + 1680 HCCHAR(chan->hc_num)); 1681 1682 dwc2_hc_set_even_odd_frame(hsotg, chan, 1683 &hcchar); 1684 } 1685 1686 /* Load OUT packet into the appropriate Tx FIFO */ 1687 dwc2_hc_write_packet(hsotg, chan); 1688 chan->requests++; 1689 return 1; 1690 } 1691 1692 return 0; 1693 } 1694 1695 /* 1696 * ========================================================================= 1697 * HCD 1698 * ========================================================================= 1699 */ 1700 1701 /* 1702 * Processes all the URBs in a single list of QHs. Completes them with 1703 * -ETIMEDOUT and frees the QTD. 1704 * 1705 * Must be called with interrupt disabled and spinlock held 1706 */ 1707 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1708 struct list_head *qh_list) 1709 { 1710 struct dwc2_qh *qh, *qh_tmp; 1711 struct dwc2_qtd *qtd, *qtd_tmp; 1712 1713 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1714 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1715 qtd_list_entry) { 1716 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1717 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1718 } 1719 } 1720 } 1721 1722 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1723 struct list_head *qh_list) 1724 { 1725 struct dwc2_qtd *qtd, *qtd_tmp; 1726 struct dwc2_qh *qh, *qh_tmp; 1727 unsigned long flags; 1728 1729 if (!qh_list->next) 1730 /* The list hasn't been initialized yet */ 1731 return; 1732 1733 spin_lock_irqsave(&hsotg->lock, flags); 1734 1735 /* Ensure there are no QTDs or URBs left */ 1736 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1737 1738 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1739 dwc2_hcd_qh_unlink(hsotg, qh); 1740 1741 /* Free each QTD in the QH's QTD list */ 1742 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1743 qtd_list_entry) 1744 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1745 1746 if (qh->channel && qh->channel->qh == qh) 1747 qh->channel->qh = NULL; 1748 1749 spin_unlock_irqrestore(&hsotg->lock, flags); 1750 dwc2_hcd_qh_free(hsotg, qh); 1751 spin_lock_irqsave(&hsotg->lock, flags); 1752 } 1753 1754 spin_unlock_irqrestore(&hsotg->lock, flags); 1755 } 1756 1757 /* 1758 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1759 * and periodic schedules. The QTD associated with each URB is removed from 1760 * the schedule and freed. This function may be called when a disconnect is 1761 * detected or when the HCD is being stopped. 1762 * 1763 * Must be called with interrupt disabled and spinlock held 1764 */ 1765 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1766 { 1767 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1768 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1769 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1770 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1771 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1772 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1773 } 1774 1775 /** 1776 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1777 * 1778 * @hsotg: Pointer to struct dwc2_hsotg 1779 */ 1780 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1781 { 1782 u32 hprt0; 1783 1784 if (hsotg->op_state == OTG_STATE_B_HOST) { 1785 /* 1786 * Reset the port. During a HNP mode switch the reset 1787 * needs to occur within 1ms and have a duration of at 1788 * least 50ms. 1789 */ 1790 hprt0 = dwc2_read_hprt0(hsotg); 1791 hprt0 |= HPRT0_RST; 1792 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1793 } 1794 1795 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1796 msecs_to_jiffies(50)); 1797 } 1798 1799 /* Must be called with interrupt disabled and spinlock held */ 1800 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1801 { 1802 int num_channels = hsotg->core_params->host_channels; 1803 struct dwc2_host_chan *channel; 1804 u32 hcchar; 1805 int i; 1806 1807 if (hsotg->core_params->dma_enable <= 0) { 1808 /* Flush out any channel requests in slave mode */ 1809 for (i = 0; i < num_channels; i++) { 1810 channel = hsotg->hc_ptr_array[i]; 1811 if (!list_empty(&channel->hc_list_entry)) 1812 continue; 1813 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1814 if (hcchar & HCCHAR_CHENA) { 1815 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1816 hcchar |= HCCHAR_CHDIS; 1817 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1818 } 1819 } 1820 } 1821 1822 for (i = 0; i < num_channels; i++) { 1823 channel = hsotg->hc_ptr_array[i]; 1824 if (!list_empty(&channel->hc_list_entry)) 1825 continue; 1826 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1827 if (hcchar & HCCHAR_CHENA) { 1828 /* Halt the channel */ 1829 hcchar |= HCCHAR_CHDIS; 1830 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1831 } 1832 1833 dwc2_hc_cleanup(hsotg, channel); 1834 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1835 /* 1836 * Added for Descriptor DMA to prevent channel double cleanup in 1837 * release_channel_ddma(), which is called from ep_disable when 1838 * device disconnects 1839 */ 1840 channel->qh = NULL; 1841 } 1842 /* All channels have been freed, mark them available */ 1843 if (hsotg->core_params->uframe_sched > 0) { 1844 hsotg->available_host_channels = 1845 hsotg->core_params->host_channels; 1846 } else { 1847 hsotg->non_periodic_channels = 0; 1848 hsotg->periodic_channels = 0; 1849 } 1850 } 1851 1852 /** 1853 * dwc2_hcd_connect() - Handles connect of the HCD 1854 * 1855 * @hsotg: Pointer to struct dwc2_hsotg 1856 * 1857 * Must be called with interrupt disabled and spinlock held 1858 */ 1859 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1860 { 1861 if (hsotg->lx_state != DWC2_L0) 1862 usb_hcd_resume_root_hub(hsotg->priv); 1863 1864 hsotg->flags.b.port_connect_status_change = 1; 1865 hsotg->flags.b.port_connect_status = 1; 1866 } 1867 1868 /** 1869 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1870 * 1871 * @hsotg: Pointer to struct dwc2_hsotg 1872 * @force: If true, we won't try to reconnect even if we see device connected. 1873 * 1874 * Must be called with interrupt disabled and spinlock held 1875 */ 1876 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1877 { 1878 u32 intr; 1879 u32 hprt0; 1880 1881 /* Set status flags for the hub driver */ 1882 hsotg->flags.b.port_connect_status_change = 1; 1883 hsotg->flags.b.port_connect_status = 0; 1884 1885 /* 1886 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1887 * interrupt mask and status bits and disabling subsequent host 1888 * channel interrupts. 1889 */ 1890 intr = dwc2_readl(hsotg->regs + GINTMSK); 1891 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1892 dwc2_writel(intr, hsotg->regs + GINTMSK); 1893 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1894 dwc2_writel(intr, hsotg->regs + GINTSTS); 1895 1896 /* 1897 * Turn off the vbus power only if the core has transitioned to device 1898 * mode. If still in host mode, need to keep power on to detect a 1899 * reconnection. 1900 */ 1901 if (dwc2_is_device_mode(hsotg)) { 1902 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1903 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1904 dwc2_writel(0, hsotg->regs + HPRT0); 1905 } 1906 1907 dwc2_disable_host_interrupts(hsotg); 1908 } 1909 1910 /* Respond with an error status to all URBs in the schedule */ 1911 dwc2_kill_all_urbs(hsotg); 1912 1913 if (dwc2_is_host_mode(hsotg)) 1914 /* Clean up any host channels that were in use */ 1915 dwc2_hcd_cleanup_channels(hsotg); 1916 1917 dwc2_host_disconnect(hsotg); 1918 1919 /* 1920 * Add an extra check here to see if we're actually connected but 1921 * we don't have a detection interrupt pending. This can happen if: 1922 * 1. hardware sees connect 1923 * 2. hardware sees disconnect 1924 * 3. hardware sees connect 1925 * 4. dwc2_port_intr() - clears connect interrupt 1926 * 5. dwc2_handle_common_intr() - calls here 1927 * 1928 * Without the extra check here we will end calling disconnect 1929 * and won't get any future interrupts to handle the connect. 1930 */ 1931 if (!force) { 1932 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1933 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1934 dwc2_hcd_connect(hsotg); 1935 } 1936 } 1937 1938 /** 1939 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1940 * 1941 * @hsotg: Pointer to struct dwc2_hsotg 1942 */ 1943 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1944 { 1945 if (hsotg->bus_suspended) { 1946 hsotg->flags.b.port_suspend_change = 1; 1947 usb_hcd_resume_root_hub(hsotg->priv); 1948 } 1949 1950 if (hsotg->lx_state == DWC2_L1) 1951 hsotg->flags.b.port_l1_change = 1; 1952 } 1953 1954 /** 1955 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1956 * 1957 * @hsotg: Pointer to struct dwc2_hsotg 1958 * 1959 * Must be called with interrupt disabled and spinlock held 1960 */ 1961 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1962 { 1963 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1964 1965 /* 1966 * The root hub should be disconnected before this function is called. 1967 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 1968 * and the QH lists (via ..._hcd_endpoint_disable). 1969 */ 1970 1971 /* Turn off all host-specific interrupts */ 1972 dwc2_disable_host_interrupts(hsotg); 1973 1974 /* Turn off the vbus power */ 1975 dev_dbg(hsotg->dev, "PortPower off\n"); 1976 dwc2_writel(0, hsotg->regs + HPRT0); 1977 } 1978 1979 /* Caller must hold driver lock */ 1980 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 1981 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 1982 struct dwc2_qtd *qtd) 1983 { 1984 u32 intr_mask; 1985 int retval; 1986 int dev_speed; 1987 1988 if (!hsotg->flags.b.port_connect_status) { 1989 /* No longer connected */ 1990 dev_err(hsotg->dev, "Not connected\n"); 1991 return -ENODEV; 1992 } 1993 1994 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1995 1996 /* Some configurations cannot support LS traffic on a FS root port */ 1997 if ((dev_speed == USB_SPEED_LOW) && 1998 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 1999 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2000 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2001 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2002 2003 if (prtspd == HPRT0_SPD_FULL_SPEED) 2004 return -ENODEV; 2005 } 2006 2007 if (!qtd) 2008 return -EINVAL; 2009 2010 dwc2_hcd_qtd_init(qtd, urb); 2011 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2012 if (retval) { 2013 dev_err(hsotg->dev, 2014 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2015 retval); 2016 return retval; 2017 } 2018 2019 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2020 if (!(intr_mask & GINTSTS_SOF)) { 2021 enum dwc2_transaction_type tr_type; 2022 2023 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2024 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2025 /* 2026 * Do not schedule SG transactions until qtd has 2027 * URB_GIVEBACK_ASAP set 2028 */ 2029 return 0; 2030 2031 tr_type = dwc2_hcd_select_transactions(hsotg); 2032 if (tr_type != DWC2_TRANSACTION_NONE) 2033 dwc2_hcd_queue_transactions(hsotg, tr_type); 2034 } 2035 2036 return 0; 2037 } 2038 2039 /* Must be called with interrupt disabled and spinlock held */ 2040 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2041 struct dwc2_hcd_urb *urb) 2042 { 2043 struct dwc2_qh *qh; 2044 struct dwc2_qtd *urb_qtd; 2045 2046 urb_qtd = urb->qtd; 2047 if (!urb_qtd) { 2048 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2049 return -EINVAL; 2050 } 2051 2052 qh = urb_qtd->qh; 2053 if (!qh) { 2054 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2055 return -EINVAL; 2056 } 2057 2058 urb->priv = NULL; 2059 2060 if (urb_qtd->in_process && qh->channel) { 2061 dwc2_dump_channel_info(hsotg, qh->channel); 2062 2063 /* The QTD is in process (it has been assigned to a channel) */ 2064 if (hsotg->flags.b.port_connect_status) 2065 /* 2066 * If still connected (i.e. in host mode), halt the 2067 * channel so it can be used for other transfers. If 2068 * no longer connected, the host registers can't be 2069 * written to halt the channel since the core is in 2070 * device mode. 2071 */ 2072 dwc2_hc_halt(hsotg, qh->channel, 2073 DWC2_HC_XFER_URB_DEQUEUE); 2074 } 2075 2076 /* 2077 * Free the QTD and clean up the associated QH. Leave the QH in the 2078 * schedule if it has any remaining QTDs. 2079 */ 2080 if (hsotg->core_params->dma_desc_enable <= 0) { 2081 u8 in_process = urb_qtd->in_process; 2082 2083 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2084 if (in_process) { 2085 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2086 qh->channel = NULL; 2087 } else if (list_empty(&qh->qtd_list)) { 2088 dwc2_hcd_qh_unlink(hsotg, qh); 2089 } 2090 } else { 2091 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2092 } 2093 2094 return 0; 2095 } 2096 2097 /* Must NOT be called with interrupt disabled or spinlock held */ 2098 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2099 struct usb_host_endpoint *ep, int retry) 2100 { 2101 struct dwc2_qtd *qtd, *qtd_tmp; 2102 struct dwc2_qh *qh; 2103 unsigned long flags; 2104 int rc; 2105 2106 spin_lock_irqsave(&hsotg->lock, flags); 2107 2108 qh = ep->hcpriv; 2109 if (!qh) { 2110 rc = -EINVAL; 2111 goto err; 2112 } 2113 2114 while (!list_empty(&qh->qtd_list) && retry--) { 2115 if (retry == 0) { 2116 dev_err(hsotg->dev, 2117 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2118 rc = -EBUSY; 2119 goto err; 2120 } 2121 2122 spin_unlock_irqrestore(&hsotg->lock, flags); 2123 usleep_range(20000, 40000); 2124 spin_lock_irqsave(&hsotg->lock, flags); 2125 qh = ep->hcpriv; 2126 if (!qh) { 2127 rc = -EINVAL; 2128 goto err; 2129 } 2130 } 2131 2132 dwc2_hcd_qh_unlink(hsotg, qh); 2133 2134 /* Free each QTD in the QH's QTD list */ 2135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2136 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2137 2138 ep->hcpriv = NULL; 2139 2140 if (qh->channel && qh->channel->qh == qh) 2141 qh->channel->qh = NULL; 2142 2143 spin_unlock_irqrestore(&hsotg->lock, flags); 2144 2145 dwc2_hcd_qh_free(hsotg, qh); 2146 2147 return 0; 2148 2149 err: 2150 ep->hcpriv = NULL; 2151 spin_unlock_irqrestore(&hsotg->lock, flags); 2152 2153 return rc; 2154 } 2155 2156 /* Must be called with interrupt disabled and spinlock held */ 2157 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2158 struct usb_host_endpoint *ep) 2159 { 2160 struct dwc2_qh *qh = ep->hcpriv; 2161 2162 if (!qh) 2163 return -EINVAL; 2164 2165 qh->data_toggle = DWC2_HC_PID_DATA0; 2166 2167 return 0; 2168 } 2169 2170 /** 2171 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2172 * prepares the core for device mode or host mode operation 2173 * 2174 * @hsotg: Programming view of the DWC_otg controller 2175 * @initial_setup: If true then this is the first init for this instance. 2176 */ 2177 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2178 { 2179 u32 usbcfg, otgctl; 2180 int retval; 2181 2182 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2183 2184 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2185 2186 /* Set ULPI External VBUS bit if needed */ 2187 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2188 if (hsotg->core_params->phy_ulpi_ext_vbus == 2189 DWC2_PHY_ULPI_EXTERNAL_VBUS) 2190 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2191 2192 /* Set external TS Dline pulsing bit if needed */ 2193 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2194 if (hsotg->core_params->ts_dline > 0) 2195 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2196 2197 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2198 2199 /* 2200 * Reset the Controller 2201 * 2202 * We only need to reset the controller if this is a re-init. 2203 * For the first init we know for sure that earlier code reset us (it 2204 * needed to in order to properly detect various parameters). 2205 */ 2206 if (!initial_setup) { 2207 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2208 if (retval) { 2209 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2210 __func__); 2211 return retval; 2212 } 2213 } 2214 2215 /* 2216 * This needs to happen in FS mode before any other programming occurs 2217 */ 2218 retval = dwc2_phy_init(hsotg, initial_setup); 2219 if (retval) 2220 return retval; 2221 2222 /* Program the GAHBCFG Register */ 2223 retval = dwc2_gahbcfg_init(hsotg); 2224 if (retval) 2225 return retval; 2226 2227 /* Program the GUSBCFG register */ 2228 dwc2_gusbcfg_init(hsotg); 2229 2230 /* Program the GOTGCTL register */ 2231 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2232 otgctl &= ~GOTGCTL_OTGVER; 2233 if (hsotg->core_params->otg_ver > 0) 2234 otgctl |= GOTGCTL_OTGVER; 2235 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2236 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); 2237 2238 /* Clear the SRP success bit for FS-I2c */ 2239 hsotg->srp_success = 0; 2240 2241 /* Enable common interrupts */ 2242 dwc2_enable_common_interrupts(hsotg); 2243 2244 /* 2245 * Do device or host initialization based on mode during PCD and 2246 * HCD initialization 2247 */ 2248 if (dwc2_is_host_mode(hsotg)) { 2249 dev_dbg(hsotg->dev, "Host Mode\n"); 2250 hsotg->op_state = OTG_STATE_A_HOST; 2251 } else { 2252 dev_dbg(hsotg->dev, "Device Mode\n"); 2253 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2254 } 2255 2256 return 0; 2257 } 2258 2259 /** 2260 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2261 * Host mode 2262 * 2263 * @hsotg: Programming view of DWC_otg controller 2264 * 2265 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2266 * request queues. Host channels are reset to ensure that they are ready for 2267 * performing transfers. 2268 */ 2269 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2270 { 2271 u32 hcfg, hfir, otgctl; 2272 2273 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2274 2275 /* Restart the Phy Clock */ 2276 dwc2_writel(0, hsotg->regs + PCGCTL); 2277 2278 /* Initialize Host Configuration Register */ 2279 dwc2_init_fs_ls_pclk_sel(hsotg); 2280 if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { 2281 hcfg = dwc2_readl(hsotg->regs + HCFG); 2282 hcfg |= HCFG_FSLSSUPP; 2283 dwc2_writel(hcfg, hsotg->regs + HCFG); 2284 } 2285 2286 /* 2287 * This bit allows dynamic reloading of the HFIR register during 2288 * runtime. This bit needs to be programmed during initial configuration 2289 * and its value must not be changed during runtime. 2290 */ 2291 if (hsotg->core_params->reload_ctl > 0) { 2292 hfir = dwc2_readl(hsotg->regs + HFIR); 2293 hfir |= HFIR_RLDCTRL; 2294 dwc2_writel(hfir, hsotg->regs + HFIR); 2295 } 2296 2297 if (hsotg->core_params->dma_desc_enable > 0) { 2298 u32 op_mode = hsotg->hw_params.op_mode; 2299 2300 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2301 !hsotg->hw_params.dma_desc_enable || 2302 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2303 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2304 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2305 dev_err(hsotg->dev, 2306 "Hardware does not support descriptor DMA mode -\n"); 2307 dev_err(hsotg->dev, 2308 "falling back to buffer DMA mode.\n"); 2309 hsotg->core_params->dma_desc_enable = 0; 2310 } else { 2311 hcfg = dwc2_readl(hsotg->regs + HCFG); 2312 hcfg |= HCFG_DESCDMA; 2313 dwc2_writel(hcfg, hsotg->regs + HCFG); 2314 } 2315 } 2316 2317 /* Configure data FIFO sizes */ 2318 dwc2_config_fifos(hsotg); 2319 2320 /* TODO - check this */ 2321 /* Clear Host Set HNP Enable in the OTG Control Register */ 2322 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2323 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2324 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2325 2326 /* Make sure the FIFOs are flushed */ 2327 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2328 dwc2_flush_rx_fifo(hsotg); 2329 2330 /* Clear Host Set HNP Enable in the OTG Control Register */ 2331 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2332 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2333 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2334 2335 if (hsotg->core_params->dma_desc_enable <= 0) { 2336 int num_channels, i; 2337 u32 hcchar; 2338 2339 /* Flush out any leftover queued requests */ 2340 num_channels = hsotg->core_params->host_channels; 2341 for (i = 0; i < num_channels; i++) { 2342 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2343 hcchar &= ~HCCHAR_CHENA; 2344 hcchar |= HCCHAR_CHDIS; 2345 hcchar &= ~HCCHAR_EPDIR; 2346 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2347 } 2348 2349 /* Halt all channels to put them into a known state */ 2350 for (i = 0; i < num_channels; i++) { 2351 int count = 0; 2352 2353 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2354 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2355 hcchar &= ~HCCHAR_EPDIR; 2356 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2357 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2358 __func__, i); 2359 do { 2360 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2361 if (++count > 1000) { 2362 dev_err(hsotg->dev, 2363 "Unable to clear enable on channel %d\n", 2364 i); 2365 break; 2366 } 2367 udelay(1); 2368 } while (hcchar & HCCHAR_CHENA); 2369 } 2370 } 2371 2372 /* Turn on the vbus power */ 2373 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2374 if (hsotg->op_state == OTG_STATE_A_HOST) { 2375 u32 hprt0 = dwc2_read_hprt0(hsotg); 2376 2377 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2378 !!(hprt0 & HPRT0_PWR)); 2379 if (!(hprt0 & HPRT0_PWR)) { 2380 hprt0 |= HPRT0_PWR; 2381 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2382 } 2383 } 2384 2385 dwc2_enable_host_interrupts(hsotg); 2386 } 2387 2388 /* 2389 * Initializes dynamic portions of the DWC_otg HCD state 2390 * 2391 * Must be called with interrupt disabled and spinlock held 2392 */ 2393 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2394 { 2395 struct dwc2_host_chan *chan, *chan_tmp; 2396 int num_channels; 2397 int i; 2398 2399 hsotg->flags.d32 = 0; 2400 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2401 2402 if (hsotg->core_params->uframe_sched > 0) { 2403 hsotg->available_host_channels = 2404 hsotg->core_params->host_channels; 2405 } else { 2406 hsotg->non_periodic_channels = 0; 2407 hsotg->periodic_channels = 0; 2408 } 2409 2410 /* 2411 * Put all channels in the free channel list and clean up channel 2412 * states 2413 */ 2414 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2415 hc_list_entry) 2416 list_del_init(&chan->hc_list_entry); 2417 2418 num_channels = hsotg->core_params->host_channels; 2419 for (i = 0; i < num_channels; i++) { 2420 chan = hsotg->hc_ptr_array[i]; 2421 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2422 dwc2_hc_cleanup(hsotg, chan); 2423 } 2424 2425 /* Initialize the DWC core for host mode operation */ 2426 dwc2_core_host_init(hsotg); 2427 } 2428 2429 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2430 struct dwc2_host_chan *chan, 2431 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2432 { 2433 int hub_addr, hub_port; 2434 2435 chan->do_split = 1; 2436 chan->xact_pos = qtd->isoc_split_pos; 2437 chan->complete_split = qtd->complete_split; 2438 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2439 chan->hub_addr = (u8)hub_addr; 2440 chan->hub_port = (u8)hub_port; 2441 } 2442 2443 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2444 struct dwc2_host_chan *chan, 2445 struct dwc2_qtd *qtd) 2446 { 2447 struct dwc2_hcd_urb *urb = qtd->urb; 2448 struct dwc2_hcd_iso_packet_desc *frame_desc; 2449 2450 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2451 case USB_ENDPOINT_XFER_CONTROL: 2452 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2453 2454 switch (qtd->control_phase) { 2455 case DWC2_CONTROL_SETUP: 2456 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2457 chan->do_ping = 0; 2458 chan->ep_is_in = 0; 2459 chan->data_pid_start = DWC2_HC_PID_SETUP; 2460 if (hsotg->core_params->dma_enable > 0) 2461 chan->xfer_dma = urb->setup_dma; 2462 else 2463 chan->xfer_buf = urb->setup_packet; 2464 chan->xfer_len = 8; 2465 break; 2466 2467 case DWC2_CONTROL_DATA: 2468 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2469 chan->data_pid_start = qtd->data_toggle; 2470 break; 2471 2472 case DWC2_CONTROL_STATUS: 2473 /* 2474 * Direction is opposite of data direction or IN if no 2475 * data 2476 */ 2477 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2478 if (urb->length == 0) 2479 chan->ep_is_in = 1; 2480 else 2481 chan->ep_is_in = 2482 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2483 if (chan->ep_is_in) 2484 chan->do_ping = 0; 2485 chan->data_pid_start = DWC2_HC_PID_DATA1; 2486 chan->xfer_len = 0; 2487 if (hsotg->core_params->dma_enable > 0) 2488 chan->xfer_dma = hsotg->status_buf_dma; 2489 else 2490 chan->xfer_buf = hsotg->status_buf; 2491 break; 2492 } 2493 break; 2494 2495 case USB_ENDPOINT_XFER_BULK: 2496 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2497 break; 2498 2499 case USB_ENDPOINT_XFER_INT: 2500 chan->ep_type = USB_ENDPOINT_XFER_INT; 2501 break; 2502 2503 case USB_ENDPOINT_XFER_ISOC: 2504 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2505 if (hsotg->core_params->dma_desc_enable > 0) 2506 break; 2507 2508 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2509 frame_desc->status = 0; 2510 2511 if (hsotg->core_params->dma_enable > 0) { 2512 chan->xfer_dma = urb->dma; 2513 chan->xfer_dma += frame_desc->offset + 2514 qtd->isoc_split_offset; 2515 } else { 2516 chan->xfer_buf = urb->buf; 2517 chan->xfer_buf += frame_desc->offset + 2518 qtd->isoc_split_offset; 2519 } 2520 2521 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2522 2523 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2524 if (chan->xfer_len <= 188) 2525 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2526 else 2527 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2528 } 2529 break; 2530 } 2531 } 2532 2533 #define DWC2_USB_DMA_ALIGN 4 2534 2535 struct dma_aligned_buffer { 2536 void *kmalloc_ptr; 2537 void *old_xfer_buffer; 2538 u8 data[0]; 2539 }; 2540 2541 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2542 { 2543 struct dma_aligned_buffer *temp; 2544 2545 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2546 return; 2547 2548 temp = container_of(urb->transfer_buffer, 2549 struct dma_aligned_buffer, data); 2550 2551 if (usb_urb_dir_in(urb)) 2552 memcpy(temp->old_xfer_buffer, temp->data, 2553 urb->transfer_buffer_length); 2554 urb->transfer_buffer = temp->old_xfer_buffer; 2555 kfree(temp->kmalloc_ptr); 2556 2557 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2558 } 2559 2560 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2561 { 2562 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2563 size_t kmalloc_size; 2564 2565 if (urb->num_sgs || urb->sg || 2566 urb->transfer_buffer_length == 0 || 2567 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2568 return 0; 2569 2570 /* Allocate a buffer with enough padding for alignment */ 2571 kmalloc_size = urb->transfer_buffer_length + 2572 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2573 2574 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2575 if (!kmalloc_ptr) 2576 return -ENOMEM; 2577 2578 /* Position our struct dma_aligned_buffer such that data is aligned */ 2579 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2580 temp->kmalloc_ptr = kmalloc_ptr; 2581 temp->old_xfer_buffer = urb->transfer_buffer; 2582 if (usb_urb_dir_out(urb)) 2583 memcpy(temp->data, urb->transfer_buffer, 2584 urb->transfer_buffer_length); 2585 urb->transfer_buffer = temp->data; 2586 2587 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2588 2589 return 0; 2590 } 2591 2592 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2593 gfp_t mem_flags) 2594 { 2595 int ret; 2596 2597 /* We assume setup_dma is always aligned; warn if not */ 2598 WARN_ON_ONCE(urb->setup_dma && 2599 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2600 2601 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2602 if (ret) 2603 return ret; 2604 2605 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2606 if (ret) 2607 dwc2_free_dma_aligned_buffer(urb); 2608 2609 return ret; 2610 } 2611 2612 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2613 { 2614 usb_hcd_unmap_urb_for_dma(hcd, urb); 2615 dwc2_free_dma_aligned_buffer(urb); 2616 } 2617 2618 /** 2619 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2620 * channel and initializes the host channel to perform the transactions. The 2621 * host channel is removed from the free list. 2622 * 2623 * @hsotg: The HCD state structure 2624 * @qh: Transactions from the first QTD for this QH are selected and assigned 2625 * to a free host channel 2626 */ 2627 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2628 { 2629 struct dwc2_host_chan *chan; 2630 struct dwc2_hcd_urb *urb; 2631 struct dwc2_qtd *qtd; 2632 2633 if (dbg_qh(qh)) 2634 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2635 2636 if (list_empty(&qh->qtd_list)) { 2637 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2638 return -ENOMEM; 2639 } 2640 2641 if (list_empty(&hsotg->free_hc_list)) { 2642 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2643 return -ENOMEM; 2644 } 2645 2646 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2647 hc_list_entry); 2648 2649 /* Remove host channel from free list */ 2650 list_del_init(&chan->hc_list_entry); 2651 2652 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2653 urb = qtd->urb; 2654 qh->channel = chan; 2655 qtd->in_process = 1; 2656 2657 /* 2658 * Use usb_pipedevice to determine device address. This address is 2659 * 0 before the SET_ADDRESS command and the correct address afterward. 2660 */ 2661 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2662 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2663 chan->speed = qh->dev_speed; 2664 chan->max_packet = dwc2_max_packet(qh->maxp); 2665 2666 chan->xfer_started = 0; 2667 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2668 chan->error_state = (qtd->error_count > 0); 2669 chan->halt_on_queue = 0; 2670 chan->halt_pending = 0; 2671 chan->requests = 0; 2672 2673 /* 2674 * The following values may be modified in the transfer type section 2675 * below. The xfer_len value may be reduced when the transfer is 2676 * started to accommodate the max widths of the XferSize and PktCnt 2677 * fields in the HCTSIZn register. 2678 */ 2679 2680 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2681 if (chan->ep_is_in) 2682 chan->do_ping = 0; 2683 else 2684 chan->do_ping = qh->ping_state; 2685 2686 chan->data_pid_start = qh->data_toggle; 2687 chan->multi_count = 1; 2688 2689 if (urb->actual_length > urb->length && 2690 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2691 urb->actual_length = urb->length; 2692 2693 if (hsotg->core_params->dma_enable > 0) 2694 chan->xfer_dma = urb->dma + urb->actual_length; 2695 else 2696 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2697 2698 chan->xfer_len = urb->length - urb->actual_length; 2699 chan->xfer_count = 0; 2700 2701 /* Set the split attributes if required */ 2702 if (qh->do_split) 2703 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2704 else 2705 chan->do_split = 0; 2706 2707 /* Set the transfer attributes */ 2708 dwc2_hc_init_xfer(hsotg, chan, qtd); 2709 2710 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2711 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2712 /* 2713 * This value may be modified when the transfer is started 2714 * to reflect the actual transfer length 2715 */ 2716 chan->multi_count = dwc2_hb_mult(qh->maxp); 2717 2718 if (hsotg->core_params->dma_desc_enable > 0) { 2719 chan->desc_list_addr = qh->desc_list_dma; 2720 chan->desc_list_sz = qh->desc_list_sz; 2721 } 2722 2723 dwc2_hc_init(hsotg, chan); 2724 chan->qh = qh; 2725 2726 return 0; 2727 } 2728 2729 /** 2730 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2731 * schedule and assigns them to available host channels. Called from the HCD 2732 * interrupt handler functions. 2733 * 2734 * @hsotg: The HCD state structure 2735 * 2736 * Return: The types of new transactions that were assigned to host channels 2737 */ 2738 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2739 struct dwc2_hsotg *hsotg) 2740 { 2741 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2742 struct list_head *qh_ptr; 2743 struct dwc2_qh *qh; 2744 int num_channels; 2745 2746 #ifdef DWC2_DEBUG_SOF 2747 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2748 #endif 2749 2750 /* Process entries in the periodic ready list */ 2751 qh_ptr = hsotg->periodic_sched_ready.next; 2752 while (qh_ptr != &hsotg->periodic_sched_ready) { 2753 if (list_empty(&hsotg->free_hc_list)) 2754 break; 2755 if (hsotg->core_params->uframe_sched > 0) { 2756 if (hsotg->available_host_channels <= 1) 2757 break; 2758 hsotg->available_host_channels--; 2759 } 2760 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2761 if (dwc2_assign_and_init_hc(hsotg, qh)) 2762 break; 2763 2764 /* 2765 * Move the QH from the periodic ready schedule to the 2766 * periodic assigned schedule 2767 */ 2768 qh_ptr = qh_ptr->next; 2769 list_move_tail(&qh->qh_list_entry, 2770 &hsotg->periodic_sched_assigned); 2771 ret_val = DWC2_TRANSACTION_PERIODIC; 2772 } 2773 2774 /* 2775 * Process entries in the inactive portion of the non-periodic 2776 * schedule. Some free host channels may not be used if they are 2777 * reserved for periodic transfers. 2778 */ 2779 num_channels = hsotg->core_params->host_channels; 2780 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2781 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2782 if (hsotg->core_params->uframe_sched <= 0 && 2783 hsotg->non_periodic_channels >= num_channels - 2784 hsotg->periodic_channels) 2785 break; 2786 if (list_empty(&hsotg->free_hc_list)) 2787 break; 2788 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2789 if (hsotg->core_params->uframe_sched > 0) { 2790 if (hsotg->available_host_channels < 1) 2791 break; 2792 hsotg->available_host_channels--; 2793 } 2794 2795 if (dwc2_assign_and_init_hc(hsotg, qh)) 2796 break; 2797 2798 /* 2799 * Move the QH from the non-periodic inactive schedule to the 2800 * non-periodic active schedule 2801 */ 2802 qh_ptr = qh_ptr->next; 2803 list_move_tail(&qh->qh_list_entry, 2804 &hsotg->non_periodic_sched_active); 2805 2806 if (ret_val == DWC2_TRANSACTION_NONE) 2807 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2808 else 2809 ret_val = DWC2_TRANSACTION_ALL; 2810 2811 if (hsotg->core_params->uframe_sched <= 0) 2812 hsotg->non_periodic_channels++; 2813 } 2814 2815 return ret_val; 2816 } 2817 2818 /** 2819 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2820 * a host channel associated with either a periodic or non-periodic transfer 2821 * 2822 * @hsotg: The HCD state structure 2823 * @chan: Host channel descriptor associated with either a periodic or 2824 * non-periodic transfer 2825 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2826 * for periodic transfers or the non-periodic Tx FIFO 2827 * for non-periodic transfers 2828 * 2829 * Return: 1 if a request is queued and more requests may be needed to 2830 * complete the transfer, 0 if no more requests are required for this 2831 * transfer, -1 if there is insufficient space in the Tx FIFO 2832 * 2833 * This function assumes that there is space available in the appropriate 2834 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2835 * it checks whether space is available in the appropriate Tx FIFO. 2836 * 2837 * Must be called with interrupt disabled and spinlock held 2838 */ 2839 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2840 struct dwc2_host_chan *chan, 2841 u16 fifo_dwords_avail) 2842 { 2843 int retval = 0; 2844 2845 if (chan->do_split) 2846 /* Put ourselves on the list to keep order straight */ 2847 list_move_tail(&chan->split_order_list_entry, 2848 &hsotg->split_order); 2849 2850 if (hsotg->core_params->dma_enable > 0) { 2851 if (hsotg->core_params->dma_desc_enable > 0) { 2852 if (!chan->xfer_started || 2853 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2854 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2855 chan->qh->ping_state = 0; 2856 } 2857 } else if (!chan->xfer_started) { 2858 dwc2_hc_start_transfer(hsotg, chan); 2859 chan->qh->ping_state = 0; 2860 } 2861 } else if (chan->halt_pending) { 2862 /* Don't queue a request if the channel has been halted */ 2863 } else if (chan->halt_on_queue) { 2864 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2865 } else if (chan->do_ping) { 2866 if (!chan->xfer_started) 2867 dwc2_hc_start_transfer(hsotg, chan); 2868 } else if (!chan->ep_is_in || 2869 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2870 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2871 if (!chan->xfer_started) { 2872 dwc2_hc_start_transfer(hsotg, chan); 2873 retval = 1; 2874 } else { 2875 retval = dwc2_hc_continue_transfer(hsotg, chan); 2876 } 2877 } else { 2878 retval = -1; 2879 } 2880 } else { 2881 if (!chan->xfer_started) { 2882 dwc2_hc_start_transfer(hsotg, chan); 2883 retval = 1; 2884 } else { 2885 retval = dwc2_hc_continue_transfer(hsotg, chan); 2886 } 2887 } 2888 2889 return retval; 2890 } 2891 2892 /* 2893 * Processes periodic channels for the next frame and queues transactions for 2894 * these channels to the DWC_otg controller. After queueing transactions, the 2895 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2896 * to queue as Periodic Tx FIFO or request queue space becomes available. 2897 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2898 * 2899 * Must be called with interrupt disabled and spinlock held 2900 */ 2901 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2902 { 2903 struct list_head *qh_ptr; 2904 struct dwc2_qh *qh; 2905 u32 tx_status; 2906 u32 fspcavail; 2907 u32 gintmsk; 2908 int status; 2909 bool no_queue_space = false; 2910 bool no_fifo_space = false; 2911 u32 qspcavail; 2912 2913 /* If empty list then just adjust interrupt enables */ 2914 if (list_empty(&hsotg->periodic_sched_assigned)) 2915 goto exit; 2916 2917 if (dbg_perio()) 2918 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2919 2920 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2921 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2922 TXSTS_QSPCAVAIL_SHIFT; 2923 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2924 TXSTS_FSPCAVAIL_SHIFT; 2925 2926 if (dbg_perio()) { 2927 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2928 qspcavail); 2929 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2930 fspcavail); 2931 } 2932 2933 qh_ptr = hsotg->periodic_sched_assigned.next; 2934 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2935 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2936 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2937 TXSTS_QSPCAVAIL_SHIFT; 2938 if (qspcavail == 0) { 2939 no_queue_space = 1; 2940 break; 2941 } 2942 2943 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2944 if (!qh->channel) { 2945 qh_ptr = qh_ptr->next; 2946 continue; 2947 } 2948 2949 /* Make sure EP's TT buffer is clean before queueing qtds */ 2950 if (qh->tt_buffer_dirty) { 2951 qh_ptr = qh_ptr->next; 2952 continue; 2953 } 2954 2955 /* 2956 * Set a flag if we're queuing high-bandwidth in slave mode. 2957 * The flag prevents any halts to get into the request queue in 2958 * the middle of multiple high-bandwidth packets getting queued. 2959 */ 2960 if (hsotg->core_params->dma_enable <= 0 && 2961 qh->channel->multi_count > 1) 2962 hsotg->queuing_high_bandwidth = 1; 2963 2964 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2965 TXSTS_FSPCAVAIL_SHIFT; 2966 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2967 if (status < 0) { 2968 no_fifo_space = 1; 2969 break; 2970 } 2971 2972 /* 2973 * In Slave mode, stay on the current transfer until there is 2974 * nothing more to do or the high-bandwidth request count is 2975 * reached. In DMA mode, only need to queue one request. The 2976 * controller automatically handles multiple packets for 2977 * high-bandwidth transfers. 2978 */ 2979 if (hsotg->core_params->dma_enable > 0 || status == 0 || 2980 qh->channel->requests == qh->channel->multi_count) { 2981 qh_ptr = qh_ptr->next; 2982 /* 2983 * Move the QH from the periodic assigned schedule to 2984 * the periodic queued schedule 2985 */ 2986 list_move_tail(&qh->qh_list_entry, 2987 &hsotg->periodic_sched_queued); 2988 2989 /* done queuing high bandwidth */ 2990 hsotg->queuing_high_bandwidth = 0; 2991 } 2992 } 2993 2994 exit: 2995 if (no_queue_space || no_fifo_space || 2996 (hsotg->core_params->dma_enable <= 0 && 2997 !list_empty(&hsotg->periodic_sched_assigned))) { 2998 /* 2999 * May need to queue more transactions as the request 3000 * queue or Tx FIFO empties. Enable the periodic Tx 3001 * FIFO empty interrupt. (Always use the half-empty 3002 * level to ensure that new requests are loaded as 3003 * soon as possible.) 3004 */ 3005 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3006 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3007 gintmsk |= GINTSTS_PTXFEMP; 3008 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3009 } 3010 } else { 3011 /* 3012 * Disable the Tx FIFO empty interrupt since there are 3013 * no more transactions that need to be queued right 3014 * now. This function is called from interrupt 3015 * handlers to queue more transactions as transfer 3016 * states change. 3017 */ 3018 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3019 if (gintmsk & GINTSTS_PTXFEMP) { 3020 gintmsk &= ~GINTSTS_PTXFEMP; 3021 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3022 } 3023 } 3024 } 3025 3026 /* 3027 * Processes active non-periodic channels and queues transactions for these 3028 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3029 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3030 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3031 * FIFO Empty interrupt is disabled. 3032 * 3033 * Must be called with interrupt disabled and spinlock held 3034 */ 3035 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3036 { 3037 struct list_head *orig_qh_ptr; 3038 struct dwc2_qh *qh; 3039 u32 tx_status; 3040 u32 qspcavail; 3041 u32 fspcavail; 3042 u32 gintmsk; 3043 int status; 3044 int no_queue_space = 0; 3045 int no_fifo_space = 0; 3046 int more_to_do = 0; 3047 3048 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3049 3050 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3051 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3052 TXSTS_QSPCAVAIL_SHIFT; 3053 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3054 TXSTS_FSPCAVAIL_SHIFT; 3055 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3056 qspcavail); 3057 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3058 fspcavail); 3059 3060 /* 3061 * Keep track of the starting point. Skip over the start-of-list 3062 * entry. 3063 */ 3064 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3065 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3066 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3067 3068 /* 3069 * Process once through the active list or until no more space is 3070 * available in the request queue or the Tx FIFO 3071 */ 3072 do { 3073 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3074 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3075 TXSTS_QSPCAVAIL_SHIFT; 3076 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 3077 no_queue_space = 1; 3078 break; 3079 } 3080 3081 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3082 qh_list_entry); 3083 if (!qh->channel) 3084 goto next; 3085 3086 /* Make sure EP's TT buffer is clean before queueing qtds */ 3087 if (qh->tt_buffer_dirty) 3088 goto next; 3089 3090 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3091 TXSTS_FSPCAVAIL_SHIFT; 3092 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3093 3094 if (status > 0) { 3095 more_to_do = 1; 3096 } else if (status < 0) { 3097 no_fifo_space = 1; 3098 break; 3099 } 3100 next: 3101 /* Advance to next QH, skipping start-of-list entry */ 3102 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3103 if (hsotg->non_periodic_qh_ptr == 3104 &hsotg->non_periodic_sched_active) 3105 hsotg->non_periodic_qh_ptr = 3106 hsotg->non_periodic_qh_ptr->next; 3107 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3108 3109 if (hsotg->core_params->dma_enable <= 0) { 3110 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3111 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3112 TXSTS_QSPCAVAIL_SHIFT; 3113 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3114 TXSTS_FSPCAVAIL_SHIFT; 3115 dev_vdbg(hsotg->dev, 3116 " NP Tx Req Queue Space Avail (after queue): %d\n", 3117 qspcavail); 3118 dev_vdbg(hsotg->dev, 3119 " NP Tx FIFO Space Avail (after queue): %d\n", 3120 fspcavail); 3121 3122 if (more_to_do || no_queue_space || no_fifo_space) { 3123 /* 3124 * May need to queue more transactions as the request 3125 * queue or Tx FIFO empties. Enable the non-periodic 3126 * Tx FIFO empty interrupt. (Always use the half-empty 3127 * level to ensure that new requests are loaded as 3128 * soon as possible.) 3129 */ 3130 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3131 gintmsk |= GINTSTS_NPTXFEMP; 3132 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3133 } else { 3134 /* 3135 * Disable the Tx FIFO empty interrupt since there are 3136 * no more transactions that need to be queued right 3137 * now. This function is called from interrupt 3138 * handlers to queue more transactions as transfer 3139 * states change. 3140 */ 3141 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3142 gintmsk &= ~GINTSTS_NPTXFEMP; 3143 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3144 } 3145 } 3146 } 3147 3148 /** 3149 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3150 * and queues transactions for these channels to the DWC_otg controller. Called 3151 * from the HCD interrupt handler functions. 3152 * 3153 * @hsotg: The HCD state structure 3154 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3155 * or both) 3156 * 3157 * Must be called with interrupt disabled and spinlock held 3158 */ 3159 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3160 enum dwc2_transaction_type tr_type) 3161 { 3162 #ifdef DWC2_DEBUG_SOF 3163 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3164 #endif 3165 /* Process host channels associated with periodic transfers */ 3166 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3167 tr_type == DWC2_TRANSACTION_ALL) 3168 dwc2_process_periodic_channels(hsotg); 3169 3170 /* Process host channels associated with non-periodic transfers */ 3171 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3172 tr_type == DWC2_TRANSACTION_ALL) { 3173 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3174 dwc2_process_non_periodic_channels(hsotg); 3175 } else { 3176 /* 3177 * Ensure NP Tx FIFO empty interrupt is disabled when 3178 * there are no non-periodic transfers to process 3179 */ 3180 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3181 3182 gintmsk &= ~GINTSTS_NPTXFEMP; 3183 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3184 } 3185 } 3186 } 3187 3188 static void dwc2_conn_id_status_change(struct work_struct *work) 3189 { 3190 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3191 wf_otg); 3192 u32 count = 0; 3193 u32 gotgctl; 3194 unsigned long flags; 3195 3196 dev_dbg(hsotg->dev, "%s()\n", __func__); 3197 3198 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3199 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3200 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3201 !!(gotgctl & GOTGCTL_CONID_B)); 3202 3203 /* B-Device connector (Device Mode) */ 3204 if (gotgctl & GOTGCTL_CONID_B) { 3205 /* Wait for switch to device mode */ 3206 dev_dbg(hsotg->dev, "connId B\n"); 3207 while (!dwc2_is_device_mode(hsotg)) { 3208 dev_info(hsotg->dev, 3209 "Waiting for Peripheral Mode, Mode=%s\n", 3210 dwc2_is_host_mode(hsotg) ? "Host" : 3211 "Peripheral"); 3212 usleep_range(20000, 40000); 3213 if (++count > 250) 3214 break; 3215 } 3216 if (count > 250) 3217 dev_err(hsotg->dev, 3218 "Connection id status change timed out\n"); 3219 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3220 dwc2_core_init(hsotg, false); 3221 dwc2_enable_global_interrupts(hsotg); 3222 spin_lock_irqsave(&hsotg->lock, flags); 3223 dwc2_hsotg_core_init_disconnected(hsotg, false); 3224 spin_unlock_irqrestore(&hsotg->lock, flags); 3225 dwc2_hsotg_core_connect(hsotg); 3226 } else { 3227 /* A-Device connector (Host Mode) */ 3228 dev_dbg(hsotg->dev, "connId A\n"); 3229 while (!dwc2_is_host_mode(hsotg)) { 3230 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3231 dwc2_is_host_mode(hsotg) ? 3232 "Host" : "Peripheral"); 3233 usleep_range(20000, 40000); 3234 if (++count > 250) 3235 break; 3236 } 3237 if (count > 250) 3238 dev_err(hsotg->dev, 3239 "Connection id status change timed out\n"); 3240 hsotg->op_state = OTG_STATE_A_HOST; 3241 3242 /* Initialize the Core for Host mode */ 3243 dwc2_core_init(hsotg, false); 3244 dwc2_enable_global_interrupts(hsotg); 3245 dwc2_hcd_start(hsotg); 3246 } 3247 } 3248 3249 static void dwc2_wakeup_detected(unsigned long data) 3250 { 3251 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 3252 u32 hprt0; 3253 3254 dev_dbg(hsotg->dev, "%s()\n", __func__); 3255 3256 /* 3257 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3258 * so that OPT tests pass with all PHYs.) 3259 */ 3260 hprt0 = dwc2_read_hprt0(hsotg); 3261 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3262 hprt0 &= ~HPRT0_RES; 3263 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3264 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3265 dwc2_readl(hsotg->regs + HPRT0)); 3266 3267 dwc2_hcd_rem_wakeup(hsotg); 3268 hsotg->bus_suspended = 0; 3269 3270 /* Change to L0 state */ 3271 hsotg->lx_state = DWC2_L0; 3272 } 3273 3274 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3275 { 3276 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3277 3278 return hcd->self.b_hnp_enable; 3279 } 3280 3281 /* Must NOT be called with interrupt disabled or spinlock held */ 3282 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3283 { 3284 unsigned long flags; 3285 u32 hprt0; 3286 u32 pcgctl; 3287 u32 gotgctl; 3288 3289 dev_dbg(hsotg->dev, "%s()\n", __func__); 3290 3291 spin_lock_irqsave(&hsotg->lock, flags); 3292 3293 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3294 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3295 gotgctl |= GOTGCTL_HSTSETHNPEN; 3296 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3297 hsotg->op_state = OTG_STATE_A_SUSPEND; 3298 } 3299 3300 hprt0 = dwc2_read_hprt0(hsotg); 3301 hprt0 |= HPRT0_SUSP; 3302 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3303 3304 hsotg->bus_suspended = 1; 3305 3306 /* 3307 * If hibernation is supported, Phy clock will be suspended 3308 * after registers are backuped. 3309 */ 3310 if (!hsotg->core_params->hibernation) { 3311 /* Suspend the Phy Clock */ 3312 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3313 pcgctl |= PCGCTL_STOPPCLK; 3314 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3315 udelay(10); 3316 } 3317 3318 /* For HNP the bus must be suspended for at least 200ms */ 3319 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3320 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3321 pcgctl &= ~PCGCTL_STOPPCLK; 3322 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3323 3324 spin_unlock_irqrestore(&hsotg->lock, flags); 3325 3326 usleep_range(200000, 250000); 3327 } else { 3328 spin_unlock_irqrestore(&hsotg->lock, flags); 3329 } 3330 } 3331 3332 /* Must NOT be called with interrupt disabled or spinlock held */ 3333 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3334 { 3335 unsigned long flags; 3336 u32 hprt0; 3337 u32 pcgctl; 3338 3339 spin_lock_irqsave(&hsotg->lock, flags); 3340 3341 /* 3342 * If hibernation is supported, Phy clock is already resumed 3343 * after registers restore. 3344 */ 3345 if (!hsotg->core_params->hibernation) { 3346 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3347 pcgctl &= ~PCGCTL_STOPPCLK; 3348 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3349 spin_unlock_irqrestore(&hsotg->lock, flags); 3350 usleep_range(20000, 40000); 3351 spin_lock_irqsave(&hsotg->lock, flags); 3352 } 3353 3354 hprt0 = dwc2_read_hprt0(hsotg); 3355 hprt0 |= HPRT0_RES; 3356 hprt0 &= ~HPRT0_SUSP; 3357 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3358 spin_unlock_irqrestore(&hsotg->lock, flags); 3359 3360 msleep(USB_RESUME_TIMEOUT); 3361 3362 spin_lock_irqsave(&hsotg->lock, flags); 3363 hprt0 = dwc2_read_hprt0(hsotg); 3364 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3365 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3366 hsotg->bus_suspended = 0; 3367 spin_unlock_irqrestore(&hsotg->lock, flags); 3368 } 3369 3370 /* Handles hub class-specific requests */ 3371 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3372 u16 wvalue, u16 windex, char *buf, u16 wlength) 3373 { 3374 struct usb_hub_descriptor *hub_desc; 3375 int retval = 0; 3376 u32 hprt0; 3377 u32 port_status; 3378 u32 speed; 3379 u32 pcgctl; 3380 3381 switch (typereq) { 3382 case ClearHubFeature: 3383 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3384 3385 switch (wvalue) { 3386 case C_HUB_LOCAL_POWER: 3387 case C_HUB_OVER_CURRENT: 3388 /* Nothing required here */ 3389 break; 3390 3391 default: 3392 retval = -EINVAL; 3393 dev_err(hsotg->dev, 3394 "ClearHubFeature request %1xh unknown\n", 3395 wvalue); 3396 } 3397 break; 3398 3399 case ClearPortFeature: 3400 if (wvalue != USB_PORT_FEAT_L1) 3401 if (!windex || windex > 1) 3402 goto error; 3403 switch (wvalue) { 3404 case USB_PORT_FEAT_ENABLE: 3405 dev_dbg(hsotg->dev, 3406 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3407 hprt0 = dwc2_read_hprt0(hsotg); 3408 hprt0 |= HPRT0_ENA; 3409 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3410 break; 3411 3412 case USB_PORT_FEAT_SUSPEND: 3413 dev_dbg(hsotg->dev, 3414 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3415 3416 if (hsotg->bus_suspended) 3417 dwc2_port_resume(hsotg); 3418 break; 3419 3420 case USB_PORT_FEAT_POWER: 3421 dev_dbg(hsotg->dev, 3422 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3423 hprt0 = dwc2_read_hprt0(hsotg); 3424 hprt0 &= ~HPRT0_PWR; 3425 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3426 break; 3427 3428 case USB_PORT_FEAT_INDICATOR: 3429 dev_dbg(hsotg->dev, 3430 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3431 /* Port indicator not supported */ 3432 break; 3433 3434 case USB_PORT_FEAT_C_CONNECTION: 3435 /* 3436 * Clears driver's internal Connect Status Change flag 3437 */ 3438 dev_dbg(hsotg->dev, 3439 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3440 hsotg->flags.b.port_connect_status_change = 0; 3441 break; 3442 3443 case USB_PORT_FEAT_C_RESET: 3444 /* Clears driver's internal Port Reset Change flag */ 3445 dev_dbg(hsotg->dev, 3446 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3447 hsotg->flags.b.port_reset_change = 0; 3448 break; 3449 3450 case USB_PORT_FEAT_C_ENABLE: 3451 /* 3452 * Clears the driver's internal Port Enable/Disable 3453 * Change flag 3454 */ 3455 dev_dbg(hsotg->dev, 3456 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3457 hsotg->flags.b.port_enable_change = 0; 3458 break; 3459 3460 case USB_PORT_FEAT_C_SUSPEND: 3461 /* 3462 * Clears the driver's internal Port Suspend Change 3463 * flag, which is set when resume signaling on the host 3464 * port is complete 3465 */ 3466 dev_dbg(hsotg->dev, 3467 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3468 hsotg->flags.b.port_suspend_change = 0; 3469 break; 3470 3471 case USB_PORT_FEAT_C_PORT_L1: 3472 dev_dbg(hsotg->dev, 3473 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3474 hsotg->flags.b.port_l1_change = 0; 3475 break; 3476 3477 case USB_PORT_FEAT_C_OVER_CURRENT: 3478 dev_dbg(hsotg->dev, 3479 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3480 hsotg->flags.b.port_over_current_change = 0; 3481 break; 3482 3483 default: 3484 retval = -EINVAL; 3485 dev_err(hsotg->dev, 3486 "ClearPortFeature request %1xh unknown or unsupported\n", 3487 wvalue); 3488 } 3489 break; 3490 3491 case GetHubDescriptor: 3492 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3493 hub_desc = (struct usb_hub_descriptor *)buf; 3494 hub_desc->bDescLength = 9; 3495 hub_desc->bDescriptorType = USB_DT_HUB; 3496 hub_desc->bNbrPorts = 1; 3497 hub_desc->wHubCharacteristics = 3498 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3499 HUB_CHAR_INDV_PORT_OCPM); 3500 hub_desc->bPwrOn2PwrGood = 1; 3501 hub_desc->bHubContrCurrent = 0; 3502 hub_desc->u.hs.DeviceRemovable[0] = 0; 3503 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3504 break; 3505 3506 case GetHubStatus: 3507 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3508 memset(buf, 0, 4); 3509 break; 3510 3511 case GetPortStatus: 3512 dev_vdbg(hsotg->dev, 3513 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3514 hsotg->flags.d32); 3515 if (!windex || windex > 1) 3516 goto error; 3517 3518 port_status = 0; 3519 if (hsotg->flags.b.port_connect_status_change) 3520 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3521 if (hsotg->flags.b.port_enable_change) 3522 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3523 if (hsotg->flags.b.port_suspend_change) 3524 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3525 if (hsotg->flags.b.port_l1_change) 3526 port_status |= USB_PORT_STAT_C_L1 << 16; 3527 if (hsotg->flags.b.port_reset_change) 3528 port_status |= USB_PORT_STAT_C_RESET << 16; 3529 if (hsotg->flags.b.port_over_current_change) { 3530 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3531 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3532 } 3533 3534 if (!hsotg->flags.b.port_connect_status) { 3535 /* 3536 * The port is disconnected, which means the core is 3537 * either in device mode or it soon will be. Just 3538 * return 0's for the remainder of the port status 3539 * since the port register can't be read if the core 3540 * is in device mode. 3541 */ 3542 *(__le32 *)buf = cpu_to_le32(port_status); 3543 break; 3544 } 3545 3546 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3547 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3548 3549 if (hprt0 & HPRT0_CONNSTS) 3550 port_status |= USB_PORT_STAT_CONNECTION; 3551 if (hprt0 & HPRT0_ENA) 3552 port_status |= USB_PORT_STAT_ENABLE; 3553 if (hprt0 & HPRT0_SUSP) 3554 port_status |= USB_PORT_STAT_SUSPEND; 3555 if (hprt0 & HPRT0_OVRCURRACT) 3556 port_status |= USB_PORT_STAT_OVERCURRENT; 3557 if (hprt0 & HPRT0_RST) 3558 port_status |= USB_PORT_STAT_RESET; 3559 if (hprt0 & HPRT0_PWR) 3560 port_status |= USB_PORT_STAT_POWER; 3561 3562 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3563 if (speed == HPRT0_SPD_HIGH_SPEED) 3564 port_status |= USB_PORT_STAT_HIGH_SPEED; 3565 else if (speed == HPRT0_SPD_LOW_SPEED) 3566 port_status |= USB_PORT_STAT_LOW_SPEED; 3567 3568 if (hprt0 & HPRT0_TSTCTL_MASK) 3569 port_status |= USB_PORT_STAT_TEST; 3570 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3571 3572 if (hsotg->core_params->dma_desc_fs_enable) { 3573 /* 3574 * Enable descriptor DMA only if a full speed 3575 * device is connected. 3576 */ 3577 if (hsotg->new_connection && 3578 ((port_status & 3579 (USB_PORT_STAT_CONNECTION | 3580 USB_PORT_STAT_HIGH_SPEED | 3581 USB_PORT_STAT_LOW_SPEED)) == 3582 USB_PORT_STAT_CONNECTION)) { 3583 u32 hcfg; 3584 3585 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3586 hsotg->core_params->dma_desc_enable = 1; 3587 hcfg = dwc2_readl(hsotg->regs + HCFG); 3588 hcfg |= HCFG_DESCDMA; 3589 dwc2_writel(hcfg, hsotg->regs + HCFG); 3590 hsotg->new_connection = false; 3591 } 3592 } 3593 3594 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3595 *(__le32 *)buf = cpu_to_le32(port_status); 3596 break; 3597 3598 case SetHubFeature: 3599 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3600 /* No HUB features supported */ 3601 break; 3602 3603 case SetPortFeature: 3604 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3605 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3606 goto error; 3607 3608 if (!hsotg->flags.b.port_connect_status) { 3609 /* 3610 * The port is disconnected, which means the core is 3611 * either in device mode or it soon will be. Just 3612 * return without doing anything since the port 3613 * register can't be written if the core is in device 3614 * mode. 3615 */ 3616 break; 3617 } 3618 3619 switch (wvalue) { 3620 case USB_PORT_FEAT_SUSPEND: 3621 dev_dbg(hsotg->dev, 3622 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3623 if (windex != hsotg->otg_port) 3624 goto error; 3625 dwc2_port_suspend(hsotg, windex); 3626 break; 3627 3628 case USB_PORT_FEAT_POWER: 3629 dev_dbg(hsotg->dev, 3630 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3631 hprt0 = dwc2_read_hprt0(hsotg); 3632 hprt0 |= HPRT0_PWR; 3633 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3634 break; 3635 3636 case USB_PORT_FEAT_RESET: 3637 hprt0 = dwc2_read_hprt0(hsotg); 3638 dev_dbg(hsotg->dev, 3639 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3640 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3641 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3642 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3643 /* ??? Original driver does this */ 3644 dwc2_writel(0, hsotg->regs + PCGCTL); 3645 3646 hprt0 = dwc2_read_hprt0(hsotg); 3647 /* Clear suspend bit if resetting from suspend state */ 3648 hprt0 &= ~HPRT0_SUSP; 3649 3650 /* 3651 * When B-Host the Port reset bit is set in the Start 3652 * HCD Callback function, so that the reset is started 3653 * within 1ms of the HNP success interrupt 3654 */ 3655 if (!dwc2_hcd_is_b_host(hsotg)) { 3656 hprt0 |= HPRT0_PWR | HPRT0_RST; 3657 dev_dbg(hsotg->dev, 3658 "In host mode, hprt0=%08x\n", hprt0); 3659 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3660 } 3661 3662 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3663 usleep_range(50000, 70000); 3664 hprt0 &= ~HPRT0_RST; 3665 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3666 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3667 break; 3668 3669 case USB_PORT_FEAT_INDICATOR: 3670 dev_dbg(hsotg->dev, 3671 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3672 /* Not supported */ 3673 break; 3674 3675 case USB_PORT_FEAT_TEST: 3676 hprt0 = dwc2_read_hprt0(hsotg); 3677 dev_dbg(hsotg->dev, 3678 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3679 hprt0 &= ~HPRT0_TSTCTL_MASK; 3680 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3681 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3682 break; 3683 3684 default: 3685 retval = -EINVAL; 3686 dev_err(hsotg->dev, 3687 "SetPortFeature %1xh unknown or unsupported\n", 3688 wvalue); 3689 break; 3690 } 3691 break; 3692 3693 default: 3694 error: 3695 retval = -EINVAL; 3696 dev_dbg(hsotg->dev, 3697 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3698 typereq, windex, wvalue); 3699 break; 3700 } 3701 3702 return retval; 3703 } 3704 3705 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3706 { 3707 int retval; 3708 3709 if (port != 1) 3710 return -EINVAL; 3711 3712 retval = (hsotg->flags.b.port_connect_status_change || 3713 hsotg->flags.b.port_reset_change || 3714 hsotg->flags.b.port_enable_change || 3715 hsotg->flags.b.port_suspend_change || 3716 hsotg->flags.b.port_over_current_change); 3717 3718 if (retval) { 3719 dev_dbg(hsotg->dev, 3720 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3721 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3722 hsotg->flags.b.port_connect_status_change); 3723 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3724 hsotg->flags.b.port_reset_change); 3725 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3726 hsotg->flags.b.port_enable_change); 3727 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3728 hsotg->flags.b.port_suspend_change); 3729 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3730 hsotg->flags.b.port_over_current_change); 3731 } 3732 3733 return retval; 3734 } 3735 3736 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3737 { 3738 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3739 3740 #ifdef DWC2_DEBUG_SOF 3741 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3742 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3743 #endif 3744 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3745 } 3746 3747 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3748 { 3749 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3750 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3751 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3752 unsigned int us_per_frame; 3753 unsigned int frame_number; 3754 unsigned int remaining; 3755 unsigned int interval; 3756 unsigned int phy_clks; 3757 3758 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3759 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3760 3761 /* Extract fields */ 3762 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3763 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3764 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3765 3766 /* 3767 * Number of phy clocks since the last tick of the frame number after 3768 * "us" has passed. 3769 */ 3770 phy_clks = (interval - remaining) + 3771 DIV_ROUND_UP(interval * us, us_per_frame); 3772 3773 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3774 } 3775 3776 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3777 { 3778 return hsotg->op_state == OTG_STATE_B_HOST; 3779 } 3780 3781 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3782 int iso_desc_count, 3783 gfp_t mem_flags) 3784 { 3785 struct dwc2_hcd_urb *urb; 3786 u32 size = sizeof(*urb) + iso_desc_count * 3787 sizeof(struct dwc2_hcd_iso_packet_desc); 3788 3789 urb = kzalloc(size, mem_flags); 3790 if (urb) 3791 urb->packet_count = iso_desc_count; 3792 return urb; 3793 } 3794 3795 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3796 struct dwc2_hcd_urb *urb, u8 dev_addr, 3797 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3798 { 3799 if (dbg_perio() || 3800 ep_type == USB_ENDPOINT_XFER_BULK || 3801 ep_type == USB_ENDPOINT_XFER_CONTROL) 3802 dev_vdbg(hsotg->dev, 3803 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3804 dev_addr, ep_num, ep_dir, ep_type, mps); 3805 urb->pipe_info.dev_addr = dev_addr; 3806 urb->pipe_info.ep_num = ep_num; 3807 urb->pipe_info.pipe_type = ep_type; 3808 urb->pipe_info.pipe_dir = ep_dir; 3809 urb->pipe_info.mps = mps; 3810 } 3811 3812 /* 3813 * NOTE: This function will be removed once the peripheral controller code 3814 * is integrated and the driver is stable 3815 */ 3816 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3817 { 3818 #ifdef DEBUG 3819 struct dwc2_host_chan *chan; 3820 struct dwc2_hcd_urb *urb; 3821 struct dwc2_qtd *qtd; 3822 int num_channels; 3823 u32 np_tx_status; 3824 u32 p_tx_status; 3825 int i; 3826 3827 num_channels = hsotg->core_params->host_channels; 3828 dev_dbg(hsotg->dev, "\n"); 3829 dev_dbg(hsotg->dev, 3830 "************************************************************\n"); 3831 dev_dbg(hsotg->dev, "HCD State:\n"); 3832 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3833 3834 for (i = 0; i < num_channels; i++) { 3835 chan = hsotg->hc_ptr_array[i]; 3836 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3837 dev_dbg(hsotg->dev, 3838 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3839 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3840 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3841 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3842 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3843 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3844 chan->data_pid_start); 3845 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3846 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3847 chan->xfer_started); 3848 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3849 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3850 (unsigned long)chan->xfer_dma); 3851 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3852 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3853 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3854 chan->halt_on_queue); 3855 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3856 chan->halt_pending); 3857 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3858 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3859 dev_dbg(hsotg->dev, " complete_split: %d\n", 3860 chan->complete_split); 3861 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3862 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3863 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3864 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3865 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3866 3867 if (chan->xfer_started) { 3868 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3869 3870 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3871 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3872 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3873 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3874 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3875 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3876 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3877 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3878 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3879 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3880 } 3881 3882 if (!(chan->xfer_started && chan->qh)) 3883 continue; 3884 3885 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3886 if (!qtd->in_process) 3887 break; 3888 urb = qtd->urb; 3889 dev_dbg(hsotg->dev, " URB Info:\n"); 3890 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3891 qtd, urb); 3892 if (urb) { 3893 dev_dbg(hsotg->dev, 3894 " Dev: %d, EP: %d %s\n", 3895 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3896 dwc2_hcd_get_ep_num(&urb->pipe_info), 3897 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3898 "IN" : "OUT"); 3899 dev_dbg(hsotg->dev, 3900 " Max packet size: %d\n", 3901 dwc2_hcd_get_mps(&urb->pipe_info)); 3902 dev_dbg(hsotg->dev, 3903 " transfer_buffer: %p\n", 3904 urb->buf); 3905 dev_dbg(hsotg->dev, 3906 " transfer_dma: %08lx\n", 3907 (unsigned long)urb->dma); 3908 dev_dbg(hsotg->dev, 3909 " transfer_buffer_length: %d\n", 3910 urb->length); 3911 dev_dbg(hsotg->dev, " actual_length: %d\n", 3912 urb->actual_length); 3913 } 3914 } 3915 } 3916 3917 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3918 hsotg->non_periodic_channels); 3919 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3920 hsotg->periodic_channels); 3921 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3922 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3923 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3924 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3925 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3926 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3927 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3928 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3929 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3930 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3931 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3932 dwc2_hcd_dump_frrem(hsotg); 3933 dwc2_dump_global_registers(hsotg); 3934 dwc2_dump_host_registers(hsotg); 3935 dev_dbg(hsotg->dev, 3936 "************************************************************\n"); 3937 dev_dbg(hsotg->dev, "\n"); 3938 #endif 3939 } 3940 3941 /* 3942 * NOTE: This function will be removed once the peripheral controller code 3943 * is integrated and the driver is stable 3944 */ 3945 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 3946 { 3947 #ifdef DWC2_DUMP_FRREM 3948 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 3949 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3950 hsotg->frrem_samples, hsotg->frrem_accum, 3951 hsotg->frrem_samples > 0 ? 3952 hsotg->frrem_accum / hsotg->frrem_samples : 0); 3953 dev_dbg(hsotg->dev, "\n"); 3954 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 3955 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3956 hsotg->hfnum_7_samples, 3957 hsotg->hfnum_7_frrem_accum, 3958 hsotg->hfnum_7_samples > 0 ? 3959 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 3960 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 3961 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3962 hsotg->hfnum_0_samples, 3963 hsotg->hfnum_0_frrem_accum, 3964 hsotg->hfnum_0_samples > 0 ? 3965 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 3966 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 3967 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3968 hsotg->hfnum_other_samples, 3969 hsotg->hfnum_other_frrem_accum, 3970 hsotg->hfnum_other_samples > 0 ? 3971 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 3972 0); 3973 dev_dbg(hsotg->dev, "\n"); 3974 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 3975 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3976 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 3977 hsotg->hfnum_7_samples_a > 0 ? 3978 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 3979 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 3980 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3981 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 3982 hsotg->hfnum_0_samples_a > 0 ? 3983 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 3984 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 3985 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3986 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 3987 hsotg->hfnum_other_samples_a > 0 ? 3988 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 3989 : 0); 3990 dev_dbg(hsotg->dev, "\n"); 3991 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 3992 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3993 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 3994 hsotg->hfnum_7_samples_b > 0 ? 3995 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 3996 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 3997 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3998 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 3999 (hsotg->hfnum_0_samples_b > 0) ? 4000 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4001 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4002 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4003 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4004 (hsotg->hfnum_other_samples_b > 0) ? 4005 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4006 : 0); 4007 #endif 4008 } 4009 4010 struct wrapper_priv_data { 4011 struct dwc2_hsotg *hsotg; 4012 }; 4013 4014 /* Gets the dwc2_hsotg from a usb_hcd */ 4015 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4016 { 4017 struct wrapper_priv_data *p; 4018 4019 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 4020 return p->hsotg; 4021 } 4022 4023 static int _dwc2_hcd_start(struct usb_hcd *hcd); 4024 4025 void dwc2_host_start(struct dwc2_hsotg *hsotg) 4026 { 4027 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 4028 4029 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 4030 _dwc2_hcd_start(hcd); 4031 } 4032 4033 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 4034 { 4035 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 4036 4037 hcd->self.is_b_host = 0; 4038 } 4039 4040 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 4041 int *hub_port) 4042 { 4043 struct urb *urb = context; 4044 4045 if (urb->dev->tt) 4046 *hub_addr = urb->dev->tt->hub->devnum; 4047 else 4048 *hub_addr = 0; 4049 *hub_port = urb->dev->ttport; 4050 } 4051 4052 /** 4053 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4054 * 4055 * This will get the dwc2_tt structure (and ttport) associated with the given 4056 * context (which is really just a struct urb pointer). 4057 * 4058 * The first time this is called for a given TT we allocate memory for our 4059 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4060 * then the refcount for the structure will go to 0 and we'll free it. 4061 * 4062 * @hsotg: The HCD state structure for the DWC OTG controller. 4063 * @qh: The QH structure. 4064 * @context: The priv pointer from a struct dwc2_hcd_urb. 4065 * @mem_flags: Flags for allocating memory. 4066 * @ttport: We'll return this device's port number here. That's used to 4067 * reference into the bitmap if we're on a multi_tt hub. 4068 * 4069 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4070 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4071 */ 4072 4073 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4074 gfp_t mem_flags, int *ttport) 4075 { 4076 struct urb *urb = context; 4077 struct dwc2_tt *dwc_tt = NULL; 4078 4079 if (urb->dev->tt) { 4080 *ttport = urb->dev->ttport; 4081 4082 dwc_tt = urb->dev->tt->hcpriv; 4083 if (dwc_tt == NULL) { 4084 size_t bitmap_size; 4085 4086 /* 4087 * For single_tt we need one schedule. For multi_tt 4088 * we need one per port. 4089 */ 4090 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4091 sizeof(dwc_tt->periodic_bitmaps[0]); 4092 if (urb->dev->tt->multi) 4093 bitmap_size *= urb->dev->tt->hub->maxchild; 4094 4095 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4096 mem_flags); 4097 if (dwc_tt == NULL) 4098 return NULL; 4099 4100 dwc_tt->usb_tt = urb->dev->tt; 4101 dwc_tt->usb_tt->hcpriv = dwc_tt; 4102 } 4103 4104 dwc_tt->refcount++; 4105 } 4106 4107 return dwc_tt; 4108 } 4109 4110 /** 4111 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4112 * 4113 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4114 * of the structure are done. 4115 * 4116 * It's OK to call this with NULL. 4117 * 4118 * @hsotg: The HCD state structure for the DWC OTG controller. 4119 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4120 */ 4121 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4122 { 4123 /* Model kfree and make put of NULL a no-op */ 4124 if (dwc_tt == NULL) 4125 return; 4126 4127 WARN_ON(dwc_tt->refcount < 1); 4128 4129 dwc_tt->refcount--; 4130 if (!dwc_tt->refcount) { 4131 dwc_tt->usb_tt->hcpriv = NULL; 4132 kfree(dwc_tt); 4133 } 4134 } 4135 4136 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4137 { 4138 struct urb *urb = context; 4139 4140 return urb->dev->speed; 4141 } 4142 4143 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4144 struct urb *urb) 4145 { 4146 struct usb_bus *bus = hcd_to_bus(hcd); 4147 4148 if (urb->interval) 4149 bus->bandwidth_allocated += bw / urb->interval; 4150 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4151 bus->bandwidth_isoc_reqs++; 4152 else 4153 bus->bandwidth_int_reqs++; 4154 } 4155 4156 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4157 struct urb *urb) 4158 { 4159 struct usb_bus *bus = hcd_to_bus(hcd); 4160 4161 if (urb->interval) 4162 bus->bandwidth_allocated -= bw / urb->interval; 4163 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4164 bus->bandwidth_isoc_reqs--; 4165 else 4166 bus->bandwidth_int_reqs--; 4167 } 4168 4169 /* 4170 * Sets the final status of an URB and returns it to the upper layer. Any 4171 * required cleanup of the URB is performed. 4172 * 4173 * Must be called with interrupt disabled and spinlock held 4174 */ 4175 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4176 int status) 4177 { 4178 struct urb *urb; 4179 int i; 4180 4181 if (!qtd) { 4182 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4183 return; 4184 } 4185 4186 if (!qtd->urb) { 4187 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4188 return; 4189 } 4190 4191 urb = qtd->urb->priv; 4192 if (!urb) { 4193 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4194 return; 4195 } 4196 4197 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4198 4199 if (dbg_urb(urb)) 4200 dev_vdbg(hsotg->dev, 4201 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4202 __func__, urb, usb_pipedevice(urb->pipe), 4203 usb_pipeendpoint(urb->pipe), 4204 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4205 urb->actual_length); 4206 4207 4208 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4209 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4210 for (i = 0; i < urb->number_of_packets; ++i) { 4211 urb->iso_frame_desc[i].actual_length = 4212 dwc2_hcd_urb_get_iso_desc_actual_length( 4213 qtd->urb, i); 4214 urb->iso_frame_desc[i].status = 4215 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4216 } 4217 } 4218 4219 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4220 for (i = 0; i < urb->number_of_packets; i++) 4221 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4222 i, urb->iso_frame_desc[i].status); 4223 } 4224 4225 urb->status = status; 4226 if (!status) { 4227 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4228 urb->actual_length < urb->transfer_buffer_length) 4229 urb->status = -EREMOTEIO; 4230 } 4231 4232 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4233 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4234 struct usb_host_endpoint *ep = urb->ep; 4235 4236 if (ep) 4237 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4238 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4239 urb); 4240 } 4241 4242 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4243 urb->hcpriv = NULL; 4244 kfree(qtd->urb); 4245 qtd->urb = NULL; 4246 4247 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4248 } 4249 4250 /* 4251 * Work queue function for starting the HCD when A-Cable is connected 4252 */ 4253 static void dwc2_hcd_start_func(struct work_struct *work) 4254 { 4255 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4256 start_work.work); 4257 4258 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4259 dwc2_host_start(hsotg); 4260 } 4261 4262 /* 4263 * Reset work queue function 4264 */ 4265 static void dwc2_hcd_reset_func(struct work_struct *work) 4266 { 4267 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4268 reset_work.work); 4269 unsigned long flags; 4270 u32 hprt0; 4271 4272 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4273 4274 spin_lock_irqsave(&hsotg->lock, flags); 4275 4276 hprt0 = dwc2_read_hprt0(hsotg); 4277 hprt0 &= ~HPRT0_RST; 4278 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4279 hsotg->flags.b.port_reset_change = 1; 4280 4281 spin_unlock_irqrestore(&hsotg->lock, flags); 4282 } 4283 4284 /* 4285 * ========================================================================= 4286 * Linux HC Driver Functions 4287 * ========================================================================= 4288 */ 4289 4290 /* 4291 * Initializes the DWC_otg controller and its root hub and prepares it for host 4292 * mode operation. Activates the root port. Returns 0 on success and a negative 4293 * error code on failure. 4294 */ 4295 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4296 { 4297 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4298 struct usb_bus *bus = hcd_to_bus(hcd); 4299 unsigned long flags; 4300 4301 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4302 4303 spin_lock_irqsave(&hsotg->lock, flags); 4304 hsotg->lx_state = DWC2_L0; 4305 hcd->state = HC_STATE_RUNNING; 4306 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4307 4308 if (dwc2_is_device_mode(hsotg)) { 4309 spin_unlock_irqrestore(&hsotg->lock, flags); 4310 return 0; /* why 0 ?? */ 4311 } 4312 4313 dwc2_hcd_reinit(hsotg); 4314 4315 /* Initialize and connect root hub if one is not already attached */ 4316 if (bus->root_hub) { 4317 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4318 /* Inform the HUB driver to resume */ 4319 usb_hcd_resume_root_hub(hcd); 4320 } 4321 4322 spin_unlock_irqrestore(&hsotg->lock, flags); 4323 return 0; 4324 } 4325 4326 /* 4327 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4328 * stopped. 4329 */ 4330 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4331 { 4332 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4333 unsigned long flags; 4334 4335 /* Turn off all host-specific interrupts */ 4336 dwc2_disable_host_interrupts(hsotg); 4337 4338 /* Wait for interrupt processing to finish */ 4339 synchronize_irq(hcd->irq); 4340 4341 spin_lock_irqsave(&hsotg->lock, flags); 4342 /* Ensure hcd is disconnected */ 4343 dwc2_hcd_disconnect(hsotg, true); 4344 dwc2_hcd_stop(hsotg); 4345 hsotg->lx_state = DWC2_L3; 4346 hcd->state = HC_STATE_HALT; 4347 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4348 spin_unlock_irqrestore(&hsotg->lock, flags); 4349 4350 usleep_range(1000, 3000); 4351 } 4352 4353 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4354 { 4355 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4356 unsigned long flags; 4357 int ret = 0; 4358 u32 hprt0; 4359 4360 spin_lock_irqsave(&hsotg->lock, flags); 4361 4362 if (hsotg->lx_state != DWC2_L0) 4363 goto unlock; 4364 4365 if (!HCD_HW_ACCESSIBLE(hcd)) 4366 goto unlock; 4367 4368 if (!hsotg->core_params->hibernation) 4369 goto skip_power_saving; 4370 4371 /* 4372 * Drive USB suspend and disable port Power 4373 * if usb bus is not suspended. 4374 */ 4375 if (!hsotg->bus_suspended) { 4376 hprt0 = dwc2_read_hprt0(hsotg); 4377 hprt0 |= HPRT0_SUSP; 4378 hprt0 &= ~HPRT0_PWR; 4379 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4380 } 4381 4382 /* Enter hibernation */ 4383 ret = dwc2_enter_hibernation(hsotg); 4384 if (ret) { 4385 if (ret != -ENOTSUPP) 4386 dev_err(hsotg->dev, 4387 "enter hibernation failed\n"); 4388 goto skip_power_saving; 4389 } 4390 4391 /* Ask phy to be suspended */ 4392 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4393 spin_unlock_irqrestore(&hsotg->lock, flags); 4394 usb_phy_set_suspend(hsotg->uphy, true); 4395 spin_lock_irqsave(&hsotg->lock, flags); 4396 } 4397 4398 /* After entering hibernation, hardware is no more accessible */ 4399 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4400 4401 skip_power_saving: 4402 hsotg->lx_state = DWC2_L2; 4403 unlock: 4404 spin_unlock_irqrestore(&hsotg->lock, flags); 4405 4406 return ret; 4407 } 4408 4409 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4410 { 4411 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4412 unsigned long flags; 4413 int ret = 0; 4414 4415 spin_lock_irqsave(&hsotg->lock, flags); 4416 4417 if (hsotg->lx_state != DWC2_L2) 4418 goto unlock; 4419 4420 if (!hsotg->core_params->hibernation) { 4421 hsotg->lx_state = DWC2_L0; 4422 goto unlock; 4423 } 4424 4425 /* 4426 * Set HW accessible bit before powering on the controller 4427 * since an interrupt may rise. 4428 */ 4429 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4430 4431 /* 4432 * Enable power if not already done. 4433 * This must not be spinlocked since duration 4434 * of this call is unknown. 4435 */ 4436 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4437 spin_unlock_irqrestore(&hsotg->lock, flags); 4438 usb_phy_set_suspend(hsotg->uphy, false); 4439 spin_lock_irqsave(&hsotg->lock, flags); 4440 } 4441 4442 /* Exit hibernation */ 4443 ret = dwc2_exit_hibernation(hsotg, true); 4444 if (ret && (ret != -ENOTSUPP)) 4445 dev_err(hsotg->dev, "exit hibernation failed\n"); 4446 4447 hsotg->lx_state = DWC2_L0; 4448 4449 spin_unlock_irqrestore(&hsotg->lock, flags); 4450 4451 if (hsotg->bus_suspended) { 4452 spin_lock_irqsave(&hsotg->lock, flags); 4453 hsotg->flags.b.port_suspend_change = 1; 4454 spin_unlock_irqrestore(&hsotg->lock, flags); 4455 dwc2_port_resume(hsotg); 4456 } else { 4457 /* Wait for controller to correctly update D+/D- level */ 4458 usleep_range(3000, 5000); 4459 4460 /* 4461 * Clear Port Enable and Port Status changes. 4462 * Enable Port Power. 4463 */ 4464 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4465 HPRT0_ENACHG, hsotg->regs + HPRT0); 4466 /* Wait for controller to detect Port Connect */ 4467 usleep_range(5000, 7000); 4468 } 4469 4470 return ret; 4471 unlock: 4472 spin_unlock_irqrestore(&hsotg->lock, flags); 4473 4474 return ret; 4475 } 4476 4477 /* Returns the current frame number */ 4478 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4479 { 4480 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4481 4482 return dwc2_hcd_get_frame_number(hsotg); 4483 } 4484 4485 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4486 char *fn_name) 4487 { 4488 #ifdef VERBOSE_DEBUG 4489 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4490 char *pipetype; 4491 char *speed; 4492 4493 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4494 dev_vdbg(hsotg->dev, " Device address: %d\n", 4495 usb_pipedevice(urb->pipe)); 4496 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4497 usb_pipeendpoint(urb->pipe), 4498 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4499 4500 switch (usb_pipetype(urb->pipe)) { 4501 case PIPE_CONTROL: 4502 pipetype = "CONTROL"; 4503 break; 4504 case PIPE_BULK: 4505 pipetype = "BULK"; 4506 break; 4507 case PIPE_INTERRUPT: 4508 pipetype = "INTERRUPT"; 4509 break; 4510 case PIPE_ISOCHRONOUS: 4511 pipetype = "ISOCHRONOUS"; 4512 break; 4513 default: 4514 pipetype = "UNKNOWN"; 4515 break; 4516 } 4517 4518 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4519 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4520 "IN" : "OUT"); 4521 4522 switch (urb->dev->speed) { 4523 case USB_SPEED_HIGH: 4524 speed = "HIGH"; 4525 break; 4526 case USB_SPEED_FULL: 4527 speed = "FULL"; 4528 break; 4529 case USB_SPEED_LOW: 4530 speed = "LOW"; 4531 break; 4532 default: 4533 speed = "UNKNOWN"; 4534 break; 4535 } 4536 4537 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4538 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4539 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4540 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4541 urb->transfer_buffer_length); 4542 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4543 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4544 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4545 urb->setup_packet, (unsigned long)urb->setup_dma); 4546 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4547 4548 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4549 int i; 4550 4551 for (i = 0; i < urb->number_of_packets; i++) { 4552 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4553 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4554 urb->iso_frame_desc[i].offset, 4555 urb->iso_frame_desc[i].length); 4556 } 4557 } 4558 #endif 4559 } 4560 4561 /* 4562 * Starts processing a USB transfer request specified by a USB Request Block 4563 * (URB). mem_flags indicates the type of memory allocation to use while 4564 * processing this URB. 4565 */ 4566 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4567 gfp_t mem_flags) 4568 { 4569 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4570 struct usb_host_endpoint *ep = urb->ep; 4571 struct dwc2_hcd_urb *dwc2_urb; 4572 int i; 4573 int retval; 4574 int alloc_bandwidth = 0; 4575 u8 ep_type = 0; 4576 u32 tflags = 0; 4577 void *buf; 4578 unsigned long flags; 4579 struct dwc2_qh *qh; 4580 bool qh_allocated = false; 4581 struct dwc2_qtd *qtd; 4582 4583 if (dbg_urb(urb)) { 4584 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4585 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4586 } 4587 4588 if (ep == NULL) 4589 return -EINVAL; 4590 4591 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4592 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4593 spin_lock_irqsave(&hsotg->lock, flags); 4594 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4595 alloc_bandwidth = 1; 4596 spin_unlock_irqrestore(&hsotg->lock, flags); 4597 } 4598 4599 switch (usb_pipetype(urb->pipe)) { 4600 case PIPE_CONTROL: 4601 ep_type = USB_ENDPOINT_XFER_CONTROL; 4602 break; 4603 case PIPE_ISOCHRONOUS: 4604 ep_type = USB_ENDPOINT_XFER_ISOC; 4605 break; 4606 case PIPE_BULK: 4607 ep_type = USB_ENDPOINT_XFER_BULK; 4608 break; 4609 case PIPE_INTERRUPT: 4610 ep_type = USB_ENDPOINT_XFER_INT; 4611 break; 4612 default: 4613 dev_warn(hsotg->dev, "Wrong ep type\n"); 4614 } 4615 4616 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4617 mem_flags); 4618 if (!dwc2_urb) 4619 return -ENOMEM; 4620 4621 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4622 usb_pipeendpoint(urb->pipe), ep_type, 4623 usb_pipein(urb->pipe), 4624 usb_maxpacket(urb->dev, urb->pipe, 4625 !(usb_pipein(urb->pipe)))); 4626 4627 buf = urb->transfer_buffer; 4628 4629 if (hcd->self.uses_dma) { 4630 if (!buf && (urb->transfer_dma & 3)) { 4631 dev_err(hsotg->dev, 4632 "%s: unaligned transfer with no transfer_buffer", 4633 __func__); 4634 retval = -EINVAL; 4635 goto fail0; 4636 } 4637 } 4638 4639 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4640 tflags |= URB_GIVEBACK_ASAP; 4641 if (urb->transfer_flags & URB_ZERO_PACKET) 4642 tflags |= URB_SEND_ZERO_PACKET; 4643 4644 dwc2_urb->priv = urb; 4645 dwc2_urb->buf = buf; 4646 dwc2_urb->dma = urb->transfer_dma; 4647 dwc2_urb->length = urb->transfer_buffer_length; 4648 dwc2_urb->setup_packet = urb->setup_packet; 4649 dwc2_urb->setup_dma = urb->setup_dma; 4650 dwc2_urb->flags = tflags; 4651 dwc2_urb->interval = urb->interval; 4652 dwc2_urb->status = -EINPROGRESS; 4653 4654 for (i = 0; i < urb->number_of_packets; ++i) 4655 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4656 urb->iso_frame_desc[i].offset, 4657 urb->iso_frame_desc[i].length); 4658 4659 urb->hcpriv = dwc2_urb; 4660 qh = (struct dwc2_qh *) ep->hcpriv; 4661 /* Create QH for the endpoint if it doesn't exist */ 4662 if (!qh) { 4663 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4664 if (!qh) { 4665 retval = -ENOMEM; 4666 goto fail0; 4667 } 4668 ep->hcpriv = qh; 4669 qh_allocated = true; 4670 } 4671 4672 qtd = kzalloc(sizeof(*qtd), mem_flags); 4673 if (!qtd) { 4674 retval = -ENOMEM; 4675 goto fail1; 4676 } 4677 4678 spin_lock_irqsave(&hsotg->lock, flags); 4679 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4680 if (retval) 4681 goto fail2; 4682 4683 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4684 if (retval) 4685 goto fail3; 4686 4687 if (alloc_bandwidth) { 4688 dwc2_allocate_bus_bandwidth(hcd, 4689 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4690 urb); 4691 } 4692 4693 spin_unlock_irqrestore(&hsotg->lock, flags); 4694 4695 return 0; 4696 4697 fail3: 4698 dwc2_urb->priv = NULL; 4699 usb_hcd_unlink_urb_from_ep(hcd, urb); 4700 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4701 qh->channel->qh = NULL; 4702 fail2: 4703 spin_unlock_irqrestore(&hsotg->lock, flags); 4704 urb->hcpriv = NULL; 4705 kfree(qtd); 4706 qtd = NULL; 4707 fail1: 4708 if (qh_allocated) { 4709 struct dwc2_qtd *qtd2, *qtd2_tmp; 4710 4711 ep->hcpriv = NULL; 4712 dwc2_hcd_qh_unlink(hsotg, qh); 4713 /* Free each QTD in the QH's QTD list */ 4714 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4715 qtd_list_entry) 4716 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4717 dwc2_hcd_qh_free(hsotg, qh); 4718 } 4719 fail0: 4720 kfree(dwc2_urb); 4721 4722 return retval; 4723 } 4724 4725 /* 4726 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4727 */ 4728 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4729 int status) 4730 { 4731 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4732 int rc; 4733 unsigned long flags; 4734 4735 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4736 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4737 4738 spin_lock_irqsave(&hsotg->lock, flags); 4739 4740 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4741 if (rc) 4742 goto out; 4743 4744 if (!urb->hcpriv) { 4745 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4746 goto out; 4747 } 4748 4749 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4750 4751 usb_hcd_unlink_urb_from_ep(hcd, urb); 4752 4753 kfree(urb->hcpriv); 4754 urb->hcpriv = NULL; 4755 4756 /* Higher layer software sets URB status */ 4757 spin_unlock(&hsotg->lock); 4758 usb_hcd_giveback_urb(hcd, urb, status); 4759 spin_lock(&hsotg->lock); 4760 4761 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4762 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4763 out: 4764 spin_unlock_irqrestore(&hsotg->lock, flags); 4765 4766 return rc; 4767 } 4768 4769 /* 4770 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4771 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4772 * must already be dequeued. 4773 */ 4774 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4775 struct usb_host_endpoint *ep) 4776 { 4777 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4778 4779 dev_dbg(hsotg->dev, 4780 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4781 ep->desc.bEndpointAddress, ep->hcpriv); 4782 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4783 } 4784 4785 /* 4786 * Resets endpoint specific parameter values, in current version used to reset 4787 * the data toggle (as a WA). This function can be called from usb_clear_halt 4788 * routine. 4789 */ 4790 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4791 struct usb_host_endpoint *ep) 4792 { 4793 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4794 unsigned long flags; 4795 4796 dev_dbg(hsotg->dev, 4797 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4798 ep->desc.bEndpointAddress); 4799 4800 spin_lock_irqsave(&hsotg->lock, flags); 4801 dwc2_hcd_endpoint_reset(hsotg, ep); 4802 spin_unlock_irqrestore(&hsotg->lock, flags); 4803 } 4804 4805 /* 4806 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4807 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4808 * interrupt. 4809 * 4810 * This function is called by the USB core when an interrupt occurs 4811 */ 4812 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4813 { 4814 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4815 4816 return dwc2_handle_hcd_intr(hsotg); 4817 } 4818 4819 /* 4820 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4821 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4822 * is the status change indicator for the single root port. Returns 1 if either 4823 * change indicator is 1, otherwise returns 0. 4824 */ 4825 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4826 { 4827 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4828 4829 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4830 return buf[0] != 0; 4831 } 4832 4833 /* Handles hub class-specific requests */ 4834 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4835 u16 windex, char *buf, u16 wlength) 4836 { 4837 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4838 wvalue, windex, buf, wlength); 4839 return retval; 4840 } 4841 4842 /* Handles hub TT buffer clear completions */ 4843 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4844 struct usb_host_endpoint *ep) 4845 { 4846 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4847 struct dwc2_qh *qh; 4848 unsigned long flags; 4849 4850 qh = ep->hcpriv; 4851 if (!qh) 4852 return; 4853 4854 spin_lock_irqsave(&hsotg->lock, flags); 4855 qh->tt_buffer_dirty = 0; 4856 4857 if (hsotg->flags.b.port_connect_status) 4858 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4859 4860 spin_unlock_irqrestore(&hsotg->lock, flags); 4861 } 4862 4863 static struct hc_driver dwc2_hc_driver = { 4864 .description = "dwc2_hsotg", 4865 .product_desc = "DWC OTG Controller", 4866 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4867 4868 .irq = _dwc2_hcd_irq, 4869 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4870 4871 .start = _dwc2_hcd_start, 4872 .stop = _dwc2_hcd_stop, 4873 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4874 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4875 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4876 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4877 .get_frame_number = _dwc2_hcd_get_frame_number, 4878 4879 .hub_status_data = _dwc2_hcd_hub_status_data, 4880 .hub_control = _dwc2_hcd_hub_control, 4881 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4882 4883 .bus_suspend = _dwc2_hcd_suspend, 4884 .bus_resume = _dwc2_hcd_resume, 4885 4886 .map_urb_for_dma = dwc2_map_urb_for_dma, 4887 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4888 }; 4889 4890 /* 4891 * Frees secondary storage associated with the dwc2_hsotg structure contained 4892 * in the struct usb_hcd field 4893 */ 4894 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4895 { 4896 u32 ahbcfg; 4897 u32 dctl; 4898 int i; 4899 4900 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4901 4902 /* Free memory for QH/QTD lists */ 4903 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4904 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4905 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4906 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4907 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4908 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4909 4910 /* Free memory for the host channels */ 4911 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4912 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4913 4914 if (chan != NULL) { 4915 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4916 i, chan); 4917 hsotg->hc_ptr_array[i] = NULL; 4918 kfree(chan); 4919 } 4920 } 4921 4922 if (hsotg->core_params->dma_enable > 0) { 4923 if (hsotg->status_buf) { 4924 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 4925 hsotg->status_buf, 4926 hsotg->status_buf_dma); 4927 hsotg->status_buf = NULL; 4928 } 4929 } else { 4930 kfree(hsotg->status_buf); 4931 hsotg->status_buf = NULL; 4932 } 4933 4934 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 4935 4936 /* Disable all interrupts */ 4937 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 4938 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 4939 dwc2_writel(0, hsotg->regs + GINTMSK); 4940 4941 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 4942 dctl = dwc2_readl(hsotg->regs + DCTL); 4943 dctl |= DCTL_SFTDISCON; 4944 dwc2_writel(dctl, hsotg->regs + DCTL); 4945 } 4946 4947 if (hsotg->wq_otg) { 4948 if (!cancel_work_sync(&hsotg->wf_otg)) 4949 flush_workqueue(hsotg->wq_otg); 4950 destroy_workqueue(hsotg->wq_otg); 4951 } 4952 4953 del_timer(&hsotg->wkp_timer); 4954 } 4955 4956 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 4957 { 4958 /* Turn off all host-specific interrupts */ 4959 dwc2_disable_host_interrupts(hsotg); 4960 4961 dwc2_hcd_free(hsotg); 4962 } 4963 4964 /* 4965 * Initializes the HCD. This function allocates memory for and initializes the 4966 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 4967 * USB bus with the core and calls the hc_driver->start() function. It returns 4968 * a negative error on failure. 4969 */ 4970 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 4971 { 4972 struct usb_hcd *hcd; 4973 struct dwc2_host_chan *channel; 4974 u32 hcfg; 4975 int i, num_channels; 4976 int retval; 4977 4978 if (usb_disabled()) 4979 return -ENODEV; 4980 4981 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 4982 4983 retval = -ENOMEM; 4984 4985 hcfg = dwc2_readl(hsotg->regs + HCFG); 4986 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 4987 4988 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 4989 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 4990 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4991 if (!hsotg->frame_num_array) 4992 goto error1; 4993 hsotg->last_frame_num_array = kzalloc( 4994 sizeof(*hsotg->last_frame_num_array) * 4995 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4996 if (!hsotg->last_frame_num_array) 4997 goto error1; 4998 #endif 4999 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5000 5001 /* Check if the bus driver or platform code has setup a dma_mask */ 5002 if (hsotg->core_params->dma_enable > 0 && 5003 hsotg->dev->dma_mask == NULL) { 5004 dev_warn(hsotg->dev, 5005 "dma_mask not set, disabling DMA\n"); 5006 hsotg->core_params->dma_enable = 0; 5007 hsotg->core_params->dma_desc_enable = 0; 5008 } 5009 5010 /* Set device flags indicating whether the HCD supports DMA */ 5011 if (hsotg->core_params->dma_enable > 0) { 5012 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5013 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5014 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5015 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5016 } 5017 5018 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5019 if (!hcd) 5020 goto error1; 5021 5022 if (hsotg->core_params->dma_enable <= 0) 5023 hcd->self.uses_dma = 0; 5024 5025 hcd->has_tt = 1; 5026 5027 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 5028 hsotg->priv = hcd; 5029 5030 /* 5031 * Disable the global interrupt until all the interrupt handlers are 5032 * installed 5033 */ 5034 dwc2_disable_global_interrupts(hsotg); 5035 5036 /* Initialize the DWC_otg core, and select the Phy type */ 5037 retval = dwc2_core_init(hsotg, true); 5038 if (retval) 5039 goto error2; 5040 5041 /* Create new workqueue and init work */ 5042 retval = -ENOMEM; 5043 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 5044 if (!hsotg->wq_otg) { 5045 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5046 goto error2; 5047 } 5048 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5049 5050 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 5051 (unsigned long)hsotg); 5052 5053 /* Initialize the non-periodic schedule */ 5054 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5055 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5056 5057 /* Initialize the periodic schedule */ 5058 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5059 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5060 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5061 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5062 5063 INIT_LIST_HEAD(&hsotg->split_order); 5064 5065 /* 5066 * Create a host channel descriptor for each host channel implemented 5067 * in the controller. Initialize the channel descriptor array. 5068 */ 5069 INIT_LIST_HEAD(&hsotg->free_hc_list); 5070 num_channels = hsotg->core_params->host_channels; 5071 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5072 5073 for (i = 0; i < num_channels; i++) { 5074 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5075 if (channel == NULL) 5076 goto error3; 5077 channel->hc_num = i; 5078 INIT_LIST_HEAD(&channel->split_order_list_entry); 5079 hsotg->hc_ptr_array[i] = channel; 5080 } 5081 5082 /* Initialize hsotg start work */ 5083 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5084 5085 /* Initialize port reset work */ 5086 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5087 5088 /* 5089 * Allocate space for storing data on status transactions. Normally no 5090 * data is sent, but this space acts as a bit bucket. This must be 5091 * done after usb_add_hcd since that function allocates the DMA buffer 5092 * pool. 5093 */ 5094 if (hsotg->core_params->dma_enable > 0) 5095 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5096 DWC2_HCD_STATUS_BUF_SIZE, 5097 &hsotg->status_buf_dma, GFP_KERNEL); 5098 else 5099 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5100 GFP_KERNEL); 5101 5102 if (!hsotg->status_buf) 5103 goto error3; 5104 5105 /* 5106 * Create kmem caches to handle descriptor buffers in descriptor 5107 * DMA mode. 5108 * Alignment must be set to 512 bytes. 5109 */ 5110 if (hsotg->core_params->dma_desc_enable || 5111 hsotg->core_params->dma_desc_fs_enable) { 5112 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5113 sizeof(struct dwc2_hcd_dma_desc) * 5114 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5115 NULL); 5116 if (!hsotg->desc_gen_cache) { 5117 dev_err(hsotg->dev, 5118 "unable to create dwc2 generic desc cache\n"); 5119 5120 /* 5121 * Disable descriptor dma mode since it will not be 5122 * usable. 5123 */ 5124 hsotg->core_params->dma_desc_enable = 0; 5125 hsotg->core_params->dma_desc_fs_enable = 0; 5126 } 5127 5128 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5129 sizeof(struct dwc2_hcd_dma_desc) * 5130 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5131 if (!hsotg->desc_hsisoc_cache) { 5132 dev_err(hsotg->dev, 5133 "unable to create dwc2 hs isoc desc cache\n"); 5134 5135 kmem_cache_destroy(hsotg->desc_gen_cache); 5136 5137 /* 5138 * Disable descriptor dma mode since it will not be 5139 * usable. 5140 */ 5141 hsotg->core_params->dma_desc_enable = 0; 5142 hsotg->core_params->dma_desc_fs_enable = 0; 5143 } 5144 } 5145 5146 hsotg->otg_port = 1; 5147 hsotg->frame_list = NULL; 5148 hsotg->frame_list_dma = 0; 5149 hsotg->periodic_qh_count = 0; 5150 5151 /* Initiate lx_state to L3 disconnected state */ 5152 hsotg->lx_state = DWC2_L3; 5153 5154 hcd->self.otg_port = hsotg->otg_port; 5155 5156 /* Don't support SG list at this point */ 5157 hcd->self.sg_tablesize = 0; 5158 5159 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5160 otg_set_host(hsotg->uphy->otg, &hcd->self); 5161 5162 /* 5163 * Finish generic HCD initialization and start the HCD. This function 5164 * allocates the DMA buffer pool, registers the USB bus, requests the 5165 * IRQ line, and calls hcd_start method. 5166 */ 5167 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 5168 if (retval < 0) 5169 goto error4; 5170 5171 device_wakeup_enable(hcd->self.controller); 5172 5173 dwc2_hcd_dump_state(hsotg); 5174 5175 dwc2_enable_global_interrupts(hsotg); 5176 5177 return 0; 5178 5179 error4: 5180 kmem_cache_destroy(hsotg->desc_gen_cache); 5181 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5182 error3: 5183 dwc2_hcd_release(hsotg); 5184 error2: 5185 usb_put_hcd(hcd); 5186 error1: 5187 kfree(hsotg->core_params); 5188 5189 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5190 kfree(hsotg->last_frame_num_array); 5191 kfree(hsotg->frame_num_array); 5192 #endif 5193 5194 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5195 return retval; 5196 } 5197 5198 /* 5199 * Removes the HCD. 5200 * Frees memory and resources associated with the HCD and deregisters the bus. 5201 */ 5202 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5203 { 5204 struct usb_hcd *hcd; 5205 5206 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5207 5208 hcd = dwc2_hsotg_to_hcd(hsotg); 5209 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5210 5211 if (!hcd) { 5212 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5213 __func__); 5214 return; 5215 } 5216 5217 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5218 otg_set_host(hsotg->uphy->otg, NULL); 5219 5220 usb_remove_hcd(hcd); 5221 hsotg->priv = NULL; 5222 5223 kmem_cache_destroy(hsotg->desc_gen_cache); 5224 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5225 5226 dwc2_hcd_release(hsotg); 5227 usb_put_hcd(hcd); 5228 5229 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5230 kfree(hsotg->last_frame_num_array); 5231 kfree(hsotg->frame_num_array); 5232 #endif 5233 } 5234 5235 /** 5236 * dwc2_backup_host_registers() - Backup controller host registers. 5237 * When suspending usb bus, registers needs to be backuped 5238 * if controller power is disabled once suspended. 5239 * 5240 * @hsotg: Programming view of the DWC_otg controller 5241 */ 5242 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5243 { 5244 struct dwc2_hregs_backup *hr; 5245 int i; 5246 5247 dev_dbg(hsotg->dev, "%s\n", __func__); 5248 5249 /* Backup Host regs */ 5250 hr = &hsotg->hr_backup; 5251 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5252 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5253 for (i = 0; i < hsotg->core_params->host_channels; ++i) 5254 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5255 5256 hr->hprt0 = dwc2_read_hprt0(hsotg); 5257 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5258 hr->valid = true; 5259 5260 return 0; 5261 } 5262 5263 /** 5264 * dwc2_restore_host_registers() - Restore controller host registers. 5265 * When resuming usb bus, device registers needs to be restored 5266 * if controller power were disabled. 5267 * 5268 * @hsotg: Programming view of the DWC_otg controller 5269 */ 5270 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5271 { 5272 struct dwc2_hregs_backup *hr; 5273 int i; 5274 5275 dev_dbg(hsotg->dev, "%s\n", __func__); 5276 5277 /* Restore host regs */ 5278 hr = &hsotg->hr_backup; 5279 if (!hr->valid) { 5280 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5281 __func__); 5282 return -EINVAL; 5283 } 5284 hr->valid = false; 5285 5286 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5287 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5288 5289 for (i = 0; i < hsotg->core_params->host_channels; ++i) 5290 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5291 5292 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5293 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5294 hsotg->frame_number = 0; 5295 5296 return 0; 5297 } 5298