1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.c - DesignWare HS OTG Controller host-mode routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * This file contains the core HCD code, and implements the Linux hc_driver 40 * API 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/platform_device.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 60 61 /* 62 * ========================================================================= 63 * Host Core Layer Functions 64 * ========================================================================= 65 */ 66 67 /** 68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 69 * used in both device and host modes 70 * 71 * @hsotg: Programming view of the DWC_otg controller 72 */ 73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 74 { 75 u32 intmsk; 76 77 /* Clear any pending OTG Interrupts */ 78 dwc2_writel(hsotg, 0xffffffff, GOTGINT); 79 80 /* Clear any pending interrupts */ 81 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 82 83 /* Enable the interrupts in the GINTMSK */ 84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 85 86 if (!hsotg->params.host_dma) 87 intmsk |= GINTSTS_RXFLVL; 88 if (!hsotg->params.external_id_pin_ctl) 89 intmsk |= GINTSTS_CONIDSTSCHNG; 90 91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 92 GINTSTS_SESSREQINT; 93 94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 95 intmsk |= GINTSTS_LPMTRANRCVD; 96 97 dwc2_writel(hsotg, intmsk, GINTMSK); 98 } 99 100 /* 101 * Initializes the FSLSPClkSel field of the HCFG register depending on the 102 * PHY type 103 */ 104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 105 { 106 u32 hcfg, val; 107 108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 110 hsotg->params.ulpi_fs_ls) || 111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 112 /* Full speed PHY */ 113 val = HCFG_FSLSPCLKSEL_48_MHZ; 114 } else { 115 /* High speed PHY running at full speed or high speed */ 116 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 117 } 118 119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 120 hcfg = dwc2_readl(hsotg, HCFG); 121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 123 dwc2_writel(hsotg, hcfg, HCFG); 124 } 125 126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 127 { 128 u32 usbcfg, ggpio, i2cctl; 129 int retval = 0; 130 131 /* 132 * core_init() is now called on every switch so only call the 133 * following for the first time through 134 */ 135 if (select_phy) { 136 dev_dbg(hsotg->dev, "FS PHY selected\n"); 137 138 usbcfg = dwc2_readl(hsotg, GUSBCFG); 139 if (!(usbcfg & GUSBCFG_PHYSEL)) { 140 usbcfg |= GUSBCFG_PHYSEL; 141 dwc2_writel(hsotg, usbcfg, GUSBCFG); 142 143 /* Reset after a PHY select */ 144 retval = dwc2_core_reset(hsotg, false); 145 146 if (retval) { 147 dev_err(hsotg->dev, 148 "%s: Reset failed, aborting", __func__); 149 return retval; 150 } 151 } 152 153 if (hsotg->params.activate_stm_fs_transceiver) { 154 ggpio = dwc2_readl(hsotg, GGPIO); 155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 156 dev_dbg(hsotg->dev, "Activating transceiver\n"); 157 /* 158 * STM32F4x9 uses the GGPIO register as general 159 * core configuration register. 160 */ 161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 162 dwc2_writel(hsotg, ggpio, GGPIO); 163 } 164 } 165 } 166 167 /* 168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 169 * do this on HNP Dev/Host mode switches (done in dev_init and 170 * host_init). 171 */ 172 if (dwc2_is_host_mode(hsotg)) 173 dwc2_init_fs_ls_pclk_sel(hsotg); 174 175 if (hsotg->params.i2c_enable) { 176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 177 178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 179 usbcfg = dwc2_readl(hsotg, GUSBCFG); 180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 181 dwc2_writel(hsotg, usbcfg, GUSBCFG); 182 183 /* Program GI2CCTL.I2CEn */ 184 i2cctl = dwc2_readl(hsotg, GI2CCTL); 185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 187 i2cctl &= ~GI2CCTL_I2CEN; 188 dwc2_writel(hsotg, i2cctl, GI2CCTL); 189 i2cctl |= GI2CCTL_I2CEN; 190 dwc2_writel(hsotg, i2cctl, GI2CCTL); 191 } 192 193 return retval; 194 } 195 196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 197 { 198 u32 usbcfg, usbcfg_old; 199 int retval = 0; 200 201 if (!select_phy) 202 return 0; 203 204 usbcfg = dwc2_readl(hsotg, GUSBCFG); 205 usbcfg_old = usbcfg; 206 207 /* 208 * HS PHY parameters. These parameters are preserved during soft reset 209 * so only program the first time. Do a soft reset immediately after 210 * setting phyif. 211 */ 212 switch (hsotg->params.phy_type) { 213 case DWC2_PHY_TYPE_PARAM_ULPI: 214 /* ULPI interface */ 215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 218 if (hsotg->params.phy_ulpi_ddr) 219 usbcfg |= GUSBCFG_DDRSEL; 220 221 /* Set external VBUS indicator as needed. */ 222 if (hsotg->params.oc_disable) 223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 224 GUSBCFG_INDICATORPASSTHROUGH); 225 break; 226 case DWC2_PHY_TYPE_PARAM_UTMI: 227 /* UTMI+ interface */ 228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 230 if (hsotg->params.phy_utmi_width == 16) 231 usbcfg |= GUSBCFG_PHYIF16; 232 break; 233 default: 234 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 235 break; 236 } 237 238 if (usbcfg != usbcfg_old) { 239 dwc2_writel(hsotg, usbcfg, GUSBCFG); 240 241 /* Reset after setting the PHY parameters */ 242 retval = dwc2_core_reset(hsotg, false); 243 if (retval) { 244 dev_err(hsotg->dev, 245 "%s: Reset failed, aborting", __func__); 246 return retval; 247 } 248 } 249 250 return retval; 251 } 252 253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 254 { 255 u32 usbcfg; 256 int retval = 0; 257 258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 261 /* If FS/LS mode with FS/LS PHY */ 262 retval = dwc2_fs_phy_init(hsotg, select_phy); 263 if (retval) 264 return retval; 265 } else { 266 /* High speed PHY */ 267 retval = dwc2_hs_phy_init(hsotg, select_phy); 268 if (retval) 269 return retval; 270 } 271 272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 274 hsotg->params.ulpi_fs_ls) { 275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 276 usbcfg = dwc2_readl(hsotg, GUSBCFG); 277 usbcfg |= GUSBCFG_ULPI_FS_LS; 278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 279 dwc2_writel(hsotg, usbcfg, GUSBCFG); 280 } else { 281 usbcfg = dwc2_readl(hsotg, GUSBCFG); 282 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 284 dwc2_writel(hsotg, usbcfg, GUSBCFG); 285 } 286 287 return retval; 288 } 289 290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 291 { 292 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 293 294 switch (hsotg->hw_params.arch) { 295 case GHWCFG2_EXT_DMA_ARCH: 296 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 297 return -EINVAL; 298 299 case GHWCFG2_INT_DMA_ARCH: 300 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 301 if (hsotg->params.ahbcfg != -1) { 302 ahbcfg &= GAHBCFG_CTRL_MASK; 303 ahbcfg |= hsotg->params.ahbcfg & 304 ~GAHBCFG_CTRL_MASK; 305 } 306 break; 307 308 case GHWCFG2_SLAVE_ONLY_ARCH: 309 default: 310 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 311 break; 312 } 313 314 if (hsotg->params.host_dma) 315 ahbcfg |= GAHBCFG_DMA_EN; 316 else 317 hsotg->params.dma_desc_enable = false; 318 319 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 320 321 return 0; 322 } 323 324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 325 { 326 u32 usbcfg; 327 328 usbcfg = dwc2_readl(hsotg, GUSBCFG); 329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 330 331 switch (hsotg->hw_params.op_mode) { 332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 333 if (hsotg->params.otg_cap == 334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 335 usbcfg |= GUSBCFG_HNPCAP; 336 if (hsotg->params.otg_cap != 337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 338 usbcfg |= GUSBCFG_SRPCAP; 339 break; 340 341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 344 if (hsotg->params.otg_cap != 345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 346 usbcfg |= GUSBCFG_SRPCAP; 347 break; 348 349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 352 default: 353 break; 354 } 355 356 dwc2_writel(hsotg, usbcfg, GUSBCFG); 357 } 358 359 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) 360 { 361 int ret; 362 363 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus"); 364 if (IS_ERR(hsotg->vbus_supply)) { 365 ret = PTR_ERR(hsotg->vbus_supply); 366 hsotg->vbus_supply = NULL; 367 return ret == -ENODEV ? 0 : ret; 368 } 369 370 return regulator_enable(hsotg->vbus_supply); 371 } 372 373 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg) 374 { 375 if (hsotg->vbus_supply) 376 return regulator_disable(hsotg->vbus_supply); 377 378 return 0; 379 } 380 381 /** 382 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 383 * 384 * @hsotg: Programming view of DWC_otg controller 385 */ 386 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 387 { 388 u32 intmsk; 389 390 dev_dbg(hsotg->dev, "%s()\n", __func__); 391 392 /* Disable all interrupts */ 393 dwc2_writel(hsotg, 0, GINTMSK); 394 dwc2_writel(hsotg, 0, HAINTMSK); 395 396 /* Enable the common interrupts */ 397 dwc2_enable_common_interrupts(hsotg); 398 399 /* Enable host mode interrupts without disturbing common interrupts */ 400 intmsk = dwc2_readl(hsotg, GINTMSK); 401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 402 dwc2_writel(hsotg, intmsk, GINTMSK); 403 } 404 405 /** 406 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 407 * 408 * @hsotg: Programming view of DWC_otg controller 409 */ 410 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 411 { 412 u32 intmsk = dwc2_readl(hsotg, GINTMSK); 413 414 /* Disable host mode interrupts without disturbing common interrupts */ 415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 417 dwc2_writel(hsotg, intmsk, GINTMSK); 418 } 419 420 /* 421 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 422 * For system that have a total fifo depth that is smaller than the default 423 * RX + TX fifo size. 424 * 425 * @hsotg: Programming view of DWC_otg controller 426 */ 427 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 428 { 429 struct dwc2_core_params *params = &hsotg->params; 430 struct dwc2_hw_params *hw = &hsotg->hw_params; 431 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 432 433 total_fifo_size = hw->total_fifo_size; 434 rxfsiz = params->host_rx_fifo_size; 435 nptxfsiz = params->host_nperio_tx_fifo_size; 436 ptxfsiz = params->host_perio_tx_fifo_size; 437 438 /* 439 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 440 * allocation with support for high bandwidth endpoints. Synopsys 441 * defines MPS(Max Packet size) for a periodic EP=1024, and for 442 * non-periodic as 512. 443 */ 444 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 445 /* 446 * For Buffer DMA mode/Scatter Gather DMA mode 447 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 448 * with n = number of host channel. 449 * 2 * ((1024/4) + 2) = 516 450 */ 451 rxfsiz = 516 + hw->host_channels; 452 453 /* 454 * min non-periodic tx fifo depth 455 * 2 * (largest non-periodic USB packet used / 4) 456 * 2 * (512/4) = 256 457 */ 458 nptxfsiz = 256; 459 460 /* 461 * min periodic tx fifo depth 462 * (largest packet size*MC)/4 463 * (1024 * 3)/4 = 768 464 */ 465 ptxfsiz = 768; 466 467 params->host_rx_fifo_size = rxfsiz; 468 params->host_nperio_tx_fifo_size = nptxfsiz; 469 params->host_perio_tx_fifo_size = ptxfsiz; 470 } 471 472 /* 473 * If the summation of RX, NPTX and PTX fifo sizes is still 474 * bigger than the total_fifo_size, then we have a problem. 475 * 476 * We won't be able to allocate as many endpoints. Right now, 477 * we're just printing an error message, but ideally this FIFO 478 * allocation algorithm would be improved in the future. 479 * 480 * FIXME improve this FIFO allocation algorithm. 481 */ 482 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 483 dev_err(hsotg->dev, "invalid fifo sizes\n"); 484 } 485 486 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 487 { 488 struct dwc2_core_params *params = &hsotg->params; 489 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 490 491 if (!params->enable_dynamic_fifo) 492 return; 493 494 dwc2_calculate_dynamic_fifo(hsotg); 495 496 /* Rx FIFO */ 497 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 500 grxfsiz |= params->host_rx_fifo_size << 501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 502 dwc2_writel(hsotg, grxfsiz, GRXFSIZ); 503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 504 dwc2_readl(hsotg, GRXFSIZ)); 505 506 /* Non-periodic Tx FIFO */ 507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 508 dwc2_readl(hsotg, GNPTXFSIZ)); 509 nptxfsiz = params->host_nperio_tx_fifo_size << 510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 511 nptxfsiz |= params->host_rx_fifo_size << 512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 513 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ); 514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 515 dwc2_readl(hsotg, GNPTXFSIZ)); 516 517 /* Periodic Tx FIFO */ 518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 519 dwc2_readl(hsotg, HPTXFSIZ)); 520 hptxfsiz = params->host_perio_tx_fifo_size << 521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 522 hptxfsiz |= (params->host_rx_fifo_size + 523 params->host_nperio_tx_fifo_size) << 524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 525 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ); 526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 527 dwc2_readl(hsotg, HPTXFSIZ)); 528 529 if (hsotg->params.en_multiple_tx_fifo && 530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 531 /* 532 * This feature was implemented in 2.91a version 533 * Global DFIFOCFG calculation for Host mode - 534 * include RxFIFO, NPTXFIFO and HPTXFIFO 535 */ 536 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 538 dfifocfg |= (params->host_rx_fifo_size + 539 params->host_nperio_tx_fifo_size + 540 params->host_perio_tx_fifo_size) << 541 GDFIFOCFG_EPINFOBASE_SHIFT & 542 GDFIFOCFG_EPINFOBASE_MASK; 543 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG); 544 } 545 } 546 547 /** 548 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 549 * the HFIR register according to PHY type and speed 550 * 551 * @hsotg: Programming view of DWC_otg controller 552 * 553 * NOTE: The caller can modify the value of the HFIR register only after the 554 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 555 * has been set 556 */ 557 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 558 { 559 u32 usbcfg; 560 u32 hprt0; 561 int clock = 60; /* default value */ 562 563 usbcfg = dwc2_readl(hsotg, GUSBCFG); 564 hprt0 = dwc2_readl(hsotg, HPRT0); 565 566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 567 !(usbcfg & GUSBCFG_PHYIF16)) 568 clock = 60; 569 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 570 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 571 clock = 48; 572 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 573 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 574 clock = 30; 575 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 576 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 577 clock = 60; 578 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 579 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 580 clock = 48; 581 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 582 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 583 clock = 48; 584 if ((usbcfg & GUSBCFG_PHYSEL) && 585 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 586 clock = 48; 587 588 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 589 /* High speed case */ 590 return 125 * clock - 1; 591 592 /* FS/LS case */ 593 return 1000 * clock - 1; 594 } 595 596 /** 597 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 598 * buffer 599 * 600 * @hsotg: Programming view of DWC_otg controller 601 * @dest: Destination buffer for the packet 602 * @bytes: Number of bytes to copy to the destination 603 */ 604 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 605 { 606 u32 *data_buf = (u32 *)dest; 607 int word_count = (bytes + 3) / 4; 608 int i; 609 610 /* 611 * Todo: Account for the case where dest is not dword aligned. This 612 * requires reading data from the FIFO into a u32 temp buffer, then 613 * moving it into the data buffer. 614 */ 615 616 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 617 618 for (i = 0; i < word_count; i++, data_buf++) 619 *data_buf = dwc2_readl(hsotg, HCFIFO(0)); 620 } 621 622 /** 623 * dwc2_dump_channel_info() - Prints the state of a host channel 624 * 625 * @hsotg: Programming view of DWC_otg controller 626 * @chan: Pointer to the channel to dump 627 * 628 * Must be called with interrupt disabled and spinlock held 629 * 630 * NOTE: This function will be removed once the peripheral controller code 631 * is integrated and the driver is stable 632 */ 633 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 634 struct dwc2_host_chan *chan) 635 { 636 #ifdef VERBOSE_DEBUG 637 int num_channels = hsotg->params.host_channels; 638 struct dwc2_qh *qh; 639 u32 hcchar; 640 u32 hcsplt; 641 u32 hctsiz; 642 u32 hc_dma; 643 int i; 644 645 if (!chan) 646 return; 647 648 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 649 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 650 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num)); 651 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num)); 652 653 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 654 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 655 hcchar, hcsplt); 656 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 657 hctsiz, hc_dma); 658 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 659 chan->dev_addr, chan->ep_num, chan->ep_is_in); 660 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 661 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 662 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 663 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 664 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 665 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 666 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 667 (unsigned long)chan->xfer_dma); 668 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 669 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 670 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 671 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 672 qh_list_entry) 673 dev_dbg(hsotg->dev, " %p\n", qh); 674 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 675 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 676 qh_list_entry) 677 dev_dbg(hsotg->dev, " %p\n", qh); 678 dev_dbg(hsotg->dev, " NP active sched:\n"); 679 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 680 qh_list_entry) 681 dev_dbg(hsotg->dev, " %p\n", qh); 682 dev_dbg(hsotg->dev, " Channels:\n"); 683 for (i = 0; i < num_channels; i++) { 684 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 685 686 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 687 } 688 #endif /* VERBOSE_DEBUG */ 689 } 690 691 static int _dwc2_hcd_start(struct usb_hcd *hcd); 692 693 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 694 { 695 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 696 697 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 698 _dwc2_hcd_start(hcd); 699 } 700 701 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 702 { 703 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 704 705 hcd->self.is_b_host = 0; 706 } 707 708 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 709 int *hub_addr, int *hub_port) 710 { 711 struct urb *urb = context; 712 713 if (urb->dev->tt) 714 *hub_addr = urb->dev->tt->hub->devnum; 715 else 716 *hub_addr = 0; 717 *hub_port = urb->dev->ttport; 718 } 719 720 /* 721 * ========================================================================= 722 * Low Level Host Channel Access Functions 723 * ========================================================================= 724 */ 725 726 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 727 struct dwc2_host_chan *chan) 728 { 729 u32 hcintmsk = HCINTMSK_CHHLTD; 730 731 switch (chan->ep_type) { 732 case USB_ENDPOINT_XFER_CONTROL: 733 case USB_ENDPOINT_XFER_BULK: 734 dev_vdbg(hsotg->dev, "control/bulk\n"); 735 hcintmsk |= HCINTMSK_XFERCOMPL; 736 hcintmsk |= HCINTMSK_STALL; 737 hcintmsk |= HCINTMSK_XACTERR; 738 hcintmsk |= HCINTMSK_DATATGLERR; 739 if (chan->ep_is_in) { 740 hcintmsk |= HCINTMSK_BBLERR; 741 } else { 742 hcintmsk |= HCINTMSK_NAK; 743 hcintmsk |= HCINTMSK_NYET; 744 if (chan->do_ping) 745 hcintmsk |= HCINTMSK_ACK; 746 } 747 748 if (chan->do_split) { 749 hcintmsk |= HCINTMSK_NAK; 750 if (chan->complete_split) 751 hcintmsk |= HCINTMSK_NYET; 752 else 753 hcintmsk |= HCINTMSK_ACK; 754 } 755 756 if (chan->error_state) 757 hcintmsk |= HCINTMSK_ACK; 758 break; 759 760 case USB_ENDPOINT_XFER_INT: 761 if (dbg_perio()) 762 dev_vdbg(hsotg->dev, "intr\n"); 763 hcintmsk |= HCINTMSK_XFERCOMPL; 764 hcintmsk |= HCINTMSK_NAK; 765 hcintmsk |= HCINTMSK_STALL; 766 hcintmsk |= HCINTMSK_XACTERR; 767 hcintmsk |= HCINTMSK_DATATGLERR; 768 hcintmsk |= HCINTMSK_FRMOVRUN; 769 770 if (chan->ep_is_in) 771 hcintmsk |= HCINTMSK_BBLERR; 772 if (chan->error_state) 773 hcintmsk |= HCINTMSK_ACK; 774 if (chan->do_split) { 775 if (chan->complete_split) 776 hcintmsk |= HCINTMSK_NYET; 777 else 778 hcintmsk |= HCINTMSK_ACK; 779 } 780 break; 781 782 case USB_ENDPOINT_XFER_ISOC: 783 if (dbg_perio()) 784 dev_vdbg(hsotg->dev, "isoc\n"); 785 hcintmsk |= HCINTMSK_XFERCOMPL; 786 hcintmsk |= HCINTMSK_FRMOVRUN; 787 hcintmsk |= HCINTMSK_ACK; 788 789 if (chan->ep_is_in) { 790 hcintmsk |= HCINTMSK_XACTERR; 791 hcintmsk |= HCINTMSK_BBLERR; 792 } 793 break; 794 default: 795 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 796 break; 797 } 798 799 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 800 if (dbg_hc(chan)) 801 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 802 } 803 804 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 805 struct dwc2_host_chan *chan) 806 { 807 u32 hcintmsk = HCINTMSK_CHHLTD; 808 809 /* 810 * For Descriptor DMA mode core halts the channel on AHB error. 811 * Interrupt is not required. 812 */ 813 if (!hsotg->params.dma_desc_enable) { 814 if (dbg_hc(chan)) 815 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 816 hcintmsk |= HCINTMSK_AHBERR; 817 } else { 818 if (dbg_hc(chan)) 819 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 820 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 821 hcintmsk |= HCINTMSK_XFERCOMPL; 822 } 823 824 if (chan->error_state && !chan->do_split && 825 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 826 if (dbg_hc(chan)) 827 dev_vdbg(hsotg->dev, "setting ACK\n"); 828 hcintmsk |= HCINTMSK_ACK; 829 if (chan->ep_is_in) { 830 hcintmsk |= HCINTMSK_DATATGLERR; 831 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 832 hcintmsk |= HCINTMSK_NAK; 833 } 834 } 835 836 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 837 if (dbg_hc(chan)) 838 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 839 } 840 841 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 842 struct dwc2_host_chan *chan) 843 { 844 u32 intmsk; 845 846 if (hsotg->params.host_dma) { 847 if (dbg_hc(chan)) 848 dev_vdbg(hsotg->dev, "DMA enabled\n"); 849 dwc2_hc_enable_dma_ints(hsotg, chan); 850 } else { 851 if (dbg_hc(chan)) 852 dev_vdbg(hsotg->dev, "DMA disabled\n"); 853 dwc2_hc_enable_slave_ints(hsotg, chan); 854 } 855 856 /* Enable the top level host channel interrupt */ 857 intmsk = dwc2_readl(hsotg, HAINTMSK); 858 intmsk |= 1 << chan->hc_num; 859 dwc2_writel(hsotg, intmsk, HAINTMSK); 860 if (dbg_hc(chan)) 861 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 862 863 /* Make sure host channel interrupts are enabled */ 864 intmsk = dwc2_readl(hsotg, GINTMSK); 865 intmsk |= GINTSTS_HCHINT; 866 dwc2_writel(hsotg, intmsk, GINTMSK); 867 if (dbg_hc(chan)) 868 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 869 } 870 871 /** 872 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 873 * a specific endpoint 874 * 875 * @hsotg: Programming view of DWC_otg controller 876 * @chan: Information needed to initialize the host channel 877 * 878 * The HCCHARn register is set up with the characteristics specified in chan. 879 * Host channel interrupts that may need to be serviced while this transfer is 880 * in progress are enabled. 881 */ 882 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 883 { 884 u8 hc_num = chan->hc_num; 885 u32 hcintmsk; 886 u32 hcchar; 887 u32 hcsplt = 0; 888 889 if (dbg_hc(chan)) 890 dev_vdbg(hsotg->dev, "%s()\n", __func__); 891 892 /* Clear old interrupt conditions for this host channel */ 893 hcintmsk = 0xffffffff; 894 hcintmsk &= ~HCINTMSK_RESERVED14_31; 895 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num)); 896 897 /* Enable channel interrupts required for this transfer */ 898 dwc2_hc_enable_ints(hsotg, chan); 899 900 /* 901 * Program the HCCHARn register with the endpoint characteristics for 902 * the current transfer 903 */ 904 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 905 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 906 if (chan->ep_is_in) 907 hcchar |= HCCHAR_EPDIR; 908 if (chan->speed == USB_SPEED_LOW) 909 hcchar |= HCCHAR_LSPDDEV; 910 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 911 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 912 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num)); 913 if (dbg_hc(chan)) { 914 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 915 hc_num, hcchar); 916 917 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 918 __func__, hc_num); 919 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 920 chan->dev_addr); 921 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 922 chan->ep_num); 923 dev_vdbg(hsotg->dev, " Is In: %d\n", 924 chan->ep_is_in); 925 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 926 chan->speed == USB_SPEED_LOW); 927 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 928 chan->ep_type); 929 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 930 chan->max_packet); 931 } 932 933 /* Program the HCSPLT register for SPLITs */ 934 if (chan->do_split) { 935 if (dbg_hc(chan)) 936 dev_vdbg(hsotg->dev, 937 "Programming HC %d with split --> %s\n", 938 hc_num, 939 chan->complete_split ? "CSPLIT" : "SSPLIT"); 940 if (chan->complete_split) 941 hcsplt |= HCSPLT_COMPSPLT; 942 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 943 HCSPLT_XACTPOS_MASK; 944 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 945 HCSPLT_HUBADDR_MASK; 946 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 947 HCSPLT_PRTADDR_MASK; 948 if (dbg_hc(chan)) { 949 dev_vdbg(hsotg->dev, " comp split %d\n", 950 chan->complete_split); 951 dev_vdbg(hsotg->dev, " xact pos %d\n", 952 chan->xact_pos); 953 dev_vdbg(hsotg->dev, " hub addr %d\n", 954 chan->hub_addr); 955 dev_vdbg(hsotg->dev, " hub port %d\n", 956 chan->hub_port); 957 dev_vdbg(hsotg->dev, " is_in %d\n", 958 chan->ep_is_in); 959 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 960 chan->max_packet); 961 dev_vdbg(hsotg->dev, " xferlen %d\n", 962 chan->xfer_len); 963 } 964 } 965 966 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num)); 967 } 968 969 /** 970 * dwc2_hc_halt() - Attempts to halt a host channel 971 * 972 * @hsotg: Controller register interface 973 * @chan: Host channel to halt 974 * @halt_status: Reason for halting the channel 975 * 976 * This function should only be called in Slave mode or to abort a transfer in 977 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 978 * controller halts the channel when the transfer is complete or a condition 979 * occurs that requires application intervention. 980 * 981 * In slave mode, checks for a free request queue entry, then sets the Channel 982 * Enable and Channel Disable bits of the Host Channel Characteristics 983 * register of the specified channel to intiate the halt. If there is no free 984 * request queue entry, sets only the Channel Disable bit of the HCCHARn 985 * register to flush requests for this channel. In the latter case, sets a 986 * flag to indicate that the host channel needs to be halted when a request 987 * queue slot is open. 988 * 989 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 990 * HCCHARn register. The controller ensures there is space in the request 991 * queue before submitting the halt request. 992 * 993 * Some time may elapse before the core flushes any posted requests for this 994 * host channel and halts. The Channel Halted interrupt handler completes the 995 * deactivation of the host channel. 996 */ 997 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 998 enum dwc2_halt_status halt_status) 999 { 1000 u32 nptxsts, hptxsts, hcchar; 1001 1002 if (dbg_hc(chan)) 1003 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1004 1005 /* 1006 * In buffer DMA or external DMA mode channel can't be halted 1007 * for non-split periodic channels. At the end of the next 1008 * uframe/frame (in the worst case), the core generates a channel 1009 * halted and disables the channel automatically. 1010 */ 1011 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || 1012 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { 1013 if (!chan->do_split && 1014 (chan->ep_type == USB_ENDPOINT_XFER_ISOC || 1015 chan->ep_type == USB_ENDPOINT_XFER_INT)) { 1016 dev_err(hsotg->dev, "%s() Channel can't be halted\n", 1017 __func__); 1018 return; 1019 } 1020 } 1021 1022 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 1023 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 1024 1025 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1026 halt_status == DWC2_HC_XFER_AHB_ERR) { 1027 /* 1028 * Disable all channel interrupts except Ch Halted. The QTD 1029 * and QH state associated with this transfer has been cleared 1030 * (in the case of URB_DEQUEUE), so the channel needs to be 1031 * shut down carefully to prevent crashes. 1032 */ 1033 u32 hcintmsk = HCINTMSK_CHHLTD; 1034 1035 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1036 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 1037 1038 /* 1039 * Make sure no other interrupts besides halt are currently 1040 * pending. Handling another interrupt could cause a crash due 1041 * to the QTD and QH state. 1042 */ 1043 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num)); 1044 1045 /* 1046 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1047 * even if the channel was already halted for some other 1048 * reason 1049 */ 1050 chan->halt_status = halt_status; 1051 1052 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1053 if (!(hcchar & HCCHAR_CHENA)) { 1054 /* 1055 * The channel is either already halted or it hasn't 1056 * started yet. In DMA mode, the transfer may halt if 1057 * it finishes normally or a condition occurs that 1058 * requires driver intervention. Don't want to halt 1059 * the channel again. In either Slave or DMA mode, 1060 * it's possible that the transfer has been assigned 1061 * to a channel, but not started yet when an URB is 1062 * dequeued. Don't want to halt a channel that hasn't 1063 * started yet. 1064 */ 1065 return; 1066 } 1067 } 1068 if (chan->halt_pending) { 1069 /* 1070 * A halt has already been issued for this channel. This might 1071 * happen when a transfer is aborted by a higher level in 1072 * the stack. 1073 */ 1074 dev_vdbg(hsotg->dev, 1075 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1076 __func__, chan->hc_num); 1077 return; 1078 } 1079 1080 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1081 1082 /* No need to set the bit in DDMA for disabling the channel */ 1083 /* TODO check it everywhere channel is disabled */ 1084 if (!hsotg->params.dma_desc_enable) { 1085 if (dbg_hc(chan)) 1086 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1087 hcchar |= HCCHAR_CHENA; 1088 } else { 1089 if (dbg_hc(chan)) 1090 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1091 } 1092 hcchar |= HCCHAR_CHDIS; 1093 1094 if (!hsotg->params.host_dma) { 1095 if (dbg_hc(chan)) 1096 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1097 hcchar |= HCCHAR_CHENA; 1098 1099 /* Check for space in the request queue to issue the halt */ 1100 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1101 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1102 dev_vdbg(hsotg->dev, "control/bulk\n"); 1103 nptxsts = dwc2_readl(hsotg, GNPTXSTS); 1104 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1105 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1106 hcchar &= ~HCCHAR_CHENA; 1107 } 1108 } else { 1109 if (dbg_perio()) 1110 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1111 hptxsts = dwc2_readl(hsotg, HPTXSTS); 1112 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1113 hsotg->queuing_high_bandwidth) { 1114 if (dbg_perio()) 1115 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1116 hcchar &= ~HCCHAR_CHENA; 1117 } 1118 } 1119 } else { 1120 if (dbg_hc(chan)) 1121 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1122 } 1123 1124 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1125 chan->halt_status = halt_status; 1126 1127 if (hcchar & HCCHAR_CHENA) { 1128 if (dbg_hc(chan)) 1129 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1130 chan->halt_pending = 1; 1131 chan->halt_on_queue = 0; 1132 } else { 1133 if (dbg_hc(chan)) 1134 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1135 chan->halt_on_queue = 1; 1136 } 1137 1138 if (dbg_hc(chan)) { 1139 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1140 chan->hc_num); 1141 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1142 hcchar); 1143 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1144 chan->halt_pending); 1145 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1146 chan->halt_on_queue); 1147 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1148 chan->halt_status); 1149 } 1150 } 1151 1152 /** 1153 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1154 * 1155 * @hsotg: Programming view of DWC_otg controller 1156 * @chan: Identifies the host channel to clean up 1157 * 1158 * This function is normally called after a transfer is done and the host 1159 * channel is being released 1160 */ 1161 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1162 { 1163 u32 hcintmsk; 1164 1165 chan->xfer_started = 0; 1166 1167 list_del_init(&chan->split_order_list_entry); 1168 1169 /* 1170 * Clear channel interrupt enables and any unhandled channel interrupt 1171 * conditions 1172 */ 1173 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num)); 1174 hcintmsk = 0xffffffff; 1175 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1176 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num)); 1177 } 1178 1179 /** 1180 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1181 * which frame a periodic transfer should occur 1182 * 1183 * @hsotg: Programming view of DWC_otg controller 1184 * @chan: Identifies the host channel to set up and its properties 1185 * @hcchar: Current value of the HCCHAR register for the specified host channel 1186 * 1187 * This function has no effect on non-periodic transfers 1188 */ 1189 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1190 struct dwc2_host_chan *chan, u32 *hcchar) 1191 { 1192 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1193 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1194 int host_speed; 1195 int xfer_ns; 1196 int xfer_us; 1197 int bytes_in_fifo; 1198 u16 fifo_space; 1199 u16 frame_number; 1200 u16 wire_frame; 1201 1202 /* 1203 * Try to figure out if we're an even or odd frame. If we set 1204 * even and the current frame number is even the the transfer 1205 * will happen immediately. Similar if both are odd. If one is 1206 * even and the other is odd then the transfer will happen when 1207 * the frame number ticks. 1208 * 1209 * There's a bit of a balancing act to get this right. 1210 * Sometimes we may want to send data in the current frame (AK 1211 * right away). We might want to do this if the frame number 1212 * _just_ ticked, but we might also want to do this in order 1213 * to continue a split transaction that happened late in a 1214 * microframe (so we didn't know to queue the next transfer 1215 * until the frame number had ticked). The problem is that we 1216 * need a lot of knowledge to know if there's actually still 1217 * time to send things or if it would be better to wait until 1218 * the next frame. 1219 * 1220 * We can look at how much time is left in the current frame 1221 * and make a guess about whether we'll have time to transfer. 1222 * We'll do that. 1223 */ 1224 1225 /* Get speed host is running at */ 1226 host_speed = (chan->speed != USB_SPEED_HIGH && 1227 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1228 1229 /* See how many bytes are in the periodic FIFO right now */ 1230 fifo_space = (dwc2_readl(hsotg, HPTXSTS) & 1231 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1232 bytes_in_fifo = sizeof(u32) * 1233 (hsotg->params.host_perio_tx_fifo_size - 1234 fifo_space); 1235 1236 /* 1237 * Roughly estimate bus time for everything in the periodic 1238 * queue + our new transfer. This is "rough" because we're 1239 * using a function that makes takes into account IN/OUT 1240 * and INT/ISO and we're just slamming in one value for all 1241 * transfers. This should be an over-estimate and that should 1242 * be OK, but we can probably tighten it. 1243 */ 1244 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1245 chan->xfer_len + bytes_in_fifo); 1246 xfer_us = NS_TO_US(xfer_ns); 1247 1248 /* See what frame number we'll be at by the time we finish */ 1249 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1250 1251 /* This is when we were scheduled to be on the wire */ 1252 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1253 1254 /* 1255 * If we'd finish _after_ the frame we're scheduled in then 1256 * it's hopeless. Just schedule right away and hope for the 1257 * best. Note that it _might_ be wise to call back into the 1258 * scheduler to pick a better frame, but this is better than 1259 * nothing. 1260 */ 1261 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1262 dwc2_sch_vdbg(hsotg, 1263 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1264 chan->qh, wire_frame, frame_number, 1265 dwc2_frame_num_dec(frame_number, 1266 wire_frame)); 1267 wire_frame = frame_number; 1268 1269 /* 1270 * We picked a different frame number; communicate this 1271 * back to the scheduler so it doesn't try to schedule 1272 * another in the same frame. 1273 * 1274 * Remember that next_active_frame is 1 before the wire 1275 * frame. 1276 */ 1277 chan->qh->next_active_frame = 1278 dwc2_frame_num_dec(frame_number, 1); 1279 } 1280 1281 if (wire_frame & 1) 1282 *hcchar |= HCCHAR_ODDFRM; 1283 else 1284 *hcchar &= ~HCCHAR_ODDFRM; 1285 } 1286 } 1287 1288 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1289 { 1290 /* Set up the initial PID for the transfer */ 1291 if (chan->speed == USB_SPEED_HIGH) { 1292 if (chan->ep_is_in) { 1293 if (chan->multi_count == 1) 1294 chan->data_pid_start = DWC2_HC_PID_DATA0; 1295 else if (chan->multi_count == 2) 1296 chan->data_pid_start = DWC2_HC_PID_DATA1; 1297 else 1298 chan->data_pid_start = DWC2_HC_PID_DATA2; 1299 } else { 1300 if (chan->multi_count == 1) 1301 chan->data_pid_start = DWC2_HC_PID_DATA0; 1302 else 1303 chan->data_pid_start = DWC2_HC_PID_MDATA; 1304 } 1305 } else { 1306 chan->data_pid_start = DWC2_HC_PID_DATA0; 1307 } 1308 } 1309 1310 /** 1311 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1312 * the Host Channel 1313 * 1314 * @hsotg: Programming view of DWC_otg controller 1315 * @chan: Information needed to initialize the host channel 1316 * 1317 * This function should only be called in Slave mode. For a channel associated 1318 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1319 * associated with a periodic EP, the periodic Tx FIFO is written. 1320 * 1321 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1322 * the number of bytes written to the Tx FIFO. 1323 */ 1324 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1325 struct dwc2_host_chan *chan) 1326 { 1327 u32 i; 1328 u32 remaining_count; 1329 u32 byte_count; 1330 u32 dword_count; 1331 u32 __iomem *data_fifo; 1332 u32 *data_buf = (u32 *)chan->xfer_buf; 1333 1334 if (dbg_hc(chan)) 1335 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1336 1337 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1338 1339 remaining_count = chan->xfer_len - chan->xfer_count; 1340 if (remaining_count > chan->max_packet) 1341 byte_count = chan->max_packet; 1342 else 1343 byte_count = remaining_count; 1344 1345 dword_count = (byte_count + 3) / 4; 1346 1347 if (((unsigned long)data_buf & 0x3) == 0) { 1348 /* xfer_buf is DWORD aligned */ 1349 for (i = 0; i < dword_count; i++, data_buf++) 1350 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num)); 1351 } else { 1352 /* xfer_buf is not DWORD aligned */ 1353 for (i = 0; i < dword_count; i++, data_buf++) { 1354 u32 data = data_buf[0] | data_buf[1] << 8 | 1355 data_buf[2] << 16 | data_buf[3] << 24; 1356 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num)); 1357 } 1358 } 1359 1360 chan->xfer_count += byte_count; 1361 chan->xfer_buf += byte_count; 1362 } 1363 1364 /** 1365 * dwc2_hc_do_ping() - Starts a PING transfer 1366 * 1367 * @hsotg: Programming view of DWC_otg controller 1368 * @chan: Information needed to initialize the host channel 1369 * 1370 * This function should only be called in Slave mode. The Do Ping bit is set in 1371 * the HCTSIZ register, then the channel is enabled. 1372 */ 1373 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1374 struct dwc2_host_chan *chan) 1375 { 1376 u32 hcchar; 1377 u32 hctsiz; 1378 1379 if (dbg_hc(chan)) 1380 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1381 chan->hc_num); 1382 1383 hctsiz = TSIZ_DOPNG; 1384 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1385 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1386 1387 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1388 hcchar |= HCCHAR_CHENA; 1389 hcchar &= ~HCCHAR_CHDIS; 1390 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1391 } 1392 1393 /** 1394 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1395 * channel and starts the transfer 1396 * 1397 * @hsotg: Programming view of DWC_otg controller 1398 * @chan: Information needed to initialize the host channel. The xfer_len value 1399 * may be reduced to accommodate the max widths of the XferSize and 1400 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1401 * changed to reflect the final xfer_len value. 1402 * 1403 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1404 * the caller must ensure that there is sufficient space in the request queue 1405 * and Tx Data FIFO. 1406 * 1407 * For an OUT transfer in Slave mode, it loads a data packet into the 1408 * appropriate FIFO. If necessary, additional data packets are loaded in the 1409 * Host ISR. 1410 * 1411 * For an IN transfer in Slave mode, a data packet is requested. The data 1412 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1413 * additional data packets are requested in the Host ISR. 1414 * 1415 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1416 * register along with a packet count of 1 and the channel is enabled. This 1417 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1418 * simply set to 0 since no data transfer occurs in this case. 1419 * 1420 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1421 * all the information required to perform the subsequent data transfer. In 1422 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1423 * controller performs the entire PING protocol, then starts the data 1424 * transfer. 1425 */ 1426 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1427 struct dwc2_host_chan *chan) 1428 { 1429 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1430 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1431 u32 hcchar; 1432 u32 hctsiz = 0; 1433 u16 num_packets; 1434 u32 ec_mc; 1435 1436 if (dbg_hc(chan)) 1437 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1438 1439 if (chan->do_ping) { 1440 if (!hsotg->params.host_dma) { 1441 if (dbg_hc(chan)) 1442 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1443 dwc2_hc_do_ping(hsotg, chan); 1444 chan->xfer_started = 1; 1445 return; 1446 } 1447 1448 if (dbg_hc(chan)) 1449 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1450 1451 hctsiz |= TSIZ_DOPNG; 1452 } 1453 1454 if (chan->do_split) { 1455 if (dbg_hc(chan)) 1456 dev_vdbg(hsotg->dev, "split\n"); 1457 num_packets = 1; 1458 1459 if (chan->complete_split && !chan->ep_is_in) 1460 /* 1461 * For CSPLIT OUT Transfer, set the size to 0 so the 1462 * core doesn't expect any data written to the FIFO 1463 */ 1464 chan->xfer_len = 0; 1465 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1466 chan->xfer_len = chan->max_packet; 1467 else if (!chan->ep_is_in && chan->xfer_len > 188) 1468 chan->xfer_len = 188; 1469 1470 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1471 TSIZ_XFERSIZE_MASK; 1472 1473 /* For split set ec_mc for immediate retries */ 1474 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1475 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1476 ec_mc = 3; 1477 else 1478 ec_mc = 1; 1479 } else { 1480 if (dbg_hc(chan)) 1481 dev_vdbg(hsotg->dev, "no split\n"); 1482 /* 1483 * Ensure that the transfer length and packet count will fit 1484 * in the widths allocated for them in the HCTSIZn register 1485 */ 1486 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1487 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1488 /* 1489 * Make sure the transfer size is no larger than one 1490 * (micro)frame's worth of data. (A check was done 1491 * when the periodic transfer was accepted to ensure 1492 * that a (micro)frame's worth of data can be 1493 * programmed into a channel.) 1494 */ 1495 u32 max_periodic_len = 1496 chan->multi_count * chan->max_packet; 1497 1498 if (chan->xfer_len > max_periodic_len) 1499 chan->xfer_len = max_periodic_len; 1500 } else if (chan->xfer_len > max_hc_xfer_size) { 1501 /* 1502 * Make sure that xfer_len is a multiple of max packet 1503 * size 1504 */ 1505 chan->xfer_len = 1506 max_hc_xfer_size - chan->max_packet + 1; 1507 } 1508 1509 if (chan->xfer_len > 0) { 1510 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1511 chan->max_packet; 1512 if (num_packets > max_hc_pkt_count) { 1513 num_packets = max_hc_pkt_count; 1514 chan->xfer_len = num_packets * chan->max_packet; 1515 } 1516 } else { 1517 /* Need 1 packet for transfer length of 0 */ 1518 num_packets = 1; 1519 } 1520 1521 if (chan->ep_is_in) 1522 /* 1523 * Always program an integral # of max packets for IN 1524 * transfers 1525 */ 1526 chan->xfer_len = num_packets * chan->max_packet; 1527 1528 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1529 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1530 /* 1531 * Make sure that the multi_count field matches the 1532 * actual transfer length 1533 */ 1534 chan->multi_count = num_packets; 1535 1536 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1537 dwc2_set_pid_isoc(chan); 1538 1539 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1540 TSIZ_XFERSIZE_MASK; 1541 1542 /* The ec_mc gets the multi_count for non-split */ 1543 ec_mc = chan->multi_count; 1544 } 1545 1546 chan->start_pkt_count = num_packets; 1547 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1548 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1549 TSIZ_SC_MC_PID_MASK; 1550 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1551 if (dbg_hc(chan)) { 1552 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1553 hctsiz, chan->hc_num); 1554 1555 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1556 chan->hc_num); 1557 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1558 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1559 TSIZ_XFERSIZE_SHIFT); 1560 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1561 (hctsiz & TSIZ_PKTCNT_MASK) >> 1562 TSIZ_PKTCNT_SHIFT); 1563 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1564 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1565 TSIZ_SC_MC_PID_SHIFT); 1566 } 1567 1568 if (hsotg->params.host_dma) { 1569 dma_addr_t dma_addr; 1570 1571 if (chan->align_buf) { 1572 if (dbg_hc(chan)) 1573 dev_vdbg(hsotg->dev, "align_buf\n"); 1574 dma_addr = chan->align_buf; 1575 } else { 1576 dma_addr = chan->xfer_dma; 1577 } 1578 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num)); 1579 1580 if (dbg_hc(chan)) 1581 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1582 (unsigned long)dma_addr, chan->hc_num); 1583 } 1584 1585 /* Start the split */ 1586 if (chan->do_split) { 1587 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 1588 1589 hcsplt |= HCSPLT_SPLTENA; 1590 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num)); 1591 } 1592 1593 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1594 hcchar &= ~HCCHAR_MULTICNT_MASK; 1595 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1596 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1597 1598 if (hcchar & HCCHAR_CHDIS) 1599 dev_warn(hsotg->dev, 1600 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1601 __func__, chan->hc_num, hcchar); 1602 1603 /* Set host channel enable after all other setup is complete */ 1604 hcchar |= HCCHAR_CHENA; 1605 hcchar &= ~HCCHAR_CHDIS; 1606 1607 if (dbg_hc(chan)) 1608 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1609 (hcchar & HCCHAR_MULTICNT_MASK) >> 1610 HCCHAR_MULTICNT_SHIFT); 1611 1612 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1613 if (dbg_hc(chan)) 1614 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1615 chan->hc_num); 1616 1617 chan->xfer_started = 1; 1618 chan->requests++; 1619 1620 if (!hsotg->params.host_dma && 1621 !chan->ep_is_in && chan->xfer_len > 0) 1622 /* Load OUT packet into the appropriate Tx FIFO */ 1623 dwc2_hc_write_packet(hsotg, chan); 1624 } 1625 1626 /** 1627 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1628 * host channel and starts the transfer in Descriptor DMA mode 1629 * 1630 * @hsotg: Programming view of DWC_otg controller 1631 * @chan: Information needed to initialize the host channel 1632 * 1633 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1634 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1635 * with micro-frame bitmap. 1636 * 1637 * Initializes HCDMA register with descriptor list address and CTD value then 1638 * starts the transfer via enabling the channel. 1639 */ 1640 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1641 struct dwc2_host_chan *chan) 1642 { 1643 u32 hcchar; 1644 u32 hctsiz = 0; 1645 1646 if (chan->do_ping) 1647 hctsiz |= TSIZ_DOPNG; 1648 1649 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1650 dwc2_set_pid_isoc(chan); 1651 1652 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1653 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1654 TSIZ_SC_MC_PID_MASK; 1655 1656 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1657 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1658 1659 /* Non-zero only for high-speed interrupt endpoints */ 1660 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1661 1662 if (dbg_hc(chan)) { 1663 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1664 chan->hc_num); 1665 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1666 chan->data_pid_start); 1667 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1668 } 1669 1670 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1671 1672 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1673 chan->desc_list_sz, DMA_TO_DEVICE); 1674 1675 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num)); 1676 1677 if (dbg_hc(chan)) 1678 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1679 &chan->desc_list_addr, chan->hc_num); 1680 1681 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1682 hcchar &= ~HCCHAR_MULTICNT_MASK; 1683 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1684 HCCHAR_MULTICNT_MASK; 1685 1686 if (hcchar & HCCHAR_CHDIS) 1687 dev_warn(hsotg->dev, 1688 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1689 __func__, chan->hc_num, hcchar); 1690 1691 /* Set host channel enable after all other setup is complete */ 1692 hcchar |= HCCHAR_CHENA; 1693 hcchar &= ~HCCHAR_CHDIS; 1694 1695 if (dbg_hc(chan)) 1696 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1697 (hcchar & HCCHAR_MULTICNT_MASK) >> 1698 HCCHAR_MULTICNT_SHIFT); 1699 1700 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1701 if (dbg_hc(chan)) 1702 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1703 chan->hc_num); 1704 1705 chan->xfer_started = 1; 1706 chan->requests++; 1707 } 1708 1709 /** 1710 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1711 * a previous call to dwc2_hc_start_transfer() 1712 * 1713 * @hsotg: Programming view of DWC_otg controller 1714 * @chan: Information needed to initialize the host channel 1715 * 1716 * The caller must ensure there is sufficient space in the request queue and Tx 1717 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1718 * the controller acts autonomously to complete transfers programmed to a host 1719 * channel. 1720 * 1721 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1722 * if there is any data remaining to be queued. For an IN transfer, another 1723 * data packet is always requested. For the SETUP phase of a control transfer, 1724 * this function does nothing. 1725 * 1726 * Return: 1 if a new request is queued, 0 if no more requests are required 1727 * for this transfer 1728 */ 1729 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1730 struct dwc2_host_chan *chan) 1731 { 1732 if (dbg_hc(chan)) 1733 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1734 chan->hc_num); 1735 1736 if (chan->do_split) 1737 /* SPLITs always queue just once per channel */ 1738 return 0; 1739 1740 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1741 /* SETUPs are queued only once since they can't be NAK'd */ 1742 return 0; 1743 1744 if (chan->ep_is_in) { 1745 /* 1746 * Always queue another request for other IN transfers. If 1747 * back-to-back INs are issued and NAKs are received for both, 1748 * the driver may still be processing the first NAK when the 1749 * second NAK is received. When the interrupt handler clears 1750 * the NAK interrupt for the first NAK, the second NAK will 1751 * not be seen. So we can't depend on the NAK interrupt 1752 * handler to requeue a NAK'd request. Instead, IN requests 1753 * are issued each time this function is called. When the 1754 * transfer completes, the extra requests for the channel will 1755 * be flushed. 1756 */ 1757 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1758 1759 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1760 hcchar |= HCCHAR_CHENA; 1761 hcchar &= ~HCCHAR_CHDIS; 1762 if (dbg_hc(chan)) 1763 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1764 hcchar); 1765 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1766 chan->requests++; 1767 return 1; 1768 } 1769 1770 /* OUT transfers */ 1771 1772 if (chan->xfer_count < chan->xfer_len) { 1773 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1774 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1775 u32 hcchar = dwc2_readl(hsotg, 1776 HCCHAR(chan->hc_num)); 1777 1778 dwc2_hc_set_even_odd_frame(hsotg, chan, 1779 &hcchar); 1780 } 1781 1782 /* Load OUT packet into the appropriate Tx FIFO */ 1783 dwc2_hc_write_packet(hsotg, chan); 1784 chan->requests++; 1785 return 1; 1786 } 1787 1788 return 0; 1789 } 1790 1791 /* 1792 * ========================================================================= 1793 * HCD 1794 * ========================================================================= 1795 */ 1796 1797 /* 1798 * Processes all the URBs in a single list of QHs. Completes them with 1799 * -ETIMEDOUT and frees the QTD. 1800 * 1801 * Must be called with interrupt disabled and spinlock held 1802 */ 1803 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1804 struct list_head *qh_list) 1805 { 1806 struct dwc2_qh *qh, *qh_tmp; 1807 struct dwc2_qtd *qtd, *qtd_tmp; 1808 1809 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1810 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1811 qtd_list_entry) { 1812 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1813 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1814 } 1815 } 1816 } 1817 1818 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1819 struct list_head *qh_list) 1820 { 1821 struct dwc2_qtd *qtd, *qtd_tmp; 1822 struct dwc2_qh *qh, *qh_tmp; 1823 unsigned long flags; 1824 1825 if (!qh_list->next) 1826 /* The list hasn't been initialized yet */ 1827 return; 1828 1829 spin_lock_irqsave(&hsotg->lock, flags); 1830 1831 /* Ensure there are no QTDs or URBs left */ 1832 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1833 1834 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1835 dwc2_hcd_qh_unlink(hsotg, qh); 1836 1837 /* Free each QTD in the QH's QTD list */ 1838 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1839 qtd_list_entry) 1840 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1841 1842 if (qh->channel && qh->channel->qh == qh) 1843 qh->channel->qh = NULL; 1844 1845 spin_unlock_irqrestore(&hsotg->lock, flags); 1846 dwc2_hcd_qh_free(hsotg, qh); 1847 spin_lock_irqsave(&hsotg->lock, flags); 1848 } 1849 1850 spin_unlock_irqrestore(&hsotg->lock, flags); 1851 } 1852 1853 /* 1854 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1855 * and periodic schedules. The QTD associated with each URB is removed from 1856 * the schedule and freed. This function may be called when a disconnect is 1857 * detected or when the HCD is being stopped. 1858 * 1859 * Must be called with interrupt disabled and spinlock held 1860 */ 1861 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1862 { 1863 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1864 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 1865 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1866 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1867 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1868 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1869 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1870 } 1871 1872 /** 1873 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1874 * 1875 * @hsotg: Pointer to struct dwc2_hsotg 1876 */ 1877 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1878 { 1879 u32 hprt0; 1880 1881 if (hsotg->op_state == OTG_STATE_B_HOST) { 1882 /* 1883 * Reset the port. During a HNP mode switch the reset 1884 * needs to occur within 1ms and have a duration of at 1885 * least 50ms. 1886 */ 1887 hprt0 = dwc2_read_hprt0(hsotg); 1888 hprt0 |= HPRT0_RST; 1889 dwc2_writel(hsotg, hprt0, HPRT0); 1890 } 1891 1892 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1893 msecs_to_jiffies(50)); 1894 } 1895 1896 /* Must be called with interrupt disabled and spinlock held */ 1897 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1898 { 1899 int num_channels = hsotg->params.host_channels; 1900 struct dwc2_host_chan *channel; 1901 u32 hcchar; 1902 int i; 1903 1904 if (!hsotg->params.host_dma) { 1905 /* Flush out any channel requests in slave mode */ 1906 for (i = 0; i < num_channels; i++) { 1907 channel = hsotg->hc_ptr_array[i]; 1908 if (!list_empty(&channel->hc_list_entry)) 1909 continue; 1910 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1911 if (hcchar & HCCHAR_CHENA) { 1912 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1913 hcchar |= HCCHAR_CHDIS; 1914 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1915 } 1916 } 1917 } 1918 1919 for (i = 0; i < num_channels; i++) { 1920 channel = hsotg->hc_ptr_array[i]; 1921 if (!list_empty(&channel->hc_list_entry)) 1922 continue; 1923 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1924 if (hcchar & HCCHAR_CHENA) { 1925 /* Halt the channel */ 1926 hcchar |= HCCHAR_CHDIS; 1927 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1928 } 1929 1930 dwc2_hc_cleanup(hsotg, channel); 1931 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1932 /* 1933 * Added for Descriptor DMA to prevent channel double cleanup in 1934 * release_channel_ddma(), which is called from ep_disable when 1935 * device disconnects 1936 */ 1937 channel->qh = NULL; 1938 } 1939 /* All channels have been freed, mark them available */ 1940 if (hsotg->params.uframe_sched) { 1941 hsotg->available_host_channels = 1942 hsotg->params.host_channels; 1943 } else { 1944 hsotg->non_periodic_channels = 0; 1945 hsotg->periodic_channels = 0; 1946 } 1947 } 1948 1949 /** 1950 * dwc2_hcd_connect() - Handles connect of the HCD 1951 * 1952 * @hsotg: Pointer to struct dwc2_hsotg 1953 * 1954 * Must be called with interrupt disabled and spinlock held 1955 */ 1956 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1957 { 1958 if (hsotg->lx_state != DWC2_L0) 1959 usb_hcd_resume_root_hub(hsotg->priv); 1960 1961 hsotg->flags.b.port_connect_status_change = 1; 1962 hsotg->flags.b.port_connect_status = 1; 1963 } 1964 1965 /** 1966 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1967 * 1968 * @hsotg: Pointer to struct dwc2_hsotg 1969 * @force: If true, we won't try to reconnect even if we see device connected. 1970 * 1971 * Must be called with interrupt disabled and spinlock held 1972 */ 1973 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1974 { 1975 u32 intr; 1976 u32 hprt0; 1977 1978 /* Set status flags for the hub driver */ 1979 hsotg->flags.b.port_connect_status_change = 1; 1980 hsotg->flags.b.port_connect_status = 0; 1981 1982 /* 1983 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1984 * interrupt mask and status bits and disabling subsequent host 1985 * channel interrupts. 1986 */ 1987 intr = dwc2_readl(hsotg, GINTMSK); 1988 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1989 dwc2_writel(hsotg, intr, GINTMSK); 1990 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1991 dwc2_writel(hsotg, intr, GINTSTS); 1992 1993 /* 1994 * Turn off the vbus power only if the core has transitioned to device 1995 * mode. If still in host mode, need to keep power on to detect a 1996 * reconnection. 1997 */ 1998 if (dwc2_is_device_mode(hsotg)) { 1999 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 2000 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 2001 dwc2_writel(hsotg, 0, HPRT0); 2002 } 2003 2004 dwc2_disable_host_interrupts(hsotg); 2005 } 2006 2007 /* Respond with an error status to all URBs in the schedule */ 2008 dwc2_kill_all_urbs(hsotg); 2009 2010 if (dwc2_is_host_mode(hsotg)) 2011 /* Clean up any host channels that were in use */ 2012 dwc2_hcd_cleanup_channels(hsotg); 2013 2014 dwc2_host_disconnect(hsotg); 2015 2016 /* 2017 * Add an extra check here to see if we're actually connected but 2018 * we don't have a detection interrupt pending. This can happen if: 2019 * 1. hardware sees connect 2020 * 2. hardware sees disconnect 2021 * 3. hardware sees connect 2022 * 4. dwc2_port_intr() - clears connect interrupt 2023 * 5. dwc2_handle_common_intr() - calls here 2024 * 2025 * Without the extra check here we will end calling disconnect 2026 * and won't get any future interrupts to handle the connect. 2027 */ 2028 if (!force) { 2029 hprt0 = dwc2_readl(hsotg, HPRT0); 2030 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 2031 dwc2_hcd_connect(hsotg); 2032 } 2033 } 2034 2035 /** 2036 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 2037 * 2038 * @hsotg: Pointer to struct dwc2_hsotg 2039 */ 2040 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 2041 { 2042 if (hsotg->bus_suspended) { 2043 hsotg->flags.b.port_suspend_change = 1; 2044 usb_hcd_resume_root_hub(hsotg->priv); 2045 } 2046 2047 if (hsotg->lx_state == DWC2_L1) 2048 hsotg->flags.b.port_l1_change = 1; 2049 } 2050 2051 /** 2052 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 2053 * 2054 * @hsotg: Pointer to struct dwc2_hsotg 2055 * 2056 * Must be called with interrupt disabled and spinlock held 2057 */ 2058 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 2059 { 2060 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 2061 2062 /* 2063 * The root hub should be disconnected before this function is called. 2064 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2065 * and the QH lists (via ..._hcd_endpoint_disable). 2066 */ 2067 2068 /* Turn off all host-specific interrupts */ 2069 dwc2_disable_host_interrupts(hsotg); 2070 2071 /* Turn off the vbus power */ 2072 dev_dbg(hsotg->dev, "PortPower off\n"); 2073 dwc2_writel(hsotg, 0, HPRT0); 2074 } 2075 2076 /* Caller must hold driver lock */ 2077 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2078 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2079 struct dwc2_qtd *qtd) 2080 { 2081 u32 intr_mask; 2082 int retval; 2083 int dev_speed; 2084 2085 if (!hsotg->flags.b.port_connect_status) { 2086 /* No longer connected */ 2087 dev_err(hsotg->dev, "Not connected\n"); 2088 return -ENODEV; 2089 } 2090 2091 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2092 2093 /* Some configurations cannot support LS traffic on a FS root port */ 2094 if ((dev_speed == USB_SPEED_LOW) && 2095 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2096 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2097 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 2098 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2099 2100 if (prtspd == HPRT0_SPD_FULL_SPEED) 2101 return -ENODEV; 2102 } 2103 2104 if (!qtd) 2105 return -EINVAL; 2106 2107 dwc2_hcd_qtd_init(qtd, urb); 2108 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2109 if (retval) { 2110 dev_err(hsotg->dev, 2111 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2112 retval); 2113 return retval; 2114 } 2115 2116 intr_mask = dwc2_readl(hsotg, GINTMSK); 2117 if (!(intr_mask & GINTSTS_SOF)) { 2118 enum dwc2_transaction_type tr_type; 2119 2120 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2121 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2122 /* 2123 * Do not schedule SG transactions until qtd has 2124 * URB_GIVEBACK_ASAP set 2125 */ 2126 return 0; 2127 2128 tr_type = dwc2_hcd_select_transactions(hsotg); 2129 if (tr_type != DWC2_TRANSACTION_NONE) 2130 dwc2_hcd_queue_transactions(hsotg, tr_type); 2131 } 2132 2133 return 0; 2134 } 2135 2136 /* Must be called with interrupt disabled and spinlock held */ 2137 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2138 struct dwc2_hcd_urb *urb) 2139 { 2140 struct dwc2_qh *qh; 2141 struct dwc2_qtd *urb_qtd; 2142 2143 urb_qtd = urb->qtd; 2144 if (!urb_qtd) { 2145 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2146 return -EINVAL; 2147 } 2148 2149 qh = urb_qtd->qh; 2150 if (!qh) { 2151 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2152 return -EINVAL; 2153 } 2154 2155 urb->priv = NULL; 2156 2157 if (urb_qtd->in_process && qh->channel) { 2158 dwc2_dump_channel_info(hsotg, qh->channel); 2159 2160 /* The QTD is in process (it has been assigned to a channel) */ 2161 if (hsotg->flags.b.port_connect_status) 2162 /* 2163 * If still connected (i.e. in host mode), halt the 2164 * channel so it can be used for other transfers. If 2165 * no longer connected, the host registers can't be 2166 * written to halt the channel since the core is in 2167 * device mode. 2168 */ 2169 dwc2_hc_halt(hsotg, qh->channel, 2170 DWC2_HC_XFER_URB_DEQUEUE); 2171 } 2172 2173 /* 2174 * Free the QTD and clean up the associated QH. Leave the QH in the 2175 * schedule if it has any remaining QTDs. 2176 */ 2177 if (!hsotg->params.dma_desc_enable) { 2178 u8 in_process = urb_qtd->in_process; 2179 2180 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2181 if (in_process) { 2182 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2183 qh->channel = NULL; 2184 } else if (list_empty(&qh->qtd_list)) { 2185 dwc2_hcd_qh_unlink(hsotg, qh); 2186 } 2187 } else { 2188 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2189 } 2190 2191 return 0; 2192 } 2193 2194 /* Must NOT be called with interrupt disabled or spinlock held */ 2195 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2196 struct usb_host_endpoint *ep, int retry) 2197 { 2198 struct dwc2_qtd *qtd, *qtd_tmp; 2199 struct dwc2_qh *qh; 2200 unsigned long flags; 2201 int rc; 2202 2203 spin_lock_irqsave(&hsotg->lock, flags); 2204 2205 qh = ep->hcpriv; 2206 if (!qh) { 2207 rc = -EINVAL; 2208 goto err; 2209 } 2210 2211 while (!list_empty(&qh->qtd_list) && retry--) { 2212 if (retry == 0) { 2213 dev_err(hsotg->dev, 2214 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2215 rc = -EBUSY; 2216 goto err; 2217 } 2218 2219 spin_unlock_irqrestore(&hsotg->lock, flags); 2220 msleep(20); 2221 spin_lock_irqsave(&hsotg->lock, flags); 2222 qh = ep->hcpriv; 2223 if (!qh) { 2224 rc = -EINVAL; 2225 goto err; 2226 } 2227 } 2228 2229 dwc2_hcd_qh_unlink(hsotg, qh); 2230 2231 /* Free each QTD in the QH's QTD list */ 2232 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2233 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2234 2235 ep->hcpriv = NULL; 2236 2237 if (qh->channel && qh->channel->qh == qh) 2238 qh->channel->qh = NULL; 2239 2240 spin_unlock_irqrestore(&hsotg->lock, flags); 2241 2242 dwc2_hcd_qh_free(hsotg, qh); 2243 2244 return 0; 2245 2246 err: 2247 ep->hcpriv = NULL; 2248 spin_unlock_irqrestore(&hsotg->lock, flags); 2249 2250 return rc; 2251 } 2252 2253 /* Must be called with interrupt disabled and spinlock held */ 2254 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2255 struct usb_host_endpoint *ep) 2256 { 2257 struct dwc2_qh *qh = ep->hcpriv; 2258 2259 if (!qh) 2260 return -EINVAL; 2261 2262 qh->data_toggle = DWC2_HC_PID_DATA0; 2263 2264 return 0; 2265 } 2266 2267 /** 2268 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2269 * prepares the core for device mode or host mode operation 2270 * 2271 * @hsotg: Programming view of the DWC_otg controller 2272 * @initial_setup: If true then this is the first init for this instance. 2273 */ 2274 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2275 { 2276 u32 usbcfg, otgctl; 2277 int retval; 2278 2279 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2280 2281 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2282 2283 /* Set ULPI External VBUS bit if needed */ 2284 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2285 if (hsotg->params.phy_ulpi_ext_vbus) 2286 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2287 2288 /* Set external TS Dline pulsing bit if needed */ 2289 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2290 if (hsotg->params.ts_dline) 2291 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2292 2293 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2294 2295 /* 2296 * Reset the Controller 2297 * 2298 * We only need to reset the controller if this is a re-init. 2299 * For the first init we know for sure that earlier code reset us (it 2300 * needed to in order to properly detect various parameters). 2301 */ 2302 if (!initial_setup) { 2303 retval = dwc2_core_reset(hsotg, false); 2304 if (retval) { 2305 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2306 __func__); 2307 return retval; 2308 } 2309 } 2310 2311 /* 2312 * This needs to happen in FS mode before any other programming occurs 2313 */ 2314 retval = dwc2_phy_init(hsotg, initial_setup); 2315 if (retval) 2316 return retval; 2317 2318 /* Program the GAHBCFG Register */ 2319 retval = dwc2_gahbcfg_init(hsotg); 2320 if (retval) 2321 return retval; 2322 2323 /* Program the GUSBCFG register */ 2324 dwc2_gusbcfg_init(hsotg); 2325 2326 /* Program the GOTGCTL register */ 2327 otgctl = dwc2_readl(hsotg, GOTGCTL); 2328 otgctl &= ~GOTGCTL_OTGVER; 2329 dwc2_writel(hsotg, otgctl, GOTGCTL); 2330 2331 /* Clear the SRP success bit for FS-I2c */ 2332 hsotg->srp_success = 0; 2333 2334 /* Enable common interrupts */ 2335 dwc2_enable_common_interrupts(hsotg); 2336 2337 /* 2338 * Do device or host initialization based on mode during PCD and 2339 * HCD initialization 2340 */ 2341 if (dwc2_is_host_mode(hsotg)) { 2342 dev_dbg(hsotg->dev, "Host Mode\n"); 2343 hsotg->op_state = OTG_STATE_A_HOST; 2344 } else { 2345 dev_dbg(hsotg->dev, "Device Mode\n"); 2346 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2347 } 2348 2349 return 0; 2350 } 2351 2352 /** 2353 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2354 * Host mode 2355 * 2356 * @hsotg: Programming view of DWC_otg controller 2357 * 2358 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2359 * request queues. Host channels are reset to ensure that they are ready for 2360 * performing transfers. 2361 */ 2362 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2363 { 2364 u32 hcfg, hfir, otgctl, usbcfg; 2365 2366 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2367 2368 /* Set HS/FS Timeout Calibration to 7 (max available value). 2369 * The number of PHY clocks that the application programs in 2370 * this field is added to the high/full speed interpacket timeout 2371 * duration in the core to account for any additional delays 2372 * introduced by the PHY. This can be required, because the delay 2373 * introduced by the PHY in generating the linestate condition 2374 * can vary from one PHY to another. 2375 */ 2376 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2377 usbcfg |= GUSBCFG_TOUTCAL(7); 2378 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2379 2380 /* Restart the Phy Clock */ 2381 dwc2_writel(hsotg, 0, PCGCTL); 2382 2383 /* Initialize Host Configuration Register */ 2384 dwc2_init_fs_ls_pclk_sel(hsotg); 2385 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2386 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2387 hcfg = dwc2_readl(hsotg, HCFG); 2388 hcfg |= HCFG_FSLSSUPP; 2389 dwc2_writel(hsotg, hcfg, HCFG); 2390 } 2391 2392 /* 2393 * This bit allows dynamic reloading of the HFIR register during 2394 * runtime. This bit needs to be programmed during initial configuration 2395 * and its value must not be changed during runtime. 2396 */ 2397 if (hsotg->params.reload_ctl) { 2398 hfir = dwc2_readl(hsotg, HFIR); 2399 hfir |= HFIR_RLDCTRL; 2400 dwc2_writel(hsotg, hfir, HFIR); 2401 } 2402 2403 if (hsotg->params.dma_desc_enable) { 2404 u32 op_mode = hsotg->hw_params.op_mode; 2405 2406 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2407 !hsotg->hw_params.dma_desc_enable || 2408 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2409 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2410 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2411 dev_err(hsotg->dev, 2412 "Hardware does not support descriptor DMA mode -\n"); 2413 dev_err(hsotg->dev, 2414 "falling back to buffer DMA mode.\n"); 2415 hsotg->params.dma_desc_enable = false; 2416 } else { 2417 hcfg = dwc2_readl(hsotg, HCFG); 2418 hcfg |= HCFG_DESCDMA; 2419 dwc2_writel(hsotg, hcfg, HCFG); 2420 } 2421 } 2422 2423 /* Configure data FIFO sizes */ 2424 dwc2_config_fifos(hsotg); 2425 2426 /* TODO - check this */ 2427 /* Clear Host Set HNP Enable in the OTG Control Register */ 2428 otgctl = dwc2_readl(hsotg, GOTGCTL); 2429 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2430 dwc2_writel(hsotg, otgctl, GOTGCTL); 2431 2432 /* Make sure the FIFOs are flushed */ 2433 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2434 dwc2_flush_rx_fifo(hsotg); 2435 2436 /* Clear Host Set HNP Enable in the OTG Control Register */ 2437 otgctl = dwc2_readl(hsotg, GOTGCTL); 2438 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2439 dwc2_writel(hsotg, otgctl, GOTGCTL); 2440 2441 if (!hsotg->params.dma_desc_enable) { 2442 int num_channels, i; 2443 u32 hcchar; 2444 2445 /* Flush out any leftover queued requests */ 2446 num_channels = hsotg->params.host_channels; 2447 for (i = 0; i < num_channels; i++) { 2448 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2449 hcchar &= ~HCCHAR_CHENA; 2450 hcchar |= HCCHAR_CHDIS; 2451 hcchar &= ~HCCHAR_EPDIR; 2452 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2453 } 2454 2455 /* Halt all channels to put them into a known state */ 2456 for (i = 0; i < num_channels; i++) { 2457 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2458 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2459 hcchar &= ~HCCHAR_EPDIR; 2460 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2461 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2462 __func__, i); 2463 2464 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), 2465 HCCHAR_CHENA, 1000)) { 2466 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n", 2467 i); 2468 } 2469 } 2470 } 2471 2472 /* Enable ACG feature in host mode, if supported */ 2473 dwc2_enable_acg(hsotg); 2474 2475 /* Turn on the vbus power */ 2476 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2477 if (hsotg->op_state == OTG_STATE_A_HOST) { 2478 u32 hprt0 = dwc2_read_hprt0(hsotg); 2479 2480 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2481 !!(hprt0 & HPRT0_PWR)); 2482 if (!(hprt0 & HPRT0_PWR)) { 2483 hprt0 |= HPRT0_PWR; 2484 dwc2_writel(hsotg, hprt0, HPRT0); 2485 } 2486 } 2487 2488 dwc2_enable_host_interrupts(hsotg); 2489 } 2490 2491 /* 2492 * Initializes dynamic portions of the DWC_otg HCD state 2493 * 2494 * Must be called with interrupt disabled and spinlock held 2495 */ 2496 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2497 { 2498 struct dwc2_host_chan *chan, *chan_tmp; 2499 int num_channels; 2500 int i; 2501 2502 hsotg->flags.d32 = 0; 2503 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2504 2505 if (hsotg->params.uframe_sched) { 2506 hsotg->available_host_channels = 2507 hsotg->params.host_channels; 2508 } else { 2509 hsotg->non_periodic_channels = 0; 2510 hsotg->periodic_channels = 0; 2511 } 2512 2513 /* 2514 * Put all channels in the free channel list and clean up channel 2515 * states 2516 */ 2517 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2518 hc_list_entry) 2519 list_del_init(&chan->hc_list_entry); 2520 2521 num_channels = hsotg->params.host_channels; 2522 for (i = 0; i < num_channels; i++) { 2523 chan = hsotg->hc_ptr_array[i]; 2524 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2525 dwc2_hc_cleanup(hsotg, chan); 2526 } 2527 2528 /* Initialize the DWC core for host mode operation */ 2529 dwc2_core_host_init(hsotg); 2530 } 2531 2532 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2533 struct dwc2_host_chan *chan, 2534 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2535 { 2536 int hub_addr, hub_port; 2537 2538 chan->do_split = 1; 2539 chan->xact_pos = qtd->isoc_split_pos; 2540 chan->complete_split = qtd->complete_split; 2541 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2542 chan->hub_addr = (u8)hub_addr; 2543 chan->hub_port = (u8)hub_port; 2544 } 2545 2546 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2547 struct dwc2_host_chan *chan, 2548 struct dwc2_qtd *qtd) 2549 { 2550 struct dwc2_hcd_urb *urb = qtd->urb; 2551 struct dwc2_hcd_iso_packet_desc *frame_desc; 2552 2553 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2554 case USB_ENDPOINT_XFER_CONTROL: 2555 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2556 2557 switch (qtd->control_phase) { 2558 case DWC2_CONTROL_SETUP: 2559 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2560 chan->do_ping = 0; 2561 chan->ep_is_in = 0; 2562 chan->data_pid_start = DWC2_HC_PID_SETUP; 2563 if (hsotg->params.host_dma) 2564 chan->xfer_dma = urb->setup_dma; 2565 else 2566 chan->xfer_buf = urb->setup_packet; 2567 chan->xfer_len = 8; 2568 break; 2569 2570 case DWC2_CONTROL_DATA: 2571 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2572 chan->data_pid_start = qtd->data_toggle; 2573 break; 2574 2575 case DWC2_CONTROL_STATUS: 2576 /* 2577 * Direction is opposite of data direction or IN if no 2578 * data 2579 */ 2580 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2581 if (urb->length == 0) 2582 chan->ep_is_in = 1; 2583 else 2584 chan->ep_is_in = 2585 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2586 if (chan->ep_is_in) 2587 chan->do_ping = 0; 2588 chan->data_pid_start = DWC2_HC_PID_DATA1; 2589 chan->xfer_len = 0; 2590 if (hsotg->params.host_dma) 2591 chan->xfer_dma = hsotg->status_buf_dma; 2592 else 2593 chan->xfer_buf = hsotg->status_buf; 2594 break; 2595 } 2596 break; 2597 2598 case USB_ENDPOINT_XFER_BULK: 2599 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2600 break; 2601 2602 case USB_ENDPOINT_XFER_INT: 2603 chan->ep_type = USB_ENDPOINT_XFER_INT; 2604 break; 2605 2606 case USB_ENDPOINT_XFER_ISOC: 2607 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2608 if (hsotg->params.dma_desc_enable) 2609 break; 2610 2611 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2612 frame_desc->status = 0; 2613 2614 if (hsotg->params.host_dma) { 2615 chan->xfer_dma = urb->dma; 2616 chan->xfer_dma += frame_desc->offset + 2617 qtd->isoc_split_offset; 2618 } else { 2619 chan->xfer_buf = urb->buf; 2620 chan->xfer_buf += frame_desc->offset + 2621 qtd->isoc_split_offset; 2622 } 2623 2624 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2625 2626 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2627 if (chan->xfer_len <= 188) 2628 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2629 else 2630 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2631 } 2632 break; 2633 } 2634 } 2635 2636 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg, 2637 struct dwc2_qh *qh, 2638 struct dwc2_host_chan *chan) 2639 { 2640 if (!hsotg->unaligned_cache || 2641 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE) 2642 return -ENOMEM; 2643 2644 if (!qh->dw_align_buf) { 2645 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache, 2646 GFP_ATOMIC | GFP_DMA); 2647 if (!qh->dw_align_buf) 2648 return -ENOMEM; 2649 } 2650 2651 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf, 2652 DWC2_KMEM_UNALIGNED_BUF_SIZE, 2653 DMA_FROM_DEVICE); 2654 2655 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 2656 dev_err(hsotg->dev, "can't map align_buf\n"); 2657 chan->align_buf = 0; 2658 return -EINVAL; 2659 } 2660 2661 chan->align_buf = qh->dw_align_buf_dma; 2662 return 0; 2663 } 2664 2665 #define DWC2_USB_DMA_ALIGN 4 2666 2667 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2668 { 2669 void *stored_xfer_buffer; 2670 size_t length; 2671 2672 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2673 return; 2674 2675 /* Restore urb->transfer_buffer from the end of the allocated area */ 2676 memcpy(&stored_xfer_buffer, urb->transfer_buffer + 2677 urb->transfer_buffer_length, sizeof(urb->transfer_buffer)); 2678 2679 if (usb_urb_dir_in(urb)) { 2680 if (usb_pipeisoc(urb->pipe)) 2681 length = urb->transfer_buffer_length; 2682 else 2683 length = urb->actual_length; 2684 2685 memcpy(stored_xfer_buffer, urb->transfer_buffer, length); 2686 } 2687 kfree(urb->transfer_buffer); 2688 urb->transfer_buffer = stored_xfer_buffer; 2689 2690 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2691 } 2692 2693 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2694 { 2695 void *kmalloc_ptr; 2696 size_t kmalloc_size; 2697 2698 if (urb->num_sgs || urb->sg || 2699 urb->transfer_buffer_length == 0 || 2700 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2701 return 0; 2702 2703 /* 2704 * Allocate a buffer with enough padding for original transfer_buffer 2705 * pointer. This allocation is guaranteed to be aligned properly for 2706 * DMA 2707 */ 2708 kmalloc_size = urb->transfer_buffer_length + 2709 sizeof(urb->transfer_buffer); 2710 2711 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2712 if (!kmalloc_ptr) 2713 return -ENOMEM; 2714 2715 /* 2716 * Position value of original urb->transfer_buffer pointer to the end 2717 * of allocation for later referencing 2718 */ 2719 memcpy(kmalloc_ptr + urb->transfer_buffer_length, 2720 &urb->transfer_buffer, sizeof(urb->transfer_buffer)); 2721 2722 if (usb_urb_dir_out(urb)) 2723 memcpy(kmalloc_ptr, urb->transfer_buffer, 2724 urb->transfer_buffer_length); 2725 urb->transfer_buffer = kmalloc_ptr; 2726 2727 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2728 2729 return 0; 2730 } 2731 2732 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2733 gfp_t mem_flags) 2734 { 2735 int ret; 2736 2737 /* We assume setup_dma is always aligned; warn if not */ 2738 WARN_ON_ONCE(urb->setup_dma && 2739 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2740 2741 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2742 if (ret) 2743 return ret; 2744 2745 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2746 if (ret) 2747 dwc2_free_dma_aligned_buffer(urb); 2748 2749 return ret; 2750 } 2751 2752 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2753 { 2754 usb_hcd_unmap_urb_for_dma(hcd, urb); 2755 dwc2_free_dma_aligned_buffer(urb); 2756 } 2757 2758 /** 2759 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2760 * channel and initializes the host channel to perform the transactions. The 2761 * host channel is removed from the free list. 2762 * 2763 * @hsotg: The HCD state structure 2764 * @qh: Transactions from the first QTD for this QH are selected and assigned 2765 * to a free host channel 2766 */ 2767 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2768 { 2769 struct dwc2_host_chan *chan; 2770 struct dwc2_hcd_urb *urb; 2771 struct dwc2_qtd *qtd; 2772 2773 if (dbg_qh(qh)) 2774 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2775 2776 if (list_empty(&qh->qtd_list)) { 2777 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2778 return -ENOMEM; 2779 } 2780 2781 if (list_empty(&hsotg->free_hc_list)) { 2782 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2783 return -ENOMEM; 2784 } 2785 2786 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2787 hc_list_entry); 2788 2789 /* Remove host channel from free list */ 2790 list_del_init(&chan->hc_list_entry); 2791 2792 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2793 urb = qtd->urb; 2794 qh->channel = chan; 2795 qtd->in_process = 1; 2796 2797 /* 2798 * Use usb_pipedevice to determine device address. This address is 2799 * 0 before the SET_ADDRESS command and the correct address afterward. 2800 */ 2801 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2802 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2803 chan->speed = qh->dev_speed; 2804 chan->max_packet = dwc2_max_packet(qh->maxp); 2805 2806 chan->xfer_started = 0; 2807 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2808 chan->error_state = (qtd->error_count > 0); 2809 chan->halt_on_queue = 0; 2810 chan->halt_pending = 0; 2811 chan->requests = 0; 2812 2813 /* 2814 * The following values may be modified in the transfer type section 2815 * below. The xfer_len value may be reduced when the transfer is 2816 * started to accommodate the max widths of the XferSize and PktCnt 2817 * fields in the HCTSIZn register. 2818 */ 2819 2820 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2821 if (chan->ep_is_in) 2822 chan->do_ping = 0; 2823 else 2824 chan->do_ping = qh->ping_state; 2825 2826 chan->data_pid_start = qh->data_toggle; 2827 chan->multi_count = 1; 2828 2829 if (urb->actual_length > urb->length && 2830 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2831 urb->actual_length = urb->length; 2832 2833 if (hsotg->params.host_dma) 2834 chan->xfer_dma = urb->dma + urb->actual_length; 2835 else 2836 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2837 2838 chan->xfer_len = urb->length - urb->actual_length; 2839 chan->xfer_count = 0; 2840 2841 /* Set the split attributes if required */ 2842 if (qh->do_split) 2843 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2844 else 2845 chan->do_split = 0; 2846 2847 /* Set the transfer attributes */ 2848 dwc2_hc_init_xfer(hsotg, chan, qtd); 2849 2850 /* For non-dword aligned buffers */ 2851 if (hsotg->params.host_dma && qh->do_split && 2852 chan->ep_is_in && (chan->xfer_dma & 0x3)) { 2853 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 2854 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) { 2855 dev_err(hsotg->dev, 2856 "Failed to allocate memory to handle non-aligned buffer\n"); 2857 /* Add channel back to free list */ 2858 chan->align_buf = 0; 2859 chan->multi_count = 0; 2860 list_add_tail(&chan->hc_list_entry, 2861 &hsotg->free_hc_list); 2862 qtd->in_process = 0; 2863 qh->channel = NULL; 2864 return -ENOMEM; 2865 } 2866 } else { 2867 /* 2868 * We assume that DMA is always aligned in non-split 2869 * case or split out case. Warn if not. 2870 */ 2871 WARN_ON_ONCE(hsotg->params.host_dma && 2872 (chan->xfer_dma & 0x3)); 2873 chan->align_buf = 0; 2874 } 2875 2876 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2877 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2878 /* 2879 * This value may be modified when the transfer is started 2880 * to reflect the actual transfer length 2881 */ 2882 chan->multi_count = dwc2_hb_mult(qh->maxp); 2883 2884 if (hsotg->params.dma_desc_enable) { 2885 chan->desc_list_addr = qh->desc_list_dma; 2886 chan->desc_list_sz = qh->desc_list_sz; 2887 } 2888 2889 dwc2_hc_init(hsotg, chan); 2890 chan->qh = qh; 2891 2892 return 0; 2893 } 2894 2895 /** 2896 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2897 * schedule and assigns them to available host channels. Called from the HCD 2898 * interrupt handler functions. 2899 * 2900 * @hsotg: The HCD state structure 2901 * 2902 * Return: The types of new transactions that were assigned to host channels 2903 */ 2904 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2905 struct dwc2_hsotg *hsotg) 2906 { 2907 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2908 struct list_head *qh_ptr; 2909 struct dwc2_qh *qh; 2910 int num_channels; 2911 2912 #ifdef DWC2_DEBUG_SOF 2913 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2914 #endif 2915 2916 /* Process entries in the periodic ready list */ 2917 qh_ptr = hsotg->periodic_sched_ready.next; 2918 while (qh_ptr != &hsotg->periodic_sched_ready) { 2919 if (list_empty(&hsotg->free_hc_list)) 2920 break; 2921 if (hsotg->params.uframe_sched) { 2922 if (hsotg->available_host_channels <= 1) 2923 break; 2924 hsotg->available_host_channels--; 2925 } 2926 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2927 if (dwc2_assign_and_init_hc(hsotg, qh)) 2928 break; 2929 2930 /* 2931 * Move the QH from the periodic ready schedule to the 2932 * periodic assigned schedule 2933 */ 2934 qh_ptr = qh_ptr->next; 2935 list_move_tail(&qh->qh_list_entry, 2936 &hsotg->periodic_sched_assigned); 2937 ret_val = DWC2_TRANSACTION_PERIODIC; 2938 } 2939 2940 /* 2941 * Process entries in the inactive portion of the non-periodic 2942 * schedule. Some free host channels may not be used if they are 2943 * reserved for periodic transfers. 2944 */ 2945 num_channels = hsotg->params.host_channels; 2946 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2947 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2948 if (!hsotg->params.uframe_sched && 2949 hsotg->non_periodic_channels >= num_channels - 2950 hsotg->periodic_channels) 2951 break; 2952 if (list_empty(&hsotg->free_hc_list)) 2953 break; 2954 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2955 if (hsotg->params.uframe_sched) { 2956 if (hsotg->available_host_channels < 1) 2957 break; 2958 hsotg->available_host_channels--; 2959 } 2960 2961 if (dwc2_assign_and_init_hc(hsotg, qh)) 2962 break; 2963 2964 /* 2965 * Move the QH from the non-periodic inactive schedule to the 2966 * non-periodic active schedule 2967 */ 2968 qh_ptr = qh_ptr->next; 2969 list_move_tail(&qh->qh_list_entry, 2970 &hsotg->non_periodic_sched_active); 2971 2972 if (ret_val == DWC2_TRANSACTION_NONE) 2973 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2974 else 2975 ret_val = DWC2_TRANSACTION_ALL; 2976 2977 if (!hsotg->params.uframe_sched) 2978 hsotg->non_periodic_channels++; 2979 } 2980 2981 return ret_val; 2982 } 2983 2984 /** 2985 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2986 * a host channel associated with either a periodic or non-periodic transfer 2987 * 2988 * @hsotg: The HCD state structure 2989 * @chan: Host channel descriptor associated with either a periodic or 2990 * non-periodic transfer 2991 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2992 * for periodic transfers or the non-periodic Tx FIFO 2993 * for non-periodic transfers 2994 * 2995 * Return: 1 if a request is queued and more requests may be needed to 2996 * complete the transfer, 0 if no more requests are required for this 2997 * transfer, -1 if there is insufficient space in the Tx FIFO 2998 * 2999 * This function assumes that there is space available in the appropriate 3000 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 3001 * it checks whether space is available in the appropriate Tx FIFO. 3002 * 3003 * Must be called with interrupt disabled and spinlock held 3004 */ 3005 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 3006 struct dwc2_host_chan *chan, 3007 u16 fifo_dwords_avail) 3008 { 3009 int retval = 0; 3010 3011 if (chan->do_split) 3012 /* Put ourselves on the list to keep order straight */ 3013 list_move_tail(&chan->split_order_list_entry, 3014 &hsotg->split_order); 3015 3016 if (hsotg->params.host_dma) { 3017 if (hsotg->params.dma_desc_enable) { 3018 if (!chan->xfer_started || 3019 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 3020 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 3021 chan->qh->ping_state = 0; 3022 } 3023 } else if (!chan->xfer_started) { 3024 dwc2_hc_start_transfer(hsotg, chan); 3025 chan->qh->ping_state = 0; 3026 } 3027 } else if (chan->halt_pending) { 3028 /* Don't queue a request if the channel has been halted */ 3029 } else if (chan->halt_on_queue) { 3030 dwc2_hc_halt(hsotg, chan, chan->halt_status); 3031 } else if (chan->do_ping) { 3032 if (!chan->xfer_started) 3033 dwc2_hc_start_transfer(hsotg, chan); 3034 } else if (!chan->ep_is_in || 3035 chan->data_pid_start == DWC2_HC_PID_SETUP) { 3036 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 3037 if (!chan->xfer_started) { 3038 dwc2_hc_start_transfer(hsotg, chan); 3039 retval = 1; 3040 } else { 3041 retval = dwc2_hc_continue_transfer(hsotg, chan); 3042 } 3043 } else { 3044 retval = -1; 3045 } 3046 } else { 3047 if (!chan->xfer_started) { 3048 dwc2_hc_start_transfer(hsotg, chan); 3049 retval = 1; 3050 } else { 3051 retval = dwc2_hc_continue_transfer(hsotg, chan); 3052 } 3053 } 3054 3055 return retval; 3056 } 3057 3058 /* 3059 * Processes periodic channels for the next frame and queues transactions for 3060 * these channels to the DWC_otg controller. After queueing transactions, the 3061 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 3062 * to queue as Periodic Tx FIFO or request queue space becomes available. 3063 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 3064 * 3065 * Must be called with interrupt disabled and spinlock held 3066 */ 3067 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 3068 { 3069 struct list_head *qh_ptr; 3070 struct dwc2_qh *qh; 3071 u32 tx_status; 3072 u32 fspcavail; 3073 u32 gintmsk; 3074 int status; 3075 bool no_queue_space = false; 3076 bool no_fifo_space = false; 3077 u32 qspcavail; 3078 3079 /* If empty list then just adjust interrupt enables */ 3080 if (list_empty(&hsotg->periodic_sched_assigned)) 3081 goto exit; 3082 3083 if (dbg_perio()) 3084 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 3085 3086 tx_status = dwc2_readl(hsotg, HPTXSTS); 3087 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3088 TXSTS_QSPCAVAIL_SHIFT; 3089 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3090 TXSTS_FSPCAVAIL_SHIFT; 3091 3092 if (dbg_perio()) { 3093 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 3094 qspcavail); 3095 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 3096 fspcavail); 3097 } 3098 3099 qh_ptr = hsotg->periodic_sched_assigned.next; 3100 while (qh_ptr != &hsotg->periodic_sched_assigned) { 3101 tx_status = dwc2_readl(hsotg, HPTXSTS); 3102 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3103 TXSTS_QSPCAVAIL_SHIFT; 3104 if (qspcavail == 0) { 3105 no_queue_space = true; 3106 break; 3107 } 3108 3109 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 3110 if (!qh->channel) { 3111 qh_ptr = qh_ptr->next; 3112 continue; 3113 } 3114 3115 /* Make sure EP's TT buffer is clean before queueing qtds */ 3116 if (qh->tt_buffer_dirty) { 3117 qh_ptr = qh_ptr->next; 3118 continue; 3119 } 3120 3121 /* 3122 * Set a flag if we're queuing high-bandwidth in slave mode. 3123 * The flag prevents any halts to get into the request queue in 3124 * the middle of multiple high-bandwidth packets getting queued. 3125 */ 3126 if (!hsotg->params.host_dma && 3127 qh->channel->multi_count > 1) 3128 hsotg->queuing_high_bandwidth = 1; 3129 3130 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3131 TXSTS_FSPCAVAIL_SHIFT; 3132 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3133 if (status < 0) { 3134 no_fifo_space = true; 3135 break; 3136 } 3137 3138 /* 3139 * In Slave mode, stay on the current transfer until there is 3140 * nothing more to do or the high-bandwidth request count is 3141 * reached. In DMA mode, only need to queue one request. The 3142 * controller automatically handles multiple packets for 3143 * high-bandwidth transfers. 3144 */ 3145 if (hsotg->params.host_dma || status == 0 || 3146 qh->channel->requests == qh->channel->multi_count) { 3147 qh_ptr = qh_ptr->next; 3148 /* 3149 * Move the QH from the periodic assigned schedule to 3150 * the periodic queued schedule 3151 */ 3152 list_move_tail(&qh->qh_list_entry, 3153 &hsotg->periodic_sched_queued); 3154 3155 /* done queuing high bandwidth */ 3156 hsotg->queuing_high_bandwidth = 0; 3157 } 3158 } 3159 3160 exit: 3161 if (no_queue_space || no_fifo_space || 3162 (!hsotg->params.host_dma && 3163 !list_empty(&hsotg->periodic_sched_assigned))) { 3164 /* 3165 * May need to queue more transactions as the request 3166 * queue or Tx FIFO empties. Enable the periodic Tx 3167 * FIFO empty interrupt. (Always use the half-empty 3168 * level to ensure that new requests are loaded as 3169 * soon as possible.) 3170 */ 3171 gintmsk = dwc2_readl(hsotg, GINTMSK); 3172 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3173 gintmsk |= GINTSTS_PTXFEMP; 3174 dwc2_writel(hsotg, gintmsk, GINTMSK); 3175 } 3176 } else { 3177 /* 3178 * Disable the Tx FIFO empty interrupt since there are 3179 * no more transactions that need to be queued right 3180 * now. This function is called from interrupt 3181 * handlers to queue more transactions as transfer 3182 * states change. 3183 */ 3184 gintmsk = dwc2_readl(hsotg, GINTMSK); 3185 if (gintmsk & GINTSTS_PTXFEMP) { 3186 gintmsk &= ~GINTSTS_PTXFEMP; 3187 dwc2_writel(hsotg, gintmsk, GINTMSK); 3188 } 3189 } 3190 } 3191 3192 /* 3193 * Processes active non-periodic channels and queues transactions for these 3194 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3195 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3196 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3197 * FIFO Empty interrupt is disabled. 3198 * 3199 * Must be called with interrupt disabled and spinlock held 3200 */ 3201 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3202 { 3203 struct list_head *orig_qh_ptr; 3204 struct dwc2_qh *qh; 3205 u32 tx_status; 3206 u32 qspcavail; 3207 u32 fspcavail; 3208 u32 gintmsk; 3209 int status; 3210 int no_queue_space = 0; 3211 int no_fifo_space = 0; 3212 int more_to_do = 0; 3213 3214 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3215 3216 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3217 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3218 TXSTS_QSPCAVAIL_SHIFT; 3219 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3220 TXSTS_FSPCAVAIL_SHIFT; 3221 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3222 qspcavail); 3223 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3224 fspcavail); 3225 3226 /* 3227 * Keep track of the starting point. Skip over the start-of-list 3228 * entry. 3229 */ 3230 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3231 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3232 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3233 3234 /* 3235 * Process once through the active list or until no more space is 3236 * available in the request queue or the Tx FIFO 3237 */ 3238 do { 3239 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3240 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3241 TXSTS_QSPCAVAIL_SHIFT; 3242 if (!hsotg->params.host_dma && qspcavail == 0) { 3243 no_queue_space = 1; 3244 break; 3245 } 3246 3247 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3248 qh_list_entry); 3249 if (!qh->channel) 3250 goto next; 3251 3252 /* Make sure EP's TT buffer is clean before queueing qtds */ 3253 if (qh->tt_buffer_dirty) 3254 goto next; 3255 3256 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3257 TXSTS_FSPCAVAIL_SHIFT; 3258 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3259 3260 if (status > 0) { 3261 more_to_do = 1; 3262 } else if (status < 0) { 3263 no_fifo_space = 1; 3264 break; 3265 } 3266 next: 3267 /* Advance to next QH, skipping start-of-list entry */ 3268 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3269 if (hsotg->non_periodic_qh_ptr == 3270 &hsotg->non_periodic_sched_active) 3271 hsotg->non_periodic_qh_ptr = 3272 hsotg->non_periodic_qh_ptr->next; 3273 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3274 3275 if (!hsotg->params.host_dma) { 3276 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3277 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3278 TXSTS_QSPCAVAIL_SHIFT; 3279 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3280 TXSTS_FSPCAVAIL_SHIFT; 3281 dev_vdbg(hsotg->dev, 3282 " NP Tx Req Queue Space Avail (after queue): %d\n", 3283 qspcavail); 3284 dev_vdbg(hsotg->dev, 3285 " NP Tx FIFO Space Avail (after queue): %d\n", 3286 fspcavail); 3287 3288 if (more_to_do || no_queue_space || no_fifo_space) { 3289 /* 3290 * May need to queue more transactions as the request 3291 * queue or Tx FIFO empties. Enable the non-periodic 3292 * Tx FIFO empty interrupt. (Always use the half-empty 3293 * level to ensure that new requests are loaded as 3294 * soon as possible.) 3295 */ 3296 gintmsk = dwc2_readl(hsotg, GINTMSK); 3297 gintmsk |= GINTSTS_NPTXFEMP; 3298 dwc2_writel(hsotg, gintmsk, GINTMSK); 3299 } else { 3300 /* 3301 * Disable the Tx FIFO empty interrupt since there are 3302 * no more transactions that need to be queued right 3303 * now. This function is called from interrupt 3304 * handlers to queue more transactions as transfer 3305 * states change. 3306 */ 3307 gintmsk = dwc2_readl(hsotg, GINTMSK); 3308 gintmsk &= ~GINTSTS_NPTXFEMP; 3309 dwc2_writel(hsotg, gintmsk, GINTMSK); 3310 } 3311 } 3312 } 3313 3314 /** 3315 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3316 * and queues transactions for these channels to the DWC_otg controller. Called 3317 * from the HCD interrupt handler functions. 3318 * 3319 * @hsotg: The HCD state structure 3320 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3321 * or both) 3322 * 3323 * Must be called with interrupt disabled and spinlock held 3324 */ 3325 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3326 enum dwc2_transaction_type tr_type) 3327 { 3328 #ifdef DWC2_DEBUG_SOF 3329 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3330 #endif 3331 /* Process host channels associated with periodic transfers */ 3332 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3333 tr_type == DWC2_TRANSACTION_ALL) 3334 dwc2_process_periodic_channels(hsotg); 3335 3336 /* Process host channels associated with non-periodic transfers */ 3337 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3338 tr_type == DWC2_TRANSACTION_ALL) { 3339 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3340 dwc2_process_non_periodic_channels(hsotg); 3341 } else { 3342 /* 3343 * Ensure NP Tx FIFO empty interrupt is disabled when 3344 * there are no non-periodic transfers to process 3345 */ 3346 u32 gintmsk = dwc2_readl(hsotg, GINTMSK); 3347 3348 gintmsk &= ~GINTSTS_NPTXFEMP; 3349 dwc2_writel(hsotg, gintmsk, GINTMSK); 3350 } 3351 } 3352 } 3353 3354 static void dwc2_conn_id_status_change(struct work_struct *work) 3355 { 3356 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3357 wf_otg); 3358 u32 count = 0; 3359 u32 gotgctl; 3360 unsigned long flags; 3361 3362 dev_dbg(hsotg->dev, "%s()\n", __func__); 3363 3364 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3365 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3366 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3367 !!(gotgctl & GOTGCTL_CONID_B)); 3368 3369 /* B-Device connector (Device Mode) */ 3370 if (gotgctl & GOTGCTL_CONID_B) { 3371 dwc2_vbus_supply_exit(hsotg); 3372 /* Wait for switch to device mode */ 3373 dev_dbg(hsotg->dev, "connId B\n"); 3374 if (hsotg->bus_suspended) { 3375 dev_info(hsotg->dev, 3376 "Do port resume before switching to device mode\n"); 3377 dwc2_port_resume(hsotg); 3378 } 3379 while (!dwc2_is_device_mode(hsotg)) { 3380 dev_info(hsotg->dev, 3381 "Waiting for Peripheral Mode, Mode=%s\n", 3382 dwc2_is_host_mode(hsotg) ? "Host" : 3383 "Peripheral"); 3384 msleep(20); 3385 /* 3386 * Sometimes the initial GOTGCTRL read is wrong, so 3387 * check it again and jump to host mode if that was 3388 * the case. 3389 */ 3390 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3391 if (!(gotgctl & GOTGCTL_CONID_B)) 3392 goto host; 3393 if (++count > 250) 3394 break; 3395 } 3396 if (count > 250) 3397 dev_err(hsotg->dev, 3398 "Connection id status change timed out\n"); 3399 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3400 dwc2_core_init(hsotg, false); 3401 dwc2_enable_global_interrupts(hsotg); 3402 spin_lock_irqsave(&hsotg->lock, flags); 3403 dwc2_hsotg_core_init_disconnected(hsotg, false); 3404 spin_unlock_irqrestore(&hsotg->lock, flags); 3405 /* Enable ACG feature in device mode,if supported */ 3406 dwc2_enable_acg(hsotg); 3407 dwc2_hsotg_core_connect(hsotg); 3408 } else { 3409 host: 3410 /* A-Device connector (Host Mode) */ 3411 dev_dbg(hsotg->dev, "connId A\n"); 3412 while (!dwc2_is_host_mode(hsotg)) { 3413 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3414 dwc2_is_host_mode(hsotg) ? 3415 "Host" : "Peripheral"); 3416 msleep(20); 3417 if (++count > 250) 3418 break; 3419 } 3420 if (count > 250) 3421 dev_err(hsotg->dev, 3422 "Connection id status change timed out\n"); 3423 3424 spin_lock_irqsave(&hsotg->lock, flags); 3425 dwc2_hsotg_disconnect(hsotg); 3426 spin_unlock_irqrestore(&hsotg->lock, flags); 3427 3428 hsotg->op_state = OTG_STATE_A_HOST; 3429 /* Initialize the Core for Host mode */ 3430 dwc2_core_init(hsotg, false); 3431 dwc2_enable_global_interrupts(hsotg); 3432 dwc2_hcd_start(hsotg); 3433 } 3434 } 3435 3436 static void dwc2_wakeup_detected(struct timer_list *t) 3437 { 3438 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); 3439 u32 hprt0; 3440 3441 dev_dbg(hsotg->dev, "%s()\n", __func__); 3442 3443 /* 3444 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3445 * so that OPT tests pass with all PHYs.) 3446 */ 3447 hprt0 = dwc2_read_hprt0(hsotg); 3448 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3449 hprt0 &= ~HPRT0_RES; 3450 dwc2_writel(hsotg, hprt0, HPRT0); 3451 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3452 dwc2_readl(hsotg, HPRT0)); 3453 3454 dwc2_hcd_rem_wakeup(hsotg); 3455 hsotg->bus_suspended = false; 3456 3457 /* Change to L0 state */ 3458 hsotg->lx_state = DWC2_L0; 3459 } 3460 3461 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3462 { 3463 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3464 3465 return hcd->self.b_hnp_enable; 3466 } 3467 3468 /* Must NOT be called with interrupt disabled or spinlock held */ 3469 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3470 { 3471 unsigned long flags; 3472 u32 hprt0; 3473 u32 pcgctl; 3474 u32 gotgctl; 3475 3476 dev_dbg(hsotg->dev, "%s()\n", __func__); 3477 3478 spin_lock_irqsave(&hsotg->lock, flags); 3479 3480 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3481 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3482 gotgctl |= GOTGCTL_HSTSETHNPEN; 3483 dwc2_writel(hsotg, gotgctl, GOTGCTL); 3484 hsotg->op_state = OTG_STATE_A_SUSPEND; 3485 } 3486 3487 hprt0 = dwc2_read_hprt0(hsotg); 3488 hprt0 |= HPRT0_SUSP; 3489 dwc2_writel(hsotg, hprt0, HPRT0); 3490 3491 hsotg->bus_suspended = true; 3492 3493 /* 3494 * If power_down is supported, Phy clock will be suspended 3495 * after registers are backuped. 3496 */ 3497 if (!hsotg->params.power_down) { 3498 /* Suspend the Phy Clock */ 3499 pcgctl = dwc2_readl(hsotg, PCGCTL); 3500 pcgctl |= PCGCTL_STOPPCLK; 3501 dwc2_writel(hsotg, pcgctl, PCGCTL); 3502 udelay(10); 3503 } 3504 3505 /* For HNP the bus must be suspended for at least 200ms */ 3506 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3507 pcgctl = dwc2_readl(hsotg, PCGCTL); 3508 pcgctl &= ~PCGCTL_STOPPCLK; 3509 dwc2_writel(hsotg, pcgctl, PCGCTL); 3510 3511 spin_unlock_irqrestore(&hsotg->lock, flags); 3512 3513 msleep(200); 3514 } else { 3515 spin_unlock_irqrestore(&hsotg->lock, flags); 3516 } 3517 } 3518 3519 /* Must NOT be called with interrupt disabled or spinlock held */ 3520 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3521 { 3522 unsigned long flags; 3523 u32 hprt0; 3524 u32 pcgctl; 3525 3526 spin_lock_irqsave(&hsotg->lock, flags); 3527 3528 /* 3529 * If power_down is supported, Phy clock is already resumed 3530 * after registers restore. 3531 */ 3532 if (!hsotg->params.power_down) { 3533 pcgctl = dwc2_readl(hsotg, PCGCTL); 3534 pcgctl &= ~PCGCTL_STOPPCLK; 3535 dwc2_writel(hsotg, pcgctl, PCGCTL); 3536 spin_unlock_irqrestore(&hsotg->lock, flags); 3537 msleep(20); 3538 spin_lock_irqsave(&hsotg->lock, flags); 3539 } 3540 3541 hprt0 = dwc2_read_hprt0(hsotg); 3542 hprt0 |= HPRT0_RES; 3543 hprt0 &= ~HPRT0_SUSP; 3544 dwc2_writel(hsotg, hprt0, HPRT0); 3545 spin_unlock_irqrestore(&hsotg->lock, flags); 3546 3547 msleep(USB_RESUME_TIMEOUT); 3548 3549 spin_lock_irqsave(&hsotg->lock, flags); 3550 hprt0 = dwc2_read_hprt0(hsotg); 3551 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3552 dwc2_writel(hsotg, hprt0, HPRT0); 3553 hsotg->bus_suspended = false; 3554 spin_unlock_irqrestore(&hsotg->lock, flags); 3555 } 3556 3557 /* Handles hub class-specific requests */ 3558 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3559 u16 wvalue, u16 windex, char *buf, u16 wlength) 3560 { 3561 struct usb_hub_descriptor *hub_desc; 3562 int retval = 0; 3563 u32 hprt0; 3564 u32 port_status; 3565 u32 speed; 3566 u32 pcgctl; 3567 3568 switch (typereq) { 3569 case ClearHubFeature: 3570 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3571 3572 switch (wvalue) { 3573 case C_HUB_LOCAL_POWER: 3574 case C_HUB_OVER_CURRENT: 3575 /* Nothing required here */ 3576 break; 3577 3578 default: 3579 retval = -EINVAL; 3580 dev_err(hsotg->dev, 3581 "ClearHubFeature request %1xh unknown\n", 3582 wvalue); 3583 } 3584 break; 3585 3586 case ClearPortFeature: 3587 if (wvalue != USB_PORT_FEAT_L1) 3588 if (!windex || windex > 1) 3589 goto error; 3590 switch (wvalue) { 3591 case USB_PORT_FEAT_ENABLE: 3592 dev_dbg(hsotg->dev, 3593 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3594 hprt0 = dwc2_read_hprt0(hsotg); 3595 hprt0 |= HPRT0_ENA; 3596 dwc2_writel(hsotg, hprt0, HPRT0); 3597 break; 3598 3599 case USB_PORT_FEAT_SUSPEND: 3600 dev_dbg(hsotg->dev, 3601 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3602 3603 if (hsotg->bus_suspended) { 3604 if (hsotg->hibernated) 3605 dwc2_exit_hibernation(hsotg, 0, 0, 1); 3606 else 3607 dwc2_port_resume(hsotg); 3608 } 3609 break; 3610 3611 case USB_PORT_FEAT_POWER: 3612 dev_dbg(hsotg->dev, 3613 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3614 hprt0 = dwc2_read_hprt0(hsotg); 3615 hprt0 &= ~HPRT0_PWR; 3616 dwc2_writel(hsotg, hprt0, HPRT0); 3617 break; 3618 3619 case USB_PORT_FEAT_INDICATOR: 3620 dev_dbg(hsotg->dev, 3621 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3622 /* Port indicator not supported */ 3623 break; 3624 3625 case USB_PORT_FEAT_C_CONNECTION: 3626 /* 3627 * Clears driver's internal Connect Status Change flag 3628 */ 3629 dev_dbg(hsotg->dev, 3630 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3631 hsotg->flags.b.port_connect_status_change = 0; 3632 break; 3633 3634 case USB_PORT_FEAT_C_RESET: 3635 /* Clears driver's internal Port Reset Change flag */ 3636 dev_dbg(hsotg->dev, 3637 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3638 hsotg->flags.b.port_reset_change = 0; 3639 break; 3640 3641 case USB_PORT_FEAT_C_ENABLE: 3642 /* 3643 * Clears the driver's internal Port Enable/Disable 3644 * Change flag 3645 */ 3646 dev_dbg(hsotg->dev, 3647 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3648 hsotg->flags.b.port_enable_change = 0; 3649 break; 3650 3651 case USB_PORT_FEAT_C_SUSPEND: 3652 /* 3653 * Clears the driver's internal Port Suspend Change 3654 * flag, which is set when resume signaling on the host 3655 * port is complete 3656 */ 3657 dev_dbg(hsotg->dev, 3658 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3659 hsotg->flags.b.port_suspend_change = 0; 3660 break; 3661 3662 case USB_PORT_FEAT_C_PORT_L1: 3663 dev_dbg(hsotg->dev, 3664 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3665 hsotg->flags.b.port_l1_change = 0; 3666 break; 3667 3668 case USB_PORT_FEAT_C_OVER_CURRENT: 3669 dev_dbg(hsotg->dev, 3670 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3671 hsotg->flags.b.port_over_current_change = 0; 3672 break; 3673 3674 default: 3675 retval = -EINVAL; 3676 dev_err(hsotg->dev, 3677 "ClearPortFeature request %1xh unknown or unsupported\n", 3678 wvalue); 3679 } 3680 break; 3681 3682 case GetHubDescriptor: 3683 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3684 hub_desc = (struct usb_hub_descriptor *)buf; 3685 hub_desc->bDescLength = 9; 3686 hub_desc->bDescriptorType = USB_DT_HUB; 3687 hub_desc->bNbrPorts = 1; 3688 hub_desc->wHubCharacteristics = 3689 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3690 HUB_CHAR_INDV_PORT_OCPM); 3691 hub_desc->bPwrOn2PwrGood = 1; 3692 hub_desc->bHubContrCurrent = 0; 3693 hub_desc->u.hs.DeviceRemovable[0] = 0; 3694 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3695 break; 3696 3697 case GetHubStatus: 3698 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3699 memset(buf, 0, 4); 3700 break; 3701 3702 case GetPortStatus: 3703 dev_vdbg(hsotg->dev, 3704 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3705 hsotg->flags.d32); 3706 if (!windex || windex > 1) 3707 goto error; 3708 3709 port_status = 0; 3710 if (hsotg->flags.b.port_connect_status_change) 3711 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3712 if (hsotg->flags.b.port_enable_change) 3713 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3714 if (hsotg->flags.b.port_suspend_change) 3715 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3716 if (hsotg->flags.b.port_l1_change) 3717 port_status |= USB_PORT_STAT_C_L1 << 16; 3718 if (hsotg->flags.b.port_reset_change) 3719 port_status |= USB_PORT_STAT_C_RESET << 16; 3720 if (hsotg->flags.b.port_over_current_change) { 3721 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3722 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3723 } 3724 3725 if (!hsotg->flags.b.port_connect_status) { 3726 /* 3727 * The port is disconnected, which means the core is 3728 * either in device mode or it soon will be. Just 3729 * return 0's for the remainder of the port status 3730 * since the port register can't be read if the core 3731 * is in device mode. 3732 */ 3733 *(__le32 *)buf = cpu_to_le32(port_status); 3734 break; 3735 } 3736 3737 hprt0 = dwc2_readl(hsotg, HPRT0); 3738 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3739 3740 if (hprt0 & HPRT0_CONNSTS) 3741 port_status |= USB_PORT_STAT_CONNECTION; 3742 if (hprt0 & HPRT0_ENA) 3743 port_status |= USB_PORT_STAT_ENABLE; 3744 if (hprt0 & HPRT0_SUSP) 3745 port_status |= USB_PORT_STAT_SUSPEND; 3746 if (hprt0 & HPRT0_OVRCURRACT) 3747 port_status |= USB_PORT_STAT_OVERCURRENT; 3748 if (hprt0 & HPRT0_RST) 3749 port_status |= USB_PORT_STAT_RESET; 3750 if (hprt0 & HPRT0_PWR) 3751 port_status |= USB_PORT_STAT_POWER; 3752 3753 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3754 if (speed == HPRT0_SPD_HIGH_SPEED) 3755 port_status |= USB_PORT_STAT_HIGH_SPEED; 3756 else if (speed == HPRT0_SPD_LOW_SPEED) 3757 port_status |= USB_PORT_STAT_LOW_SPEED; 3758 3759 if (hprt0 & HPRT0_TSTCTL_MASK) 3760 port_status |= USB_PORT_STAT_TEST; 3761 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3762 3763 if (hsotg->params.dma_desc_fs_enable) { 3764 /* 3765 * Enable descriptor DMA only if a full speed 3766 * device is connected. 3767 */ 3768 if (hsotg->new_connection && 3769 ((port_status & 3770 (USB_PORT_STAT_CONNECTION | 3771 USB_PORT_STAT_HIGH_SPEED | 3772 USB_PORT_STAT_LOW_SPEED)) == 3773 USB_PORT_STAT_CONNECTION)) { 3774 u32 hcfg; 3775 3776 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3777 hsotg->params.dma_desc_enable = true; 3778 hcfg = dwc2_readl(hsotg, HCFG); 3779 hcfg |= HCFG_DESCDMA; 3780 dwc2_writel(hsotg, hcfg, HCFG); 3781 hsotg->new_connection = false; 3782 } 3783 } 3784 3785 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3786 *(__le32 *)buf = cpu_to_le32(port_status); 3787 break; 3788 3789 case SetHubFeature: 3790 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3791 /* No HUB features supported */ 3792 break; 3793 3794 case SetPortFeature: 3795 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3796 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3797 goto error; 3798 3799 if (!hsotg->flags.b.port_connect_status) { 3800 /* 3801 * The port is disconnected, which means the core is 3802 * either in device mode or it soon will be. Just 3803 * return without doing anything since the port 3804 * register can't be written if the core is in device 3805 * mode. 3806 */ 3807 break; 3808 } 3809 3810 switch (wvalue) { 3811 case USB_PORT_FEAT_SUSPEND: 3812 dev_dbg(hsotg->dev, 3813 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3814 if (windex != hsotg->otg_port) 3815 goto error; 3816 if (hsotg->params.power_down == 2) 3817 dwc2_enter_hibernation(hsotg, 1); 3818 else 3819 dwc2_port_suspend(hsotg, windex); 3820 break; 3821 3822 case USB_PORT_FEAT_POWER: 3823 dev_dbg(hsotg->dev, 3824 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3825 hprt0 = dwc2_read_hprt0(hsotg); 3826 hprt0 |= HPRT0_PWR; 3827 dwc2_writel(hsotg, hprt0, HPRT0); 3828 break; 3829 3830 case USB_PORT_FEAT_RESET: 3831 if (hsotg->params.power_down == 2 && 3832 hsotg->hibernated) 3833 dwc2_exit_hibernation(hsotg, 0, 1, 1); 3834 hprt0 = dwc2_read_hprt0(hsotg); 3835 dev_dbg(hsotg->dev, 3836 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3837 pcgctl = dwc2_readl(hsotg, PCGCTL); 3838 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3839 dwc2_writel(hsotg, pcgctl, PCGCTL); 3840 /* ??? Original driver does this */ 3841 dwc2_writel(hsotg, 0, PCGCTL); 3842 3843 hprt0 = dwc2_read_hprt0(hsotg); 3844 /* Clear suspend bit if resetting from suspend state */ 3845 hprt0 &= ~HPRT0_SUSP; 3846 3847 /* 3848 * When B-Host the Port reset bit is set in the Start 3849 * HCD Callback function, so that the reset is started 3850 * within 1ms of the HNP success interrupt 3851 */ 3852 if (!dwc2_hcd_is_b_host(hsotg)) { 3853 hprt0 |= HPRT0_PWR | HPRT0_RST; 3854 dev_dbg(hsotg->dev, 3855 "In host mode, hprt0=%08x\n", hprt0); 3856 dwc2_writel(hsotg, hprt0, HPRT0); 3857 } 3858 3859 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3860 msleep(50); 3861 hprt0 &= ~HPRT0_RST; 3862 dwc2_writel(hsotg, hprt0, HPRT0); 3863 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3864 break; 3865 3866 case USB_PORT_FEAT_INDICATOR: 3867 dev_dbg(hsotg->dev, 3868 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3869 /* Not supported */ 3870 break; 3871 3872 case USB_PORT_FEAT_TEST: 3873 hprt0 = dwc2_read_hprt0(hsotg); 3874 dev_dbg(hsotg->dev, 3875 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3876 hprt0 &= ~HPRT0_TSTCTL_MASK; 3877 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3878 dwc2_writel(hsotg, hprt0, HPRT0); 3879 break; 3880 3881 default: 3882 retval = -EINVAL; 3883 dev_err(hsotg->dev, 3884 "SetPortFeature %1xh unknown or unsupported\n", 3885 wvalue); 3886 break; 3887 } 3888 break; 3889 3890 default: 3891 error: 3892 retval = -EINVAL; 3893 dev_dbg(hsotg->dev, 3894 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3895 typereq, windex, wvalue); 3896 break; 3897 } 3898 3899 return retval; 3900 } 3901 3902 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3903 { 3904 int retval; 3905 3906 if (port != 1) 3907 return -EINVAL; 3908 3909 retval = (hsotg->flags.b.port_connect_status_change || 3910 hsotg->flags.b.port_reset_change || 3911 hsotg->flags.b.port_enable_change || 3912 hsotg->flags.b.port_suspend_change || 3913 hsotg->flags.b.port_over_current_change); 3914 3915 if (retval) { 3916 dev_dbg(hsotg->dev, 3917 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3918 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3919 hsotg->flags.b.port_connect_status_change); 3920 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3921 hsotg->flags.b.port_reset_change); 3922 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3923 hsotg->flags.b.port_enable_change); 3924 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3925 hsotg->flags.b.port_suspend_change); 3926 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3927 hsotg->flags.b.port_over_current_change); 3928 } 3929 3930 return retval; 3931 } 3932 3933 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3934 { 3935 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3936 3937 #ifdef DWC2_DEBUG_SOF 3938 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3939 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3940 #endif 3941 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3942 } 3943 3944 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3945 { 3946 u32 hprt = dwc2_readl(hsotg, HPRT0); 3947 u32 hfir = dwc2_readl(hsotg, HFIR); 3948 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3949 unsigned int us_per_frame; 3950 unsigned int frame_number; 3951 unsigned int remaining; 3952 unsigned int interval; 3953 unsigned int phy_clks; 3954 3955 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3956 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3957 3958 /* Extract fields */ 3959 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3960 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3961 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3962 3963 /* 3964 * Number of phy clocks since the last tick of the frame number after 3965 * "us" has passed. 3966 */ 3967 phy_clks = (interval - remaining) + 3968 DIV_ROUND_UP(interval * us, us_per_frame); 3969 3970 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3971 } 3972 3973 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3974 { 3975 return hsotg->op_state == OTG_STATE_B_HOST; 3976 } 3977 3978 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3979 int iso_desc_count, 3980 gfp_t mem_flags) 3981 { 3982 struct dwc2_hcd_urb *urb; 3983 u32 size = sizeof(*urb) + iso_desc_count * 3984 sizeof(struct dwc2_hcd_iso_packet_desc); 3985 3986 urb = kzalloc(size, mem_flags); 3987 if (urb) 3988 urb->packet_count = iso_desc_count; 3989 return urb; 3990 } 3991 3992 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3993 struct dwc2_hcd_urb *urb, u8 dev_addr, 3994 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3995 { 3996 if (dbg_perio() || 3997 ep_type == USB_ENDPOINT_XFER_BULK || 3998 ep_type == USB_ENDPOINT_XFER_CONTROL) 3999 dev_vdbg(hsotg->dev, 4000 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 4001 dev_addr, ep_num, ep_dir, ep_type, mps); 4002 urb->pipe_info.dev_addr = dev_addr; 4003 urb->pipe_info.ep_num = ep_num; 4004 urb->pipe_info.pipe_type = ep_type; 4005 urb->pipe_info.pipe_dir = ep_dir; 4006 urb->pipe_info.mps = mps; 4007 } 4008 4009 /* 4010 * NOTE: This function will be removed once the peripheral controller code 4011 * is integrated and the driver is stable 4012 */ 4013 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 4014 { 4015 #ifdef DEBUG 4016 struct dwc2_host_chan *chan; 4017 struct dwc2_hcd_urb *urb; 4018 struct dwc2_qtd *qtd; 4019 int num_channels; 4020 u32 np_tx_status; 4021 u32 p_tx_status; 4022 int i; 4023 4024 num_channels = hsotg->params.host_channels; 4025 dev_dbg(hsotg->dev, "\n"); 4026 dev_dbg(hsotg->dev, 4027 "************************************************************\n"); 4028 dev_dbg(hsotg->dev, "HCD State:\n"); 4029 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 4030 4031 for (i = 0; i < num_channels; i++) { 4032 chan = hsotg->hc_ptr_array[i]; 4033 dev_dbg(hsotg->dev, " Channel %d:\n", i); 4034 dev_dbg(hsotg->dev, 4035 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 4036 chan->dev_addr, chan->ep_num, chan->ep_is_in); 4037 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 4038 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 4039 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 4040 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 4041 chan->data_pid_start); 4042 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 4043 dev_dbg(hsotg->dev, " xfer_started: %d\n", 4044 chan->xfer_started); 4045 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 4046 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 4047 (unsigned long)chan->xfer_dma); 4048 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 4049 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 4050 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 4051 chan->halt_on_queue); 4052 dev_dbg(hsotg->dev, " halt_pending: %d\n", 4053 chan->halt_pending); 4054 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 4055 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 4056 dev_dbg(hsotg->dev, " complete_split: %d\n", 4057 chan->complete_split); 4058 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 4059 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 4060 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 4061 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 4062 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 4063 4064 if (chan->xfer_started) { 4065 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 4066 4067 hfnum = dwc2_readl(hsotg, HFNUM); 4068 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 4069 hctsiz = dwc2_readl(hsotg, HCTSIZ(i)); 4070 hcint = dwc2_readl(hsotg, HCINT(i)); 4071 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i)); 4072 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 4073 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 4074 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 4075 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 4076 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 4077 } 4078 4079 if (!(chan->xfer_started && chan->qh)) 4080 continue; 4081 4082 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 4083 if (!qtd->in_process) 4084 break; 4085 urb = qtd->urb; 4086 dev_dbg(hsotg->dev, " URB Info:\n"); 4087 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 4088 qtd, urb); 4089 if (urb) { 4090 dev_dbg(hsotg->dev, 4091 " Dev: %d, EP: %d %s\n", 4092 dwc2_hcd_get_dev_addr(&urb->pipe_info), 4093 dwc2_hcd_get_ep_num(&urb->pipe_info), 4094 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 4095 "IN" : "OUT"); 4096 dev_dbg(hsotg->dev, 4097 " Max packet size: %d\n", 4098 dwc2_hcd_get_mps(&urb->pipe_info)); 4099 dev_dbg(hsotg->dev, 4100 " transfer_buffer: %p\n", 4101 urb->buf); 4102 dev_dbg(hsotg->dev, 4103 " transfer_dma: %08lx\n", 4104 (unsigned long)urb->dma); 4105 dev_dbg(hsotg->dev, 4106 " transfer_buffer_length: %d\n", 4107 urb->length); 4108 dev_dbg(hsotg->dev, " actual_length: %d\n", 4109 urb->actual_length); 4110 } 4111 } 4112 } 4113 4114 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 4115 hsotg->non_periodic_channels); 4116 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 4117 hsotg->periodic_channels); 4118 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 4119 np_tx_status = dwc2_readl(hsotg, GNPTXSTS); 4120 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 4121 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4122 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 4123 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4124 p_tx_status = dwc2_readl(hsotg, HPTXSTS); 4125 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 4126 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4127 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 4128 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4129 dwc2_dump_global_registers(hsotg); 4130 dwc2_dump_host_registers(hsotg); 4131 dev_dbg(hsotg->dev, 4132 "************************************************************\n"); 4133 dev_dbg(hsotg->dev, "\n"); 4134 #endif 4135 } 4136 4137 struct wrapper_priv_data { 4138 struct dwc2_hsotg *hsotg; 4139 }; 4140 4141 /* Gets the dwc2_hsotg from a usb_hcd */ 4142 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4143 { 4144 struct wrapper_priv_data *p; 4145 4146 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4147 return p->hsotg; 4148 } 4149 4150 /** 4151 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4152 * 4153 * This will get the dwc2_tt structure (and ttport) associated with the given 4154 * context (which is really just a struct urb pointer). 4155 * 4156 * The first time this is called for a given TT we allocate memory for our 4157 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4158 * then the refcount for the structure will go to 0 and we'll free it. 4159 * 4160 * @hsotg: The HCD state structure for the DWC OTG controller. 4161 * @context: The priv pointer from a struct dwc2_hcd_urb. 4162 * @mem_flags: Flags for allocating memory. 4163 * @ttport: We'll return this device's port number here. That's used to 4164 * reference into the bitmap if we're on a multi_tt hub. 4165 * 4166 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4167 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4168 */ 4169 4170 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4171 gfp_t mem_flags, int *ttport) 4172 { 4173 struct urb *urb = context; 4174 struct dwc2_tt *dwc_tt = NULL; 4175 4176 if (urb->dev->tt) { 4177 *ttport = urb->dev->ttport; 4178 4179 dwc_tt = urb->dev->tt->hcpriv; 4180 if (!dwc_tt) { 4181 size_t bitmap_size; 4182 4183 /* 4184 * For single_tt we need one schedule. For multi_tt 4185 * we need one per port. 4186 */ 4187 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4188 sizeof(dwc_tt->periodic_bitmaps[0]); 4189 if (urb->dev->tt->multi) 4190 bitmap_size *= urb->dev->tt->hub->maxchild; 4191 4192 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4193 mem_flags); 4194 if (!dwc_tt) 4195 return NULL; 4196 4197 dwc_tt->usb_tt = urb->dev->tt; 4198 dwc_tt->usb_tt->hcpriv = dwc_tt; 4199 } 4200 4201 dwc_tt->refcount++; 4202 } 4203 4204 return dwc_tt; 4205 } 4206 4207 /** 4208 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4209 * 4210 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4211 * of the structure are done. 4212 * 4213 * It's OK to call this with NULL. 4214 * 4215 * @hsotg: The HCD state structure for the DWC OTG controller. 4216 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4217 */ 4218 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4219 { 4220 /* Model kfree and make put of NULL a no-op */ 4221 if (!dwc_tt) 4222 return; 4223 4224 WARN_ON(dwc_tt->refcount < 1); 4225 4226 dwc_tt->refcount--; 4227 if (!dwc_tt->refcount) { 4228 dwc_tt->usb_tt->hcpriv = NULL; 4229 kfree(dwc_tt); 4230 } 4231 } 4232 4233 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4234 { 4235 struct urb *urb = context; 4236 4237 return urb->dev->speed; 4238 } 4239 4240 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4241 struct urb *urb) 4242 { 4243 struct usb_bus *bus = hcd_to_bus(hcd); 4244 4245 if (urb->interval) 4246 bus->bandwidth_allocated += bw / urb->interval; 4247 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4248 bus->bandwidth_isoc_reqs++; 4249 else 4250 bus->bandwidth_int_reqs++; 4251 } 4252 4253 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4254 struct urb *urb) 4255 { 4256 struct usb_bus *bus = hcd_to_bus(hcd); 4257 4258 if (urb->interval) 4259 bus->bandwidth_allocated -= bw / urb->interval; 4260 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4261 bus->bandwidth_isoc_reqs--; 4262 else 4263 bus->bandwidth_int_reqs--; 4264 } 4265 4266 /* 4267 * Sets the final status of an URB and returns it to the upper layer. Any 4268 * required cleanup of the URB is performed. 4269 * 4270 * Must be called with interrupt disabled and spinlock held 4271 */ 4272 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4273 int status) 4274 { 4275 struct urb *urb; 4276 int i; 4277 4278 if (!qtd) { 4279 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4280 return; 4281 } 4282 4283 if (!qtd->urb) { 4284 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4285 return; 4286 } 4287 4288 urb = qtd->urb->priv; 4289 if (!urb) { 4290 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4291 return; 4292 } 4293 4294 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4295 4296 if (dbg_urb(urb)) 4297 dev_vdbg(hsotg->dev, 4298 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4299 __func__, urb, usb_pipedevice(urb->pipe), 4300 usb_pipeendpoint(urb->pipe), 4301 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4302 urb->actual_length); 4303 4304 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4305 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4306 for (i = 0; i < urb->number_of_packets; ++i) { 4307 urb->iso_frame_desc[i].actual_length = 4308 dwc2_hcd_urb_get_iso_desc_actual_length( 4309 qtd->urb, i); 4310 urb->iso_frame_desc[i].status = 4311 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4312 } 4313 } 4314 4315 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4316 for (i = 0; i < urb->number_of_packets; i++) 4317 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4318 i, urb->iso_frame_desc[i].status); 4319 } 4320 4321 urb->status = status; 4322 if (!status) { 4323 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4324 urb->actual_length < urb->transfer_buffer_length) 4325 urb->status = -EREMOTEIO; 4326 } 4327 4328 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4329 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4330 struct usb_host_endpoint *ep = urb->ep; 4331 4332 if (ep) 4333 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4334 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4335 urb); 4336 } 4337 4338 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4339 urb->hcpriv = NULL; 4340 kfree(qtd->urb); 4341 qtd->urb = NULL; 4342 4343 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4344 } 4345 4346 /* 4347 * Work queue function for starting the HCD when A-Cable is connected 4348 */ 4349 static void dwc2_hcd_start_func(struct work_struct *work) 4350 { 4351 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4352 start_work.work); 4353 4354 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4355 dwc2_host_start(hsotg); 4356 } 4357 4358 /* 4359 * Reset work queue function 4360 */ 4361 static void dwc2_hcd_reset_func(struct work_struct *work) 4362 { 4363 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4364 reset_work.work); 4365 unsigned long flags; 4366 u32 hprt0; 4367 4368 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4369 4370 spin_lock_irqsave(&hsotg->lock, flags); 4371 4372 hprt0 = dwc2_read_hprt0(hsotg); 4373 hprt0 &= ~HPRT0_RST; 4374 dwc2_writel(hsotg, hprt0, HPRT0); 4375 hsotg->flags.b.port_reset_change = 1; 4376 4377 spin_unlock_irqrestore(&hsotg->lock, flags); 4378 } 4379 4380 /* 4381 * ========================================================================= 4382 * Linux HC Driver Functions 4383 * ========================================================================= 4384 */ 4385 4386 /* 4387 * Initializes the DWC_otg controller and its root hub and prepares it for host 4388 * mode operation. Activates the root port. Returns 0 on success and a negative 4389 * error code on failure. 4390 */ 4391 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4392 { 4393 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4394 struct usb_bus *bus = hcd_to_bus(hcd); 4395 unsigned long flags; 4396 4397 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4398 4399 spin_lock_irqsave(&hsotg->lock, flags); 4400 hsotg->lx_state = DWC2_L0; 4401 hcd->state = HC_STATE_RUNNING; 4402 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4403 4404 if (dwc2_is_device_mode(hsotg)) { 4405 spin_unlock_irqrestore(&hsotg->lock, flags); 4406 return 0; /* why 0 ?? */ 4407 } 4408 4409 dwc2_hcd_reinit(hsotg); 4410 4411 /* Initialize and connect root hub if one is not already attached */ 4412 if (bus->root_hub) { 4413 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4414 /* Inform the HUB driver to resume */ 4415 usb_hcd_resume_root_hub(hcd); 4416 } 4417 4418 spin_unlock_irqrestore(&hsotg->lock, flags); 4419 4420 return dwc2_vbus_supply_init(hsotg); 4421 } 4422 4423 /* 4424 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4425 * stopped. 4426 */ 4427 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4428 { 4429 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4430 unsigned long flags; 4431 4432 /* Turn off all host-specific interrupts */ 4433 dwc2_disable_host_interrupts(hsotg); 4434 4435 /* Wait for interrupt processing to finish */ 4436 synchronize_irq(hcd->irq); 4437 4438 spin_lock_irqsave(&hsotg->lock, flags); 4439 /* Ensure hcd is disconnected */ 4440 dwc2_hcd_disconnect(hsotg, true); 4441 dwc2_hcd_stop(hsotg); 4442 hsotg->lx_state = DWC2_L3; 4443 hcd->state = HC_STATE_HALT; 4444 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4445 spin_unlock_irqrestore(&hsotg->lock, flags); 4446 4447 dwc2_vbus_supply_exit(hsotg); 4448 4449 usleep_range(1000, 3000); 4450 } 4451 4452 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4453 { 4454 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4455 unsigned long flags; 4456 int ret = 0; 4457 u32 hprt0; 4458 4459 spin_lock_irqsave(&hsotg->lock, flags); 4460 4461 if (dwc2_is_device_mode(hsotg)) 4462 goto unlock; 4463 4464 if (hsotg->lx_state != DWC2_L0) 4465 goto unlock; 4466 4467 if (!HCD_HW_ACCESSIBLE(hcd)) 4468 goto unlock; 4469 4470 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4471 goto unlock; 4472 4473 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) 4474 goto skip_power_saving; 4475 4476 /* 4477 * Drive USB suspend and disable port Power 4478 * if usb bus is not suspended. 4479 */ 4480 if (!hsotg->bus_suspended) { 4481 hprt0 = dwc2_read_hprt0(hsotg); 4482 hprt0 |= HPRT0_SUSP; 4483 hprt0 &= ~HPRT0_PWR; 4484 dwc2_writel(hsotg, hprt0, HPRT0); 4485 dwc2_vbus_supply_exit(hsotg); 4486 } 4487 4488 /* Enter partial_power_down */ 4489 ret = dwc2_enter_partial_power_down(hsotg); 4490 if (ret) { 4491 if (ret != -ENOTSUPP) 4492 dev_err(hsotg->dev, 4493 "enter partial_power_down failed\n"); 4494 goto skip_power_saving; 4495 } 4496 4497 /* Ask phy to be suspended */ 4498 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4499 spin_unlock_irqrestore(&hsotg->lock, flags); 4500 usb_phy_set_suspend(hsotg->uphy, true); 4501 spin_lock_irqsave(&hsotg->lock, flags); 4502 } 4503 4504 /* After entering partial_power_down, hardware is no more accessible */ 4505 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4506 4507 skip_power_saving: 4508 hsotg->lx_state = DWC2_L2; 4509 unlock: 4510 spin_unlock_irqrestore(&hsotg->lock, flags); 4511 4512 return ret; 4513 } 4514 4515 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4516 { 4517 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4518 unsigned long flags; 4519 int ret = 0; 4520 4521 spin_lock_irqsave(&hsotg->lock, flags); 4522 4523 if (dwc2_is_device_mode(hsotg)) 4524 goto unlock; 4525 4526 if (hsotg->lx_state != DWC2_L2) 4527 goto unlock; 4528 4529 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) { 4530 hsotg->lx_state = DWC2_L0; 4531 goto unlock; 4532 } 4533 4534 /* 4535 * Set HW accessible bit before powering on the controller 4536 * since an interrupt may rise. 4537 */ 4538 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4539 4540 /* 4541 * Enable power if not already done. 4542 * This must not be spinlocked since duration 4543 * of this call is unknown. 4544 */ 4545 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4546 spin_unlock_irqrestore(&hsotg->lock, flags); 4547 usb_phy_set_suspend(hsotg->uphy, false); 4548 spin_lock_irqsave(&hsotg->lock, flags); 4549 } 4550 4551 /* Exit partial_power_down */ 4552 ret = dwc2_exit_partial_power_down(hsotg, true); 4553 if (ret && (ret != -ENOTSUPP)) 4554 dev_err(hsotg->dev, "exit partial_power_down failed\n"); 4555 4556 hsotg->lx_state = DWC2_L0; 4557 4558 spin_unlock_irqrestore(&hsotg->lock, flags); 4559 4560 if (hsotg->bus_suspended) { 4561 spin_lock_irqsave(&hsotg->lock, flags); 4562 hsotg->flags.b.port_suspend_change = 1; 4563 spin_unlock_irqrestore(&hsotg->lock, flags); 4564 dwc2_port_resume(hsotg); 4565 } else { 4566 dwc2_vbus_supply_init(hsotg); 4567 4568 /* Wait for controller to correctly update D+/D- level */ 4569 usleep_range(3000, 5000); 4570 4571 /* 4572 * Clear Port Enable and Port Status changes. 4573 * Enable Port Power. 4574 */ 4575 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET | 4576 HPRT0_ENACHG, HPRT0); 4577 /* Wait for controller to detect Port Connect */ 4578 usleep_range(5000, 7000); 4579 } 4580 4581 return ret; 4582 unlock: 4583 spin_unlock_irqrestore(&hsotg->lock, flags); 4584 4585 return ret; 4586 } 4587 4588 /* Returns the current frame number */ 4589 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4590 { 4591 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4592 4593 return dwc2_hcd_get_frame_number(hsotg); 4594 } 4595 4596 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4597 char *fn_name) 4598 { 4599 #ifdef VERBOSE_DEBUG 4600 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4601 char *pipetype = NULL; 4602 char *speed = NULL; 4603 4604 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4605 dev_vdbg(hsotg->dev, " Device address: %d\n", 4606 usb_pipedevice(urb->pipe)); 4607 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4608 usb_pipeendpoint(urb->pipe), 4609 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4610 4611 switch (usb_pipetype(urb->pipe)) { 4612 case PIPE_CONTROL: 4613 pipetype = "CONTROL"; 4614 break; 4615 case PIPE_BULK: 4616 pipetype = "BULK"; 4617 break; 4618 case PIPE_INTERRUPT: 4619 pipetype = "INTERRUPT"; 4620 break; 4621 case PIPE_ISOCHRONOUS: 4622 pipetype = "ISOCHRONOUS"; 4623 break; 4624 } 4625 4626 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4627 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4628 "IN" : "OUT"); 4629 4630 switch (urb->dev->speed) { 4631 case USB_SPEED_HIGH: 4632 speed = "HIGH"; 4633 break; 4634 case USB_SPEED_FULL: 4635 speed = "FULL"; 4636 break; 4637 case USB_SPEED_LOW: 4638 speed = "LOW"; 4639 break; 4640 default: 4641 speed = "UNKNOWN"; 4642 break; 4643 } 4644 4645 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4646 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4647 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4648 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4649 urb->transfer_buffer_length); 4650 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4651 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4652 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4653 urb->setup_packet, (unsigned long)urb->setup_dma); 4654 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4655 4656 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4657 int i; 4658 4659 for (i = 0; i < urb->number_of_packets; i++) { 4660 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4661 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4662 urb->iso_frame_desc[i].offset, 4663 urb->iso_frame_desc[i].length); 4664 } 4665 } 4666 #endif 4667 } 4668 4669 /* 4670 * Starts processing a USB transfer request specified by a USB Request Block 4671 * (URB). mem_flags indicates the type of memory allocation to use while 4672 * processing this URB. 4673 */ 4674 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4675 gfp_t mem_flags) 4676 { 4677 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4678 struct usb_host_endpoint *ep = urb->ep; 4679 struct dwc2_hcd_urb *dwc2_urb; 4680 int i; 4681 int retval; 4682 int alloc_bandwidth = 0; 4683 u8 ep_type = 0; 4684 u32 tflags = 0; 4685 void *buf; 4686 unsigned long flags; 4687 struct dwc2_qh *qh; 4688 bool qh_allocated = false; 4689 struct dwc2_qtd *qtd; 4690 4691 if (dbg_urb(urb)) { 4692 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4693 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4694 } 4695 4696 if (!ep) 4697 return -EINVAL; 4698 4699 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4700 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4701 spin_lock_irqsave(&hsotg->lock, flags); 4702 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4703 alloc_bandwidth = 1; 4704 spin_unlock_irqrestore(&hsotg->lock, flags); 4705 } 4706 4707 switch (usb_pipetype(urb->pipe)) { 4708 case PIPE_CONTROL: 4709 ep_type = USB_ENDPOINT_XFER_CONTROL; 4710 break; 4711 case PIPE_ISOCHRONOUS: 4712 ep_type = USB_ENDPOINT_XFER_ISOC; 4713 break; 4714 case PIPE_BULK: 4715 ep_type = USB_ENDPOINT_XFER_BULK; 4716 break; 4717 case PIPE_INTERRUPT: 4718 ep_type = USB_ENDPOINT_XFER_INT; 4719 break; 4720 } 4721 4722 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4723 mem_flags); 4724 if (!dwc2_urb) 4725 return -ENOMEM; 4726 4727 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4728 usb_pipeendpoint(urb->pipe), ep_type, 4729 usb_pipein(urb->pipe), 4730 usb_maxpacket(urb->dev, urb->pipe, 4731 !(usb_pipein(urb->pipe)))); 4732 4733 buf = urb->transfer_buffer; 4734 4735 if (hcd->self.uses_dma) { 4736 if (!buf && (urb->transfer_dma & 3)) { 4737 dev_err(hsotg->dev, 4738 "%s: unaligned transfer with no transfer_buffer", 4739 __func__); 4740 retval = -EINVAL; 4741 goto fail0; 4742 } 4743 } 4744 4745 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4746 tflags |= URB_GIVEBACK_ASAP; 4747 if (urb->transfer_flags & URB_ZERO_PACKET) 4748 tflags |= URB_SEND_ZERO_PACKET; 4749 4750 dwc2_urb->priv = urb; 4751 dwc2_urb->buf = buf; 4752 dwc2_urb->dma = urb->transfer_dma; 4753 dwc2_urb->length = urb->transfer_buffer_length; 4754 dwc2_urb->setup_packet = urb->setup_packet; 4755 dwc2_urb->setup_dma = urb->setup_dma; 4756 dwc2_urb->flags = tflags; 4757 dwc2_urb->interval = urb->interval; 4758 dwc2_urb->status = -EINPROGRESS; 4759 4760 for (i = 0; i < urb->number_of_packets; ++i) 4761 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4762 urb->iso_frame_desc[i].offset, 4763 urb->iso_frame_desc[i].length); 4764 4765 urb->hcpriv = dwc2_urb; 4766 qh = (struct dwc2_qh *)ep->hcpriv; 4767 /* Create QH for the endpoint if it doesn't exist */ 4768 if (!qh) { 4769 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4770 if (!qh) { 4771 retval = -ENOMEM; 4772 goto fail0; 4773 } 4774 ep->hcpriv = qh; 4775 qh_allocated = true; 4776 } 4777 4778 qtd = kzalloc(sizeof(*qtd), mem_flags); 4779 if (!qtd) { 4780 retval = -ENOMEM; 4781 goto fail1; 4782 } 4783 4784 spin_lock_irqsave(&hsotg->lock, flags); 4785 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4786 if (retval) 4787 goto fail2; 4788 4789 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4790 if (retval) 4791 goto fail3; 4792 4793 if (alloc_bandwidth) { 4794 dwc2_allocate_bus_bandwidth(hcd, 4795 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4796 urb); 4797 } 4798 4799 spin_unlock_irqrestore(&hsotg->lock, flags); 4800 4801 return 0; 4802 4803 fail3: 4804 dwc2_urb->priv = NULL; 4805 usb_hcd_unlink_urb_from_ep(hcd, urb); 4806 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4807 qh->channel->qh = NULL; 4808 fail2: 4809 spin_unlock_irqrestore(&hsotg->lock, flags); 4810 urb->hcpriv = NULL; 4811 kfree(qtd); 4812 qtd = NULL; 4813 fail1: 4814 if (qh_allocated) { 4815 struct dwc2_qtd *qtd2, *qtd2_tmp; 4816 4817 ep->hcpriv = NULL; 4818 dwc2_hcd_qh_unlink(hsotg, qh); 4819 /* Free each QTD in the QH's QTD list */ 4820 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4821 qtd_list_entry) 4822 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4823 dwc2_hcd_qh_free(hsotg, qh); 4824 } 4825 fail0: 4826 kfree(dwc2_urb); 4827 4828 return retval; 4829 } 4830 4831 /* 4832 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4833 */ 4834 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4835 int status) 4836 { 4837 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4838 int rc; 4839 unsigned long flags; 4840 4841 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4842 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4843 4844 spin_lock_irqsave(&hsotg->lock, flags); 4845 4846 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4847 if (rc) 4848 goto out; 4849 4850 if (!urb->hcpriv) { 4851 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4852 goto out; 4853 } 4854 4855 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4856 4857 usb_hcd_unlink_urb_from_ep(hcd, urb); 4858 4859 kfree(urb->hcpriv); 4860 urb->hcpriv = NULL; 4861 4862 /* Higher layer software sets URB status */ 4863 spin_unlock(&hsotg->lock); 4864 usb_hcd_giveback_urb(hcd, urb, status); 4865 spin_lock(&hsotg->lock); 4866 4867 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4868 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4869 out: 4870 spin_unlock_irqrestore(&hsotg->lock, flags); 4871 4872 return rc; 4873 } 4874 4875 /* 4876 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4877 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4878 * must already be dequeued. 4879 */ 4880 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4881 struct usb_host_endpoint *ep) 4882 { 4883 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4884 4885 dev_dbg(hsotg->dev, 4886 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4887 ep->desc.bEndpointAddress, ep->hcpriv); 4888 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4889 } 4890 4891 /* 4892 * Resets endpoint specific parameter values, in current version used to reset 4893 * the data toggle (as a WA). This function can be called from usb_clear_halt 4894 * routine. 4895 */ 4896 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4897 struct usb_host_endpoint *ep) 4898 { 4899 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4900 unsigned long flags; 4901 4902 dev_dbg(hsotg->dev, 4903 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4904 ep->desc.bEndpointAddress); 4905 4906 spin_lock_irqsave(&hsotg->lock, flags); 4907 dwc2_hcd_endpoint_reset(hsotg, ep); 4908 spin_unlock_irqrestore(&hsotg->lock, flags); 4909 } 4910 4911 /* 4912 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4913 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4914 * interrupt. 4915 * 4916 * This function is called by the USB core when an interrupt occurs 4917 */ 4918 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4919 { 4920 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4921 4922 return dwc2_handle_hcd_intr(hsotg); 4923 } 4924 4925 /* 4926 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4927 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4928 * is the status change indicator for the single root port. Returns 1 if either 4929 * change indicator is 1, otherwise returns 0. 4930 */ 4931 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4932 { 4933 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4934 4935 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4936 return buf[0] != 0; 4937 } 4938 4939 /* Handles hub class-specific requests */ 4940 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4941 u16 windex, char *buf, u16 wlength) 4942 { 4943 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4944 wvalue, windex, buf, wlength); 4945 return retval; 4946 } 4947 4948 /* Handles hub TT buffer clear completions */ 4949 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4950 struct usb_host_endpoint *ep) 4951 { 4952 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4953 struct dwc2_qh *qh; 4954 unsigned long flags; 4955 4956 qh = ep->hcpriv; 4957 if (!qh) 4958 return; 4959 4960 spin_lock_irqsave(&hsotg->lock, flags); 4961 qh->tt_buffer_dirty = 0; 4962 4963 if (hsotg->flags.b.port_connect_status) 4964 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4965 4966 spin_unlock_irqrestore(&hsotg->lock, flags); 4967 } 4968 4969 /* 4970 * HPRT0_SPD_HIGH_SPEED: high speed 4971 * HPRT0_SPD_FULL_SPEED: full speed 4972 */ 4973 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4974 { 4975 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4976 4977 if (hsotg->params.speed == speed) 4978 return; 4979 4980 hsotg->params.speed = speed; 4981 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4982 } 4983 4984 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4985 { 4986 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4987 4988 if (!hsotg->params.change_speed_quirk) 4989 return; 4990 4991 /* 4992 * On removal, set speed to default high-speed. 4993 */ 4994 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4995 udev->parent->speed < USB_SPEED_HIGH) { 4996 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4997 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4998 } 4999 } 5000 5001 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 5002 { 5003 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 5004 5005 if (!hsotg->params.change_speed_quirk) 5006 return 0; 5007 5008 if (udev->speed == USB_SPEED_HIGH) { 5009 dev_info(hsotg->dev, "Set speed to high-speed\n"); 5010 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 5011 } else if ((udev->speed == USB_SPEED_FULL || 5012 udev->speed == USB_SPEED_LOW)) { 5013 /* 5014 * Change speed setting to full-speed if there's 5015 * a full-speed or low-speed device plugged in. 5016 */ 5017 dev_info(hsotg->dev, "Set speed to full-speed\n"); 5018 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 5019 } 5020 5021 return 0; 5022 } 5023 5024 static struct hc_driver dwc2_hc_driver = { 5025 .description = "dwc2_hsotg", 5026 .product_desc = "DWC OTG Controller", 5027 .hcd_priv_size = sizeof(struct wrapper_priv_data), 5028 5029 .irq = _dwc2_hcd_irq, 5030 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 5031 5032 .start = _dwc2_hcd_start, 5033 .stop = _dwc2_hcd_stop, 5034 .urb_enqueue = _dwc2_hcd_urb_enqueue, 5035 .urb_dequeue = _dwc2_hcd_urb_dequeue, 5036 .endpoint_disable = _dwc2_hcd_endpoint_disable, 5037 .endpoint_reset = _dwc2_hcd_endpoint_reset, 5038 .get_frame_number = _dwc2_hcd_get_frame_number, 5039 5040 .hub_status_data = _dwc2_hcd_hub_status_data, 5041 .hub_control = _dwc2_hcd_hub_control, 5042 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 5043 5044 .bus_suspend = _dwc2_hcd_suspend, 5045 .bus_resume = _dwc2_hcd_resume, 5046 5047 .map_urb_for_dma = dwc2_map_urb_for_dma, 5048 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 5049 }; 5050 5051 /* 5052 * Frees secondary storage associated with the dwc2_hsotg structure contained 5053 * in the struct usb_hcd field 5054 */ 5055 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 5056 { 5057 u32 ahbcfg; 5058 u32 dctl; 5059 int i; 5060 5061 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 5062 5063 /* Free memory for QH/QTD lists */ 5064 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 5065 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 5066 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 5067 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 5068 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 5069 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 5070 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 5071 5072 /* Free memory for the host channels */ 5073 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 5074 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 5075 5076 if (chan) { 5077 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 5078 i, chan); 5079 hsotg->hc_ptr_array[i] = NULL; 5080 kfree(chan); 5081 } 5082 } 5083 5084 if (hsotg->params.host_dma) { 5085 if (hsotg->status_buf) { 5086 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 5087 hsotg->status_buf, 5088 hsotg->status_buf_dma); 5089 hsotg->status_buf = NULL; 5090 } 5091 } else { 5092 kfree(hsotg->status_buf); 5093 hsotg->status_buf = NULL; 5094 } 5095 5096 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 5097 5098 /* Disable all interrupts */ 5099 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5100 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 5101 dwc2_writel(hsotg, 0, GINTMSK); 5102 5103 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5104 dctl = dwc2_readl(hsotg, DCTL); 5105 dctl |= DCTL_SFTDISCON; 5106 dwc2_writel(hsotg, dctl, DCTL); 5107 } 5108 5109 if (hsotg->wq_otg) { 5110 if (!cancel_work_sync(&hsotg->wf_otg)) 5111 flush_workqueue(hsotg->wq_otg); 5112 destroy_workqueue(hsotg->wq_otg); 5113 } 5114 5115 del_timer(&hsotg->wkp_timer); 5116 } 5117 5118 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5119 { 5120 /* Turn off all host-specific interrupts */ 5121 dwc2_disable_host_interrupts(hsotg); 5122 5123 dwc2_hcd_free(hsotg); 5124 } 5125 5126 /* 5127 * Initializes the HCD. This function allocates memory for and initializes the 5128 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5129 * USB bus with the core and calls the hc_driver->start() function. It returns 5130 * a negative error on failure. 5131 */ 5132 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5133 { 5134 struct platform_device *pdev = to_platform_device(hsotg->dev); 5135 struct resource *res; 5136 struct usb_hcd *hcd; 5137 struct dwc2_host_chan *channel; 5138 u32 hcfg; 5139 int i, num_channels; 5140 int retval; 5141 5142 if (usb_disabled()) 5143 return -ENODEV; 5144 5145 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5146 5147 retval = -ENOMEM; 5148 5149 hcfg = dwc2_readl(hsotg, HCFG); 5150 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5151 5152 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5153 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE, 5154 sizeof(*hsotg->frame_num_array), 5155 GFP_KERNEL); 5156 if (!hsotg->frame_num_array) 5157 goto error1; 5158 hsotg->last_frame_num_array = 5159 kcalloc(FRAME_NUM_ARRAY_SIZE, 5160 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL); 5161 if (!hsotg->last_frame_num_array) 5162 goto error1; 5163 #endif 5164 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5165 5166 /* Check if the bus driver or platform code has setup a dma_mask */ 5167 if (hsotg->params.host_dma && 5168 !hsotg->dev->dma_mask) { 5169 dev_warn(hsotg->dev, 5170 "dma_mask not set, disabling DMA\n"); 5171 hsotg->params.host_dma = false; 5172 hsotg->params.dma_desc_enable = false; 5173 } 5174 5175 /* Set device flags indicating whether the HCD supports DMA */ 5176 if (hsotg->params.host_dma) { 5177 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5178 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5179 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5180 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5181 } 5182 5183 if (hsotg->params.change_speed_quirk) { 5184 dwc2_hc_driver.free_dev = dwc2_free_dev; 5185 dwc2_hc_driver.reset_device = dwc2_reset_device; 5186 } 5187 5188 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5189 if (!hcd) 5190 goto error1; 5191 5192 if (!hsotg->params.host_dma) 5193 hcd->self.uses_dma = 0; 5194 5195 hcd->has_tt = 1; 5196 5197 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5198 hcd->rsrc_start = res->start; 5199 hcd->rsrc_len = resource_size(res); 5200 5201 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5202 hsotg->priv = hcd; 5203 5204 /* 5205 * Disable the global interrupt until all the interrupt handlers are 5206 * installed 5207 */ 5208 dwc2_disable_global_interrupts(hsotg); 5209 5210 /* Initialize the DWC_otg core, and select the Phy type */ 5211 retval = dwc2_core_init(hsotg, true); 5212 if (retval) 5213 goto error2; 5214 5215 /* Create new workqueue and init work */ 5216 retval = -ENOMEM; 5217 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5218 if (!hsotg->wq_otg) { 5219 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5220 goto error2; 5221 } 5222 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5223 5224 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); 5225 5226 /* Initialize the non-periodic schedule */ 5227 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5228 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 5229 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5230 5231 /* Initialize the periodic schedule */ 5232 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5233 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5234 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5235 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5236 5237 INIT_LIST_HEAD(&hsotg->split_order); 5238 5239 /* 5240 * Create a host channel descriptor for each host channel implemented 5241 * in the controller. Initialize the channel descriptor array. 5242 */ 5243 INIT_LIST_HEAD(&hsotg->free_hc_list); 5244 num_channels = hsotg->params.host_channels; 5245 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5246 5247 for (i = 0; i < num_channels; i++) { 5248 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5249 if (!channel) 5250 goto error3; 5251 channel->hc_num = i; 5252 INIT_LIST_HEAD(&channel->split_order_list_entry); 5253 hsotg->hc_ptr_array[i] = channel; 5254 } 5255 5256 /* Initialize hsotg start work */ 5257 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5258 5259 /* Initialize port reset work */ 5260 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5261 5262 /* 5263 * Allocate space for storing data on status transactions. Normally no 5264 * data is sent, but this space acts as a bit bucket. This must be 5265 * done after usb_add_hcd since that function allocates the DMA buffer 5266 * pool. 5267 */ 5268 if (hsotg->params.host_dma) 5269 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5270 DWC2_HCD_STATUS_BUF_SIZE, 5271 &hsotg->status_buf_dma, GFP_KERNEL); 5272 else 5273 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5274 GFP_KERNEL); 5275 5276 if (!hsotg->status_buf) 5277 goto error3; 5278 5279 /* 5280 * Create kmem caches to handle descriptor buffers in descriptor 5281 * DMA mode. 5282 * Alignment must be set to 512 bytes. 5283 */ 5284 if (hsotg->params.dma_desc_enable || 5285 hsotg->params.dma_desc_fs_enable) { 5286 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5287 sizeof(struct dwc2_dma_desc) * 5288 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5289 NULL); 5290 if (!hsotg->desc_gen_cache) { 5291 dev_err(hsotg->dev, 5292 "unable to create dwc2 generic desc cache\n"); 5293 5294 /* 5295 * Disable descriptor dma mode since it will not be 5296 * usable. 5297 */ 5298 hsotg->params.dma_desc_enable = false; 5299 hsotg->params.dma_desc_fs_enable = false; 5300 } 5301 5302 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5303 sizeof(struct dwc2_dma_desc) * 5304 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5305 if (!hsotg->desc_hsisoc_cache) { 5306 dev_err(hsotg->dev, 5307 "unable to create dwc2 hs isoc desc cache\n"); 5308 5309 kmem_cache_destroy(hsotg->desc_gen_cache); 5310 5311 /* 5312 * Disable descriptor dma mode since it will not be 5313 * usable. 5314 */ 5315 hsotg->params.dma_desc_enable = false; 5316 hsotg->params.dma_desc_fs_enable = false; 5317 } 5318 } 5319 5320 if (hsotg->params.host_dma) { 5321 /* 5322 * Create kmem caches to handle non-aligned buffer 5323 * in Buffer DMA mode. 5324 */ 5325 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma", 5326 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4, 5327 SLAB_CACHE_DMA, NULL); 5328 if (!hsotg->unaligned_cache) 5329 dev_err(hsotg->dev, 5330 "unable to create dwc2 unaligned cache\n"); 5331 } 5332 5333 hsotg->otg_port = 1; 5334 hsotg->frame_list = NULL; 5335 hsotg->frame_list_dma = 0; 5336 hsotg->periodic_qh_count = 0; 5337 5338 /* Initiate lx_state to L3 disconnected state */ 5339 hsotg->lx_state = DWC2_L3; 5340 5341 hcd->self.otg_port = hsotg->otg_port; 5342 5343 /* Don't support SG list at this point */ 5344 hcd->self.sg_tablesize = 0; 5345 5346 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5347 otg_set_host(hsotg->uphy->otg, &hcd->self); 5348 5349 /* 5350 * Finish generic HCD initialization and start the HCD. This function 5351 * allocates the DMA buffer pool, registers the USB bus, requests the 5352 * IRQ line, and calls hcd_start method. 5353 */ 5354 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5355 if (retval < 0) 5356 goto error4; 5357 5358 device_wakeup_enable(hcd->self.controller); 5359 5360 dwc2_hcd_dump_state(hsotg); 5361 5362 dwc2_enable_global_interrupts(hsotg); 5363 5364 return 0; 5365 5366 error4: 5367 kmem_cache_destroy(hsotg->unaligned_cache); 5368 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5369 kmem_cache_destroy(hsotg->desc_gen_cache); 5370 error3: 5371 dwc2_hcd_release(hsotg); 5372 error2: 5373 usb_put_hcd(hcd); 5374 error1: 5375 5376 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5377 kfree(hsotg->last_frame_num_array); 5378 kfree(hsotg->frame_num_array); 5379 #endif 5380 5381 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5382 return retval; 5383 } 5384 5385 /* 5386 * Removes the HCD. 5387 * Frees memory and resources associated with the HCD and deregisters the bus. 5388 */ 5389 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5390 { 5391 struct usb_hcd *hcd; 5392 5393 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5394 5395 hcd = dwc2_hsotg_to_hcd(hsotg); 5396 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5397 5398 if (!hcd) { 5399 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5400 __func__); 5401 return; 5402 } 5403 5404 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5405 otg_set_host(hsotg->uphy->otg, NULL); 5406 5407 usb_remove_hcd(hcd); 5408 hsotg->priv = NULL; 5409 5410 kmem_cache_destroy(hsotg->unaligned_cache); 5411 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5412 kmem_cache_destroy(hsotg->desc_gen_cache); 5413 5414 dwc2_hcd_release(hsotg); 5415 usb_put_hcd(hcd); 5416 5417 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5418 kfree(hsotg->last_frame_num_array); 5419 kfree(hsotg->frame_num_array); 5420 #endif 5421 } 5422 5423 /** 5424 * dwc2_backup_host_registers() - Backup controller host registers. 5425 * When suspending usb bus, registers needs to be backuped 5426 * if controller power is disabled once suspended. 5427 * 5428 * @hsotg: Programming view of the DWC_otg controller 5429 */ 5430 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5431 { 5432 struct dwc2_hregs_backup *hr; 5433 int i; 5434 5435 dev_dbg(hsotg->dev, "%s\n", __func__); 5436 5437 /* Backup Host regs */ 5438 hr = &hsotg->hr_backup; 5439 hr->hcfg = dwc2_readl(hsotg, HCFG); 5440 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK); 5441 for (i = 0; i < hsotg->params.host_channels; ++i) 5442 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i)); 5443 5444 hr->hprt0 = dwc2_read_hprt0(hsotg); 5445 hr->hfir = dwc2_readl(hsotg, HFIR); 5446 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 5447 hr->valid = true; 5448 5449 return 0; 5450 } 5451 5452 /** 5453 * dwc2_restore_host_registers() - Restore controller host registers. 5454 * When resuming usb bus, device registers needs to be restored 5455 * if controller power were disabled. 5456 * 5457 * @hsotg: Programming view of the DWC_otg controller 5458 */ 5459 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5460 { 5461 struct dwc2_hregs_backup *hr; 5462 int i; 5463 5464 dev_dbg(hsotg->dev, "%s\n", __func__); 5465 5466 /* Restore host regs */ 5467 hr = &hsotg->hr_backup; 5468 if (!hr->valid) { 5469 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5470 __func__); 5471 return -EINVAL; 5472 } 5473 hr->valid = false; 5474 5475 dwc2_writel(hsotg, hr->hcfg, HCFG); 5476 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK); 5477 5478 for (i = 0; i < hsotg->params.host_channels; ++i) 5479 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i)); 5480 5481 dwc2_writel(hsotg, hr->hprt0, HPRT0); 5482 dwc2_writel(hsotg, hr->hfir, HFIR); 5483 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ); 5484 hsotg->frame_number = 0; 5485 5486 return 0; 5487 } 5488 5489 /** 5490 * dwc2_host_enter_hibernation() - Put controller in Hibernation. 5491 * 5492 * @hsotg: Programming view of the DWC_otg controller 5493 */ 5494 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 5495 { 5496 unsigned long flags; 5497 int ret = 0; 5498 u32 hprt0; 5499 u32 pcgcctl; 5500 u32 gusbcfg; 5501 u32 gpwrdn; 5502 5503 dev_dbg(hsotg->dev, "Preparing host for hibernation\n"); 5504 ret = dwc2_backup_global_registers(hsotg); 5505 if (ret) { 5506 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5507 __func__); 5508 return ret; 5509 } 5510 ret = dwc2_backup_host_registers(hsotg); 5511 if (ret) { 5512 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 5513 __func__); 5514 return ret; 5515 } 5516 5517 /* Enter USB Suspend Mode */ 5518 hprt0 = dwc2_readl(hsotg, HPRT0); 5519 hprt0 |= HPRT0_SUSP; 5520 hprt0 &= ~HPRT0_ENA; 5521 dwc2_writel(hsotg, hprt0, HPRT0); 5522 5523 /* Wait for the HPRT0.PrtSusp register field to be set */ 5524 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) 5525 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); 5526 5527 /* 5528 * We need to disable interrupts to prevent servicing of any IRQ 5529 * during going to hibernation 5530 */ 5531 spin_lock_irqsave(&hsotg->lock, flags); 5532 hsotg->lx_state = DWC2_L2; 5533 5534 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 5535 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5536 /* ULPI interface */ 5537 /* Suspend the Phy Clock */ 5538 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5539 pcgcctl |= PCGCTL_STOPPCLK; 5540 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5541 udelay(10); 5542 5543 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5544 gpwrdn |= GPWRDN_PMUACTV; 5545 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5546 udelay(10); 5547 } else { 5548 /* UTMI+ Interface */ 5549 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5550 gpwrdn |= GPWRDN_PMUACTV; 5551 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5552 udelay(10); 5553 5554 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5555 pcgcctl |= PCGCTL_STOPPCLK; 5556 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5557 udelay(10); 5558 } 5559 5560 /* Enable interrupts from wake up logic */ 5561 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5562 gpwrdn |= GPWRDN_PMUINTSEL; 5563 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5564 udelay(10); 5565 5566 /* Unmask host mode interrupts in GPWRDN */ 5567 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5568 gpwrdn |= GPWRDN_DISCONN_DET_MSK; 5569 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5570 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5571 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5572 udelay(10); 5573 5574 /* Enable Power Down Clamp */ 5575 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5576 gpwrdn |= GPWRDN_PWRDNCLMP; 5577 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5578 udelay(10); 5579 5580 /* Switch off VDD */ 5581 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5582 gpwrdn |= GPWRDN_PWRDNSWTCH; 5583 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5584 5585 hsotg->hibernated = 1; 5586 hsotg->bus_suspended = 1; 5587 dev_dbg(hsotg->dev, "Host hibernation completed\n"); 5588 spin_unlock_irqrestore(&hsotg->lock, flags); 5589 return ret; 5590 } 5591 5592 /* 5593 * dwc2_host_exit_hibernation() 5594 * 5595 * @hsotg: Programming view of the DWC_otg controller 5596 * @rem_wakeup: indicates whether resume is initiated by Device or Host. 5597 * @param reset: indicates whether resume is initiated by Reset. 5598 * 5599 * Return: non-zero if failed to enter to hibernation. 5600 * 5601 * This function is for exiting from Host mode hibernation by 5602 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. 5603 */ 5604 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 5605 int reset) 5606 { 5607 u32 gpwrdn; 5608 u32 hprt0; 5609 int ret = 0; 5610 struct dwc2_gregs_backup *gr; 5611 struct dwc2_hregs_backup *hr; 5612 5613 gr = &hsotg->gr_backup; 5614 hr = &hsotg->hr_backup; 5615 5616 dev_dbg(hsotg->dev, 5617 "%s: called with rem_wakeup = %d reset = %d\n", 5618 __func__, rem_wakeup, reset); 5619 5620 dwc2_hib_restore_common(hsotg, rem_wakeup, 1); 5621 hsotg->hibernated = 0; 5622 5623 /* 5624 * This step is not described in functional spec but if not wait for 5625 * this delay, mismatch interrupts occurred because just after restore 5626 * core is in Device mode(gintsts.curmode == 0) 5627 */ 5628 mdelay(100); 5629 5630 /* Clear all pending interupts */ 5631 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5632 5633 /* De-assert Restore */ 5634 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5635 gpwrdn &= ~GPWRDN_RESTORE; 5636 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5637 udelay(10); 5638 5639 /* Restore GUSBCFG, HCFG */ 5640 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 5641 dwc2_writel(hsotg, hr->hcfg, HCFG); 5642 5643 /* De-assert Wakeup Logic */ 5644 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5645 gpwrdn &= ~GPWRDN_PMUACTV; 5646 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5647 udelay(10); 5648 5649 hprt0 = hr->hprt0; 5650 hprt0 |= HPRT0_PWR; 5651 hprt0 &= ~HPRT0_ENA; 5652 hprt0 &= ~HPRT0_SUSP; 5653 dwc2_writel(hsotg, hprt0, HPRT0); 5654 5655 hprt0 = hr->hprt0; 5656 hprt0 |= HPRT0_PWR; 5657 hprt0 &= ~HPRT0_ENA; 5658 hprt0 &= ~HPRT0_SUSP; 5659 5660 if (reset) { 5661 hprt0 |= HPRT0_RST; 5662 dwc2_writel(hsotg, hprt0, HPRT0); 5663 5664 /* Wait for Resume time and then program HPRT again */ 5665 mdelay(60); 5666 hprt0 &= ~HPRT0_RST; 5667 dwc2_writel(hsotg, hprt0, HPRT0); 5668 } else { 5669 hprt0 |= HPRT0_RES; 5670 dwc2_writel(hsotg, hprt0, HPRT0); 5671 5672 /* Wait for Resume time and then program HPRT again */ 5673 mdelay(100); 5674 hprt0 &= ~HPRT0_RES; 5675 dwc2_writel(hsotg, hprt0, HPRT0); 5676 } 5677 /* Clear all interrupt status */ 5678 hprt0 = dwc2_readl(hsotg, HPRT0); 5679 hprt0 |= HPRT0_CONNDET; 5680 hprt0 |= HPRT0_ENACHG; 5681 hprt0 &= ~HPRT0_ENA; 5682 dwc2_writel(hsotg, hprt0, HPRT0); 5683 5684 hprt0 = dwc2_readl(hsotg, HPRT0); 5685 5686 /* Clear all pending interupts */ 5687 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5688 5689 /* Restore global registers */ 5690 ret = dwc2_restore_global_registers(hsotg); 5691 if (ret) { 5692 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5693 __func__); 5694 return ret; 5695 } 5696 5697 /* Restore host registers */ 5698 ret = dwc2_restore_host_registers(hsotg); 5699 if (ret) { 5700 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 5701 __func__); 5702 return ret; 5703 } 5704 5705 dwc2_hcd_rem_wakeup(hsotg); 5706 5707 hsotg->hibernated = 0; 5708 hsotg->bus_suspended = 0; 5709 hsotg->lx_state = DWC2_L0; 5710 dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); 5711 return ret; 5712 } 5713