1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173 } 174 175 /* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184 { 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191 } 192 193 /** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199 { 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 dwc2_writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215 } 216 217 /* Must be called with interrupt disabled and spinlock held */ 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219 { 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260 /* All channels have been freed, mark them available */ 261 if (hsotg->core_params->uframe_sched > 0) { 262 hsotg->available_host_channels = 263 hsotg->core_params->host_channels; 264 } else { 265 hsotg->non_periodic_channels = 0; 266 hsotg->periodic_channels = 0; 267 } 268 } 269 270 /** 271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 272 * 273 * @hsotg: Pointer to struct dwc2_hsotg 274 * 275 * Must be called with interrupt disabled and spinlock held 276 */ 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 278 { 279 u32 intr; 280 281 /* Set status flags for the hub driver */ 282 hsotg->flags.b.port_connect_status_change = 1; 283 hsotg->flags.b.port_connect_status = 0; 284 285 /* 286 * Shutdown any transfers in process by clearing the Tx FIFO Empty 287 * interrupt mask and status bits and disabling subsequent host 288 * channel interrupts. 289 */ 290 intr = dwc2_readl(hsotg->regs + GINTMSK); 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 292 dwc2_writel(intr, hsotg->regs + GINTMSK); 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 294 dwc2_writel(intr, hsotg->regs + GINTSTS); 295 296 /* 297 * Turn off the vbus power only if the core has transitioned to device 298 * mode. If still in host mode, need to keep power on to detect a 299 * reconnection. 300 */ 301 if (dwc2_is_device_mode(hsotg)) { 302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 304 dwc2_writel(0, hsotg->regs + HPRT0); 305 } 306 307 dwc2_disable_host_interrupts(hsotg); 308 } 309 310 /* Respond with an error status to all URBs in the schedule */ 311 dwc2_kill_all_urbs(hsotg); 312 313 if (dwc2_is_host_mode(hsotg)) 314 /* Clean up any host channels that were in use */ 315 dwc2_hcd_cleanup_channels(hsotg); 316 317 dwc2_host_disconnect(hsotg); 318 } 319 320 /** 321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 322 * 323 * @hsotg: Pointer to struct dwc2_hsotg 324 */ 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 326 { 327 if (hsotg->lx_state == DWC2_L2) { 328 hsotg->flags.b.port_suspend_change = 1; 329 usb_hcd_resume_root_hub(hsotg->priv); 330 } else { 331 hsotg->flags.b.port_l1_change = 1; 332 } 333 } 334 335 /** 336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 337 * 338 * @hsotg: Pointer to struct dwc2_hsotg 339 * 340 * Must be called with interrupt disabled and spinlock held 341 */ 342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 343 { 344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 345 346 /* 347 * The root hub should be disconnected before this function is called. 348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 349 * and the QH lists (via ..._hcd_endpoint_disable). 350 */ 351 352 /* Turn off all host-specific interrupts */ 353 dwc2_disable_host_interrupts(hsotg); 354 355 /* Turn off the vbus power */ 356 dev_dbg(hsotg->dev, "PortPower off\n"); 357 dwc2_writel(0, hsotg->regs + HPRT0); 358 } 359 360 /* Caller must hold driver lock */ 361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 362 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 363 struct dwc2_qtd *qtd) 364 { 365 u32 intr_mask; 366 int retval; 367 int dev_speed; 368 369 if (!hsotg->flags.b.port_connect_status) { 370 /* No longer connected */ 371 dev_err(hsotg->dev, "Not connected\n"); 372 return -ENODEV; 373 } 374 375 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 376 377 /* Some configurations cannot support LS traffic on a FS root port */ 378 if ((dev_speed == USB_SPEED_LOW) && 379 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 380 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 381 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 382 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 383 384 if (prtspd == HPRT0_SPD_FULL_SPEED) 385 return -ENODEV; 386 } 387 388 if (!qtd) 389 return -EINVAL; 390 391 dwc2_hcd_qtd_init(qtd, urb); 392 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 393 if (retval) { 394 dev_err(hsotg->dev, 395 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 396 retval); 397 return retval; 398 } 399 400 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 401 if (!(intr_mask & GINTSTS_SOF)) { 402 enum dwc2_transaction_type tr_type; 403 404 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 405 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 406 /* 407 * Do not schedule SG transactions until qtd has 408 * URB_GIVEBACK_ASAP set 409 */ 410 return 0; 411 412 tr_type = dwc2_hcd_select_transactions(hsotg); 413 if (tr_type != DWC2_TRANSACTION_NONE) 414 dwc2_hcd_queue_transactions(hsotg, tr_type); 415 } 416 417 return 0; 418 } 419 420 /* Must be called with interrupt disabled and spinlock held */ 421 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 422 struct dwc2_hcd_urb *urb) 423 { 424 struct dwc2_qh *qh; 425 struct dwc2_qtd *urb_qtd; 426 427 urb_qtd = urb->qtd; 428 if (!urb_qtd) { 429 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 430 return -EINVAL; 431 } 432 433 qh = urb_qtd->qh; 434 if (!qh) { 435 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 436 return -EINVAL; 437 } 438 439 urb->priv = NULL; 440 441 if (urb_qtd->in_process && qh->channel) { 442 dwc2_dump_channel_info(hsotg, qh->channel); 443 444 /* The QTD is in process (it has been assigned to a channel) */ 445 if (hsotg->flags.b.port_connect_status) 446 /* 447 * If still connected (i.e. in host mode), halt the 448 * channel so it can be used for other transfers. If 449 * no longer connected, the host registers can't be 450 * written to halt the channel since the core is in 451 * device mode. 452 */ 453 dwc2_hc_halt(hsotg, qh->channel, 454 DWC2_HC_XFER_URB_DEQUEUE); 455 } 456 457 /* 458 * Free the QTD and clean up the associated QH. Leave the QH in the 459 * schedule if it has any remaining QTDs. 460 */ 461 if (hsotg->core_params->dma_desc_enable <= 0) { 462 u8 in_process = urb_qtd->in_process; 463 464 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 465 if (in_process) { 466 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 467 qh->channel = NULL; 468 } else if (list_empty(&qh->qtd_list)) { 469 dwc2_hcd_qh_unlink(hsotg, qh); 470 } 471 } else { 472 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 473 } 474 475 return 0; 476 } 477 478 /* Must NOT be called with interrupt disabled or spinlock held */ 479 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 480 struct usb_host_endpoint *ep, int retry) 481 { 482 struct dwc2_qtd *qtd, *qtd_tmp; 483 struct dwc2_qh *qh; 484 unsigned long flags; 485 int rc; 486 487 spin_lock_irqsave(&hsotg->lock, flags); 488 489 qh = ep->hcpriv; 490 if (!qh) { 491 rc = -EINVAL; 492 goto err; 493 } 494 495 while (!list_empty(&qh->qtd_list) && retry--) { 496 if (retry == 0) { 497 dev_err(hsotg->dev, 498 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 499 rc = -EBUSY; 500 goto err; 501 } 502 503 spin_unlock_irqrestore(&hsotg->lock, flags); 504 usleep_range(20000, 40000); 505 spin_lock_irqsave(&hsotg->lock, flags); 506 qh = ep->hcpriv; 507 if (!qh) { 508 rc = -EINVAL; 509 goto err; 510 } 511 } 512 513 dwc2_hcd_qh_unlink(hsotg, qh); 514 515 /* Free each QTD in the QH's QTD list */ 516 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 517 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 518 519 ep->hcpriv = NULL; 520 spin_unlock_irqrestore(&hsotg->lock, flags); 521 dwc2_hcd_qh_free(hsotg, qh); 522 523 return 0; 524 525 err: 526 ep->hcpriv = NULL; 527 spin_unlock_irqrestore(&hsotg->lock, flags); 528 529 return rc; 530 } 531 532 /* Must be called with interrupt disabled and spinlock held */ 533 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 534 struct usb_host_endpoint *ep) 535 { 536 struct dwc2_qh *qh = ep->hcpriv; 537 538 if (!qh) 539 return -EINVAL; 540 541 qh->data_toggle = DWC2_HC_PID_DATA0; 542 543 return 0; 544 } 545 546 /* 547 * Initializes dynamic portions of the DWC_otg HCD state 548 * 549 * Must be called with interrupt disabled and spinlock held 550 */ 551 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 552 { 553 struct dwc2_host_chan *chan, *chan_tmp; 554 int num_channels; 555 int i; 556 557 hsotg->flags.d32 = 0; 558 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 559 560 if (hsotg->core_params->uframe_sched > 0) { 561 hsotg->available_host_channels = 562 hsotg->core_params->host_channels; 563 } else { 564 hsotg->non_periodic_channels = 0; 565 hsotg->periodic_channels = 0; 566 } 567 568 /* 569 * Put all channels in the free channel list and clean up channel 570 * states 571 */ 572 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 573 hc_list_entry) 574 list_del_init(&chan->hc_list_entry); 575 576 num_channels = hsotg->core_params->host_channels; 577 for (i = 0; i < num_channels; i++) { 578 chan = hsotg->hc_ptr_array[i]; 579 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 580 dwc2_hc_cleanup(hsotg, chan); 581 } 582 583 /* Initialize the DWC core for host mode operation */ 584 dwc2_core_host_init(hsotg); 585 } 586 587 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 588 struct dwc2_host_chan *chan, 589 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 590 { 591 int hub_addr, hub_port; 592 593 chan->do_split = 1; 594 chan->xact_pos = qtd->isoc_split_pos; 595 chan->complete_split = qtd->complete_split; 596 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 597 chan->hub_addr = (u8)hub_addr; 598 chan->hub_port = (u8)hub_port; 599 } 600 601 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 602 struct dwc2_host_chan *chan, 603 struct dwc2_qtd *qtd, void *bufptr) 604 { 605 struct dwc2_hcd_urb *urb = qtd->urb; 606 struct dwc2_hcd_iso_packet_desc *frame_desc; 607 608 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 609 case USB_ENDPOINT_XFER_CONTROL: 610 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 611 612 switch (qtd->control_phase) { 613 case DWC2_CONTROL_SETUP: 614 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 615 chan->do_ping = 0; 616 chan->ep_is_in = 0; 617 chan->data_pid_start = DWC2_HC_PID_SETUP; 618 if (hsotg->core_params->dma_enable > 0) 619 chan->xfer_dma = urb->setup_dma; 620 else 621 chan->xfer_buf = urb->setup_packet; 622 chan->xfer_len = 8; 623 bufptr = NULL; 624 break; 625 626 case DWC2_CONTROL_DATA: 627 dev_vdbg(hsotg->dev, " Control data transaction\n"); 628 chan->data_pid_start = qtd->data_toggle; 629 break; 630 631 case DWC2_CONTROL_STATUS: 632 /* 633 * Direction is opposite of data direction or IN if no 634 * data 635 */ 636 dev_vdbg(hsotg->dev, " Control status transaction\n"); 637 if (urb->length == 0) 638 chan->ep_is_in = 1; 639 else 640 chan->ep_is_in = 641 dwc2_hcd_is_pipe_out(&urb->pipe_info); 642 if (chan->ep_is_in) 643 chan->do_ping = 0; 644 chan->data_pid_start = DWC2_HC_PID_DATA1; 645 chan->xfer_len = 0; 646 if (hsotg->core_params->dma_enable > 0) 647 chan->xfer_dma = hsotg->status_buf_dma; 648 else 649 chan->xfer_buf = hsotg->status_buf; 650 bufptr = NULL; 651 break; 652 } 653 break; 654 655 case USB_ENDPOINT_XFER_BULK: 656 chan->ep_type = USB_ENDPOINT_XFER_BULK; 657 break; 658 659 case USB_ENDPOINT_XFER_INT: 660 chan->ep_type = USB_ENDPOINT_XFER_INT; 661 break; 662 663 case USB_ENDPOINT_XFER_ISOC: 664 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 665 if (hsotg->core_params->dma_desc_enable > 0) 666 break; 667 668 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 669 frame_desc->status = 0; 670 671 if (hsotg->core_params->dma_enable > 0) { 672 chan->xfer_dma = urb->dma; 673 chan->xfer_dma += frame_desc->offset + 674 qtd->isoc_split_offset; 675 } else { 676 chan->xfer_buf = urb->buf; 677 chan->xfer_buf += frame_desc->offset + 678 qtd->isoc_split_offset; 679 } 680 681 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 682 683 /* For non-dword aligned buffers */ 684 if (hsotg->core_params->dma_enable > 0 && 685 (chan->xfer_dma & 0x3)) 686 bufptr = (u8 *)urb->buf + frame_desc->offset + 687 qtd->isoc_split_offset; 688 else 689 bufptr = NULL; 690 691 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 692 if (chan->xfer_len <= 188) 693 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 694 else 695 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 696 } 697 break; 698 } 699 700 return bufptr; 701 } 702 703 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 704 struct dwc2_host_chan *chan, 705 struct dwc2_hcd_urb *urb, void *bufptr) 706 { 707 u32 buf_size; 708 struct urb *usb_urb; 709 struct usb_hcd *hcd; 710 711 if (!qh->dw_align_buf) { 712 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 713 buf_size = hsotg->core_params->max_transfer_size; 714 else 715 /* 3072 = 3 max-size Isoc packets */ 716 buf_size = 3072; 717 718 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA); 719 if (!qh->dw_align_buf) 720 return -ENOMEM; 721 qh->dw_align_buf_size = buf_size; 722 } 723 724 if (chan->xfer_len) { 725 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 726 usb_urb = urb->priv; 727 728 if (usb_urb) { 729 if (usb_urb->transfer_flags & 730 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 731 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 732 hcd = dwc2_hsotg_to_hcd(hsotg); 733 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 734 } 735 if (!chan->ep_is_in) 736 memcpy(qh->dw_align_buf, bufptr, 737 chan->xfer_len); 738 } else { 739 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 740 } 741 } 742 743 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, 744 qh->dw_align_buf, qh->dw_align_buf_size, 745 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 746 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 747 dev_err(hsotg->dev, "can't map align_buf\n"); 748 chan->align_buf = 0; 749 return -EINVAL; 750 } 751 752 chan->align_buf = qh->dw_align_buf_dma; 753 return 0; 754 } 755 756 /** 757 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 758 * channel and initializes the host channel to perform the transactions. The 759 * host channel is removed from the free list. 760 * 761 * @hsotg: The HCD state structure 762 * @qh: Transactions from the first QTD for this QH are selected and assigned 763 * to a free host channel 764 */ 765 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 766 { 767 struct dwc2_host_chan *chan; 768 struct dwc2_hcd_urb *urb; 769 struct dwc2_qtd *qtd; 770 void *bufptr = NULL; 771 772 if (dbg_qh(qh)) 773 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 774 775 if (list_empty(&qh->qtd_list)) { 776 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 777 return -ENOMEM; 778 } 779 780 if (list_empty(&hsotg->free_hc_list)) { 781 dev_dbg(hsotg->dev, "No free channel to assign\n"); 782 return -ENOMEM; 783 } 784 785 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 786 hc_list_entry); 787 788 /* Remove host channel from free list */ 789 list_del_init(&chan->hc_list_entry); 790 791 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 792 urb = qtd->urb; 793 qh->channel = chan; 794 qtd->in_process = 1; 795 796 /* 797 * Use usb_pipedevice to determine device address. This address is 798 * 0 before the SET_ADDRESS command and the correct address afterward. 799 */ 800 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 801 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 802 chan->speed = qh->dev_speed; 803 chan->max_packet = dwc2_max_packet(qh->maxp); 804 805 chan->xfer_started = 0; 806 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 807 chan->error_state = (qtd->error_count > 0); 808 chan->halt_on_queue = 0; 809 chan->halt_pending = 0; 810 chan->requests = 0; 811 812 /* 813 * The following values may be modified in the transfer type section 814 * below. The xfer_len value may be reduced when the transfer is 815 * started to accommodate the max widths of the XferSize and PktCnt 816 * fields in the HCTSIZn register. 817 */ 818 819 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 820 if (chan->ep_is_in) 821 chan->do_ping = 0; 822 else 823 chan->do_ping = qh->ping_state; 824 825 chan->data_pid_start = qh->data_toggle; 826 chan->multi_count = 1; 827 828 if (urb->actual_length > urb->length && 829 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 830 urb->actual_length = urb->length; 831 832 if (hsotg->core_params->dma_enable > 0) { 833 chan->xfer_dma = urb->dma + urb->actual_length; 834 835 /* For non-dword aligned case */ 836 if (hsotg->core_params->dma_desc_enable <= 0 && 837 (chan->xfer_dma & 0x3)) 838 bufptr = (u8 *)urb->buf + urb->actual_length; 839 } else { 840 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 841 } 842 843 chan->xfer_len = urb->length - urb->actual_length; 844 chan->xfer_count = 0; 845 846 /* Set the split attributes if required */ 847 if (qh->do_split) 848 dwc2_hc_init_split(hsotg, chan, qtd, urb); 849 else 850 chan->do_split = 0; 851 852 /* Set the transfer attributes */ 853 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 854 855 /* Non DWORD-aligned buffer case */ 856 if (bufptr) { 857 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 858 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 859 dev_err(hsotg->dev, 860 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 861 __func__); 862 /* Add channel back to free list */ 863 chan->align_buf = 0; 864 chan->multi_count = 0; 865 list_add_tail(&chan->hc_list_entry, 866 &hsotg->free_hc_list); 867 qtd->in_process = 0; 868 qh->channel = NULL; 869 return -ENOMEM; 870 } 871 } else { 872 chan->align_buf = 0; 873 } 874 875 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 876 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 877 /* 878 * This value may be modified when the transfer is started 879 * to reflect the actual transfer length 880 */ 881 chan->multi_count = dwc2_hb_mult(qh->maxp); 882 883 if (hsotg->core_params->dma_desc_enable > 0) 884 chan->desc_list_addr = qh->desc_list_dma; 885 886 dwc2_hc_init(hsotg, chan); 887 chan->qh = qh; 888 889 return 0; 890 } 891 892 /** 893 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 894 * schedule and assigns them to available host channels. Called from the HCD 895 * interrupt handler functions. 896 * 897 * @hsotg: The HCD state structure 898 * 899 * Return: The types of new transactions that were assigned to host channels 900 */ 901 enum dwc2_transaction_type dwc2_hcd_select_transactions( 902 struct dwc2_hsotg *hsotg) 903 { 904 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 905 struct list_head *qh_ptr; 906 struct dwc2_qh *qh; 907 int num_channels; 908 909 #ifdef DWC2_DEBUG_SOF 910 dev_vdbg(hsotg->dev, " Select Transactions\n"); 911 #endif 912 913 /* Process entries in the periodic ready list */ 914 qh_ptr = hsotg->periodic_sched_ready.next; 915 while (qh_ptr != &hsotg->periodic_sched_ready) { 916 if (list_empty(&hsotg->free_hc_list)) 917 break; 918 if (hsotg->core_params->uframe_sched > 0) { 919 if (hsotg->available_host_channels <= 1) 920 break; 921 hsotg->available_host_channels--; 922 } 923 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 924 if (dwc2_assign_and_init_hc(hsotg, qh)) 925 break; 926 927 /* 928 * Move the QH from the periodic ready schedule to the 929 * periodic assigned schedule 930 */ 931 qh_ptr = qh_ptr->next; 932 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 933 ret_val = DWC2_TRANSACTION_PERIODIC; 934 } 935 936 /* 937 * Process entries in the inactive portion of the non-periodic 938 * schedule. Some free host channels may not be used if they are 939 * reserved for periodic transfers. 940 */ 941 num_channels = hsotg->core_params->host_channels; 942 qh_ptr = hsotg->non_periodic_sched_inactive.next; 943 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 944 if (hsotg->core_params->uframe_sched <= 0 && 945 hsotg->non_periodic_channels >= num_channels - 946 hsotg->periodic_channels) 947 break; 948 if (list_empty(&hsotg->free_hc_list)) 949 break; 950 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 951 if (hsotg->core_params->uframe_sched > 0) { 952 if (hsotg->available_host_channels < 1) 953 break; 954 hsotg->available_host_channels--; 955 } 956 957 if (dwc2_assign_and_init_hc(hsotg, qh)) 958 break; 959 960 /* 961 * Move the QH from the non-periodic inactive schedule to the 962 * non-periodic active schedule 963 */ 964 qh_ptr = qh_ptr->next; 965 list_move(&qh->qh_list_entry, 966 &hsotg->non_periodic_sched_active); 967 968 if (ret_val == DWC2_TRANSACTION_NONE) 969 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 970 else 971 ret_val = DWC2_TRANSACTION_ALL; 972 973 if (hsotg->core_params->uframe_sched <= 0) 974 hsotg->non_periodic_channels++; 975 } 976 977 return ret_val; 978 } 979 980 /** 981 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 982 * a host channel associated with either a periodic or non-periodic transfer 983 * 984 * @hsotg: The HCD state structure 985 * @chan: Host channel descriptor associated with either a periodic or 986 * non-periodic transfer 987 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 988 * for periodic transfers or the non-periodic Tx FIFO 989 * for non-periodic transfers 990 * 991 * Return: 1 if a request is queued and more requests may be needed to 992 * complete the transfer, 0 if no more requests are required for this 993 * transfer, -1 if there is insufficient space in the Tx FIFO 994 * 995 * This function assumes that there is space available in the appropriate 996 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 997 * it checks whether space is available in the appropriate Tx FIFO. 998 * 999 * Must be called with interrupt disabled and spinlock held 1000 */ 1001 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1002 struct dwc2_host_chan *chan, 1003 u16 fifo_dwords_avail) 1004 { 1005 int retval = 0; 1006 1007 if (hsotg->core_params->dma_enable > 0) { 1008 if (hsotg->core_params->dma_desc_enable > 0) { 1009 if (!chan->xfer_started || 1010 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1011 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1012 chan->qh->ping_state = 0; 1013 } 1014 } else if (!chan->xfer_started) { 1015 dwc2_hc_start_transfer(hsotg, chan); 1016 chan->qh->ping_state = 0; 1017 } 1018 } else if (chan->halt_pending) { 1019 /* Don't queue a request if the channel has been halted */ 1020 } else if (chan->halt_on_queue) { 1021 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1022 } else if (chan->do_ping) { 1023 if (!chan->xfer_started) 1024 dwc2_hc_start_transfer(hsotg, chan); 1025 } else if (!chan->ep_is_in || 1026 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1027 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1028 if (!chan->xfer_started) { 1029 dwc2_hc_start_transfer(hsotg, chan); 1030 retval = 1; 1031 } else { 1032 retval = dwc2_hc_continue_transfer(hsotg, chan); 1033 } 1034 } else { 1035 retval = -1; 1036 } 1037 } else { 1038 if (!chan->xfer_started) { 1039 dwc2_hc_start_transfer(hsotg, chan); 1040 retval = 1; 1041 } else { 1042 retval = dwc2_hc_continue_transfer(hsotg, chan); 1043 } 1044 } 1045 1046 return retval; 1047 } 1048 1049 /* 1050 * Processes periodic channels for the next frame and queues transactions for 1051 * these channels to the DWC_otg controller. After queueing transactions, the 1052 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1053 * to queue as Periodic Tx FIFO or request queue space becomes available. 1054 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1055 * 1056 * Must be called with interrupt disabled and spinlock held 1057 */ 1058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1059 { 1060 struct list_head *qh_ptr; 1061 struct dwc2_qh *qh; 1062 u32 tx_status; 1063 u32 fspcavail; 1064 u32 gintmsk; 1065 int status; 1066 int no_queue_space = 0; 1067 int no_fifo_space = 0; 1068 u32 qspcavail; 1069 1070 if (dbg_perio()) 1071 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1072 1073 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1074 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1075 TXSTS_QSPCAVAIL_SHIFT; 1076 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1077 TXSTS_FSPCAVAIL_SHIFT; 1078 1079 if (dbg_perio()) { 1080 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1081 qspcavail); 1082 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1083 fspcavail); 1084 } 1085 1086 qh_ptr = hsotg->periodic_sched_assigned.next; 1087 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1088 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1089 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1090 TXSTS_QSPCAVAIL_SHIFT; 1091 if (qspcavail == 0) { 1092 no_queue_space = 1; 1093 break; 1094 } 1095 1096 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1097 if (!qh->channel) { 1098 qh_ptr = qh_ptr->next; 1099 continue; 1100 } 1101 1102 /* Make sure EP's TT buffer is clean before queueing qtds */ 1103 if (qh->tt_buffer_dirty) { 1104 qh_ptr = qh_ptr->next; 1105 continue; 1106 } 1107 1108 /* 1109 * Set a flag if we're queuing high-bandwidth in slave mode. 1110 * The flag prevents any halts to get into the request queue in 1111 * the middle of multiple high-bandwidth packets getting queued. 1112 */ 1113 if (hsotg->core_params->dma_enable <= 0 && 1114 qh->channel->multi_count > 1) 1115 hsotg->queuing_high_bandwidth = 1; 1116 1117 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1118 TXSTS_FSPCAVAIL_SHIFT; 1119 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1120 if (status < 0) { 1121 no_fifo_space = 1; 1122 break; 1123 } 1124 1125 /* 1126 * In Slave mode, stay on the current transfer until there is 1127 * nothing more to do or the high-bandwidth request count is 1128 * reached. In DMA mode, only need to queue one request. The 1129 * controller automatically handles multiple packets for 1130 * high-bandwidth transfers. 1131 */ 1132 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1133 qh->channel->requests == qh->channel->multi_count) { 1134 qh_ptr = qh_ptr->next; 1135 /* 1136 * Move the QH from the periodic assigned schedule to 1137 * the periodic queued schedule 1138 */ 1139 list_move(&qh->qh_list_entry, 1140 &hsotg->periodic_sched_queued); 1141 1142 /* done queuing high bandwidth */ 1143 hsotg->queuing_high_bandwidth = 0; 1144 } 1145 } 1146 1147 if (hsotg->core_params->dma_enable <= 0) { 1148 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1149 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1150 TXSTS_QSPCAVAIL_SHIFT; 1151 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1152 TXSTS_FSPCAVAIL_SHIFT; 1153 if (dbg_perio()) { 1154 dev_vdbg(hsotg->dev, 1155 " P Tx Req Queue Space Avail (after queue): %d\n", 1156 qspcavail); 1157 dev_vdbg(hsotg->dev, 1158 " P Tx FIFO Space Avail (after queue): %d\n", 1159 fspcavail); 1160 } 1161 1162 if (!list_empty(&hsotg->periodic_sched_assigned) || 1163 no_queue_space || no_fifo_space) { 1164 /* 1165 * May need to queue more transactions as the request 1166 * queue or Tx FIFO empties. Enable the periodic Tx 1167 * FIFO empty interrupt. (Always use the half-empty 1168 * level to ensure that new requests are loaded as 1169 * soon as possible.) 1170 */ 1171 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1172 gintmsk |= GINTSTS_PTXFEMP; 1173 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1174 } else { 1175 /* 1176 * Disable the Tx FIFO empty interrupt since there are 1177 * no more transactions that need to be queued right 1178 * now. This function is called from interrupt 1179 * handlers to queue more transactions as transfer 1180 * states change. 1181 */ 1182 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1183 gintmsk &= ~GINTSTS_PTXFEMP; 1184 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1185 } 1186 } 1187 } 1188 1189 /* 1190 * Processes active non-periodic channels and queues transactions for these 1191 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1192 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1193 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1194 * FIFO Empty interrupt is disabled. 1195 * 1196 * Must be called with interrupt disabled and spinlock held 1197 */ 1198 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1199 { 1200 struct list_head *orig_qh_ptr; 1201 struct dwc2_qh *qh; 1202 u32 tx_status; 1203 u32 qspcavail; 1204 u32 fspcavail; 1205 u32 gintmsk; 1206 int status; 1207 int no_queue_space = 0; 1208 int no_fifo_space = 0; 1209 int more_to_do = 0; 1210 1211 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1212 1213 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1214 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1215 TXSTS_QSPCAVAIL_SHIFT; 1216 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1217 TXSTS_FSPCAVAIL_SHIFT; 1218 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1219 qspcavail); 1220 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1221 fspcavail); 1222 1223 /* 1224 * Keep track of the starting point. Skip over the start-of-list 1225 * entry. 1226 */ 1227 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1228 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1229 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1230 1231 /* 1232 * Process once through the active list or until no more space is 1233 * available in the request queue or the Tx FIFO 1234 */ 1235 do { 1236 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1237 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1238 TXSTS_QSPCAVAIL_SHIFT; 1239 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1240 no_queue_space = 1; 1241 break; 1242 } 1243 1244 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1245 qh_list_entry); 1246 if (!qh->channel) 1247 goto next; 1248 1249 /* Make sure EP's TT buffer is clean before queueing qtds */ 1250 if (qh->tt_buffer_dirty) 1251 goto next; 1252 1253 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1254 TXSTS_FSPCAVAIL_SHIFT; 1255 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1256 1257 if (status > 0) { 1258 more_to_do = 1; 1259 } else if (status < 0) { 1260 no_fifo_space = 1; 1261 break; 1262 } 1263 next: 1264 /* Advance to next QH, skipping start-of-list entry */ 1265 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1266 if (hsotg->non_periodic_qh_ptr == 1267 &hsotg->non_periodic_sched_active) 1268 hsotg->non_periodic_qh_ptr = 1269 hsotg->non_periodic_qh_ptr->next; 1270 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1271 1272 if (hsotg->core_params->dma_enable <= 0) { 1273 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1274 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1275 TXSTS_QSPCAVAIL_SHIFT; 1276 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1277 TXSTS_FSPCAVAIL_SHIFT; 1278 dev_vdbg(hsotg->dev, 1279 " NP Tx Req Queue Space Avail (after queue): %d\n", 1280 qspcavail); 1281 dev_vdbg(hsotg->dev, 1282 " NP Tx FIFO Space Avail (after queue): %d\n", 1283 fspcavail); 1284 1285 if (more_to_do || no_queue_space || no_fifo_space) { 1286 /* 1287 * May need to queue more transactions as the request 1288 * queue or Tx FIFO empties. Enable the non-periodic 1289 * Tx FIFO empty interrupt. (Always use the half-empty 1290 * level to ensure that new requests are loaded as 1291 * soon as possible.) 1292 */ 1293 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1294 gintmsk |= GINTSTS_NPTXFEMP; 1295 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1296 } else { 1297 /* 1298 * Disable the Tx FIFO empty interrupt since there are 1299 * no more transactions that need to be queued right 1300 * now. This function is called from interrupt 1301 * handlers to queue more transactions as transfer 1302 * states change. 1303 */ 1304 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1305 gintmsk &= ~GINTSTS_NPTXFEMP; 1306 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1307 } 1308 } 1309 } 1310 1311 /** 1312 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1313 * and queues transactions for these channels to the DWC_otg controller. Called 1314 * from the HCD interrupt handler functions. 1315 * 1316 * @hsotg: The HCD state structure 1317 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1318 * or both) 1319 * 1320 * Must be called with interrupt disabled and spinlock held 1321 */ 1322 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1323 enum dwc2_transaction_type tr_type) 1324 { 1325 #ifdef DWC2_DEBUG_SOF 1326 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1327 #endif 1328 /* Process host channels associated with periodic transfers */ 1329 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1330 tr_type == DWC2_TRANSACTION_ALL) && 1331 !list_empty(&hsotg->periodic_sched_assigned)) 1332 dwc2_process_periodic_channels(hsotg); 1333 1334 /* Process host channels associated with non-periodic transfers */ 1335 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1336 tr_type == DWC2_TRANSACTION_ALL) { 1337 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1338 dwc2_process_non_periodic_channels(hsotg); 1339 } else { 1340 /* 1341 * Ensure NP Tx FIFO empty interrupt is disabled when 1342 * there are no non-periodic transfers to process 1343 */ 1344 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1345 1346 gintmsk &= ~GINTSTS_NPTXFEMP; 1347 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1348 } 1349 } 1350 } 1351 1352 static void dwc2_conn_id_status_change(struct work_struct *work) 1353 { 1354 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1355 wf_otg); 1356 u32 count = 0; 1357 u32 gotgctl; 1358 unsigned long flags; 1359 1360 dev_dbg(hsotg->dev, "%s()\n", __func__); 1361 1362 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1363 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1364 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1365 !!(gotgctl & GOTGCTL_CONID_B)); 1366 1367 /* B-Device connector (Device Mode) */ 1368 if (gotgctl & GOTGCTL_CONID_B) { 1369 /* Wait for switch to device mode */ 1370 dev_dbg(hsotg->dev, "connId B\n"); 1371 while (!dwc2_is_device_mode(hsotg)) { 1372 dev_info(hsotg->dev, 1373 "Waiting for Peripheral Mode, Mode=%s\n", 1374 dwc2_is_host_mode(hsotg) ? "Host" : 1375 "Peripheral"); 1376 usleep_range(20000, 40000); 1377 if (++count > 250) 1378 break; 1379 } 1380 if (count > 250) 1381 dev_err(hsotg->dev, 1382 "Connection id status change timed out\n"); 1383 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1384 dwc2_core_init(hsotg, false, -1); 1385 dwc2_enable_global_interrupts(hsotg); 1386 spin_lock_irqsave(&hsotg->lock, flags); 1387 dwc2_hsotg_core_init_disconnected(hsotg, false); 1388 spin_unlock_irqrestore(&hsotg->lock, flags); 1389 dwc2_hsotg_core_connect(hsotg); 1390 } else { 1391 /* A-Device connector (Host Mode) */ 1392 dev_dbg(hsotg->dev, "connId A\n"); 1393 while (!dwc2_is_host_mode(hsotg)) { 1394 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1395 dwc2_is_host_mode(hsotg) ? 1396 "Host" : "Peripheral"); 1397 usleep_range(20000, 40000); 1398 if (++count > 250) 1399 break; 1400 } 1401 if (count > 250) 1402 dev_err(hsotg->dev, 1403 "Connection id status change timed out\n"); 1404 hsotg->op_state = OTG_STATE_A_HOST; 1405 1406 /* Initialize the Core for Host mode */ 1407 dwc2_core_init(hsotg, false, -1); 1408 dwc2_enable_global_interrupts(hsotg); 1409 dwc2_hcd_start(hsotg); 1410 } 1411 } 1412 1413 static void dwc2_wakeup_detected(unsigned long data) 1414 { 1415 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1416 u32 hprt0; 1417 1418 dev_dbg(hsotg->dev, "%s()\n", __func__); 1419 1420 /* 1421 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1422 * so that OPT tests pass with all PHYs.) 1423 */ 1424 hprt0 = dwc2_read_hprt0(hsotg); 1425 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1426 hprt0 &= ~HPRT0_RES; 1427 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1428 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1429 dwc2_readl(hsotg->regs + HPRT0)); 1430 1431 hsotg->bus_suspended = 0; 1432 dwc2_hcd_rem_wakeup(hsotg); 1433 1434 /* Change to L0 state */ 1435 hsotg->lx_state = DWC2_L0; 1436 } 1437 1438 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1439 { 1440 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1441 1442 return hcd->self.b_hnp_enable; 1443 } 1444 1445 /* Must NOT be called with interrupt disabled or spinlock held */ 1446 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1447 { 1448 unsigned long flags; 1449 u32 hprt0; 1450 u32 pcgctl; 1451 u32 gotgctl; 1452 1453 dev_dbg(hsotg->dev, "%s()\n", __func__); 1454 1455 spin_lock_irqsave(&hsotg->lock, flags); 1456 1457 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1458 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1459 gotgctl |= GOTGCTL_HSTSETHNPEN; 1460 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 1461 hsotg->op_state = OTG_STATE_A_SUSPEND; 1462 } 1463 1464 hprt0 = dwc2_read_hprt0(hsotg); 1465 hprt0 |= HPRT0_SUSP; 1466 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1467 1468 hsotg->bus_suspended = 1; 1469 1470 /* 1471 * If hibernation is supported, Phy clock will be suspended 1472 * after registers are backuped. 1473 */ 1474 if (!hsotg->core_params->hibernation) { 1475 /* Suspend the Phy Clock */ 1476 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1477 pcgctl |= PCGCTL_STOPPCLK; 1478 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1479 udelay(10); 1480 } 1481 1482 /* For HNP the bus must be suspended for at least 200ms */ 1483 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1484 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1485 pcgctl &= ~PCGCTL_STOPPCLK; 1486 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1487 1488 spin_unlock_irqrestore(&hsotg->lock, flags); 1489 1490 usleep_range(200000, 250000); 1491 } else { 1492 spin_unlock_irqrestore(&hsotg->lock, flags); 1493 } 1494 } 1495 1496 /* Must NOT be called with interrupt disabled or spinlock held */ 1497 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1498 { 1499 unsigned long flags; 1500 u32 hprt0; 1501 u32 pcgctl; 1502 1503 spin_lock_irqsave(&hsotg->lock, flags); 1504 1505 /* 1506 * If hibernation is supported, Phy clock is already resumed 1507 * after registers restore. 1508 */ 1509 if (!hsotg->core_params->hibernation) { 1510 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1511 pcgctl &= ~PCGCTL_STOPPCLK; 1512 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1513 spin_unlock_irqrestore(&hsotg->lock, flags); 1514 usleep_range(20000, 40000); 1515 spin_lock_irqsave(&hsotg->lock, flags); 1516 } 1517 1518 hprt0 = dwc2_read_hprt0(hsotg); 1519 hprt0 |= HPRT0_RES; 1520 hprt0 &= ~HPRT0_SUSP; 1521 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1522 spin_unlock_irqrestore(&hsotg->lock, flags); 1523 1524 msleep(USB_RESUME_TIMEOUT); 1525 1526 spin_lock_irqsave(&hsotg->lock, flags); 1527 hprt0 = dwc2_read_hprt0(hsotg); 1528 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1529 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1530 hsotg->bus_suspended = 0; 1531 spin_unlock_irqrestore(&hsotg->lock, flags); 1532 } 1533 1534 /* Handles hub class-specific requests */ 1535 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1536 u16 wvalue, u16 windex, char *buf, u16 wlength) 1537 { 1538 struct usb_hub_descriptor *hub_desc; 1539 int retval = 0; 1540 u32 hprt0; 1541 u32 port_status; 1542 u32 speed; 1543 u32 pcgctl; 1544 1545 switch (typereq) { 1546 case ClearHubFeature: 1547 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1548 1549 switch (wvalue) { 1550 case C_HUB_LOCAL_POWER: 1551 case C_HUB_OVER_CURRENT: 1552 /* Nothing required here */ 1553 break; 1554 1555 default: 1556 retval = -EINVAL; 1557 dev_err(hsotg->dev, 1558 "ClearHubFeature request %1xh unknown\n", 1559 wvalue); 1560 } 1561 break; 1562 1563 case ClearPortFeature: 1564 if (wvalue != USB_PORT_FEAT_L1) 1565 if (!windex || windex > 1) 1566 goto error; 1567 switch (wvalue) { 1568 case USB_PORT_FEAT_ENABLE: 1569 dev_dbg(hsotg->dev, 1570 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1571 hprt0 = dwc2_read_hprt0(hsotg); 1572 hprt0 |= HPRT0_ENA; 1573 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1574 break; 1575 1576 case USB_PORT_FEAT_SUSPEND: 1577 dev_dbg(hsotg->dev, 1578 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1579 1580 if (hsotg->bus_suspended) 1581 dwc2_port_resume(hsotg); 1582 break; 1583 1584 case USB_PORT_FEAT_POWER: 1585 dev_dbg(hsotg->dev, 1586 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1587 hprt0 = dwc2_read_hprt0(hsotg); 1588 hprt0 &= ~HPRT0_PWR; 1589 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1590 break; 1591 1592 case USB_PORT_FEAT_INDICATOR: 1593 dev_dbg(hsotg->dev, 1594 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1595 /* Port indicator not supported */ 1596 break; 1597 1598 case USB_PORT_FEAT_C_CONNECTION: 1599 /* 1600 * Clears driver's internal Connect Status Change flag 1601 */ 1602 dev_dbg(hsotg->dev, 1603 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1604 hsotg->flags.b.port_connect_status_change = 0; 1605 break; 1606 1607 case USB_PORT_FEAT_C_RESET: 1608 /* Clears driver's internal Port Reset Change flag */ 1609 dev_dbg(hsotg->dev, 1610 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1611 hsotg->flags.b.port_reset_change = 0; 1612 break; 1613 1614 case USB_PORT_FEAT_C_ENABLE: 1615 /* 1616 * Clears the driver's internal Port Enable/Disable 1617 * Change flag 1618 */ 1619 dev_dbg(hsotg->dev, 1620 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1621 hsotg->flags.b.port_enable_change = 0; 1622 break; 1623 1624 case USB_PORT_FEAT_C_SUSPEND: 1625 /* 1626 * Clears the driver's internal Port Suspend Change 1627 * flag, which is set when resume signaling on the host 1628 * port is complete 1629 */ 1630 dev_dbg(hsotg->dev, 1631 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1632 hsotg->flags.b.port_suspend_change = 0; 1633 break; 1634 1635 case USB_PORT_FEAT_C_PORT_L1: 1636 dev_dbg(hsotg->dev, 1637 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1638 hsotg->flags.b.port_l1_change = 0; 1639 break; 1640 1641 case USB_PORT_FEAT_C_OVER_CURRENT: 1642 dev_dbg(hsotg->dev, 1643 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1644 hsotg->flags.b.port_over_current_change = 0; 1645 break; 1646 1647 default: 1648 retval = -EINVAL; 1649 dev_err(hsotg->dev, 1650 "ClearPortFeature request %1xh unknown or unsupported\n", 1651 wvalue); 1652 } 1653 break; 1654 1655 case GetHubDescriptor: 1656 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1657 hub_desc = (struct usb_hub_descriptor *)buf; 1658 hub_desc->bDescLength = 9; 1659 hub_desc->bDescriptorType = USB_DT_HUB; 1660 hub_desc->bNbrPorts = 1; 1661 hub_desc->wHubCharacteristics = 1662 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1663 HUB_CHAR_INDV_PORT_OCPM); 1664 hub_desc->bPwrOn2PwrGood = 1; 1665 hub_desc->bHubContrCurrent = 0; 1666 hub_desc->u.hs.DeviceRemovable[0] = 0; 1667 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1668 break; 1669 1670 case GetHubStatus: 1671 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1672 memset(buf, 0, 4); 1673 break; 1674 1675 case GetPortStatus: 1676 dev_vdbg(hsotg->dev, 1677 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1678 hsotg->flags.d32); 1679 if (!windex || windex > 1) 1680 goto error; 1681 1682 port_status = 0; 1683 if (hsotg->flags.b.port_connect_status_change) 1684 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1685 if (hsotg->flags.b.port_enable_change) 1686 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1687 if (hsotg->flags.b.port_suspend_change) 1688 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1689 if (hsotg->flags.b.port_l1_change) 1690 port_status |= USB_PORT_STAT_C_L1 << 16; 1691 if (hsotg->flags.b.port_reset_change) 1692 port_status |= USB_PORT_STAT_C_RESET << 16; 1693 if (hsotg->flags.b.port_over_current_change) { 1694 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1695 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1696 } 1697 1698 if (!hsotg->flags.b.port_connect_status) { 1699 /* 1700 * The port is disconnected, which means the core is 1701 * either in device mode or it soon will be. Just 1702 * return 0's for the remainder of the port status 1703 * since the port register can't be read if the core 1704 * is in device mode. 1705 */ 1706 *(__le32 *)buf = cpu_to_le32(port_status); 1707 break; 1708 } 1709 1710 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1711 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1712 1713 if (hprt0 & HPRT0_CONNSTS) 1714 port_status |= USB_PORT_STAT_CONNECTION; 1715 if (hprt0 & HPRT0_ENA) 1716 port_status |= USB_PORT_STAT_ENABLE; 1717 if (hprt0 & HPRT0_SUSP) 1718 port_status |= USB_PORT_STAT_SUSPEND; 1719 if (hprt0 & HPRT0_OVRCURRACT) 1720 port_status |= USB_PORT_STAT_OVERCURRENT; 1721 if (hprt0 & HPRT0_RST) 1722 port_status |= USB_PORT_STAT_RESET; 1723 if (hprt0 & HPRT0_PWR) 1724 port_status |= USB_PORT_STAT_POWER; 1725 1726 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1727 if (speed == HPRT0_SPD_HIGH_SPEED) 1728 port_status |= USB_PORT_STAT_HIGH_SPEED; 1729 else if (speed == HPRT0_SPD_LOW_SPEED) 1730 port_status |= USB_PORT_STAT_LOW_SPEED; 1731 1732 if (hprt0 & HPRT0_TSTCTL_MASK) 1733 port_status |= USB_PORT_STAT_TEST; 1734 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1735 1736 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1737 *(__le32 *)buf = cpu_to_le32(port_status); 1738 break; 1739 1740 case SetHubFeature: 1741 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1742 /* No HUB features supported */ 1743 break; 1744 1745 case SetPortFeature: 1746 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1747 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1748 goto error; 1749 1750 if (!hsotg->flags.b.port_connect_status) { 1751 /* 1752 * The port is disconnected, which means the core is 1753 * either in device mode or it soon will be. Just 1754 * return without doing anything since the port 1755 * register can't be written if the core is in device 1756 * mode. 1757 */ 1758 break; 1759 } 1760 1761 switch (wvalue) { 1762 case USB_PORT_FEAT_SUSPEND: 1763 dev_dbg(hsotg->dev, 1764 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1765 if (windex != hsotg->otg_port) 1766 goto error; 1767 dwc2_port_suspend(hsotg, windex); 1768 break; 1769 1770 case USB_PORT_FEAT_POWER: 1771 dev_dbg(hsotg->dev, 1772 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1773 hprt0 = dwc2_read_hprt0(hsotg); 1774 hprt0 |= HPRT0_PWR; 1775 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1776 break; 1777 1778 case USB_PORT_FEAT_RESET: 1779 hprt0 = dwc2_read_hprt0(hsotg); 1780 dev_dbg(hsotg->dev, 1781 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1782 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1783 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1784 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1785 /* ??? Original driver does this */ 1786 dwc2_writel(0, hsotg->regs + PCGCTL); 1787 1788 hprt0 = dwc2_read_hprt0(hsotg); 1789 /* Clear suspend bit if resetting from suspend state */ 1790 hprt0 &= ~HPRT0_SUSP; 1791 1792 /* 1793 * When B-Host the Port reset bit is set in the Start 1794 * HCD Callback function, so that the reset is started 1795 * within 1ms of the HNP success interrupt 1796 */ 1797 if (!dwc2_hcd_is_b_host(hsotg)) { 1798 hprt0 |= HPRT0_PWR | HPRT0_RST; 1799 dev_dbg(hsotg->dev, 1800 "In host mode, hprt0=%08x\n", hprt0); 1801 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1802 } 1803 1804 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1805 usleep_range(50000, 70000); 1806 hprt0 &= ~HPRT0_RST; 1807 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1808 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1809 break; 1810 1811 case USB_PORT_FEAT_INDICATOR: 1812 dev_dbg(hsotg->dev, 1813 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1814 /* Not supported */ 1815 break; 1816 1817 case USB_PORT_FEAT_TEST: 1818 hprt0 = dwc2_read_hprt0(hsotg); 1819 dev_dbg(hsotg->dev, 1820 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1821 hprt0 &= ~HPRT0_TSTCTL_MASK; 1822 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1823 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1824 break; 1825 1826 default: 1827 retval = -EINVAL; 1828 dev_err(hsotg->dev, 1829 "SetPortFeature %1xh unknown or unsupported\n", 1830 wvalue); 1831 break; 1832 } 1833 break; 1834 1835 default: 1836 error: 1837 retval = -EINVAL; 1838 dev_dbg(hsotg->dev, 1839 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1840 typereq, windex, wvalue); 1841 break; 1842 } 1843 1844 return retval; 1845 } 1846 1847 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1848 { 1849 int retval; 1850 1851 if (port != 1) 1852 return -EINVAL; 1853 1854 retval = (hsotg->flags.b.port_connect_status_change || 1855 hsotg->flags.b.port_reset_change || 1856 hsotg->flags.b.port_enable_change || 1857 hsotg->flags.b.port_suspend_change || 1858 hsotg->flags.b.port_over_current_change); 1859 1860 if (retval) { 1861 dev_dbg(hsotg->dev, 1862 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1863 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1864 hsotg->flags.b.port_connect_status_change); 1865 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1866 hsotg->flags.b.port_reset_change); 1867 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1868 hsotg->flags.b.port_enable_change); 1869 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1870 hsotg->flags.b.port_suspend_change); 1871 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1872 hsotg->flags.b.port_over_current_change); 1873 } 1874 1875 return retval; 1876 } 1877 1878 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1879 { 1880 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1881 1882 #ifdef DWC2_DEBUG_SOF 1883 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1884 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1885 #endif 1886 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1887 } 1888 1889 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1890 { 1891 return hsotg->op_state == OTG_STATE_B_HOST; 1892 } 1893 1894 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1895 int iso_desc_count, 1896 gfp_t mem_flags) 1897 { 1898 struct dwc2_hcd_urb *urb; 1899 u32 size = sizeof(*urb) + iso_desc_count * 1900 sizeof(struct dwc2_hcd_iso_packet_desc); 1901 1902 urb = kzalloc(size, mem_flags); 1903 if (urb) 1904 urb->packet_count = iso_desc_count; 1905 return urb; 1906 } 1907 1908 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1909 struct dwc2_hcd_urb *urb, u8 dev_addr, 1910 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1911 { 1912 if (dbg_perio() || 1913 ep_type == USB_ENDPOINT_XFER_BULK || 1914 ep_type == USB_ENDPOINT_XFER_CONTROL) 1915 dev_vdbg(hsotg->dev, 1916 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1917 dev_addr, ep_num, ep_dir, ep_type, mps); 1918 urb->pipe_info.dev_addr = dev_addr; 1919 urb->pipe_info.ep_num = ep_num; 1920 urb->pipe_info.pipe_type = ep_type; 1921 urb->pipe_info.pipe_dir = ep_dir; 1922 urb->pipe_info.mps = mps; 1923 } 1924 1925 /* 1926 * NOTE: This function will be removed once the peripheral controller code 1927 * is integrated and the driver is stable 1928 */ 1929 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1930 { 1931 #ifdef DEBUG 1932 struct dwc2_host_chan *chan; 1933 struct dwc2_hcd_urb *urb; 1934 struct dwc2_qtd *qtd; 1935 int num_channels; 1936 u32 np_tx_status; 1937 u32 p_tx_status; 1938 int i; 1939 1940 num_channels = hsotg->core_params->host_channels; 1941 dev_dbg(hsotg->dev, "\n"); 1942 dev_dbg(hsotg->dev, 1943 "************************************************************\n"); 1944 dev_dbg(hsotg->dev, "HCD State:\n"); 1945 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1946 1947 for (i = 0; i < num_channels; i++) { 1948 chan = hsotg->hc_ptr_array[i]; 1949 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1950 dev_dbg(hsotg->dev, 1951 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1952 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1953 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1954 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1955 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1956 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1957 chan->data_pid_start); 1958 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1959 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1960 chan->xfer_started); 1961 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1962 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1963 (unsigned long)chan->xfer_dma); 1964 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1965 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1966 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1967 chan->halt_on_queue); 1968 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1969 chan->halt_pending); 1970 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1971 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1972 dev_dbg(hsotg->dev, " complete_split: %d\n", 1973 chan->complete_split); 1974 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1975 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1976 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1977 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1978 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1979 1980 if (chan->xfer_started) { 1981 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1982 1983 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1984 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1985 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 1986 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 1987 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 1988 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1989 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1990 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1991 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1992 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1993 } 1994 1995 if (!(chan->xfer_started && chan->qh)) 1996 continue; 1997 1998 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1999 if (!qtd->in_process) 2000 break; 2001 urb = qtd->urb; 2002 dev_dbg(hsotg->dev, " URB Info:\n"); 2003 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2004 qtd, urb); 2005 if (urb) { 2006 dev_dbg(hsotg->dev, 2007 " Dev: %d, EP: %d %s\n", 2008 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2009 dwc2_hcd_get_ep_num(&urb->pipe_info), 2010 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2011 "IN" : "OUT"); 2012 dev_dbg(hsotg->dev, 2013 " Max packet size: %d\n", 2014 dwc2_hcd_get_mps(&urb->pipe_info)); 2015 dev_dbg(hsotg->dev, 2016 " transfer_buffer: %p\n", 2017 urb->buf); 2018 dev_dbg(hsotg->dev, 2019 " transfer_dma: %08lx\n", 2020 (unsigned long)urb->dma); 2021 dev_dbg(hsotg->dev, 2022 " transfer_buffer_length: %d\n", 2023 urb->length); 2024 dev_dbg(hsotg->dev, " actual_length: %d\n", 2025 urb->actual_length); 2026 } 2027 } 2028 } 2029 2030 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2031 hsotg->non_periodic_channels); 2032 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2033 hsotg->periodic_channels); 2034 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2035 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 2036 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2037 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2038 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2039 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2040 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2041 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2042 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2043 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2044 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2045 dwc2_hcd_dump_frrem(hsotg); 2046 dwc2_dump_global_registers(hsotg); 2047 dwc2_dump_host_registers(hsotg); 2048 dev_dbg(hsotg->dev, 2049 "************************************************************\n"); 2050 dev_dbg(hsotg->dev, "\n"); 2051 #endif 2052 } 2053 2054 /* 2055 * NOTE: This function will be removed once the peripheral controller code 2056 * is integrated and the driver is stable 2057 */ 2058 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2059 { 2060 #ifdef DWC2_DUMP_FRREM 2061 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2062 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2063 hsotg->frrem_samples, hsotg->frrem_accum, 2064 hsotg->frrem_samples > 0 ? 2065 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2066 dev_dbg(hsotg->dev, "\n"); 2067 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2068 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2069 hsotg->hfnum_7_samples, 2070 hsotg->hfnum_7_frrem_accum, 2071 hsotg->hfnum_7_samples > 0 ? 2072 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2073 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2074 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2075 hsotg->hfnum_0_samples, 2076 hsotg->hfnum_0_frrem_accum, 2077 hsotg->hfnum_0_samples > 0 ? 2078 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2079 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2080 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2081 hsotg->hfnum_other_samples, 2082 hsotg->hfnum_other_frrem_accum, 2083 hsotg->hfnum_other_samples > 0 ? 2084 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2085 0); 2086 dev_dbg(hsotg->dev, "\n"); 2087 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2088 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2089 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2090 hsotg->hfnum_7_samples_a > 0 ? 2091 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2092 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2093 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2094 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2095 hsotg->hfnum_0_samples_a > 0 ? 2096 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2097 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2098 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2099 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2100 hsotg->hfnum_other_samples_a > 0 ? 2101 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2102 : 0); 2103 dev_dbg(hsotg->dev, "\n"); 2104 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2105 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2106 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2107 hsotg->hfnum_7_samples_b > 0 ? 2108 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2109 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2110 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2111 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2112 (hsotg->hfnum_0_samples_b > 0) ? 2113 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2114 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2115 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2116 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2117 (hsotg->hfnum_other_samples_b > 0) ? 2118 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2119 : 0); 2120 #endif 2121 } 2122 2123 struct wrapper_priv_data { 2124 struct dwc2_hsotg *hsotg; 2125 }; 2126 2127 /* Gets the dwc2_hsotg from a usb_hcd */ 2128 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2129 { 2130 struct wrapper_priv_data *p; 2131 2132 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2133 return p->hsotg; 2134 } 2135 2136 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2137 2138 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2139 { 2140 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2141 2142 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2143 _dwc2_hcd_start(hcd); 2144 } 2145 2146 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2147 { 2148 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2149 2150 hcd->self.is_b_host = 0; 2151 } 2152 2153 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2154 int *hub_port) 2155 { 2156 struct urb *urb = context; 2157 2158 if (urb->dev->tt) 2159 *hub_addr = urb->dev->tt->hub->devnum; 2160 else 2161 *hub_addr = 0; 2162 *hub_port = urb->dev->ttport; 2163 } 2164 2165 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2166 { 2167 struct urb *urb = context; 2168 2169 return urb->dev->speed; 2170 } 2171 2172 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2173 struct urb *urb) 2174 { 2175 struct usb_bus *bus = hcd_to_bus(hcd); 2176 2177 if (urb->interval) 2178 bus->bandwidth_allocated += bw / urb->interval; 2179 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2180 bus->bandwidth_isoc_reqs++; 2181 else 2182 bus->bandwidth_int_reqs++; 2183 } 2184 2185 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2186 struct urb *urb) 2187 { 2188 struct usb_bus *bus = hcd_to_bus(hcd); 2189 2190 if (urb->interval) 2191 bus->bandwidth_allocated -= bw / urb->interval; 2192 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2193 bus->bandwidth_isoc_reqs--; 2194 else 2195 bus->bandwidth_int_reqs--; 2196 } 2197 2198 /* 2199 * Sets the final status of an URB and returns it to the upper layer. Any 2200 * required cleanup of the URB is performed. 2201 * 2202 * Must be called with interrupt disabled and spinlock held 2203 */ 2204 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2205 int status) 2206 { 2207 struct urb *urb; 2208 int i; 2209 2210 if (!qtd) { 2211 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2212 return; 2213 } 2214 2215 if (!qtd->urb) { 2216 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2217 return; 2218 } 2219 2220 urb = qtd->urb->priv; 2221 if (!urb) { 2222 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2223 return; 2224 } 2225 2226 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2227 2228 if (dbg_urb(urb)) 2229 dev_vdbg(hsotg->dev, 2230 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2231 __func__, urb, usb_pipedevice(urb->pipe), 2232 usb_pipeendpoint(urb->pipe), 2233 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2234 urb->actual_length); 2235 2236 2237 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2238 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2239 for (i = 0; i < urb->number_of_packets; ++i) { 2240 urb->iso_frame_desc[i].actual_length = 2241 dwc2_hcd_urb_get_iso_desc_actual_length( 2242 qtd->urb, i); 2243 urb->iso_frame_desc[i].status = 2244 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2245 } 2246 } 2247 2248 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2249 for (i = 0; i < urb->number_of_packets; i++) 2250 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2251 i, urb->iso_frame_desc[i].status); 2252 } 2253 2254 urb->status = status; 2255 if (!status) { 2256 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2257 urb->actual_length < urb->transfer_buffer_length) 2258 urb->status = -EREMOTEIO; 2259 } 2260 2261 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2262 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2263 struct usb_host_endpoint *ep = urb->ep; 2264 2265 if (ep) 2266 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2267 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2268 urb); 2269 } 2270 2271 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2272 urb->hcpriv = NULL; 2273 kfree(qtd->urb); 2274 qtd->urb = NULL; 2275 2276 spin_unlock(&hsotg->lock); 2277 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2278 spin_lock(&hsotg->lock); 2279 } 2280 2281 /* 2282 * Work queue function for starting the HCD when A-Cable is connected 2283 */ 2284 static void dwc2_hcd_start_func(struct work_struct *work) 2285 { 2286 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2287 start_work.work); 2288 2289 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2290 dwc2_host_start(hsotg); 2291 } 2292 2293 /* 2294 * Reset work queue function 2295 */ 2296 static void dwc2_hcd_reset_func(struct work_struct *work) 2297 { 2298 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2299 reset_work.work); 2300 u32 hprt0; 2301 2302 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2303 hprt0 = dwc2_read_hprt0(hsotg); 2304 hprt0 &= ~HPRT0_RST; 2305 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2306 hsotg->flags.b.port_reset_change = 1; 2307 } 2308 2309 /* 2310 * ========================================================================= 2311 * Linux HC Driver Functions 2312 * ========================================================================= 2313 */ 2314 2315 /* 2316 * Initializes the DWC_otg controller and its root hub and prepares it for host 2317 * mode operation. Activates the root port. Returns 0 on success and a negative 2318 * error code on failure. 2319 */ 2320 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2321 { 2322 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2323 struct usb_bus *bus = hcd_to_bus(hcd); 2324 unsigned long flags; 2325 2326 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2327 2328 spin_lock_irqsave(&hsotg->lock, flags); 2329 hsotg->lx_state = DWC2_L0; 2330 hcd->state = HC_STATE_RUNNING; 2331 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2332 2333 if (dwc2_is_device_mode(hsotg)) { 2334 spin_unlock_irqrestore(&hsotg->lock, flags); 2335 return 0; /* why 0 ?? */ 2336 } 2337 2338 dwc2_hcd_reinit(hsotg); 2339 2340 /* Initialize and connect root hub if one is not already attached */ 2341 if (bus->root_hub) { 2342 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2343 /* Inform the HUB driver to resume */ 2344 usb_hcd_resume_root_hub(hcd); 2345 } 2346 2347 spin_unlock_irqrestore(&hsotg->lock, flags); 2348 return 0; 2349 } 2350 2351 /* 2352 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2353 * stopped. 2354 */ 2355 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2356 { 2357 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2358 unsigned long flags; 2359 2360 /* Turn off all host-specific interrupts */ 2361 dwc2_disable_host_interrupts(hsotg); 2362 2363 /* Wait for interrupt processing to finish */ 2364 synchronize_irq(hcd->irq); 2365 2366 spin_lock_irqsave(&hsotg->lock, flags); 2367 /* Ensure hcd is disconnected */ 2368 dwc2_hcd_disconnect(hsotg); 2369 dwc2_hcd_stop(hsotg); 2370 hsotg->lx_state = DWC2_L3; 2371 hcd->state = HC_STATE_HALT; 2372 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2373 spin_unlock_irqrestore(&hsotg->lock, flags); 2374 2375 usleep_range(1000, 3000); 2376 } 2377 2378 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2379 { 2380 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2381 unsigned long flags; 2382 int ret = 0; 2383 u32 hprt0; 2384 2385 spin_lock_irqsave(&hsotg->lock, flags); 2386 2387 if (hsotg->lx_state != DWC2_L0) 2388 goto unlock; 2389 2390 if (!HCD_HW_ACCESSIBLE(hcd)) 2391 goto unlock; 2392 2393 if (!hsotg->core_params->hibernation) 2394 goto skip_power_saving; 2395 2396 /* 2397 * Drive USB suspend and disable port Power 2398 * if usb bus is not suspended. 2399 */ 2400 if (!hsotg->bus_suspended) { 2401 hprt0 = dwc2_read_hprt0(hsotg); 2402 hprt0 |= HPRT0_SUSP; 2403 hprt0 &= ~HPRT0_PWR; 2404 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2405 } 2406 2407 /* Enter hibernation */ 2408 ret = dwc2_enter_hibernation(hsotg); 2409 if (ret) { 2410 if (ret != -ENOTSUPP) 2411 dev_err(hsotg->dev, 2412 "enter hibernation failed\n"); 2413 goto skip_power_saving; 2414 } 2415 2416 /* Ask phy to be suspended */ 2417 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2418 spin_unlock_irqrestore(&hsotg->lock, flags); 2419 usb_phy_set_suspend(hsotg->uphy, true); 2420 spin_lock_irqsave(&hsotg->lock, flags); 2421 } 2422 2423 /* After entering hibernation, hardware is no more accessible */ 2424 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2425 2426 skip_power_saving: 2427 hsotg->lx_state = DWC2_L2; 2428 unlock: 2429 spin_unlock_irqrestore(&hsotg->lock, flags); 2430 2431 return ret; 2432 } 2433 2434 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2435 { 2436 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2437 unsigned long flags; 2438 int ret = 0; 2439 2440 spin_lock_irqsave(&hsotg->lock, flags); 2441 2442 if (hsotg->lx_state != DWC2_L2) 2443 goto unlock; 2444 2445 if (!hsotg->core_params->hibernation) { 2446 hsotg->lx_state = DWC2_L0; 2447 goto unlock; 2448 } 2449 2450 /* 2451 * Set HW accessible bit before powering on the controller 2452 * since an interrupt may rise. 2453 */ 2454 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2455 2456 /* 2457 * Enable power if not already done. 2458 * This must not be spinlocked since duration 2459 * of this call is unknown. 2460 */ 2461 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2462 spin_unlock_irqrestore(&hsotg->lock, flags); 2463 usb_phy_set_suspend(hsotg->uphy, false); 2464 spin_lock_irqsave(&hsotg->lock, flags); 2465 } 2466 2467 /* Exit hibernation */ 2468 ret = dwc2_exit_hibernation(hsotg, true); 2469 if (ret && (ret != -ENOTSUPP)) 2470 dev_err(hsotg->dev, "exit hibernation failed\n"); 2471 2472 hsotg->lx_state = DWC2_L0; 2473 2474 spin_unlock_irqrestore(&hsotg->lock, flags); 2475 2476 if (hsotg->bus_suspended) { 2477 spin_lock_irqsave(&hsotg->lock, flags); 2478 hsotg->flags.b.port_suspend_change = 1; 2479 spin_unlock_irqrestore(&hsotg->lock, flags); 2480 dwc2_port_resume(hsotg); 2481 } else { 2482 /* Wait for controller to correctly update D+/D- level */ 2483 usleep_range(3000, 5000); 2484 2485 /* 2486 * Clear Port Enable and Port Status changes. 2487 * Enable Port Power. 2488 */ 2489 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 2490 HPRT0_ENACHG, hsotg->regs + HPRT0); 2491 /* Wait for controller to detect Port Connect */ 2492 usleep_range(5000, 7000); 2493 } 2494 2495 return ret; 2496 unlock: 2497 spin_unlock_irqrestore(&hsotg->lock, flags); 2498 2499 return ret; 2500 } 2501 2502 /* Returns the current frame number */ 2503 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2504 { 2505 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2506 2507 return dwc2_hcd_get_frame_number(hsotg); 2508 } 2509 2510 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2511 char *fn_name) 2512 { 2513 #ifdef VERBOSE_DEBUG 2514 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2515 char *pipetype; 2516 char *speed; 2517 2518 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2519 dev_vdbg(hsotg->dev, " Device address: %d\n", 2520 usb_pipedevice(urb->pipe)); 2521 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2522 usb_pipeendpoint(urb->pipe), 2523 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2524 2525 switch (usb_pipetype(urb->pipe)) { 2526 case PIPE_CONTROL: 2527 pipetype = "CONTROL"; 2528 break; 2529 case PIPE_BULK: 2530 pipetype = "BULK"; 2531 break; 2532 case PIPE_INTERRUPT: 2533 pipetype = "INTERRUPT"; 2534 break; 2535 case PIPE_ISOCHRONOUS: 2536 pipetype = "ISOCHRONOUS"; 2537 break; 2538 default: 2539 pipetype = "UNKNOWN"; 2540 break; 2541 } 2542 2543 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2544 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2545 "IN" : "OUT"); 2546 2547 switch (urb->dev->speed) { 2548 case USB_SPEED_HIGH: 2549 speed = "HIGH"; 2550 break; 2551 case USB_SPEED_FULL: 2552 speed = "FULL"; 2553 break; 2554 case USB_SPEED_LOW: 2555 speed = "LOW"; 2556 break; 2557 default: 2558 speed = "UNKNOWN"; 2559 break; 2560 } 2561 2562 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2563 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2564 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2565 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2566 urb->transfer_buffer_length); 2567 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2568 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2569 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2570 urb->setup_packet, (unsigned long)urb->setup_dma); 2571 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2572 2573 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2574 int i; 2575 2576 for (i = 0; i < urb->number_of_packets; i++) { 2577 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2578 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2579 urb->iso_frame_desc[i].offset, 2580 urb->iso_frame_desc[i].length); 2581 } 2582 } 2583 #endif 2584 } 2585 2586 /* 2587 * Starts processing a USB transfer request specified by a USB Request Block 2588 * (URB). mem_flags indicates the type of memory allocation to use while 2589 * processing this URB. 2590 */ 2591 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2592 gfp_t mem_flags) 2593 { 2594 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2595 struct usb_host_endpoint *ep = urb->ep; 2596 struct dwc2_hcd_urb *dwc2_urb; 2597 int i; 2598 int retval; 2599 int alloc_bandwidth = 0; 2600 u8 ep_type = 0; 2601 u32 tflags = 0; 2602 void *buf; 2603 unsigned long flags; 2604 struct dwc2_qh *qh; 2605 bool qh_allocated = false; 2606 struct dwc2_qtd *qtd; 2607 2608 if (dbg_urb(urb)) { 2609 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2610 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2611 } 2612 2613 if (ep == NULL) 2614 return -EINVAL; 2615 2616 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2617 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2618 spin_lock_irqsave(&hsotg->lock, flags); 2619 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2620 alloc_bandwidth = 1; 2621 spin_unlock_irqrestore(&hsotg->lock, flags); 2622 } 2623 2624 switch (usb_pipetype(urb->pipe)) { 2625 case PIPE_CONTROL: 2626 ep_type = USB_ENDPOINT_XFER_CONTROL; 2627 break; 2628 case PIPE_ISOCHRONOUS: 2629 ep_type = USB_ENDPOINT_XFER_ISOC; 2630 break; 2631 case PIPE_BULK: 2632 ep_type = USB_ENDPOINT_XFER_BULK; 2633 break; 2634 case PIPE_INTERRUPT: 2635 ep_type = USB_ENDPOINT_XFER_INT; 2636 break; 2637 default: 2638 dev_warn(hsotg->dev, "Wrong ep type\n"); 2639 } 2640 2641 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2642 mem_flags); 2643 if (!dwc2_urb) 2644 return -ENOMEM; 2645 2646 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2647 usb_pipeendpoint(urb->pipe), ep_type, 2648 usb_pipein(urb->pipe), 2649 usb_maxpacket(urb->dev, urb->pipe, 2650 !(usb_pipein(urb->pipe)))); 2651 2652 buf = urb->transfer_buffer; 2653 2654 if (hcd->self.uses_dma) { 2655 if (!buf && (urb->transfer_dma & 3)) { 2656 dev_err(hsotg->dev, 2657 "%s: unaligned transfer with no transfer_buffer", 2658 __func__); 2659 retval = -EINVAL; 2660 goto fail0; 2661 } 2662 } 2663 2664 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2665 tflags |= URB_GIVEBACK_ASAP; 2666 if (urb->transfer_flags & URB_ZERO_PACKET) 2667 tflags |= URB_SEND_ZERO_PACKET; 2668 2669 dwc2_urb->priv = urb; 2670 dwc2_urb->buf = buf; 2671 dwc2_urb->dma = urb->transfer_dma; 2672 dwc2_urb->length = urb->transfer_buffer_length; 2673 dwc2_urb->setup_packet = urb->setup_packet; 2674 dwc2_urb->setup_dma = urb->setup_dma; 2675 dwc2_urb->flags = tflags; 2676 dwc2_urb->interval = urb->interval; 2677 dwc2_urb->status = -EINPROGRESS; 2678 2679 for (i = 0; i < urb->number_of_packets; ++i) 2680 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2681 urb->iso_frame_desc[i].offset, 2682 urb->iso_frame_desc[i].length); 2683 2684 urb->hcpriv = dwc2_urb; 2685 qh = (struct dwc2_qh *) ep->hcpriv; 2686 /* Create QH for the endpoint if it doesn't exist */ 2687 if (!qh) { 2688 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2689 if (!qh) { 2690 retval = -ENOMEM; 2691 goto fail0; 2692 } 2693 ep->hcpriv = qh; 2694 qh_allocated = true; 2695 } 2696 2697 qtd = kzalloc(sizeof(*qtd), mem_flags); 2698 if (!qtd) { 2699 retval = -ENOMEM; 2700 goto fail1; 2701 } 2702 2703 spin_lock_irqsave(&hsotg->lock, flags); 2704 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2705 if (retval) 2706 goto fail2; 2707 2708 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2709 if (retval) 2710 goto fail3; 2711 2712 if (alloc_bandwidth) { 2713 dwc2_allocate_bus_bandwidth(hcd, 2714 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2715 urb); 2716 } 2717 2718 spin_unlock_irqrestore(&hsotg->lock, flags); 2719 2720 return 0; 2721 2722 fail3: 2723 dwc2_urb->priv = NULL; 2724 usb_hcd_unlink_urb_from_ep(hcd, urb); 2725 fail2: 2726 spin_unlock_irqrestore(&hsotg->lock, flags); 2727 urb->hcpriv = NULL; 2728 kfree(qtd); 2729 fail1: 2730 if (qh_allocated) { 2731 struct dwc2_qtd *qtd2, *qtd2_tmp; 2732 2733 ep->hcpriv = NULL; 2734 dwc2_hcd_qh_unlink(hsotg, qh); 2735 /* Free each QTD in the QH's QTD list */ 2736 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2737 qtd_list_entry) 2738 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2739 dwc2_hcd_qh_free(hsotg, qh); 2740 } 2741 fail0: 2742 kfree(dwc2_urb); 2743 2744 return retval; 2745 } 2746 2747 /* 2748 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2749 */ 2750 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2751 int status) 2752 { 2753 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2754 int rc; 2755 unsigned long flags; 2756 2757 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2758 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2759 2760 spin_lock_irqsave(&hsotg->lock, flags); 2761 2762 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2763 if (rc) 2764 goto out; 2765 2766 if (!urb->hcpriv) { 2767 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2768 goto out; 2769 } 2770 2771 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2772 2773 usb_hcd_unlink_urb_from_ep(hcd, urb); 2774 2775 kfree(urb->hcpriv); 2776 urb->hcpriv = NULL; 2777 2778 /* Higher layer software sets URB status */ 2779 spin_unlock(&hsotg->lock); 2780 usb_hcd_giveback_urb(hcd, urb, status); 2781 spin_lock(&hsotg->lock); 2782 2783 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2784 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2785 out: 2786 spin_unlock_irqrestore(&hsotg->lock, flags); 2787 2788 return rc; 2789 } 2790 2791 /* 2792 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2793 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2794 * must already be dequeued. 2795 */ 2796 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2797 struct usb_host_endpoint *ep) 2798 { 2799 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2800 2801 dev_dbg(hsotg->dev, 2802 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2803 ep->desc.bEndpointAddress, ep->hcpriv); 2804 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2805 } 2806 2807 /* 2808 * Resets endpoint specific parameter values, in current version used to reset 2809 * the data toggle (as a WA). This function can be called from usb_clear_halt 2810 * routine. 2811 */ 2812 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2813 struct usb_host_endpoint *ep) 2814 { 2815 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2816 unsigned long flags; 2817 2818 dev_dbg(hsotg->dev, 2819 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2820 ep->desc.bEndpointAddress); 2821 2822 spin_lock_irqsave(&hsotg->lock, flags); 2823 dwc2_hcd_endpoint_reset(hsotg, ep); 2824 spin_unlock_irqrestore(&hsotg->lock, flags); 2825 } 2826 2827 /* 2828 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2829 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2830 * interrupt. 2831 * 2832 * This function is called by the USB core when an interrupt occurs 2833 */ 2834 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2835 { 2836 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2837 2838 return dwc2_handle_hcd_intr(hsotg); 2839 } 2840 2841 /* 2842 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2843 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2844 * is the status change indicator for the single root port. Returns 1 if either 2845 * change indicator is 1, otherwise returns 0. 2846 */ 2847 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2848 { 2849 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2850 2851 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2852 return buf[0] != 0; 2853 } 2854 2855 /* Handles hub class-specific requests */ 2856 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2857 u16 windex, char *buf, u16 wlength) 2858 { 2859 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2860 wvalue, windex, buf, wlength); 2861 return retval; 2862 } 2863 2864 /* Handles hub TT buffer clear completions */ 2865 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2866 struct usb_host_endpoint *ep) 2867 { 2868 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2869 struct dwc2_qh *qh; 2870 unsigned long flags; 2871 2872 qh = ep->hcpriv; 2873 if (!qh) 2874 return; 2875 2876 spin_lock_irqsave(&hsotg->lock, flags); 2877 qh->tt_buffer_dirty = 0; 2878 2879 if (hsotg->flags.b.port_connect_status) 2880 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2881 2882 spin_unlock_irqrestore(&hsotg->lock, flags); 2883 } 2884 2885 static struct hc_driver dwc2_hc_driver = { 2886 .description = "dwc2_hsotg", 2887 .product_desc = "DWC OTG Controller", 2888 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2889 2890 .irq = _dwc2_hcd_irq, 2891 .flags = HCD_MEMORY | HCD_USB2, 2892 2893 .start = _dwc2_hcd_start, 2894 .stop = _dwc2_hcd_stop, 2895 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2896 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2897 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2898 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2899 .get_frame_number = _dwc2_hcd_get_frame_number, 2900 2901 .hub_status_data = _dwc2_hcd_hub_status_data, 2902 .hub_control = _dwc2_hcd_hub_control, 2903 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2904 2905 .bus_suspend = _dwc2_hcd_suspend, 2906 .bus_resume = _dwc2_hcd_resume, 2907 }; 2908 2909 /* 2910 * Frees secondary storage associated with the dwc2_hsotg structure contained 2911 * in the struct usb_hcd field 2912 */ 2913 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2914 { 2915 u32 ahbcfg; 2916 u32 dctl; 2917 int i; 2918 2919 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2920 2921 /* Free memory for QH/QTD lists */ 2922 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2923 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2924 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2925 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2926 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2927 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2928 2929 /* Free memory for the host channels */ 2930 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2931 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2932 2933 if (chan != NULL) { 2934 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2935 i, chan); 2936 hsotg->hc_ptr_array[i] = NULL; 2937 kfree(chan); 2938 } 2939 } 2940 2941 if (hsotg->core_params->dma_enable > 0) { 2942 if (hsotg->status_buf) { 2943 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2944 hsotg->status_buf, 2945 hsotg->status_buf_dma); 2946 hsotg->status_buf = NULL; 2947 } 2948 } else { 2949 kfree(hsotg->status_buf); 2950 hsotg->status_buf = NULL; 2951 } 2952 2953 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 2954 2955 /* Disable all interrupts */ 2956 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2957 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 2958 dwc2_writel(0, hsotg->regs + GINTMSK); 2959 2960 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2961 dctl = dwc2_readl(hsotg->regs + DCTL); 2962 dctl |= DCTL_SFTDISCON; 2963 dwc2_writel(dctl, hsotg->regs + DCTL); 2964 } 2965 2966 if (hsotg->wq_otg) { 2967 if (!cancel_work_sync(&hsotg->wf_otg)) 2968 flush_workqueue(hsotg->wq_otg); 2969 destroy_workqueue(hsotg->wq_otg); 2970 } 2971 2972 del_timer(&hsotg->wkp_timer); 2973 } 2974 2975 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2976 { 2977 /* Turn off all host-specific interrupts */ 2978 dwc2_disable_host_interrupts(hsotg); 2979 2980 dwc2_hcd_free(hsotg); 2981 } 2982 2983 /* 2984 * Initializes the HCD. This function allocates memory for and initializes the 2985 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2986 * USB bus with the core and calls the hc_driver->start() function. It returns 2987 * a negative error on failure. 2988 */ 2989 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 2990 { 2991 struct usb_hcd *hcd; 2992 struct dwc2_host_chan *channel; 2993 u32 hcfg; 2994 int i, num_channels; 2995 int retval; 2996 2997 if (usb_disabled()) 2998 return -ENODEV; 2999 3000 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 3001 3002 retval = -ENOMEM; 3003 3004 hcfg = dwc2_readl(hsotg->regs + HCFG); 3005 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 3006 3007 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3008 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 3009 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3010 if (!hsotg->frame_num_array) 3011 goto error1; 3012 hsotg->last_frame_num_array = kzalloc( 3013 sizeof(*hsotg->last_frame_num_array) * 3014 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3015 if (!hsotg->last_frame_num_array) 3016 goto error1; 3017 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 3018 #endif 3019 3020 /* Check if the bus driver or platform code has setup a dma_mask */ 3021 if (hsotg->core_params->dma_enable > 0 && 3022 hsotg->dev->dma_mask == NULL) { 3023 dev_warn(hsotg->dev, 3024 "dma_mask not set, disabling DMA\n"); 3025 hsotg->core_params->dma_enable = 0; 3026 hsotg->core_params->dma_desc_enable = 0; 3027 } 3028 3029 /* Set device flags indicating whether the HCD supports DMA */ 3030 if (hsotg->core_params->dma_enable > 0) { 3031 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3032 dev_warn(hsotg->dev, "can't set DMA mask\n"); 3033 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3034 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 3035 } 3036 3037 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 3038 if (!hcd) 3039 goto error1; 3040 3041 if (hsotg->core_params->dma_enable <= 0) 3042 hcd->self.uses_dma = 0; 3043 3044 hcd->has_tt = 1; 3045 3046 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 3047 hsotg->priv = hcd; 3048 3049 /* 3050 * Disable the global interrupt until all the interrupt handlers are 3051 * installed 3052 */ 3053 dwc2_disable_global_interrupts(hsotg); 3054 3055 /* Initialize the DWC_otg core, and select the Phy type */ 3056 retval = dwc2_core_init(hsotg, true, irq); 3057 if (retval) 3058 goto error2; 3059 3060 /* Create new workqueue and init work */ 3061 retval = -ENOMEM; 3062 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 3063 if (!hsotg->wq_otg) { 3064 dev_err(hsotg->dev, "Failed to create workqueue\n"); 3065 goto error2; 3066 } 3067 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 3068 3069 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 3070 (unsigned long)hsotg); 3071 3072 /* Initialize the non-periodic schedule */ 3073 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 3074 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 3075 3076 /* Initialize the periodic schedule */ 3077 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 3078 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 3079 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 3080 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 3081 3082 /* 3083 * Create a host channel descriptor for each host channel implemented 3084 * in the controller. Initialize the channel descriptor array. 3085 */ 3086 INIT_LIST_HEAD(&hsotg->free_hc_list); 3087 num_channels = hsotg->core_params->host_channels; 3088 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 3089 3090 for (i = 0; i < num_channels; i++) { 3091 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 3092 if (channel == NULL) 3093 goto error3; 3094 channel->hc_num = i; 3095 hsotg->hc_ptr_array[i] = channel; 3096 } 3097 3098 if (hsotg->core_params->uframe_sched > 0) 3099 dwc2_hcd_init_usecs(hsotg); 3100 3101 /* Initialize hsotg start work */ 3102 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 3103 3104 /* Initialize port reset work */ 3105 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 3106 3107 /* 3108 * Allocate space for storing data on status transactions. Normally no 3109 * data is sent, but this space acts as a bit bucket. This must be 3110 * done after usb_add_hcd since that function allocates the DMA buffer 3111 * pool. 3112 */ 3113 if (hsotg->core_params->dma_enable > 0) 3114 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 3115 DWC2_HCD_STATUS_BUF_SIZE, 3116 &hsotg->status_buf_dma, GFP_KERNEL); 3117 else 3118 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 3119 GFP_KERNEL); 3120 3121 if (!hsotg->status_buf) 3122 goto error3; 3123 3124 hsotg->otg_port = 1; 3125 hsotg->frame_list = NULL; 3126 hsotg->frame_list_dma = 0; 3127 hsotg->periodic_qh_count = 0; 3128 3129 /* Initiate lx_state to L3 disconnected state */ 3130 hsotg->lx_state = DWC2_L3; 3131 3132 hcd->self.otg_port = hsotg->otg_port; 3133 3134 /* Don't support SG list at this point */ 3135 hcd->self.sg_tablesize = 0; 3136 3137 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3138 otg_set_host(hsotg->uphy->otg, &hcd->self); 3139 3140 /* 3141 * Finish generic HCD initialization and start the HCD. This function 3142 * allocates the DMA buffer pool, registers the USB bus, requests the 3143 * IRQ line, and calls hcd_start method. 3144 */ 3145 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3146 if (retval < 0) 3147 goto error3; 3148 3149 device_wakeup_enable(hcd->self.controller); 3150 3151 dwc2_hcd_dump_state(hsotg); 3152 3153 dwc2_enable_global_interrupts(hsotg); 3154 3155 return 0; 3156 3157 error3: 3158 dwc2_hcd_release(hsotg); 3159 error2: 3160 usb_put_hcd(hcd); 3161 error1: 3162 kfree(hsotg->core_params); 3163 3164 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3165 kfree(hsotg->last_frame_num_array); 3166 kfree(hsotg->frame_num_array); 3167 #endif 3168 3169 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3170 return retval; 3171 } 3172 3173 /* 3174 * Removes the HCD. 3175 * Frees memory and resources associated with the HCD and deregisters the bus. 3176 */ 3177 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3178 { 3179 struct usb_hcd *hcd; 3180 3181 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3182 3183 hcd = dwc2_hsotg_to_hcd(hsotg); 3184 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3185 3186 if (!hcd) { 3187 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3188 __func__); 3189 return; 3190 } 3191 3192 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3193 otg_set_host(hsotg->uphy->otg, NULL); 3194 3195 usb_remove_hcd(hcd); 3196 hsotg->priv = NULL; 3197 dwc2_hcd_release(hsotg); 3198 usb_put_hcd(hcd); 3199 3200 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3201 kfree(hsotg->last_frame_num_array); 3202 kfree(hsotg->frame_num_array); 3203 #endif 3204 } 3205