1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173 } 174 175 /* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184 { 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191 } 192 193 /** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199 { 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 dwc2_writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215 } 216 217 /* Must be called with interrupt disabled and spinlock held */ 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219 { 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260 /* All channels have been freed, mark them available */ 261 if (hsotg->core_params->uframe_sched > 0) { 262 hsotg->available_host_channels = 263 hsotg->core_params->host_channels; 264 } else { 265 hsotg->non_periodic_channels = 0; 266 hsotg->periodic_channels = 0; 267 } 268 } 269 270 /** 271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 272 * 273 * @hsotg: Pointer to struct dwc2_hsotg 274 * 275 * Must be called with interrupt disabled and spinlock held 276 */ 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 278 { 279 u32 intr; 280 281 /* Set status flags for the hub driver */ 282 hsotg->flags.b.port_connect_status_change = 1; 283 hsotg->flags.b.port_connect_status = 0; 284 285 /* 286 * Shutdown any transfers in process by clearing the Tx FIFO Empty 287 * interrupt mask and status bits and disabling subsequent host 288 * channel interrupts. 289 */ 290 intr = dwc2_readl(hsotg->regs + GINTMSK); 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 292 dwc2_writel(intr, hsotg->regs + GINTMSK); 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 294 dwc2_writel(intr, hsotg->regs + GINTSTS); 295 296 /* 297 * Turn off the vbus power only if the core has transitioned to device 298 * mode. If still in host mode, need to keep power on to detect a 299 * reconnection. 300 */ 301 if (dwc2_is_device_mode(hsotg)) { 302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 304 dwc2_writel(0, hsotg->regs + HPRT0); 305 } 306 307 dwc2_disable_host_interrupts(hsotg); 308 } 309 310 /* Respond with an error status to all URBs in the schedule */ 311 dwc2_kill_all_urbs(hsotg); 312 313 if (dwc2_is_host_mode(hsotg)) 314 /* Clean up any host channels that were in use */ 315 dwc2_hcd_cleanup_channels(hsotg); 316 317 dwc2_host_disconnect(hsotg); 318 } 319 320 /** 321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 322 * 323 * @hsotg: Pointer to struct dwc2_hsotg 324 */ 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 326 { 327 if (hsotg->bus_suspended) { 328 hsotg->flags.b.port_suspend_change = 1; 329 usb_hcd_resume_root_hub(hsotg->priv); 330 } 331 332 if (hsotg->lx_state == DWC2_L1) 333 hsotg->flags.b.port_l1_change = 1; 334 } 335 336 /** 337 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 338 * 339 * @hsotg: Pointer to struct dwc2_hsotg 340 * 341 * Must be called with interrupt disabled and spinlock held 342 */ 343 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 344 { 345 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 346 347 /* 348 * The root hub should be disconnected before this function is called. 349 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 350 * and the QH lists (via ..._hcd_endpoint_disable). 351 */ 352 353 /* Turn off all host-specific interrupts */ 354 dwc2_disable_host_interrupts(hsotg); 355 356 /* Turn off the vbus power */ 357 dev_dbg(hsotg->dev, "PortPower off\n"); 358 dwc2_writel(0, hsotg->regs + HPRT0); 359 } 360 361 /* Caller must hold driver lock */ 362 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 363 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 364 struct dwc2_qtd *qtd) 365 { 366 u32 intr_mask; 367 int retval; 368 int dev_speed; 369 370 if (!hsotg->flags.b.port_connect_status) { 371 /* No longer connected */ 372 dev_err(hsotg->dev, "Not connected\n"); 373 return -ENODEV; 374 } 375 376 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 377 378 /* Some configurations cannot support LS traffic on a FS root port */ 379 if ((dev_speed == USB_SPEED_LOW) && 380 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 381 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 382 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 383 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 384 385 if (prtspd == HPRT0_SPD_FULL_SPEED) 386 return -ENODEV; 387 } 388 389 if (!qtd) 390 return -EINVAL; 391 392 dwc2_hcd_qtd_init(qtd, urb); 393 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 394 if (retval) { 395 dev_err(hsotg->dev, 396 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 397 retval); 398 return retval; 399 } 400 401 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 402 if (!(intr_mask & GINTSTS_SOF)) { 403 enum dwc2_transaction_type tr_type; 404 405 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 406 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 407 /* 408 * Do not schedule SG transactions until qtd has 409 * URB_GIVEBACK_ASAP set 410 */ 411 return 0; 412 413 tr_type = dwc2_hcd_select_transactions(hsotg); 414 if (tr_type != DWC2_TRANSACTION_NONE) 415 dwc2_hcd_queue_transactions(hsotg, tr_type); 416 } 417 418 return 0; 419 } 420 421 /* Must be called with interrupt disabled and spinlock held */ 422 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 423 struct dwc2_hcd_urb *urb) 424 { 425 struct dwc2_qh *qh; 426 struct dwc2_qtd *urb_qtd; 427 428 urb_qtd = urb->qtd; 429 if (!urb_qtd) { 430 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 431 return -EINVAL; 432 } 433 434 qh = urb_qtd->qh; 435 if (!qh) { 436 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 437 return -EINVAL; 438 } 439 440 urb->priv = NULL; 441 442 if (urb_qtd->in_process && qh->channel) { 443 dwc2_dump_channel_info(hsotg, qh->channel); 444 445 /* The QTD is in process (it has been assigned to a channel) */ 446 if (hsotg->flags.b.port_connect_status) 447 /* 448 * If still connected (i.e. in host mode), halt the 449 * channel so it can be used for other transfers. If 450 * no longer connected, the host registers can't be 451 * written to halt the channel since the core is in 452 * device mode. 453 */ 454 dwc2_hc_halt(hsotg, qh->channel, 455 DWC2_HC_XFER_URB_DEQUEUE); 456 } 457 458 /* 459 * Free the QTD and clean up the associated QH. Leave the QH in the 460 * schedule if it has any remaining QTDs. 461 */ 462 if (hsotg->core_params->dma_desc_enable <= 0) { 463 u8 in_process = urb_qtd->in_process; 464 465 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 466 if (in_process) { 467 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 468 qh->channel = NULL; 469 } else if (list_empty(&qh->qtd_list)) { 470 dwc2_hcd_qh_unlink(hsotg, qh); 471 } 472 } else { 473 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 474 } 475 476 return 0; 477 } 478 479 /* Must NOT be called with interrupt disabled or spinlock held */ 480 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 481 struct usb_host_endpoint *ep, int retry) 482 { 483 struct dwc2_qtd *qtd, *qtd_tmp; 484 struct dwc2_qh *qh; 485 unsigned long flags; 486 int rc; 487 488 spin_lock_irqsave(&hsotg->lock, flags); 489 490 qh = ep->hcpriv; 491 if (!qh) { 492 rc = -EINVAL; 493 goto err; 494 } 495 496 while (!list_empty(&qh->qtd_list) && retry--) { 497 if (retry == 0) { 498 dev_err(hsotg->dev, 499 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 500 rc = -EBUSY; 501 goto err; 502 } 503 504 spin_unlock_irqrestore(&hsotg->lock, flags); 505 usleep_range(20000, 40000); 506 spin_lock_irqsave(&hsotg->lock, flags); 507 qh = ep->hcpriv; 508 if (!qh) { 509 rc = -EINVAL; 510 goto err; 511 } 512 } 513 514 dwc2_hcd_qh_unlink(hsotg, qh); 515 516 /* Free each QTD in the QH's QTD list */ 517 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 518 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 519 520 ep->hcpriv = NULL; 521 spin_unlock_irqrestore(&hsotg->lock, flags); 522 dwc2_hcd_qh_free(hsotg, qh); 523 524 return 0; 525 526 err: 527 ep->hcpriv = NULL; 528 spin_unlock_irqrestore(&hsotg->lock, flags); 529 530 return rc; 531 } 532 533 /* Must be called with interrupt disabled and spinlock held */ 534 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 535 struct usb_host_endpoint *ep) 536 { 537 struct dwc2_qh *qh = ep->hcpriv; 538 539 if (!qh) 540 return -EINVAL; 541 542 qh->data_toggle = DWC2_HC_PID_DATA0; 543 544 return 0; 545 } 546 547 /* 548 * Initializes dynamic portions of the DWC_otg HCD state 549 * 550 * Must be called with interrupt disabled and spinlock held 551 */ 552 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 553 { 554 struct dwc2_host_chan *chan, *chan_tmp; 555 int num_channels; 556 int i; 557 558 hsotg->flags.d32 = 0; 559 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 560 561 if (hsotg->core_params->uframe_sched > 0) { 562 hsotg->available_host_channels = 563 hsotg->core_params->host_channels; 564 } else { 565 hsotg->non_periodic_channels = 0; 566 hsotg->periodic_channels = 0; 567 } 568 569 /* 570 * Put all channels in the free channel list and clean up channel 571 * states 572 */ 573 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 574 hc_list_entry) 575 list_del_init(&chan->hc_list_entry); 576 577 num_channels = hsotg->core_params->host_channels; 578 for (i = 0; i < num_channels; i++) { 579 chan = hsotg->hc_ptr_array[i]; 580 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 581 dwc2_hc_cleanup(hsotg, chan); 582 } 583 584 /* Initialize the DWC core for host mode operation */ 585 dwc2_core_host_init(hsotg); 586 } 587 588 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 589 struct dwc2_host_chan *chan, 590 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 591 { 592 int hub_addr, hub_port; 593 594 chan->do_split = 1; 595 chan->xact_pos = qtd->isoc_split_pos; 596 chan->complete_split = qtd->complete_split; 597 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 598 chan->hub_addr = (u8)hub_addr; 599 chan->hub_port = (u8)hub_port; 600 } 601 602 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 603 struct dwc2_host_chan *chan, 604 struct dwc2_qtd *qtd, void *bufptr) 605 { 606 struct dwc2_hcd_urb *urb = qtd->urb; 607 struct dwc2_hcd_iso_packet_desc *frame_desc; 608 609 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 610 case USB_ENDPOINT_XFER_CONTROL: 611 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 612 613 switch (qtd->control_phase) { 614 case DWC2_CONTROL_SETUP: 615 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 616 chan->do_ping = 0; 617 chan->ep_is_in = 0; 618 chan->data_pid_start = DWC2_HC_PID_SETUP; 619 if (hsotg->core_params->dma_enable > 0) 620 chan->xfer_dma = urb->setup_dma; 621 else 622 chan->xfer_buf = urb->setup_packet; 623 chan->xfer_len = 8; 624 bufptr = NULL; 625 break; 626 627 case DWC2_CONTROL_DATA: 628 dev_vdbg(hsotg->dev, " Control data transaction\n"); 629 chan->data_pid_start = qtd->data_toggle; 630 break; 631 632 case DWC2_CONTROL_STATUS: 633 /* 634 * Direction is opposite of data direction or IN if no 635 * data 636 */ 637 dev_vdbg(hsotg->dev, " Control status transaction\n"); 638 if (urb->length == 0) 639 chan->ep_is_in = 1; 640 else 641 chan->ep_is_in = 642 dwc2_hcd_is_pipe_out(&urb->pipe_info); 643 if (chan->ep_is_in) 644 chan->do_ping = 0; 645 chan->data_pid_start = DWC2_HC_PID_DATA1; 646 chan->xfer_len = 0; 647 if (hsotg->core_params->dma_enable > 0) 648 chan->xfer_dma = hsotg->status_buf_dma; 649 else 650 chan->xfer_buf = hsotg->status_buf; 651 bufptr = NULL; 652 break; 653 } 654 break; 655 656 case USB_ENDPOINT_XFER_BULK: 657 chan->ep_type = USB_ENDPOINT_XFER_BULK; 658 break; 659 660 case USB_ENDPOINT_XFER_INT: 661 chan->ep_type = USB_ENDPOINT_XFER_INT; 662 break; 663 664 case USB_ENDPOINT_XFER_ISOC: 665 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 666 if (hsotg->core_params->dma_desc_enable > 0) 667 break; 668 669 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 670 frame_desc->status = 0; 671 672 if (hsotg->core_params->dma_enable > 0) { 673 chan->xfer_dma = urb->dma; 674 chan->xfer_dma += frame_desc->offset + 675 qtd->isoc_split_offset; 676 } else { 677 chan->xfer_buf = urb->buf; 678 chan->xfer_buf += frame_desc->offset + 679 qtd->isoc_split_offset; 680 } 681 682 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 683 684 /* For non-dword aligned buffers */ 685 if (hsotg->core_params->dma_enable > 0 && 686 (chan->xfer_dma & 0x3)) 687 bufptr = (u8 *)urb->buf + frame_desc->offset + 688 qtd->isoc_split_offset; 689 else 690 bufptr = NULL; 691 692 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 693 if (chan->xfer_len <= 188) 694 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 695 else 696 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 697 } 698 break; 699 } 700 701 return bufptr; 702 } 703 704 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 705 struct dwc2_host_chan *chan, 706 struct dwc2_hcd_urb *urb, void *bufptr) 707 { 708 u32 buf_size; 709 struct urb *usb_urb; 710 struct usb_hcd *hcd; 711 712 if (!qh->dw_align_buf) { 713 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 714 buf_size = hsotg->core_params->max_transfer_size; 715 else 716 /* 3072 = 3 max-size Isoc packets */ 717 buf_size = 3072; 718 719 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA); 720 if (!qh->dw_align_buf) 721 return -ENOMEM; 722 qh->dw_align_buf_size = buf_size; 723 } 724 725 if (chan->xfer_len) { 726 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 727 usb_urb = urb->priv; 728 729 if (usb_urb) { 730 if (usb_urb->transfer_flags & 731 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 732 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 733 hcd = dwc2_hsotg_to_hcd(hsotg); 734 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 735 } 736 if (!chan->ep_is_in) 737 memcpy(qh->dw_align_buf, bufptr, 738 chan->xfer_len); 739 } else { 740 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 741 } 742 } 743 744 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, 745 qh->dw_align_buf, qh->dw_align_buf_size, 746 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 747 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 748 dev_err(hsotg->dev, "can't map align_buf\n"); 749 chan->align_buf = 0; 750 return -EINVAL; 751 } 752 753 chan->align_buf = qh->dw_align_buf_dma; 754 return 0; 755 } 756 757 /** 758 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 759 * channel and initializes the host channel to perform the transactions. The 760 * host channel is removed from the free list. 761 * 762 * @hsotg: The HCD state structure 763 * @qh: Transactions from the first QTD for this QH are selected and assigned 764 * to a free host channel 765 */ 766 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 767 { 768 struct dwc2_host_chan *chan; 769 struct dwc2_hcd_urb *urb; 770 struct dwc2_qtd *qtd; 771 void *bufptr = NULL; 772 773 if (dbg_qh(qh)) 774 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 775 776 if (list_empty(&qh->qtd_list)) { 777 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 778 return -ENOMEM; 779 } 780 781 if (list_empty(&hsotg->free_hc_list)) { 782 dev_dbg(hsotg->dev, "No free channel to assign\n"); 783 return -ENOMEM; 784 } 785 786 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 787 hc_list_entry); 788 789 /* Remove host channel from free list */ 790 list_del_init(&chan->hc_list_entry); 791 792 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 793 urb = qtd->urb; 794 qh->channel = chan; 795 qtd->in_process = 1; 796 797 /* 798 * Use usb_pipedevice to determine device address. This address is 799 * 0 before the SET_ADDRESS command and the correct address afterward. 800 */ 801 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 802 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 803 chan->speed = qh->dev_speed; 804 chan->max_packet = dwc2_max_packet(qh->maxp); 805 806 chan->xfer_started = 0; 807 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 808 chan->error_state = (qtd->error_count > 0); 809 chan->halt_on_queue = 0; 810 chan->halt_pending = 0; 811 chan->requests = 0; 812 813 /* 814 * The following values may be modified in the transfer type section 815 * below. The xfer_len value may be reduced when the transfer is 816 * started to accommodate the max widths of the XferSize and PktCnt 817 * fields in the HCTSIZn register. 818 */ 819 820 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 821 if (chan->ep_is_in) 822 chan->do_ping = 0; 823 else 824 chan->do_ping = qh->ping_state; 825 826 chan->data_pid_start = qh->data_toggle; 827 chan->multi_count = 1; 828 829 if (urb->actual_length > urb->length && 830 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 831 urb->actual_length = urb->length; 832 833 if (hsotg->core_params->dma_enable > 0) { 834 chan->xfer_dma = urb->dma + urb->actual_length; 835 836 /* For non-dword aligned case */ 837 if (hsotg->core_params->dma_desc_enable <= 0 && 838 (chan->xfer_dma & 0x3)) 839 bufptr = (u8 *)urb->buf + urb->actual_length; 840 } else { 841 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 842 } 843 844 chan->xfer_len = urb->length - urb->actual_length; 845 chan->xfer_count = 0; 846 847 /* Set the split attributes if required */ 848 if (qh->do_split) 849 dwc2_hc_init_split(hsotg, chan, qtd, urb); 850 else 851 chan->do_split = 0; 852 853 /* Set the transfer attributes */ 854 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 855 856 /* Non DWORD-aligned buffer case */ 857 if (bufptr) { 858 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 859 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 860 dev_err(hsotg->dev, 861 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 862 __func__); 863 /* Add channel back to free list */ 864 chan->align_buf = 0; 865 chan->multi_count = 0; 866 list_add_tail(&chan->hc_list_entry, 867 &hsotg->free_hc_list); 868 qtd->in_process = 0; 869 qh->channel = NULL; 870 return -ENOMEM; 871 } 872 } else { 873 chan->align_buf = 0; 874 } 875 876 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 877 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 878 /* 879 * This value may be modified when the transfer is started 880 * to reflect the actual transfer length 881 */ 882 chan->multi_count = dwc2_hb_mult(qh->maxp); 883 884 if (hsotg->core_params->dma_desc_enable > 0) 885 chan->desc_list_addr = qh->desc_list_dma; 886 887 dwc2_hc_init(hsotg, chan); 888 chan->qh = qh; 889 890 return 0; 891 } 892 893 /** 894 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 895 * schedule and assigns them to available host channels. Called from the HCD 896 * interrupt handler functions. 897 * 898 * @hsotg: The HCD state structure 899 * 900 * Return: The types of new transactions that were assigned to host channels 901 */ 902 enum dwc2_transaction_type dwc2_hcd_select_transactions( 903 struct dwc2_hsotg *hsotg) 904 { 905 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 906 struct list_head *qh_ptr; 907 struct dwc2_qh *qh; 908 int num_channels; 909 910 #ifdef DWC2_DEBUG_SOF 911 dev_vdbg(hsotg->dev, " Select Transactions\n"); 912 #endif 913 914 /* Process entries in the periodic ready list */ 915 qh_ptr = hsotg->periodic_sched_ready.next; 916 while (qh_ptr != &hsotg->periodic_sched_ready) { 917 if (list_empty(&hsotg->free_hc_list)) 918 break; 919 if (hsotg->core_params->uframe_sched > 0) { 920 if (hsotg->available_host_channels <= 1) 921 break; 922 hsotg->available_host_channels--; 923 } 924 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 925 if (dwc2_assign_and_init_hc(hsotg, qh)) 926 break; 927 928 /* 929 * Move the QH from the periodic ready schedule to the 930 * periodic assigned schedule 931 */ 932 qh_ptr = qh_ptr->next; 933 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 934 ret_val = DWC2_TRANSACTION_PERIODIC; 935 } 936 937 /* 938 * Process entries in the inactive portion of the non-periodic 939 * schedule. Some free host channels may not be used if they are 940 * reserved for periodic transfers. 941 */ 942 num_channels = hsotg->core_params->host_channels; 943 qh_ptr = hsotg->non_periodic_sched_inactive.next; 944 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 945 if (hsotg->core_params->uframe_sched <= 0 && 946 hsotg->non_periodic_channels >= num_channels - 947 hsotg->periodic_channels) 948 break; 949 if (list_empty(&hsotg->free_hc_list)) 950 break; 951 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 952 if (hsotg->core_params->uframe_sched > 0) { 953 if (hsotg->available_host_channels < 1) 954 break; 955 hsotg->available_host_channels--; 956 } 957 958 if (dwc2_assign_and_init_hc(hsotg, qh)) 959 break; 960 961 /* 962 * Move the QH from the non-periodic inactive schedule to the 963 * non-periodic active schedule 964 */ 965 qh_ptr = qh_ptr->next; 966 list_move(&qh->qh_list_entry, 967 &hsotg->non_periodic_sched_active); 968 969 if (ret_val == DWC2_TRANSACTION_NONE) 970 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 971 else 972 ret_val = DWC2_TRANSACTION_ALL; 973 974 if (hsotg->core_params->uframe_sched <= 0) 975 hsotg->non_periodic_channels++; 976 } 977 978 return ret_val; 979 } 980 981 /** 982 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 983 * a host channel associated with either a periodic or non-periodic transfer 984 * 985 * @hsotg: The HCD state structure 986 * @chan: Host channel descriptor associated with either a periodic or 987 * non-periodic transfer 988 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 989 * for periodic transfers or the non-periodic Tx FIFO 990 * for non-periodic transfers 991 * 992 * Return: 1 if a request is queued and more requests may be needed to 993 * complete the transfer, 0 if no more requests are required for this 994 * transfer, -1 if there is insufficient space in the Tx FIFO 995 * 996 * This function assumes that there is space available in the appropriate 997 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 998 * it checks whether space is available in the appropriate Tx FIFO. 999 * 1000 * Must be called with interrupt disabled and spinlock held 1001 */ 1002 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1003 struct dwc2_host_chan *chan, 1004 u16 fifo_dwords_avail) 1005 { 1006 int retval = 0; 1007 1008 if (hsotg->core_params->dma_enable > 0) { 1009 if (hsotg->core_params->dma_desc_enable > 0) { 1010 if (!chan->xfer_started || 1011 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1012 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1013 chan->qh->ping_state = 0; 1014 } 1015 } else if (!chan->xfer_started) { 1016 dwc2_hc_start_transfer(hsotg, chan); 1017 chan->qh->ping_state = 0; 1018 } 1019 } else if (chan->halt_pending) { 1020 /* Don't queue a request if the channel has been halted */ 1021 } else if (chan->halt_on_queue) { 1022 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1023 } else if (chan->do_ping) { 1024 if (!chan->xfer_started) 1025 dwc2_hc_start_transfer(hsotg, chan); 1026 } else if (!chan->ep_is_in || 1027 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1028 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1029 if (!chan->xfer_started) { 1030 dwc2_hc_start_transfer(hsotg, chan); 1031 retval = 1; 1032 } else { 1033 retval = dwc2_hc_continue_transfer(hsotg, chan); 1034 } 1035 } else { 1036 retval = -1; 1037 } 1038 } else { 1039 if (!chan->xfer_started) { 1040 dwc2_hc_start_transfer(hsotg, chan); 1041 retval = 1; 1042 } else { 1043 retval = dwc2_hc_continue_transfer(hsotg, chan); 1044 } 1045 } 1046 1047 return retval; 1048 } 1049 1050 /* 1051 * Processes periodic channels for the next frame and queues transactions for 1052 * these channels to the DWC_otg controller. After queueing transactions, the 1053 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1054 * to queue as Periodic Tx FIFO or request queue space becomes available. 1055 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1056 * 1057 * Must be called with interrupt disabled and spinlock held 1058 */ 1059 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1060 { 1061 struct list_head *qh_ptr; 1062 struct dwc2_qh *qh; 1063 u32 tx_status; 1064 u32 fspcavail; 1065 u32 gintmsk; 1066 int status; 1067 int no_queue_space = 0; 1068 int no_fifo_space = 0; 1069 u32 qspcavail; 1070 1071 if (dbg_perio()) 1072 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1073 1074 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1075 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1076 TXSTS_QSPCAVAIL_SHIFT; 1077 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1078 TXSTS_FSPCAVAIL_SHIFT; 1079 1080 if (dbg_perio()) { 1081 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1082 qspcavail); 1083 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1084 fspcavail); 1085 } 1086 1087 qh_ptr = hsotg->periodic_sched_assigned.next; 1088 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1089 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1090 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1091 TXSTS_QSPCAVAIL_SHIFT; 1092 if (qspcavail == 0) { 1093 no_queue_space = 1; 1094 break; 1095 } 1096 1097 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1098 if (!qh->channel) { 1099 qh_ptr = qh_ptr->next; 1100 continue; 1101 } 1102 1103 /* Make sure EP's TT buffer is clean before queueing qtds */ 1104 if (qh->tt_buffer_dirty) { 1105 qh_ptr = qh_ptr->next; 1106 continue; 1107 } 1108 1109 /* 1110 * Set a flag if we're queuing high-bandwidth in slave mode. 1111 * The flag prevents any halts to get into the request queue in 1112 * the middle of multiple high-bandwidth packets getting queued. 1113 */ 1114 if (hsotg->core_params->dma_enable <= 0 && 1115 qh->channel->multi_count > 1) 1116 hsotg->queuing_high_bandwidth = 1; 1117 1118 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1119 TXSTS_FSPCAVAIL_SHIFT; 1120 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1121 if (status < 0) { 1122 no_fifo_space = 1; 1123 break; 1124 } 1125 1126 /* 1127 * In Slave mode, stay on the current transfer until there is 1128 * nothing more to do or the high-bandwidth request count is 1129 * reached. In DMA mode, only need to queue one request. The 1130 * controller automatically handles multiple packets for 1131 * high-bandwidth transfers. 1132 */ 1133 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1134 qh->channel->requests == qh->channel->multi_count) { 1135 qh_ptr = qh_ptr->next; 1136 /* 1137 * Move the QH from the periodic assigned schedule to 1138 * the periodic queued schedule 1139 */ 1140 list_move(&qh->qh_list_entry, 1141 &hsotg->periodic_sched_queued); 1142 1143 /* done queuing high bandwidth */ 1144 hsotg->queuing_high_bandwidth = 0; 1145 } 1146 } 1147 1148 if (hsotg->core_params->dma_enable <= 0) { 1149 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1150 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1151 TXSTS_QSPCAVAIL_SHIFT; 1152 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1153 TXSTS_FSPCAVAIL_SHIFT; 1154 if (dbg_perio()) { 1155 dev_vdbg(hsotg->dev, 1156 " P Tx Req Queue Space Avail (after queue): %d\n", 1157 qspcavail); 1158 dev_vdbg(hsotg->dev, 1159 " P Tx FIFO Space Avail (after queue): %d\n", 1160 fspcavail); 1161 } 1162 1163 if (!list_empty(&hsotg->periodic_sched_assigned) || 1164 no_queue_space || no_fifo_space) { 1165 /* 1166 * May need to queue more transactions as the request 1167 * queue or Tx FIFO empties. Enable the periodic Tx 1168 * FIFO empty interrupt. (Always use the half-empty 1169 * level to ensure that new requests are loaded as 1170 * soon as possible.) 1171 */ 1172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1173 gintmsk |= GINTSTS_PTXFEMP; 1174 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1175 } else { 1176 /* 1177 * Disable the Tx FIFO empty interrupt since there are 1178 * no more transactions that need to be queued right 1179 * now. This function is called from interrupt 1180 * handlers to queue more transactions as transfer 1181 * states change. 1182 */ 1183 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1184 gintmsk &= ~GINTSTS_PTXFEMP; 1185 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1186 } 1187 } 1188 } 1189 1190 /* 1191 * Processes active non-periodic channels and queues transactions for these 1192 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1193 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1194 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1195 * FIFO Empty interrupt is disabled. 1196 * 1197 * Must be called with interrupt disabled and spinlock held 1198 */ 1199 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1200 { 1201 struct list_head *orig_qh_ptr; 1202 struct dwc2_qh *qh; 1203 u32 tx_status; 1204 u32 qspcavail; 1205 u32 fspcavail; 1206 u32 gintmsk; 1207 int status; 1208 int no_queue_space = 0; 1209 int no_fifo_space = 0; 1210 int more_to_do = 0; 1211 1212 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1213 1214 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1215 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1216 TXSTS_QSPCAVAIL_SHIFT; 1217 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1218 TXSTS_FSPCAVAIL_SHIFT; 1219 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1220 qspcavail); 1221 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1222 fspcavail); 1223 1224 /* 1225 * Keep track of the starting point. Skip over the start-of-list 1226 * entry. 1227 */ 1228 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1229 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1230 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1231 1232 /* 1233 * Process once through the active list or until no more space is 1234 * available in the request queue or the Tx FIFO 1235 */ 1236 do { 1237 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1238 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1239 TXSTS_QSPCAVAIL_SHIFT; 1240 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1241 no_queue_space = 1; 1242 break; 1243 } 1244 1245 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1246 qh_list_entry); 1247 if (!qh->channel) 1248 goto next; 1249 1250 /* Make sure EP's TT buffer is clean before queueing qtds */ 1251 if (qh->tt_buffer_dirty) 1252 goto next; 1253 1254 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1255 TXSTS_FSPCAVAIL_SHIFT; 1256 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1257 1258 if (status > 0) { 1259 more_to_do = 1; 1260 } else if (status < 0) { 1261 no_fifo_space = 1; 1262 break; 1263 } 1264 next: 1265 /* Advance to next QH, skipping start-of-list entry */ 1266 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1267 if (hsotg->non_periodic_qh_ptr == 1268 &hsotg->non_periodic_sched_active) 1269 hsotg->non_periodic_qh_ptr = 1270 hsotg->non_periodic_qh_ptr->next; 1271 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1272 1273 if (hsotg->core_params->dma_enable <= 0) { 1274 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1275 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1276 TXSTS_QSPCAVAIL_SHIFT; 1277 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1278 TXSTS_FSPCAVAIL_SHIFT; 1279 dev_vdbg(hsotg->dev, 1280 " NP Tx Req Queue Space Avail (after queue): %d\n", 1281 qspcavail); 1282 dev_vdbg(hsotg->dev, 1283 " NP Tx FIFO Space Avail (after queue): %d\n", 1284 fspcavail); 1285 1286 if (more_to_do || no_queue_space || no_fifo_space) { 1287 /* 1288 * May need to queue more transactions as the request 1289 * queue or Tx FIFO empties. Enable the non-periodic 1290 * Tx FIFO empty interrupt. (Always use the half-empty 1291 * level to ensure that new requests are loaded as 1292 * soon as possible.) 1293 */ 1294 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1295 gintmsk |= GINTSTS_NPTXFEMP; 1296 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1297 } else { 1298 /* 1299 * Disable the Tx FIFO empty interrupt since there are 1300 * no more transactions that need to be queued right 1301 * now. This function is called from interrupt 1302 * handlers to queue more transactions as transfer 1303 * states change. 1304 */ 1305 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1306 gintmsk &= ~GINTSTS_NPTXFEMP; 1307 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1308 } 1309 } 1310 } 1311 1312 /** 1313 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1314 * and queues transactions for these channels to the DWC_otg controller. Called 1315 * from the HCD interrupt handler functions. 1316 * 1317 * @hsotg: The HCD state structure 1318 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1319 * or both) 1320 * 1321 * Must be called with interrupt disabled and spinlock held 1322 */ 1323 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1324 enum dwc2_transaction_type tr_type) 1325 { 1326 #ifdef DWC2_DEBUG_SOF 1327 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1328 #endif 1329 /* Process host channels associated with periodic transfers */ 1330 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1331 tr_type == DWC2_TRANSACTION_ALL) && 1332 !list_empty(&hsotg->periodic_sched_assigned)) 1333 dwc2_process_periodic_channels(hsotg); 1334 1335 /* Process host channels associated with non-periodic transfers */ 1336 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1337 tr_type == DWC2_TRANSACTION_ALL) { 1338 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1339 dwc2_process_non_periodic_channels(hsotg); 1340 } else { 1341 /* 1342 * Ensure NP Tx FIFO empty interrupt is disabled when 1343 * there are no non-periodic transfers to process 1344 */ 1345 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1346 1347 gintmsk &= ~GINTSTS_NPTXFEMP; 1348 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1349 } 1350 } 1351 } 1352 1353 static void dwc2_conn_id_status_change(struct work_struct *work) 1354 { 1355 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1356 wf_otg); 1357 u32 count = 0; 1358 u32 gotgctl; 1359 unsigned long flags; 1360 1361 dev_dbg(hsotg->dev, "%s()\n", __func__); 1362 1363 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1364 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1365 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1366 !!(gotgctl & GOTGCTL_CONID_B)); 1367 1368 /* B-Device connector (Device Mode) */ 1369 if (gotgctl & GOTGCTL_CONID_B) { 1370 /* Wait for switch to device mode */ 1371 dev_dbg(hsotg->dev, "connId B\n"); 1372 while (!dwc2_is_device_mode(hsotg)) { 1373 dev_info(hsotg->dev, 1374 "Waiting for Peripheral Mode, Mode=%s\n", 1375 dwc2_is_host_mode(hsotg) ? "Host" : 1376 "Peripheral"); 1377 usleep_range(20000, 40000); 1378 if (++count > 250) 1379 break; 1380 } 1381 if (count > 250) 1382 dev_err(hsotg->dev, 1383 "Connection id status change timed out\n"); 1384 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1385 dwc2_core_init(hsotg, false, -1); 1386 dwc2_enable_global_interrupts(hsotg); 1387 spin_lock_irqsave(&hsotg->lock, flags); 1388 dwc2_hsotg_core_init_disconnected(hsotg, false); 1389 spin_unlock_irqrestore(&hsotg->lock, flags); 1390 dwc2_hsotg_core_connect(hsotg); 1391 } else { 1392 /* A-Device connector (Host Mode) */ 1393 dev_dbg(hsotg->dev, "connId A\n"); 1394 while (!dwc2_is_host_mode(hsotg)) { 1395 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1396 dwc2_is_host_mode(hsotg) ? 1397 "Host" : "Peripheral"); 1398 usleep_range(20000, 40000); 1399 if (++count > 250) 1400 break; 1401 } 1402 if (count > 250) 1403 dev_err(hsotg->dev, 1404 "Connection id status change timed out\n"); 1405 hsotg->op_state = OTG_STATE_A_HOST; 1406 1407 /* Initialize the Core for Host mode */ 1408 dwc2_core_init(hsotg, false, -1); 1409 dwc2_enable_global_interrupts(hsotg); 1410 dwc2_hcd_start(hsotg); 1411 } 1412 } 1413 1414 static void dwc2_wakeup_detected(unsigned long data) 1415 { 1416 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1417 u32 hprt0; 1418 1419 dev_dbg(hsotg->dev, "%s()\n", __func__); 1420 1421 /* 1422 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1423 * so that OPT tests pass with all PHYs.) 1424 */ 1425 hprt0 = dwc2_read_hprt0(hsotg); 1426 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1427 hprt0 &= ~HPRT0_RES; 1428 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1429 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1430 dwc2_readl(hsotg->regs + HPRT0)); 1431 1432 dwc2_hcd_rem_wakeup(hsotg); 1433 hsotg->bus_suspended = 0; 1434 1435 /* Change to L0 state */ 1436 hsotg->lx_state = DWC2_L0; 1437 } 1438 1439 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1440 { 1441 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1442 1443 return hcd->self.b_hnp_enable; 1444 } 1445 1446 /* Must NOT be called with interrupt disabled or spinlock held */ 1447 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1448 { 1449 unsigned long flags; 1450 u32 hprt0; 1451 u32 pcgctl; 1452 u32 gotgctl; 1453 1454 dev_dbg(hsotg->dev, "%s()\n", __func__); 1455 1456 spin_lock_irqsave(&hsotg->lock, flags); 1457 1458 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1459 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1460 gotgctl |= GOTGCTL_HSTSETHNPEN; 1461 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 1462 hsotg->op_state = OTG_STATE_A_SUSPEND; 1463 } 1464 1465 hprt0 = dwc2_read_hprt0(hsotg); 1466 hprt0 |= HPRT0_SUSP; 1467 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1468 1469 hsotg->bus_suspended = 1; 1470 1471 /* 1472 * If hibernation is supported, Phy clock will be suspended 1473 * after registers are backuped. 1474 */ 1475 if (!hsotg->core_params->hibernation) { 1476 /* Suspend the Phy Clock */ 1477 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1478 pcgctl |= PCGCTL_STOPPCLK; 1479 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1480 udelay(10); 1481 } 1482 1483 /* For HNP the bus must be suspended for at least 200ms */ 1484 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1485 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1486 pcgctl &= ~PCGCTL_STOPPCLK; 1487 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1488 1489 spin_unlock_irqrestore(&hsotg->lock, flags); 1490 1491 usleep_range(200000, 250000); 1492 } else { 1493 spin_unlock_irqrestore(&hsotg->lock, flags); 1494 } 1495 } 1496 1497 /* Must NOT be called with interrupt disabled or spinlock held */ 1498 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1499 { 1500 unsigned long flags; 1501 u32 hprt0; 1502 u32 pcgctl; 1503 1504 spin_lock_irqsave(&hsotg->lock, flags); 1505 1506 /* 1507 * If hibernation is supported, Phy clock is already resumed 1508 * after registers restore. 1509 */ 1510 if (!hsotg->core_params->hibernation) { 1511 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1512 pcgctl &= ~PCGCTL_STOPPCLK; 1513 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1514 spin_unlock_irqrestore(&hsotg->lock, flags); 1515 usleep_range(20000, 40000); 1516 spin_lock_irqsave(&hsotg->lock, flags); 1517 } 1518 1519 hprt0 = dwc2_read_hprt0(hsotg); 1520 hprt0 |= HPRT0_RES; 1521 hprt0 &= ~HPRT0_SUSP; 1522 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1523 spin_unlock_irqrestore(&hsotg->lock, flags); 1524 1525 msleep(USB_RESUME_TIMEOUT); 1526 1527 spin_lock_irqsave(&hsotg->lock, flags); 1528 hprt0 = dwc2_read_hprt0(hsotg); 1529 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1530 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1531 hsotg->bus_suspended = 0; 1532 spin_unlock_irqrestore(&hsotg->lock, flags); 1533 } 1534 1535 /* Handles hub class-specific requests */ 1536 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1537 u16 wvalue, u16 windex, char *buf, u16 wlength) 1538 { 1539 struct usb_hub_descriptor *hub_desc; 1540 int retval = 0; 1541 u32 hprt0; 1542 u32 port_status; 1543 u32 speed; 1544 u32 pcgctl; 1545 1546 switch (typereq) { 1547 case ClearHubFeature: 1548 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1549 1550 switch (wvalue) { 1551 case C_HUB_LOCAL_POWER: 1552 case C_HUB_OVER_CURRENT: 1553 /* Nothing required here */ 1554 break; 1555 1556 default: 1557 retval = -EINVAL; 1558 dev_err(hsotg->dev, 1559 "ClearHubFeature request %1xh unknown\n", 1560 wvalue); 1561 } 1562 break; 1563 1564 case ClearPortFeature: 1565 if (wvalue != USB_PORT_FEAT_L1) 1566 if (!windex || windex > 1) 1567 goto error; 1568 switch (wvalue) { 1569 case USB_PORT_FEAT_ENABLE: 1570 dev_dbg(hsotg->dev, 1571 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1572 hprt0 = dwc2_read_hprt0(hsotg); 1573 hprt0 |= HPRT0_ENA; 1574 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1575 break; 1576 1577 case USB_PORT_FEAT_SUSPEND: 1578 dev_dbg(hsotg->dev, 1579 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1580 1581 if (hsotg->bus_suspended) 1582 dwc2_port_resume(hsotg); 1583 break; 1584 1585 case USB_PORT_FEAT_POWER: 1586 dev_dbg(hsotg->dev, 1587 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1588 hprt0 = dwc2_read_hprt0(hsotg); 1589 hprt0 &= ~HPRT0_PWR; 1590 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1591 break; 1592 1593 case USB_PORT_FEAT_INDICATOR: 1594 dev_dbg(hsotg->dev, 1595 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1596 /* Port indicator not supported */ 1597 break; 1598 1599 case USB_PORT_FEAT_C_CONNECTION: 1600 /* 1601 * Clears driver's internal Connect Status Change flag 1602 */ 1603 dev_dbg(hsotg->dev, 1604 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1605 hsotg->flags.b.port_connect_status_change = 0; 1606 break; 1607 1608 case USB_PORT_FEAT_C_RESET: 1609 /* Clears driver's internal Port Reset Change flag */ 1610 dev_dbg(hsotg->dev, 1611 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1612 hsotg->flags.b.port_reset_change = 0; 1613 break; 1614 1615 case USB_PORT_FEAT_C_ENABLE: 1616 /* 1617 * Clears the driver's internal Port Enable/Disable 1618 * Change flag 1619 */ 1620 dev_dbg(hsotg->dev, 1621 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1622 hsotg->flags.b.port_enable_change = 0; 1623 break; 1624 1625 case USB_PORT_FEAT_C_SUSPEND: 1626 /* 1627 * Clears the driver's internal Port Suspend Change 1628 * flag, which is set when resume signaling on the host 1629 * port is complete 1630 */ 1631 dev_dbg(hsotg->dev, 1632 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1633 hsotg->flags.b.port_suspend_change = 0; 1634 break; 1635 1636 case USB_PORT_FEAT_C_PORT_L1: 1637 dev_dbg(hsotg->dev, 1638 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1639 hsotg->flags.b.port_l1_change = 0; 1640 break; 1641 1642 case USB_PORT_FEAT_C_OVER_CURRENT: 1643 dev_dbg(hsotg->dev, 1644 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1645 hsotg->flags.b.port_over_current_change = 0; 1646 break; 1647 1648 default: 1649 retval = -EINVAL; 1650 dev_err(hsotg->dev, 1651 "ClearPortFeature request %1xh unknown or unsupported\n", 1652 wvalue); 1653 } 1654 break; 1655 1656 case GetHubDescriptor: 1657 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1658 hub_desc = (struct usb_hub_descriptor *)buf; 1659 hub_desc->bDescLength = 9; 1660 hub_desc->bDescriptorType = USB_DT_HUB; 1661 hub_desc->bNbrPorts = 1; 1662 hub_desc->wHubCharacteristics = 1663 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1664 HUB_CHAR_INDV_PORT_OCPM); 1665 hub_desc->bPwrOn2PwrGood = 1; 1666 hub_desc->bHubContrCurrent = 0; 1667 hub_desc->u.hs.DeviceRemovable[0] = 0; 1668 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1669 break; 1670 1671 case GetHubStatus: 1672 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1673 memset(buf, 0, 4); 1674 break; 1675 1676 case GetPortStatus: 1677 dev_vdbg(hsotg->dev, 1678 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1679 hsotg->flags.d32); 1680 if (!windex || windex > 1) 1681 goto error; 1682 1683 port_status = 0; 1684 if (hsotg->flags.b.port_connect_status_change) 1685 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1686 if (hsotg->flags.b.port_enable_change) 1687 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1688 if (hsotg->flags.b.port_suspend_change) 1689 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1690 if (hsotg->flags.b.port_l1_change) 1691 port_status |= USB_PORT_STAT_C_L1 << 16; 1692 if (hsotg->flags.b.port_reset_change) 1693 port_status |= USB_PORT_STAT_C_RESET << 16; 1694 if (hsotg->flags.b.port_over_current_change) { 1695 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1696 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1697 } 1698 1699 if (!hsotg->flags.b.port_connect_status) { 1700 /* 1701 * The port is disconnected, which means the core is 1702 * either in device mode or it soon will be. Just 1703 * return 0's for the remainder of the port status 1704 * since the port register can't be read if the core 1705 * is in device mode. 1706 */ 1707 *(__le32 *)buf = cpu_to_le32(port_status); 1708 break; 1709 } 1710 1711 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1712 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1713 1714 if (hprt0 & HPRT0_CONNSTS) 1715 port_status |= USB_PORT_STAT_CONNECTION; 1716 if (hprt0 & HPRT0_ENA) 1717 port_status |= USB_PORT_STAT_ENABLE; 1718 if (hprt0 & HPRT0_SUSP) 1719 port_status |= USB_PORT_STAT_SUSPEND; 1720 if (hprt0 & HPRT0_OVRCURRACT) 1721 port_status |= USB_PORT_STAT_OVERCURRENT; 1722 if (hprt0 & HPRT0_RST) 1723 port_status |= USB_PORT_STAT_RESET; 1724 if (hprt0 & HPRT0_PWR) 1725 port_status |= USB_PORT_STAT_POWER; 1726 1727 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1728 if (speed == HPRT0_SPD_HIGH_SPEED) 1729 port_status |= USB_PORT_STAT_HIGH_SPEED; 1730 else if (speed == HPRT0_SPD_LOW_SPEED) 1731 port_status |= USB_PORT_STAT_LOW_SPEED; 1732 1733 if (hprt0 & HPRT0_TSTCTL_MASK) 1734 port_status |= USB_PORT_STAT_TEST; 1735 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1736 1737 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1738 *(__le32 *)buf = cpu_to_le32(port_status); 1739 break; 1740 1741 case SetHubFeature: 1742 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1743 /* No HUB features supported */ 1744 break; 1745 1746 case SetPortFeature: 1747 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1748 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1749 goto error; 1750 1751 if (!hsotg->flags.b.port_connect_status) { 1752 /* 1753 * The port is disconnected, which means the core is 1754 * either in device mode or it soon will be. Just 1755 * return without doing anything since the port 1756 * register can't be written if the core is in device 1757 * mode. 1758 */ 1759 break; 1760 } 1761 1762 switch (wvalue) { 1763 case USB_PORT_FEAT_SUSPEND: 1764 dev_dbg(hsotg->dev, 1765 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1766 if (windex != hsotg->otg_port) 1767 goto error; 1768 dwc2_port_suspend(hsotg, windex); 1769 break; 1770 1771 case USB_PORT_FEAT_POWER: 1772 dev_dbg(hsotg->dev, 1773 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1774 hprt0 = dwc2_read_hprt0(hsotg); 1775 hprt0 |= HPRT0_PWR; 1776 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1777 break; 1778 1779 case USB_PORT_FEAT_RESET: 1780 hprt0 = dwc2_read_hprt0(hsotg); 1781 dev_dbg(hsotg->dev, 1782 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1783 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1784 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1785 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1786 /* ??? Original driver does this */ 1787 dwc2_writel(0, hsotg->regs + PCGCTL); 1788 1789 hprt0 = dwc2_read_hprt0(hsotg); 1790 /* Clear suspend bit if resetting from suspend state */ 1791 hprt0 &= ~HPRT0_SUSP; 1792 1793 /* 1794 * When B-Host the Port reset bit is set in the Start 1795 * HCD Callback function, so that the reset is started 1796 * within 1ms of the HNP success interrupt 1797 */ 1798 if (!dwc2_hcd_is_b_host(hsotg)) { 1799 hprt0 |= HPRT0_PWR | HPRT0_RST; 1800 dev_dbg(hsotg->dev, 1801 "In host mode, hprt0=%08x\n", hprt0); 1802 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1803 } 1804 1805 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1806 usleep_range(50000, 70000); 1807 hprt0 &= ~HPRT0_RST; 1808 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1809 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1810 break; 1811 1812 case USB_PORT_FEAT_INDICATOR: 1813 dev_dbg(hsotg->dev, 1814 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1815 /* Not supported */ 1816 break; 1817 1818 case USB_PORT_FEAT_TEST: 1819 hprt0 = dwc2_read_hprt0(hsotg); 1820 dev_dbg(hsotg->dev, 1821 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1822 hprt0 &= ~HPRT0_TSTCTL_MASK; 1823 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1824 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1825 break; 1826 1827 default: 1828 retval = -EINVAL; 1829 dev_err(hsotg->dev, 1830 "SetPortFeature %1xh unknown or unsupported\n", 1831 wvalue); 1832 break; 1833 } 1834 break; 1835 1836 default: 1837 error: 1838 retval = -EINVAL; 1839 dev_dbg(hsotg->dev, 1840 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1841 typereq, windex, wvalue); 1842 break; 1843 } 1844 1845 return retval; 1846 } 1847 1848 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1849 { 1850 int retval; 1851 1852 if (port != 1) 1853 return -EINVAL; 1854 1855 retval = (hsotg->flags.b.port_connect_status_change || 1856 hsotg->flags.b.port_reset_change || 1857 hsotg->flags.b.port_enable_change || 1858 hsotg->flags.b.port_suspend_change || 1859 hsotg->flags.b.port_over_current_change); 1860 1861 if (retval) { 1862 dev_dbg(hsotg->dev, 1863 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1864 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1865 hsotg->flags.b.port_connect_status_change); 1866 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1867 hsotg->flags.b.port_reset_change); 1868 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1869 hsotg->flags.b.port_enable_change); 1870 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1871 hsotg->flags.b.port_suspend_change); 1872 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1873 hsotg->flags.b.port_over_current_change); 1874 } 1875 1876 return retval; 1877 } 1878 1879 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1880 { 1881 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1882 1883 #ifdef DWC2_DEBUG_SOF 1884 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1885 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1886 #endif 1887 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1888 } 1889 1890 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1891 { 1892 return hsotg->op_state == OTG_STATE_B_HOST; 1893 } 1894 1895 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1896 int iso_desc_count, 1897 gfp_t mem_flags) 1898 { 1899 struct dwc2_hcd_urb *urb; 1900 u32 size = sizeof(*urb) + iso_desc_count * 1901 sizeof(struct dwc2_hcd_iso_packet_desc); 1902 1903 urb = kzalloc(size, mem_flags); 1904 if (urb) 1905 urb->packet_count = iso_desc_count; 1906 return urb; 1907 } 1908 1909 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1910 struct dwc2_hcd_urb *urb, u8 dev_addr, 1911 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1912 { 1913 if (dbg_perio() || 1914 ep_type == USB_ENDPOINT_XFER_BULK || 1915 ep_type == USB_ENDPOINT_XFER_CONTROL) 1916 dev_vdbg(hsotg->dev, 1917 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1918 dev_addr, ep_num, ep_dir, ep_type, mps); 1919 urb->pipe_info.dev_addr = dev_addr; 1920 urb->pipe_info.ep_num = ep_num; 1921 urb->pipe_info.pipe_type = ep_type; 1922 urb->pipe_info.pipe_dir = ep_dir; 1923 urb->pipe_info.mps = mps; 1924 } 1925 1926 /* 1927 * NOTE: This function will be removed once the peripheral controller code 1928 * is integrated and the driver is stable 1929 */ 1930 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1931 { 1932 #ifdef DEBUG 1933 struct dwc2_host_chan *chan; 1934 struct dwc2_hcd_urb *urb; 1935 struct dwc2_qtd *qtd; 1936 int num_channels; 1937 u32 np_tx_status; 1938 u32 p_tx_status; 1939 int i; 1940 1941 num_channels = hsotg->core_params->host_channels; 1942 dev_dbg(hsotg->dev, "\n"); 1943 dev_dbg(hsotg->dev, 1944 "************************************************************\n"); 1945 dev_dbg(hsotg->dev, "HCD State:\n"); 1946 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1947 1948 for (i = 0; i < num_channels; i++) { 1949 chan = hsotg->hc_ptr_array[i]; 1950 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1951 dev_dbg(hsotg->dev, 1952 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1953 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1954 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1955 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1956 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1957 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1958 chan->data_pid_start); 1959 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1960 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1961 chan->xfer_started); 1962 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1963 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1964 (unsigned long)chan->xfer_dma); 1965 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1966 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1967 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1968 chan->halt_on_queue); 1969 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1970 chan->halt_pending); 1971 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1972 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1973 dev_dbg(hsotg->dev, " complete_split: %d\n", 1974 chan->complete_split); 1975 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1976 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1977 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1978 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1979 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1980 1981 if (chan->xfer_started) { 1982 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1983 1984 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1985 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1986 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 1987 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 1988 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 1989 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1990 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1991 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1992 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1993 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1994 } 1995 1996 if (!(chan->xfer_started && chan->qh)) 1997 continue; 1998 1999 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2000 if (!qtd->in_process) 2001 break; 2002 urb = qtd->urb; 2003 dev_dbg(hsotg->dev, " URB Info:\n"); 2004 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2005 qtd, urb); 2006 if (urb) { 2007 dev_dbg(hsotg->dev, 2008 " Dev: %d, EP: %d %s\n", 2009 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2010 dwc2_hcd_get_ep_num(&urb->pipe_info), 2011 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2012 "IN" : "OUT"); 2013 dev_dbg(hsotg->dev, 2014 " Max packet size: %d\n", 2015 dwc2_hcd_get_mps(&urb->pipe_info)); 2016 dev_dbg(hsotg->dev, 2017 " transfer_buffer: %p\n", 2018 urb->buf); 2019 dev_dbg(hsotg->dev, 2020 " transfer_dma: %08lx\n", 2021 (unsigned long)urb->dma); 2022 dev_dbg(hsotg->dev, 2023 " transfer_buffer_length: %d\n", 2024 urb->length); 2025 dev_dbg(hsotg->dev, " actual_length: %d\n", 2026 urb->actual_length); 2027 } 2028 } 2029 } 2030 2031 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2032 hsotg->non_periodic_channels); 2033 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2034 hsotg->periodic_channels); 2035 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2036 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 2037 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2038 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2039 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2040 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2041 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2042 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2043 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2044 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2045 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2046 dwc2_hcd_dump_frrem(hsotg); 2047 dwc2_dump_global_registers(hsotg); 2048 dwc2_dump_host_registers(hsotg); 2049 dev_dbg(hsotg->dev, 2050 "************************************************************\n"); 2051 dev_dbg(hsotg->dev, "\n"); 2052 #endif 2053 } 2054 2055 /* 2056 * NOTE: This function will be removed once the peripheral controller code 2057 * is integrated and the driver is stable 2058 */ 2059 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2060 { 2061 #ifdef DWC2_DUMP_FRREM 2062 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2063 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2064 hsotg->frrem_samples, hsotg->frrem_accum, 2065 hsotg->frrem_samples > 0 ? 2066 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2067 dev_dbg(hsotg->dev, "\n"); 2068 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2069 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2070 hsotg->hfnum_7_samples, 2071 hsotg->hfnum_7_frrem_accum, 2072 hsotg->hfnum_7_samples > 0 ? 2073 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2074 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2075 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2076 hsotg->hfnum_0_samples, 2077 hsotg->hfnum_0_frrem_accum, 2078 hsotg->hfnum_0_samples > 0 ? 2079 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2080 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2081 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2082 hsotg->hfnum_other_samples, 2083 hsotg->hfnum_other_frrem_accum, 2084 hsotg->hfnum_other_samples > 0 ? 2085 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2086 0); 2087 dev_dbg(hsotg->dev, "\n"); 2088 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2089 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2090 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2091 hsotg->hfnum_7_samples_a > 0 ? 2092 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2093 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2094 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2095 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2096 hsotg->hfnum_0_samples_a > 0 ? 2097 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2098 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2099 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2100 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2101 hsotg->hfnum_other_samples_a > 0 ? 2102 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2103 : 0); 2104 dev_dbg(hsotg->dev, "\n"); 2105 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2106 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2107 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2108 hsotg->hfnum_7_samples_b > 0 ? 2109 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2110 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2111 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2112 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2113 (hsotg->hfnum_0_samples_b > 0) ? 2114 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2115 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2116 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2117 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2118 (hsotg->hfnum_other_samples_b > 0) ? 2119 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2120 : 0); 2121 #endif 2122 } 2123 2124 struct wrapper_priv_data { 2125 struct dwc2_hsotg *hsotg; 2126 }; 2127 2128 /* Gets the dwc2_hsotg from a usb_hcd */ 2129 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2130 { 2131 struct wrapper_priv_data *p; 2132 2133 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2134 return p->hsotg; 2135 } 2136 2137 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2138 2139 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2140 { 2141 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2142 2143 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2144 _dwc2_hcd_start(hcd); 2145 } 2146 2147 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2148 { 2149 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2150 2151 hcd->self.is_b_host = 0; 2152 } 2153 2154 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2155 int *hub_port) 2156 { 2157 struct urb *urb = context; 2158 2159 if (urb->dev->tt) 2160 *hub_addr = urb->dev->tt->hub->devnum; 2161 else 2162 *hub_addr = 0; 2163 *hub_port = urb->dev->ttport; 2164 } 2165 2166 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2167 { 2168 struct urb *urb = context; 2169 2170 return urb->dev->speed; 2171 } 2172 2173 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2174 struct urb *urb) 2175 { 2176 struct usb_bus *bus = hcd_to_bus(hcd); 2177 2178 if (urb->interval) 2179 bus->bandwidth_allocated += bw / urb->interval; 2180 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2181 bus->bandwidth_isoc_reqs++; 2182 else 2183 bus->bandwidth_int_reqs++; 2184 } 2185 2186 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2187 struct urb *urb) 2188 { 2189 struct usb_bus *bus = hcd_to_bus(hcd); 2190 2191 if (urb->interval) 2192 bus->bandwidth_allocated -= bw / urb->interval; 2193 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2194 bus->bandwidth_isoc_reqs--; 2195 else 2196 bus->bandwidth_int_reqs--; 2197 } 2198 2199 /* 2200 * Sets the final status of an URB and returns it to the upper layer. Any 2201 * required cleanup of the URB is performed. 2202 * 2203 * Must be called with interrupt disabled and spinlock held 2204 */ 2205 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2206 int status) 2207 { 2208 struct urb *urb; 2209 int i; 2210 2211 if (!qtd) { 2212 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2213 return; 2214 } 2215 2216 if (!qtd->urb) { 2217 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2218 return; 2219 } 2220 2221 urb = qtd->urb->priv; 2222 if (!urb) { 2223 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2224 return; 2225 } 2226 2227 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2228 2229 if (dbg_urb(urb)) 2230 dev_vdbg(hsotg->dev, 2231 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2232 __func__, urb, usb_pipedevice(urb->pipe), 2233 usb_pipeendpoint(urb->pipe), 2234 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2235 urb->actual_length); 2236 2237 2238 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2239 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2240 for (i = 0; i < urb->number_of_packets; ++i) { 2241 urb->iso_frame_desc[i].actual_length = 2242 dwc2_hcd_urb_get_iso_desc_actual_length( 2243 qtd->urb, i); 2244 urb->iso_frame_desc[i].status = 2245 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2246 } 2247 } 2248 2249 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2250 for (i = 0; i < urb->number_of_packets; i++) 2251 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2252 i, urb->iso_frame_desc[i].status); 2253 } 2254 2255 urb->status = status; 2256 if (!status) { 2257 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2258 urb->actual_length < urb->transfer_buffer_length) 2259 urb->status = -EREMOTEIO; 2260 } 2261 2262 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2263 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2264 struct usb_host_endpoint *ep = urb->ep; 2265 2266 if (ep) 2267 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2268 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2269 urb); 2270 } 2271 2272 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2273 urb->hcpriv = NULL; 2274 kfree(qtd->urb); 2275 qtd->urb = NULL; 2276 2277 spin_unlock(&hsotg->lock); 2278 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2279 spin_lock(&hsotg->lock); 2280 } 2281 2282 /* 2283 * Work queue function for starting the HCD when A-Cable is connected 2284 */ 2285 static void dwc2_hcd_start_func(struct work_struct *work) 2286 { 2287 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2288 start_work.work); 2289 2290 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2291 dwc2_host_start(hsotg); 2292 } 2293 2294 /* 2295 * Reset work queue function 2296 */ 2297 static void dwc2_hcd_reset_func(struct work_struct *work) 2298 { 2299 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2300 reset_work.work); 2301 u32 hprt0; 2302 2303 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2304 hprt0 = dwc2_read_hprt0(hsotg); 2305 hprt0 &= ~HPRT0_RST; 2306 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2307 hsotg->flags.b.port_reset_change = 1; 2308 } 2309 2310 /* 2311 * ========================================================================= 2312 * Linux HC Driver Functions 2313 * ========================================================================= 2314 */ 2315 2316 /* 2317 * Initializes the DWC_otg controller and its root hub and prepares it for host 2318 * mode operation. Activates the root port. Returns 0 on success and a negative 2319 * error code on failure. 2320 */ 2321 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2322 { 2323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2324 struct usb_bus *bus = hcd_to_bus(hcd); 2325 unsigned long flags; 2326 2327 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2328 2329 spin_lock_irqsave(&hsotg->lock, flags); 2330 hsotg->lx_state = DWC2_L0; 2331 hcd->state = HC_STATE_RUNNING; 2332 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2333 2334 if (dwc2_is_device_mode(hsotg)) { 2335 spin_unlock_irqrestore(&hsotg->lock, flags); 2336 return 0; /* why 0 ?? */ 2337 } 2338 2339 dwc2_hcd_reinit(hsotg); 2340 2341 /* Initialize and connect root hub if one is not already attached */ 2342 if (bus->root_hub) { 2343 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2344 /* Inform the HUB driver to resume */ 2345 usb_hcd_resume_root_hub(hcd); 2346 } 2347 2348 spin_unlock_irqrestore(&hsotg->lock, flags); 2349 return 0; 2350 } 2351 2352 /* 2353 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2354 * stopped. 2355 */ 2356 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2357 { 2358 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2359 unsigned long flags; 2360 2361 /* Turn off all host-specific interrupts */ 2362 dwc2_disable_host_interrupts(hsotg); 2363 2364 /* Wait for interrupt processing to finish */ 2365 synchronize_irq(hcd->irq); 2366 2367 spin_lock_irqsave(&hsotg->lock, flags); 2368 /* Ensure hcd is disconnected */ 2369 dwc2_hcd_disconnect(hsotg); 2370 dwc2_hcd_stop(hsotg); 2371 hsotg->lx_state = DWC2_L3; 2372 hcd->state = HC_STATE_HALT; 2373 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2374 spin_unlock_irqrestore(&hsotg->lock, flags); 2375 2376 usleep_range(1000, 3000); 2377 } 2378 2379 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2380 { 2381 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2382 unsigned long flags; 2383 int ret = 0; 2384 u32 hprt0; 2385 2386 spin_lock_irqsave(&hsotg->lock, flags); 2387 2388 if (hsotg->lx_state != DWC2_L0) 2389 goto unlock; 2390 2391 if (!HCD_HW_ACCESSIBLE(hcd)) 2392 goto unlock; 2393 2394 if (!hsotg->core_params->hibernation) 2395 goto skip_power_saving; 2396 2397 /* 2398 * Drive USB suspend and disable port Power 2399 * if usb bus is not suspended. 2400 */ 2401 if (!hsotg->bus_suspended) { 2402 hprt0 = dwc2_read_hprt0(hsotg); 2403 hprt0 |= HPRT0_SUSP; 2404 hprt0 &= ~HPRT0_PWR; 2405 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2406 } 2407 2408 /* Enter hibernation */ 2409 ret = dwc2_enter_hibernation(hsotg); 2410 if (ret) { 2411 if (ret != -ENOTSUPP) 2412 dev_err(hsotg->dev, 2413 "enter hibernation failed\n"); 2414 goto skip_power_saving; 2415 } 2416 2417 /* Ask phy to be suspended */ 2418 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2419 spin_unlock_irqrestore(&hsotg->lock, flags); 2420 usb_phy_set_suspend(hsotg->uphy, true); 2421 spin_lock_irqsave(&hsotg->lock, flags); 2422 } 2423 2424 /* After entering hibernation, hardware is no more accessible */ 2425 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2426 2427 skip_power_saving: 2428 hsotg->lx_state = DWC2_L2; 2429 unlock: 2430 spin_unlock_irqrestore(&hsotg->lock, flags); 2431 2432 return ret; 2433 } 2434 2435 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2436 { 2437 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2438 unsigned long flags; 2439 int ret = 0; 2440 2441 spin_lock_irqsave(&hsotg->lock, flags); 2442 2443 if (hsotg->lx_state != DWC2_L2) 2444 goto unlock; 2445 2446 if (!hsotg->core_params->hibernation) { 2447 hsotg->lx_state = DWC2_L0; 2448 goto unlock; 2449 } 2450 2451 /* 2452 * Set HW accessible bit before powering on the controller 2453 * since an interrupt may rise. 2454 */ 2455 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2456 2457 /* 2458 * Enable power if not already done. 2459 * This must not be spinlocked since duration 2460 * of this call is unknown. 2461 */ 2462 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2463 spin_unlock_irqrestore(&hsotg->lock, flags); 2464 usb_phy_set_suspend(hsotg->uphy, false); 2465 spin_lock_irqsave(&hsotg->lock, flags); 2466 } 2467 2468 /* Exit hibernation */ 2469 ret = dwc2_exit_hibernation(hsotg, true); 2470 if (ret && (ret != -ENOTSUPP)) 2471 dev_err(hsotg->dev, "exit hibernation failed\n"); 2472 2473 hsotg->lx_state = DWC2_L0; 2474 2475 spin_unlock_irqrestore(&hsotg->lock, flags); 2476 2477 if (hsotg->bus_suspended) { 2478 spin_lock_irqsave(&hsotg->lock, flags); 2479 hsotg->flags.b.port_suspend_change = 1; 2480 spin_unlock_irqrestore(&hsotg->lock, flags); 2481 dwc2_port_resume(hsotg); 2482 } else { 2483 /* Wait for controller to correctly update D+/D- level */ 2484 usleep_range(3000, 5000); 2485 2486 /* 2487 * Clear Port Enable and Port Status changes. 2488 * Enable Port Power. 2489 */ 2490 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 2491 HPRT0_ENACHG, hsotg->regs + HPRT0); 2492 /* Wait for controller to detect Port Connect */ 2493 usleep_range(5000, 7000); 2494 } 2495 2496 return ret; 2497 unlock: 2498 spin_unlock_irqrestore(&hsotg->lock, flags); 2499 2500 return ret; 2501 } 2502 2503 /* Returns the current frame number */ 2504 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2505 { 2506 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2507 2508 return dwc2_hcd_get_frame_number(hsotg); 2509 } 2510 2511 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2512 char *fn_name) 2513 { 2514 #ifdef VERBOSE_DEBUG 2515 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2516 char *pipetype; 2517 char *speed; 2518 2519 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2520 dev_vdbg(hsotg->dev, " Device address: %d\n", 2521 usb_pipedevice(urb->pipe)); 2522 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2523 usb_pipeendpoint(urb->pipe), 2524 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2525 2526 switch (usb_pipetype(urb->pipe)) { 2527 case PIPE_CONTROL: 2528 pipetype = "CONTROL"; 2529 break; 2530 case PIPE_BULK: 2531 pipetype = "BULK"; 2532 break; 2533 case PIPE_INTERRUPT: 2534 pipetype = "INTERRUPT"; 2535 break; 2536 case PIPE_ISOCHRONOUS: 2537 pipetype = "ISOCHRONOUS"; 2538 break; 2539 default: 2540 pipetype = "UNKNOWN"; 2541 break; 2542 } 2543 2544 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2545 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2546 "IN" : "OUT"); 2547 2548 switch (urb->dev->speed) { 2549 case USB_SPEED_HIGH: 2550 speed = "HIGH"; 2551 break; 2552 case USB_SPEED_FULL: 2553 speed = "FULL"; 2554 break; 2555 case USB_SPEED_LOW: 2556 speed = "LOW"; 2557 break; 2558 default: 2559 speed = "UNKNOWN"; 2560 break; 2561 } 2562 2563 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2564 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2565 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2566 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2567 urb->transfer_buffer_length); 2568 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2569 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2570 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2571 urb->setup_packet, (unsigned long)urb->setup_dma); 2572 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2573 2574 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2575 int i; 2576 2577 for (i = 0; i < urb->number_of_packets; i++) { 2578 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2579 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2580 urb->iso_frame_desc[i].offset, 2581 urb->iso_frame_desc[i].length); 2582 } 2583 } 2584 #endif 2585 } 2586 2587 /* 2588 * Starts processing a USB transfer request specified by a USB Request Block 2589 * (URB). mem_flags indicates the type of memory allocation to use while 2590 * processing this URB. 2591 */ 2592 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2593 gfp_t mem_flags) 2594 { 2595 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2596 struct usb_host_endpoint *ep = urb->ep; 2597 struct dwc2_hcd_urb *dwc2_urb; 2598 int i; 2599 int retval; 2600 int alloc_bandwidth = 0; 2601 u8 ep_type = 0; 2602 u32 tflags = 0; 2603 void *buf; 2604 unsigned long flags; 2605 struct dwc2_qh *qh; 2606 bool qh_allocated = false; 2607 struct dwc2_qtd *qtd; 2608 2609 if (dbg_urb(urb)) { 2610 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2611 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2612 } 2613 2614 if (ep == NULL) 2615 return -EINVAL; 2616 2617 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2618 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2619 spin_lock_irqsave(&hsotg->lock, flags); 2620 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2621 alloc_bandwidth = 1; 2622 spin_unlock_irqrestore(&hsotg->lock, flags); 2623 } 2624 2625 switch (usb_pipetype(urb->pipe)) { 2626 case PIPE_CONTROL: 2627 ep_type = USB_ENDPOINT_XFER_CONTROL; 2628 break; 2629 case PIPE_ISOCHRONOUS: 2630 ep_type = USB_ENDPOINT_XFER_ISOC; 2631 break; 2632 case PIPE_BULK: 2633 ep_type = USB_ENDPOINT_XFER_BULK; 2634 break; 2635 case PIPE_INTERRUPT: 2636 ep_type = USB_ENDPOINT_XFER_INT; 2637 break; 2638 default: 2639 dev_warn(hsotg->dev, "Wrong ep type\n"); 2640 } 2641 2642 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2643 mem_flags); 2644 if (!dwc2_urb) 2645 return -ENOMEM; 2646 2647 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2648 usb_pipeendpoint(urb->pipe), ep_type, 2649 usb_pipein(urb->pipe), 2650 usb_maxpacket(urb->dev, urb->pipe, 2651 !(usb_pipein(urb->pipe)))); 2652 2653 buf = urb->transfer_buffer; 2654 2655 if (hcd->self.uses_dma) { 2656 if (!buf && (urb->transfer_dma & 3)) { 2657 dev_err(hsotg->dev, 2658 "%s: unaligned transfer with no transfer_buffer", 2659 __func__); 2660 retval = -EINVAL; 2661 goto fail0; 2662 } 2663 } 2664 2665 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2666 tflags |= URB_GIVEBACK_ASAP; 2667 if (urb->transfer_flags & URB_ZERO_PACKET) 2668 tflags |= URB_SEND_ZERO_PACKET; 2669 2670 dwc2_urb->priv = urb; 2671 dwc2_urb->buf = buf; 2672 dwc2_urb->dma = urb->transfer_dma; 2673 dwc2_urb->length = urb->transfer_buffer_length; 2674 dwc2_urb->setup_packet = urb->setup_packet; 2675 dwc2_urb->setup_dma = urb->setup_dma; 2676 dwc2_urb->flags = tflags; 2677 dwc2_urb->interval = urb->interval; 2678 dwc2_urb->status = -EINPROGRESS; 2679 2680 for (i = 0; i < urb->number_of_packets; ++i) 2681 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2682 urb->iso_frame_desc[i].offset, 2683 urb->iso_frame_desc[i].length); 2684 2685 urb->hcpriv = dwc2_urb; 2686 qh = (struct dwc2_qh *) ep->hcpriv; 2687 /* Create QH for the endpoint if it doesn't exist */ 2688 if (!qh) { 2689 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2690 if (!qh) { 2691 retval = -ENOMEM; 2692 goto fail0; 2693 } 2694 ep->hcpriv = qh; 2695 qh_allocated = true; 2696 } 2697 2698 qtd = kzalloc(sizeof(*qtd), mem_flags); 2699 if (!qtd) { 2700 retval = -ENOMEM; 2701 goto fail1; 2702 } 2703 2704 spin_lock_irqsave(&hsotg->lock, flags); 2705 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2706 if (retval) 2707 goto fail2; 2708 2709 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2710 if (retval) 2711 goto fail3; 2712 2713 if (alloc_bandwidth) { 2714 dwc2_allocate_bus_bandwidth(hcd, 2715 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2716 urb); 2717 } 2718 2719 spin_unlock_irqrestore(&hsotg->lock, flags); 2720 2721 return 0; 2722 2723 fail3: 2724 dwc2_urb->priv = NULL; 2725 usb_hcd_unlink_urb_from_ep(hcd, urb); 2726 fail2: 2727 spin_unlock_irqrestore(&hsotg->lock, flags); 2728 urb->hcpriv = NULL; 2729 kfree(qtd); 2730 fail1: 2731 if (qh_allocated) { 2732 struct dwc2_qtd *qtd2, *qtd2_tmp; 2733 2734 ep->hcpriv = NULL; 2735 dwc2_hcd_qh_unlink(hsotg, qh); 2736 /* Free each QTD in the QH's QTD list */ 2737 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2738 qtd_list_entry) 2739 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2740 dwc2_hcd_qh_free(hsotg, qh); 2741 } 2742 fail0: 2743 kfree(dwc2_urb); 2744 2745 return retval; 2746 } 2747 2748 /* 2749 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2750 */ 2751 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2752 int status) 2753 { 2754 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2755 int rc; 2756 unsigned long flags; 2757 2758 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2759 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2760 2761 spin_lock_irqsave(&hsotg->lock, flags); 2762 2763 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2764 if (rc) 2765 goto out; 2766 2767 if (!urb->hcpriv) { 2768 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2769 goto out; 2770 } 2771 2772 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2773 2774 usb_hcd_unlink_urb_from_ep(hcd, urb); 2775 2776 kfree(urb->hcpriv); 2777 urb->hcpriv = NULL; 2778 2779 /* Higher layer software sets URB status */ 2780 spin_unlock(&hsotg->lock); 2781 usb_hcd_giveback_urb(hcd, urb, status); 2782 spin_lock(&hsotg->lock); 2783 2784 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2785 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2786 out: 2787 spin_unlock_irqrestore(&hsotg->lock, flags); 2788 2789 return rc; 2790 } 2791 2792 /* 2793 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2794 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2795 * must already be dequeued. 2796 */ 2797 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2798 struct usb_host_endpoint *ep) 2799 { 2800 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2801 2802 dev_dbg(hsotg->dev, 2803 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2804 ep->desc.bEndpointAddress, ep->hcpriv); 2805 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2806 } 2807 2808 /* 2809 * Resets endpoint specific parameter values, in current version used to reset 2810 * the data toggle (as a WA). This function can be called from usb_clear_halt 2811 * routine. 2812 */ 2813 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2814 struct usb_host_endpoint *ep) 2815 { 2816 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2817 unsigned long flags; 2818 2819 dev_dbg(hsotg->dev, 2820 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2821 ep->desc.bEndpointAddress); 2822 2823 spin_lock_irqsave(&hsotg->lock, flags); 2824 dwc2_hcd_endpoint_reset(hsotg, ep); 2825 spin_unlock_irqrestore(&hsotg->lock, flags); 2826 } 2827 2828 /* 2829 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2830 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2831 * interrupt. 2832 * 2833 * This function is called by the USB core when an interrupt occurs 2834 */ 2835 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2836 { 2837 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2838 2839 return dwc2_handle_hcd_intr(hsotg); 2840 } 2841 2842 /* 2843 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2844 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2845 * is the status change indicator for the single root port. Returns 1 if either 2846 * change indicator is 1, otherwise returns 0. 2847 */ 2848 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2849 { 2850 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2851 2852 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2853 return buf[0] != 0; 2854 } 2855 2856 /* Handles hub class-specific requests */ 2857 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2858 u16 windex, char *buf, u16 wlength) 2859 { 2860 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2861 wvalue, windex, buf, wlength); 2862 return retval; 2863 } 2864 2865 /* Handles hub TT buffer clear completions */ 2866 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2867 struct usb_host_endpoint *ep) 2868 { 2869 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2870 struct dwc2_qh *qh; 2871 unsigned long flags; 2872 2873 qh = ep->hcpriv; 2874 if (!qh) 2875 return; 2876 2877 spin_lock_irqsave(&hsotg->lock, flags); 2878 qh->tt_buffer_dirty = 0; 2879 2880 if (hsotg->flags.b.port_connect_status) 2881 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2882 2883 spin_unlock_irqrestore(&hsotg->lock, flags); 2884 } 2885 2886 static struct hc_driver dwc2_hc_driver = { 2887 .description = "dwc2_hsotg", 2888 .product_desc = "DWC OTG Controller", 2889 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2890 2891 .irq = _dwc2_hcd_irq, 2892 .flags = HCD_MEMORY | HCD_USB2, 2893 2894 .start = _dwc2_hcd_start, 2895 .stop = _dwc2_hcd_stop, 2896 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2897 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2898 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2899 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2900 .get_frame_number = _dwc2_hcd_get_frame_number, 2901 2902 .hub_status_data = _dwc2_hcd_hub_status_data, 2903 .hub_control = _dwc2_hcd_hub_control, 2904 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2905 2906 .bus_suspend = _dwc2_hcd_suspend, 2907 .bus_resume = _dwc2_hcd_resume, 2908 }; 2909 2910 /* 2911 * Frees secondary storage associated with the dwc2_hsotg structure contained 2912 * in the struct usb_hcd field 2913 */ 2914 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2915 { 2916 u32 ahbcfg; 2917 u32 dctl; 2918 int i; 2919 2920 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2921 2922 /* Free memory for QH/QTD lists */ 2923 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2924 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2925 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2926 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2927 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2928 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2929 2930 /* Free memory for the host channels */ 2931 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2932 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2933 2934 if (chan != NULL) { 2935 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2936 i, chan); 2937 hsotg->hc_ptr_array[i] = NULL; 2938 kfree(chan); 2939 } 2940 } 2941 2942 if (hsotg->core_params->dma_enable > 0) { 2943 if (hsotg->status_buf) { 2944 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2945 hsotg->status_buf, 2946 hsotg->status_buf_dma); 2947 hsotg->status_buf = NULL; 2948 } 2949 } else { 2950 kfree(hsotg->status_buf); 2951 hsotg->status_buf = NULL; 2952 } 2953 2954 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 2955 2956 /* Disable all interrupts */ 2957 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2958 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 2959 dwc2_writel(0, hsotg->regs + GINTMSK); 2960 2961 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2962 dctl = dwc2_readl(hsotg->regs + DCTL); 2963 dctl |= DCTL_SFTDISCON; 2964 dwc2_writel(dctl, hsotg->regs + DCTL); 2965 } 2966 2967 if (hsotg->wq_otg) { 2968 if (!cancel_work_sync(&hsotg->wf_otg)) 2969 flush_workqueue(hsotg->wq_otg); 2970 destroy_workqueue(hsotg->wq_otg); 2971 } 2972 2973 del_timer(&hsotg->wkp_timer); 2974 } 2975 2976 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2977 { 2978 /* Turn off all host-specific interrupts */ 2979 dwc2_disable_host_interrupts(hsotg); 2980 2981 dwc2_hcd_free(hsotg); 2982 } 2983 2984 /* 2985 * Initializes the HCD. This function allocates memory for and initializes the 2986 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2987 * USB bus with the core and calls the hc_driver->start() function. It returns 2988 * a negative error on failure. 2989 */ 2990 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 2991 { 2992 struct usb_hcd *hcd; 2993 struct dwc2_host_chan *channel; 2994 u32 hcfg; 2995 int i, num_channels; 2996 int retval; 2997 2998 if (usb_disabled()) 2999 return -ENODEV; 3000 3001 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 3002 3003 retval = -ENOMEM; 3004 3005 hcfg = dwc2_readl(hsotg->regs + HCFG); 3006 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 3007 3008 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3009 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 3010 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3011 if (!hsotg->frame_num_array) 3012 goto error1; 3013 hsotg->last_frame_num_array = kzalloc( 3014 sizeof(*hsotg->last_frame_num_array) * 3015 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3016 if (!hsotg->last_frame_num_array) 3017 goto error1; 3018 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 3019 #endif 3020 3021 /* Check if the bus driver or platform code has setup a dma_mask */ 3022 if (hsotg->core_params->dma_enable > 0 && 3023 hsotg->dev->dma_mask == NULL) { 3024 dev_warn(hsotg->dev, 3025 "dma_mask not set, disabling DMA\n"); 3026 hsotg->core_params->dma_enable = 0; 3027 hsotg->core_params->dma_desc_enable = 0; 3028 } 3029 3030 /* Set device flags indicating whether the HCD supports DMA */ 3031 if (hsotg->core_params->dma_enable > 0) { 3032 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3033 dev_warn(hsotg->dev, "can't set DMA mask\n"); 3034 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3035 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 3036 } 3037 3038 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 3039 if (!hcd) 3040 goto error1; 3041 3042 if (hsotg->core_params->dma_enable <= 0) 3043 hcd->self.uses_dma = 0; 3044 3045 hcd->has_tt = 1; 3046 3047 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 3048 hsotg->priv = hcd; 3049 3050 /* 3051 * Disable the global interrupt until all the interrupt handlers are 3052 * installed 3053 */ 3054 dwc2_disable_global_interrupts(hsotg); 3055 3056 /* Initialize the DWC_otg core, and select the Phy type */ 3057 retval = dwc2_core_init(hsotg, true, irq); 3058 if (retval) 3059 goto error2; 3060 3061 /* Create new workqueue and init work */ 3062 retval = -ENOMEM; 3063 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 3064 if (!hsotg->wq_otg) { 3065 dev_err(hsotg->dev, "Failed to create workqueue\n"); 3066 goto error2; 3067 } 3068 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 3069 3070 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 3071 (unsigned long)hsotg); 3072 3073 /* Initialize the non-periodic schedule */ 3074 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 3075 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 3076 3077 /* Initialize the periodic schedule */ 3078 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 3079 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 3080 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 3081 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 3082 3083 /* 3084 * Create a host channel descriptor for each host channel implemented 3085 * in the controller. Initialize the channel descriptor array. 3086 */ 3087 INIT_LIST_HEAD(&hsotg->free_hc_list); 3088 num_channels = hsotg->core_params->host_channels; 3089 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 3090 3091 for (i = 0; i < num_channels; i++) { 3092 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 3093 if (channel == NULL) 3094 goto error3; 3095 channel->hc_num = i; 3096 hsotg->hc_ptr_array[i] = channel; 3097 } 3098 3099 if (hsotg->core_params->uframe_sched > 0) 3100 dwc2_hcd_init_usecs(hsotg); 3101 3102 /* Initialize hsotg start work */ 3103 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 3104 3105 /* Initialize port reset work */ 3106 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 3107 3108 /* 3109 * Allocate space for storing data on status transactions. Normally no 3110 * data is sent, but this space acts as a bit bucket. This must be 3111 * done after usb_add_hcd since that function allocates the DMA buffer 3112 * pool. 3113 */ 3114 if (hsotg->core_params->dma_enable > 0) 3115 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 3116 DWC2_HCD_STATUS_BUF_SIZE, 3117 &hsotg->status_buf_dma, GFP_KERNEL); 3118 else 3119 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 3120 GFP_KERNEL); 3121 3122 if (!hsotg->status_buf) 3123 goto error3; 3124 3125 hsotg->otg_port = 1; 3126 hsotg->frame_list = NULL; 3127 hsotg->frame_list_dma = 0; 3128 hsotg->periodic_qh_count = 0; 3129 3130 /* Initiate lx_state to L3 disconnected state */ 3131 hsotg->lx_state = DWC2_L3; 3132 3133 hcd->self.otg_port = hsotg->otg_port; 3134 3135 /* Don't support SG list at this point */ 3136 hcd->self.sg_tablesize = 0; 3137 3138 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3139 otg_set_host(hsotg->uphy->otg, &hcd->self); 3140 3141 /* 3142 * Finish generic HCD initialization and start the HCD. This function 3143 * allocates the DMA buffer pool, registers the USB bus, requests the 3144 * IRQ line, and calls hcd_start method. 3145 */ 3146 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3147 if (retval < 0) 3148 goto error3; 3149 3150 device_wakeup_enable(hcd->self.controller); 3151 3152 dwc2_hcd_dump_state(hsotg); 3153 3154 dwc2_enable_global_interrupts(hsotg); 3155 3156 return 0; 3157 3158 error3: 3159 dwc2_hcd_release(hsotg); 3160 error2: 3161 usb_put_hcd(hcd); 3162 error1: 3163 kfree(hsotg->core_params); 3164 3165 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3166 kfree(hsotg->last_frame_num_array); 3167 kfree(hsotg->frame_num_array); 3168 #endif 3169 3170 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3171 return retval; 3172 } 3173 3174 /* 3175 * Removes the HCD. 3176 * Frees memory and resources associated with the HCD and deregisters the bus. 3177 */ 3178 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3179 { 3180 struct usb_hcd *hcd; 3181 3182 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3183 3184 hcd = dwc2_hsotg_to_hcd(hsotg); 3185 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3186 3187 if (!hcd) { 3188 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3189 __func__); 3190 return; 3191 } 3192 3193 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3194 otg_set_host(hsotg->uphy->otg, NULL); 3195 3196 usb_remove_hcd(hcd); 3197 hsotg->priv = NULL; 3198 dwc2_hcd_release(hsotg); 3199 usb_put_hcd(hcd); 3200 3201 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3202 kfree(hsotg->last_frame_num_array); 3203 kfree(hsotg->frame_num_array); 3204 #endif 3205 } 3206