1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.c - DesignWare HS OTG Controller host-mode routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8 /* 9 * This file contains the core HCD code, and implements the Linux hc_driver 10 * API 11 */ 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/spinlock.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/delay.h> 19 #include <linux/io.h> 20 #include <linux/slab.h> 21 #include <linux/usb.h> 22 23 #include <linux/usb/hcd.h> 24 #include <linux/usb/ch11.h> 25 #include <linux/usb/of.h> 26 27 #include "core.h" 28 #include "hcd.h" 29 30 /* 31 * ========================================================================= 32 * Host Core Layer Functions 33 * ========================================================================= 34 */ 35 36 /** 37 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 38 * used in both device and host modes 39 * 40 * @hsotg: Programming view of the DWC_otg controller 41 */ 42 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 43 { 44 u32 intmsk; 45 46 /* Clear any pending OTG Interrupts */ 47 dwc2_writel(hsotg, 0xffffffff, GOTGINT); 48 49 /* Clear any pending interrupts */ 50 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 51 52 /* Enable the interrupts in the GINTMSK */ 53 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 54 55 if (!hsotg->params.host_dma) 56 intmsk |= GINTSTS_RXFLVL; 57 if (!hsotg->params.external_id_pin_ctl) 58 intmsk |= GINTSTS_CONIDSTSCHNG; 59 60 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 61 GINTSTS_SESSREQINT; 62 63 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 64 intmsk |= GINTSTS_LPMTRANRCVD; 65 66 dwc2_writel(hsotg, intmsk, GINTMSK); 67 } 68 69 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 70 { 71 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 72 73 switch (hsotg->hw_params.arch) { 74 case GHWCFG2_EXT_DMA_ARCH: 75 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 76 return -EINVAL; 77 78 case GHWCFG2_INT_DMA_ARCH: 79 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 80 if (hsotg->params.ahbcfg != -1) { 81 ahbcfg &= GAHBCFG_CTRL_MASK; 82 ahbcfg |= hsotg->params.ahbcfg & 83 ~GAHBCFG_CTRL_MASK; 84 } 85 break; 86 87 case GHWCFG2_SLAVE_ONLY_ARCH: 88 default: 89 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 90 break; 91 } 92 93 if (hsotg->params.host_dma) 94 ahbcfg |= GAHBCFG_DMA_EN; 95 else 96 hsotg->params.dma_desc_enable = false; 97 98 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 99 100 return 0; 101 } 102 103 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 104 { 105 u32 usbcfg; 106 107 usbcfg = dwc2_readl(hsotg, GUSBCFG); 108 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 109 110 switch (hsotg->hw_params.op_mode) { 111 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 112 if (hsotg->params.otg_caps.hnp_support && 113 hsotg->params.otg_caps.srp_support) 114 usbcfg |= GUSBCFG_HNPCAP; 115 fallthrough; 116 117 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 118 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 119 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 120 if (hsotg->params.otg_caps.srp_support) 121 usbcfg |= GUSBCFG_SRPCAP; 122 break; 123 124 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 125 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 126 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 127 default: 128 break; 129 } 130 131 dwc2_writel(hsotg, usbcfg, GUSBCFG); 132 } 133 134 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) 135 { 136 if (hsotg->vbus_supply) 137 return regulator_enable(hsotg->vbus_supply); 138 139 return 0; 140 } 141 142 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg) 143 { 144 if (hsotg->vbus_supply) 145 return regulator_disable(hsotg->vbus_supply); 146 147 return 0; 148 } 149 150 /** 151 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 152 * 153 * @hsotg: Programming view of DWC_otg controller 154 */ 155 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 156 { 157 u32 intmsk; 158 159 dev_dbg(hsotg->dev, "%s()\n", __func__); 160 161 /* Disable all interrupts */ 162 dwc2_writel(hsotg, 0, GINTMSK); 163 dwc2_writel(hsotg, 0, HAINTMSK); 164 165 /* Enable the common interrupts */ 166 dwc2_enable_common_interrupts(hsotg); 167 168 /* Enable host mode interrupts without disturbing common interrupts */ 169 intmsk = dwc2_readl(hsotg, GINTMSK); 170 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 171 dwc2_writel(hsotg, intmsk, GINTMSK); 172 } 173 174 /** 175 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 176 * 177 * @hsotg: Programming view of DWC_otg controller 178 */ 179 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 180 { 181 u32 intmsk = dwc2_readl(hsotg, GINTMSK); 182 183 /* Disable host mode interrupts without disturbing common interrupts */ 184 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 185 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 186 dwc2_writel(hsotg, intmsk, GINTMSK); 187 } 188 189 /* 190 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 191 * For system that have a total fifo depth that is smaller than the default 192 * RX + TX fifo size. 193 * 194 * @hsotg: Programming view of DWC_otg controller 195 */ 196 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 197 { 198 struct dwc2_core_params *params = &hsotg->params; 199 struct dwc2_hw_params *hw = &hsotg->hw_params; 200 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 201 202 total_fifo_size = hw->total_fifo_size; 203 rxfsiz = params->host_rx_fifo_size; 204 nptxfsiz = params->host_nperio_tx_fifo_size; 205 ptxfsiz = params->host_perio_tx_fifo_size; 206 207 /* 208 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 209 * allocation with support for high bandwidth endpoints. Synopsys 210 * defines MPS(Max Packet size) for a periodic EP=1024, and for 211 * non-periodic as 512. 212 */ 213 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 214 /* 215 * For Buffer DMA mode/Scatter Gather DMA mode 216 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 217 * with n = number of host channel. 218 * 2 * ((1024/4) + 2) = 516 219 */ 220 rxfsiz = 516 + hw->host_channels; 221 222 /* 223 * min non-periodic tx fifo depth 224 * 2 * (largest non-periodic USB packet used / 4) 225 * 2 * (512/4) = 256 226 */ 227 nptxfsiz = 256; 228 229 /* 230 * min periodic tx fifo depth 231 * (largest packet size*MC)/4 232 * (1024 * 3)/4 = 768 233 */ 234 ptxfsiz = 768; 235 236 params->host_rx_fifo_size = rxfsiz; 237 params->host_nperio_tx_fifo_size = nptxfsiz; 238 params->host_perio_tx_fifo_size = ptxfsiz; 239 } 240 241 /* 242 * If the summation of RX, NPTX and PTX fifo sizes is still 243 * bigger than the total_fifo_size, then we have a problem. 244 * 245 * We won't be able to allocate as many endpoints. Right now, 246 * we're just printing an error message, but ideally this FIFO 247 * allocation algorithm would be improved in the future. 248 * 249 * FIXME improve this FIFO allocation algorithm. 250 */ 251 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 252 dev_err(hsotg->dev, "invalid fifo sizes\n"); 253 } 254 255 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 256 { 257 struct dwc2_core_params *params = &hsotg->params; 258 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 259 260 if (!params->enable_dynamic_fifo) 261 return; 262 263 dwc2_calculate_dynamic_fifo(hsotg); 264 265 /* Rx FIFO */ 266 grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 267 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 268 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 269 grxfsiz |= params->host_rx_fifo_size << 270 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 271 dwc2_writel(hsotg, grxfsiz, GRXFSIZ); 272 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 273 dwc2_readl(hsotg, GRXFSIZ)); 274 275 /* Non-periodic Tx FIFO */ 276 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 277 dwc2_readl(hsotg, GNPTXFSIZ)); 278 nptxfsiz = params->host_nperio_tx_fifo_size << 279 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 280 nptxfsiz |= params->host_rx_fifo_size << 281 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 282 dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ); 283 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 284 dwc2_readl(hsotg, GNPTXFSIZ)); 285 286 /* Periodic Tx FIFO */ 287 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 288 dwc2_readl(hsotg, HPTXFSIZ)); 289 hptxfsiz = params->host_perio_tx_fifo_size << 290 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 291 hptxfsiz |= (params->host_rx_fifo_size + 292 params->host_nperio_tx_fifo_size) << 293 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 294 dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ); 295 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 296 dwc2_readl(hsotg, HPTXFSIZ)); 297 298 if (hsotg->params.en_multiple_tx_fifo && 299 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 300 /* 301 * This feature was implemented in 2.91a version 302 * Global DFIFOCFG calculation for Host mode - 303 * include RxFIFO, NPTXFIFO and HPTXFIFO 304 */ 305 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 306 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 307 dfifocfg |= (params->host_rx_fifo_size + 308 params->host_nperio_tx_fifo_size + 309 params->host_perio_tx_fifo_size) << 310 GDFIFOCFG_EPINFOBASE_SHIFT & 311 GDFIFOCFG_EPINFOBASE_MASK; 312 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG); 313 } 314 } 315 316 /** 317 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 318 * the HFIR register according to PHY type and speed 319 * 320 * @hsotg: Programming view of DWC_otg controller 321 * 322 * NOTE: The caller can modify the value of the HFIR register only after the 323 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 324 * has been set 325 */ 326 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 327 { 328 u32 usbcfg; 329 u32 hprt0; 330 int clock = 60; /* default value */ 331 332 usbcfg = dwc2_readl(hsotg, GUSBCFG); 333 hprt0 = dwc2_readl(hsotg, HPRT0); 334 335 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 336 !(usbcfg & GUSBCFG_PHYIF16)) 337 clock = 60; 338 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 339 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 340 clock = 48; 341 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 342 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 343 clock = 30; 344 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 345 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 346 clock = 60; 347 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 348 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 349 clock = 48; 350 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 351 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 352 clock = 48; 353 if ((usbcfg & GUSBCFG_PHYSEL) && 354 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 355 clock = 48; 356 357 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 358 /* High speed case */ 359 return 125 * clock - 1; 360 361 /* FS/LS case */ 362 return 1000 * clock - 1; 363 } 364 365 /** 366 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 367 * buffer 368 * 369 * @hsotg: Programming view of DWC_otg controller 370 * @dest: Destination buffer for the packet 371 * @bytes: Number of bytes to copy to the destination 372 */ 373 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 374 { 375 u32 *data_buf = (u32 *)dest; 376 int word_count = (bytes + 3) / 4; 377 int i; 378 379 /* 380 * Todo: Account for the case where dest is not dword aligned. This 381 * requires reading data from the FIFO into a u32 temp buffer, then 382 * moving it into the data buffer. 383 */ 384 385 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 386 387 for (i = 0; i < word_count; i++, data_buf++) 388 *data_buf = dwc2_readl(hsotg, HCFIFO(0)); 389 } 390 391 /** 392 * dwc2_dump_channel_info() - Prints the state of a host channel 393 * 394 * @hsotg: Programming view of DWC_otg controller 395 * @chan: Pointer to the channel to dump 396 * 397 * Must be called with interrupt disabled and spinlock held 398 * 399 * NOTE: This function will be removed once the peripheral controller code 400 * is integrated and the driver is stable 401 */ 402 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 403 struct dwc2_host_chan *chan) 404 { 405 #ifdef VERBOSE_DEBUG 406 int num_channels = hsotg->params.host_channels; 407 struct dwc2_qh *qh; 408 u32 hcchar; 409 u32 hcsplt; 410 u32 hctsiz; 411 u32 hc_dma; 412 int i; 413 414 if (!chan) 415 return; 416 417 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 418 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 419 hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num)); 420 hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num)); 421 422 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 423 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 424 hcchar, hcsplt); 425 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 426 hctsiz, hc_dma); 427 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 428 chan->dev_addr, chan->ep_num, chan->ep_is_in); 429 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 430 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 431 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 432 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 433 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 434 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 435 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 436 (unsigned long)chan->xfer_dma); 437 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 438 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 439 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 440 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 441 qh_list_entry) 442 dev_dbg(hsotg->dev, " %p\n", qh); 443 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 444 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 445 qh_list_entry) 446 dev_dbg(hsotg->dev, " %p\n", qh); 447 dev_dbg(hsotg->dev, " NP active sched:\n"); 448 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 449 qh_list_entry) 450 dev_dbg(hsotg->dev, " %p\n", qh); 451 dev_dbg(hsotg->dev, " Channels:\n"); 452 for (i = 0; i < num_channels; i++) { 453 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 454 455 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 456 } 457 #endif /* VERBOSE_DEBUG */ 458 } 459 460 static int _dwc2_hcd_start(struct usb_hcd *hcd); 461 462 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 463 { 464 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 465 466 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 467 _dwc2_hcd_start(hcd); 468 } 469 470 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 471 { 472 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 473 474 hcd->self.is_b_host = 0; 475 } 476 477 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 478 int *hub_addr, int *hub_port) 479 { 480 struct urb *urb = context; 481 482 if (urb->dev->tt) 483 *hub_addr = urb->dev->tt->hub->devnum; 484 else 485 *hub_addr = 0; 486 *hub_port = urb->dev->ttport; 487 } 488 489 /* 490 * ========================================================================= 491 * Low Level Host Channel Access Functions 492 * ========================================================================= 493 */ 494 495 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 496 struct dwc2_host_chan *chan) 497 { 498 u32 hcintmsk = HCINTMSK_CHHLTD; 499 500 switch (chan->ep_type) { 501 case USB_ENDPOINT_XFER_CONTROL: 502 case USB_ENDPOINT_XFER_BULK: 503 dev_vdbg(hsotg->dev, "control/bulk\n"); 504 hcintmsk |= HCINTMSK_XFERCOMPL; 505 hcintmsk |= HCINTMSK_STALL; 506 hcintmsk |= HCINTMSK_XACTERR; 507 hcintmsk |= HCINTMSK_DATATGLERR; 508 if (chan->ep_is_in) { 509 hcintmsk |= HCINTMSK_BBLERR; 510 } else { 511 hcintmsk |= HCINTMSK_NAK; 512 hcintmsk |= HCINTMSK_NYET; 513 if (chan->do_ping) 514 hcintmsk |= HCINTMSK_ACK; 515 } 516 517 if (chan->do_split) { 518 hcintmsk |= HCINTMSK_NAK; 519 if (chan->complete_split) 520 hcintmsk |= HCINTMSK_NYET; 521 else 522 hcintmsk |= HCINTMSK_ACK; 523 } 524 525 if (chan->error_state) 526 hcintmsk |= HCINTMSK_ACK; 527 break; 528 529 case USB_ENDPOINT_XFER_INT: 530 if (dbg_perio()) 531 dev_vdbg(hsotg->dev, "intr\n"); 532 hcintmsk |= HCINTMSK_XFERCOMPL; 533 hcintmsk |= HCINTMSK_NAK; 534 hcintmsk |= HCINTMSK_STALL; 535 hcintmsk |= HCINTMSK_XACTERR; 536 hcintmsk |= HCINTMSK_DATATGLERR; 537 hcintmsk |= HCINTMSK_FRMOVRUN; 538 539 if (chan->ep_is_in) 540 hcintmsk |= HCINTMSK_BBLERR; 541 if (chan->error_state) 542 hcintmsk |= HCINTMSK_ACK; 543 if (chan->do_split) { 544 if (chan->complete_split) 545 hcintmsk |= HCINTMSK_NYET; 546 else 547 hcintmsk |= HCINTMSK_ACK; 548 } 549 break; 550 551 case USB_ENDPOINT_XFER_ISOC: 552 if (dbg_perio()) 553 dev_vdbg(hsotg->dev, "isoc\n"); 554 hcintmsk |= HCINTMSK_XFERCOMPL; 555 hcintmsk |= HCINTMSK_FRMOVRUN; 556 hcintmsk |= HCINTMSK_ACK; 557 558 if (chan->ep_is_in) { 559 hcintmsk |= HCINTMSK_XACTERR; 560 hcintmsk |= HCINTMSK_BBLERR; 561 } 562 break; 563 default: 564 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 565 break; 566 } 567 568 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 569 if (dbg_hc(chan)) 570 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 571 } 572 573 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 574 struct dwc2_host_chan *chan) 575 { 576 u32 hcintmsk = HCINTMSK_CHHLTD; 577 578 /* 579 * For Descriptor DMA mode core halts the channel on AHB error. 580 * Interrupt is not required. 581 */ 582 if (!hsotg->params.dma_desc_enable) { 583 if (dbg_hc(chan)) 584 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 585 hcintmsk |= HCINTMSK_AHBERR; 586 } else { 587 if (dbg_hc(chan)) 588 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 589 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 590 hcintmsk |= HCINTMSK_XFERCOMPL; 591 } 592 593 if (chan->error_state && !chan->do_split && 594 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 595 if (dbg_hc(chan)) 596 dev_vdbg(hsotg->dev, "setting ACK\n"); 597 hcintmsk |= HCINTMSK_ACK; 598 if (chan->ep_is_in) { 599 hcintmsk |= HCINTMSK_DATATGLERR; 600 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 601 hcintmsk |= HCINTMSK_NAK; 602 } 603 } 604 605 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 606 if (dbg_hc(chan)) 607 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 608 } 609 610 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 611 struct dwc2_host_chan *chan) 612 { 613 u32 intmsk; 614 615 if (hsotg->params.host_dma) { 616 if (dbg_hc(chan)) 617 dev_vdbg(hsotg->dev, "DMA enabled\n"); 618 dwc2_hc_enable_dma_ints(hsotg, chan); 619 } else { 620 if (dbg_hc(chan)) 621 dev_vdbg(hsotg->dev, "DMA disabled\n"); 622 dwc2_hc_enable_slave_ints(hsotg, chan); 623 } 624 625 /* Enable the top level host channel interrupt */ 626 intmsk = dwc2_readl(hsotg, HAINTMSK); 627 intmsk |= 1 << chan->hc_num; 628 dwc2_writel(hsotg, intmsk, HAINTMSK); 629 if (dbg_hc(chan)) 630 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 631 632 /* Make sure host channel interrupts are enabled */ 633 intmsk = dwc2_readl(hsotg, GINTMSK); 634 intmsk |= GINTSTS_HCHINT; 635 dwc2_writel(hsotg, intmsk, GINTMSK); 636 if (dbg_hc(chan)) 637 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 638 } 639 640 /** 641 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 642 * a specific endpoint 643 * 644 * @hsotg: Programming view of DWC_otg controller 645 * @chan: Information needed to initialize the host channel 646 * 647 * The HCCHARn register is set up with the characteristics specified in chan. 648 * Host channel interrupts that may need to be serviced while this transfer is 649 * in progress are enabled. 650 */ 651 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 652 { 653 u8 hc_num = chan->hc_num; 654 u32 hcintmsk; 655 u32 hcchar; 656 u32 hcsplt = 0; 657 658 if (dbg_hc(chan)) 659 dev_vdbg(hsotg->dev, "%s()\n", __func__); 660 661 /* Clear old interrupt conditions for this host channel */ 662 hcintmsk = 0xffffffff; 663 hcintmsk &= ~HCINTMSK_RESERVED14_31; 664 dwc2_writel(hsotg, hcintmsk, HCINT(hc_num)); 665 666 /* Enable channel interrupts required for this transfer */ 667 dwc2_hc_enable_ints(hsotg, chan); 668 669 /* 670 * Program the HCCHARn register with the endpoint characteristics for 671 * the current transfer 672 */ 673 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 674 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 675 if (chan->ep_is_in) 676 hcchar |= HCCHAR_EPDIR; 677 if (chan->speed == USB_SPEED_LOW) 678 hcchar |= HCCHAR_LSPDDEV; 679 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 680 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 681 dwc2_writel(hsotg, hcchar, HCCHAR(hc_num)); 682 if (dbg_hc(chan)) { 683 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 684 hc_num, hcchar); 685 686 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 687 __func__, hc_num); 688 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 689 chan->dev_addr); 690 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 691 chan->ep_num); 692 dev_vdbg(hsotg->dev, " Is In: %d\n", 693 chan->ep_is_in); 694 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 695 chan->speed == USB_SPEED_LOW); 696 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 697 chan->ep_type); 698 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 699 chan->max_packet); 700 } 701 702 /* Program the HCSPLT register for SPLITs */ 703 if (chan->do_split) { 704 if (dbg_hc(chan)) 705 dev_vdbg(hsotg->dev, 706 "Programming HC %d with split --> %s\n", 707 hc_num, 708 chan->complete_split ? "CSPLIT" : "SSPLIT"); 709 if (chan->complete_split) 710 hcsplt |= HCSPLT_COMPSPLT; 711 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 712 HCSPLT_XACTPOS_MASK; 713 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 714 HCSPLT_HUBADDR_MASK; 715 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 716 HCSPLT_PRTADDR_MASK; 717 if (dbg_hc(chan)) { 718 dev_vdbg(hsotg->dev, " comp split %d\n", 719 chan->complete_split); 720 dev_vdbg(hsotg->dev, " xact pos %d\n", 721 chan->xact_pos); 722 dev_vdbg(hsotg->dev, " hub addr %d\n", 723 chan->hub_addr); 724 dev_vdbg(hsotg->dev, " hub port %d\n", 725 chan->hub_port); 726 dev_vdbg(hsotg->dev, " is_in %d\n", 727 chan->ep_is_in); 728 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 729 chan->max_packet); 730 dev_vdbg(hsotg->dev, " xferlen %d\n", 731 chan->xfer_len); 732 } 733 } 734 735 dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num)); 736 } 737 738 /** 739 * dwc2_hc_halt() - Attempts to halt a host channel 740 * 741 * @hsotg: Controller register interface 742 * @chan: Host channel to halt 743 * @halt_status: Reason for halting the channel 744 * 745 * This function should only be called in Slave mode or to abort a transfer in 746 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 747 * controller halts the channel when the transfer is complete or a condition 748 * occurs that requires application intervention. 749 * 750 * In slave mode, checks for a free request queue entry, then sets the Channel 751 * Enable and Channel Disable bits of the Host Channel Characteristics 752 * register of the specified channel to intiate the halt. If there is no free 753 * request queue entry, sets only the Channel Disable bit of the HCCHARn 754 * register to flush requests for this channel. In the latter case, sets a 755 * flag to indicate that the host channel needs to be halted when a request 756 * queue slot is open. 757 * 758 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 759 * HCCHARn register. The controller ensures there is space in the request 760 * queue before submitting the halt request. 761 * 762 * Some time may elapse before the core flushes any posted requests for this 763 * host channel and halts. The Channel Halted interrupt handler completes the 764 * deactivation of the host channel. 765 */ 766 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 767 enum dwc2_halt_status halt_status) 768 { 769 u32 nptxsts, hptxsts, hcchar; 770 771 if (dbg_hc(chan)) 772 dev_vdbg(hsotg->dev, "%s()\n", __func__); 773 774 /* 775 * In buffer DMA or external DMA mode channel can't be halted 776 * for non-split periodic channels. At the end of the next 777 * uframe/frame (in the worst case), the core generates a channel 778 * halted and disables the channel automatically. 779 */ 780 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || 781 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { 782 if (!chan->do_split && 783 (chan->ep_type == USB_ENDPOINT_XFER_ISOC || 784 chan->ep_type == USB_ENDPOINT_XFER_INT)) { 785 dev_err(hsotg->dev, "%s() Channel can't be halted\n", 786 __func__); 787 return; 788 } 789 } 790 791 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 792 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 793 794 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 795 halt_status == DWC2_HC_XFER_AHB_ERR) { 796 /* 797 * Disable all channel interrupts except Ch Halted. The QTD 798 * and QH state associated with this transfer has been cleared 799 * (in the case of URB_DEQUEUE), so the channel needs to be 800 * shut down carefully to prevent crashes. 801 */ 802 u32 hcintmsk = HCINTMSK_CHHLTD; 803 804 dev_vdbg(hsotg->dev, "dequeue/error\n"); 805 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); 806 807 /* 808 * Make sure no other interrupts besides halt are currently 809 * pending. Handling another interrupt could cause a crash due 810 * to the QTD and QH state. 811 */ 812 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num)); 813 814 /* 815 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 816 * even if the channel was already halted for some other 817 * reason 818 */ 819 chan->halt_status = halt_status; 820 821 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 822 if (!(hcchar & HCCHAR_CHENA)) { 823 /* 824 * The channel is either already halted or it hasn't 825 * started yet. In DMA mode, the transfer may halt if 826 * it finishes normally or a condition occurs that 827 * requires driver intervention. Don't want to halt 828 * the channel again. In either Slave or DMA mode, 829 * it's possible that the transfer has been assigned 830 * to a channel, but not started yet when an URB is 831 * dequeued. Don't want to halt a channel that hasn't 832 * started yet. 833 */ 834 return; 835 } 836 } 837 if (chan->halt_pending) { 838 /* 839 * A halt has already been issued for this channel. This might 840 * happen when a transfer is aborted by a higher level in 841 * the stack. 842 */ 843 dev_vdbg(hsotg->dev, 844 "*** %s: Channel %d, chan->halt_pending already set ***\n", 845 __func__, chan->hc_num); 846 return; 847 } 848 849 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 850 851 /* No need to set the bit in DDMA for disabling the channel */ 852 /* TODO check it everywhere channel is disabled */ 853 if (!hsotg->params.dma_desc_enable) { 854 if (dbg_hc(chan)) 855 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 856 hcchar |= HCCHAR_CHENA; 857 } else { 858 if (dbg_hc(chan)) 859 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 860 } 861 hcchar |= HCCHAR_CHDIS; 862 863 if (!hsotg->params.host_dma) { 864 if (dbg_hc(chan)) 865 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 866 hcchar |= HCCHAR_CHENA; 867 868 /* Check for space in the request queue to issue the halt */ 869 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 870 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 871 dev_vdbg(hsotg->dev, "control/bulk\n"); 872 nptxsts = dwc2_readl(hsotg, GNPTXSTS); 873 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 874 dev_vdbg(hsotg->dev, "Disabling channel\n"); 875 hcchar &= ~HCCHAR_CHENA; 876 } 877 } else { 878 if (dbg_perio()) 879 dev_vdbg(hsotg->dev, "isoc/intr\n"); 880 hptxsts = dwc2_readl(hsotg, HPTXSTS); 881 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 882 hsotg->queuing_high_bandwidth) { 883 if (dbg_perio()) 884 dev_vdbg(hsotg->dev, "Disabling channel\n"); 885 hcchar &= ~HCCHAR_CHENA; 886 } 887 } 888 } else { 889 if (dbg_hc(chan)) 890 dev_vdbg(hsotg->dev, "DMA enabled\n"); 891 } 892 893 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 894 chan->halt_status = halt_status; 895 896 if (hcchar & HCCHAR_CHENA) { 897 if (dbg_hc(chan)) 898 dev_vdbg(hsotg->dev, "Channel enabled\n"); 899 chan->halt_pending = 1; 900 chan->halt_on_queue = 0; 901 } else { 902 if (dbg_hc(chan)) 903 dev_vdbg(hsotg->dev, "Channel disabled\n"); 904 chan->halt_on_queue = 1; 905 } 906 907 if (dbg_hc(chan)) { 908 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 909 chan->hc_num); 910 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 911 hcchar); 912 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 913 chan->halt_pending); 914 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 915 chan->halt_on_queue); 916 dev_vdbg(hsotg->dev, " halt_status: %d\n", 917 chan->halt_status); 918 } 919 } 920 921 /** 922 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 923 * 924 * @hsotg: Programming view of DWC_otg controller 925 * @chan: Identifies the host channel to clean up 926 * 927 * This function is normally called after a transfer is done and the host 928 * channel is being released 929 */ 930 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 931 { 932 u32 hcintmsk; 933 934 chan->xfer_started = 0; 935 936 list_del_init(&chan->split_order_list_entry); 937 938 /* 939 * Clear channel interrupt enables and any unhandled channel interrupt 940 * conditions 941 */ 942 dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num)); 943 hcintmsk = 0xffffffff; 944 hcintmsk &= ~HCINTMSK_RESERVED14_31; 945 dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num)); 946 } 947 948 /** 949 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 950 * which frame a periodic transfer should occur 951 * 952 * @hsotg: Programming view of DWC_otg controller 953 * @chan: Identifies the host channel to set up and its properties 954 * @hcchar: Current value of the HCCHAR register for the specified host channel 955 * 956 * This function has no effect on non-periodic transfers 957 */ 958 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 959 struct dwc2_host_chan *chan, u32 *hcchar) 960 { 961 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 962 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 963 int host_speed; 964 int xfer_ns; 965 int xfer_us; 966 int bytes_in_fifo; 967 u16 fifo_space; 968 u16 frame_number; 969 u16 wire_frame; 970 971 /* 972 * Try to figure out if we're an even or odd frame. If we set 973 * even and the current frame number is even the transfer 974 * will happen immediately. Similar if both are odd. If one is 975 * even and the other is odd then the transfer will happen when 976 * the frame number ticks. 977 * 978 * There's a bit of a balancing act to get this right. 979 * Sometimes we may want to send data in the current frame (AK 980 * right away). We might want to do this if the frame number 981 * _just_ ticked, but we might also want to do this in order 982 * to continue a split transaction that happened late in a 983 * microframe (so we didn't know to queue the next transfer 984 * until the frame number had ticked). The problem is that we 985 * need a lot of knowledge to know if there's actually still 986 * time to send things or if it would be better to wait until 987 * the next frame. 988 * 989 * We can look at how much time is left in the current frame 990 * and make a guess about whether we'll have time to transfer. 991 * We'll do that. 992 */ 993 994 /* Get speed host is running at */ 995 host_speed = (chan->speed != USB_SPEED_HIGH && 996 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 997 998 /* See how many bytes are in the periodic FIFO right now */ 999 fifo_space = (dwc2_readl(hsotg, HPTXSTS) & 1000 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1001 bytes_in_fifo = sizeof(u32) * 1002 (hsotg->params.host_perio_tx_fifo_size - 1003 fifo_space); 1004 1005 /* 1006 * Roughly estimate bus time for everything in the periodic 1007 * queue + our new transfer. This is "rough" because we're 1008 * using a function that makes takes into account IN/OUT 1009 * and INT/ISO and we're just slamming in one value for all 1010 * transfers. This should be an over-estimate and that should 1011 * be OK, but we can probably tighten it. 1012 */ 1013 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1014 chan->xfer_len + bytes_in_fifo); 1015 xfer_us = NS_TO_US(xfer_ns); 1016 1017 /* See what frame number we'll be at by the time we finish */ 1018 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1019 1020 /* This is when we were scheduled to be on the wire */ 1021 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1022 1023 /* 1024 * If we'd finish _after_ the frame we're scheduled in then 1025 * it's hopeless. Just schedule right away and hope for the 1026 * best. Note that it _might_ be wise to call back into the 1027 * scheduler to pick a better frame, but this is better than 1028 * nothing. 1029 */ 1030 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1031 dwc2_sch_vdbg(hsotg, 1032 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1033 chan->qh, wire_frame, frame_number, 1034 dwc2_frame_num_dec(frame_number, 1035 wire_frame)); 1036 wire_frame = frame_number; 1037 1038 /* 1039 * We picked a different frame number; communicate this 1040 * back to the scheduler so it doesn't try to schedule 1041 * another in the same frame. 1042 * 1043 * Remember that next_active_frame is 1 before the wire 1044 * frame. 1045 */ 1046 chan->qh->next_active_frame = 1047 dwc2_frame_num_dec(frame_number, 1); 1048 } 1049 1050 if (wire_frame & 1) 1051 *hcchar |= HCCHAR_ODDFRM; 1052 else 1053 *hcchar &= ~HCCHAR_ODDFRM; 1054 } 1055 } 1056 1057 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1058 { 1059 /* Set up the initial PID for the transfer */ 1060 if (chan->speed == USB_SPEED_HIGH) { 1061 if (chan->ep_is_in) { 1062 if (chan->multi_count == 1) 1063 chan->data_pid_start = DWC2_HC_PID_DATA0; 1064 else if (chan->multi_count == 2) 1065 chan->data_pid_start = DWC2_HC_PID_DATA1; 1066 else 1067 chan->data_pid_start = DWC2_HC_PID_DATA2; 1068 } else { 1069 if (chan->multi_count == 1) 1070 chan->data_pid_start = DWC2_HC_PID_DATA0; 1071 else 1072 chan->data_pid_start = DWC2_HC_PID_MDATA; 1073 } 1074 } else { 1075 chan->data_pid_start = DWC2_HC_PID_DATA0; 1076 } 1077 } 1078 1079 /** 1080 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1081 * the Host Channel 1082 * 1083 * @hsotg: Programming view of DWC_otg controller 1084 * @chan: Information needed to initialize the host channel 1085 * 1086 * This function should only be called in Slave mode. For a channel associated 1087 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1088 * associated with a periodic EP, the periodic Tx FIFO is written. 1089 * 1090 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1091 * the number of bytes written to the Tx FIFO. 1092 */ 1093 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1094 struct dwc2_host_chan *chan) 1095 { 1096 u32 i; 1097 u32 remaining_count; 1098 u32 byte_count; 1099 u32 dword_count; 1100 u32 *data_buf = (u32 *)chan->xfer_buf; 1101 1102 if (dbg_hc(chan)) 1103 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1104 1105 remaining_count = chan->xfer_len - chan->xfer_count; 1106 if (remaining_count > chan->max_packet) 1107 byte_count = chan->max_packet; 1108 else 1109 byte_count = remaining_count; 1110 1111 dword_count = (byte_count + 3) / 4; 1112 1113 if (((unsigned long)data_buf & 0x3) == 0) { 1114 /* xfer_buf is DWORD aligned */ 1115 for (i = 0; i < dword_count; i++, data_buf++) 1116 dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num)); 1117 } else { 1118 /* xfer_buf is not DWORD aligned */ 1119 for (i = 0; i < dword_count; i++, data_buf++) { 1120 u32 data = data_buf[0] | data_buf[1] << 8 | 1121 data_buf[2] << 16 | data_buf[3] << 24; 1122 dwc2_writel(hsotg, data, HCFIFO(chan->hc_num)); 1123 } 1124 } 1125 1126 chan->xfer_count += byte_count; 1127 chan->xfer_buf += byte_count; 1128 } 1129 1130 /** 1131 * dwc2_hc_do_ping() - Starts a PING transfer 1132 * 1133 * @hsotg: Programming view of DWC_otg controller 1134 * @chan: Information needed to initialize the host channel 1135 * 1136 * This function should only be called in Slave mode. The Do Ping bit is set in 1137 * the HCTSIZ register, then the channel is enabled. 1138 */ 1139 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1140 struct dwc2_host_chan *chan) 1141 { 1142 u32 hcchar; 1143 u32 hctsiz; 1144 1145 if (dbg_hc(chan)) 1146 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1147 chan->hc_num); 1148 1149 hctsiz = TSIZ_DOPNG; 1150 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1151 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1152 1153 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1154 hcchar |= HCCHAR_CHENA; 1155 hcchar &= ~HCCHAR_CHDIS; 1156 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1157 } 1158 1159 /** 1160 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1161 * channel and starts the transfer 1162 * 1163 * @hsotg: Programming view of DWC_otg controller 1164 * @chan: Information needed to initialize the host channel. The xfer_len value 1165 * may be reduced to accommodate the max widths of the XferSize and 1166 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1167 * changed to reflect the final xfer_len value. 1168 * 1169 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1170 * the caller must ensure that there is sufficient space in the request queue 1171 * and Tx Data FIFO. 1172 * 1173 * For an OUT transfer in Slave mode, it loads a data packet into the 1174 * appropriate FIFO. If necessary, additional data packets are loaded in the 1175 * Host ISR. 1176 * 1177 * For an IN transfer in Slave mode, a data packet is requested. The data 1178 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1179 * additional data packets are requested in the Host ISR. 1180 * 1181 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1182 * register along with a packet count of 1 and the channel is enabled. This 1183 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1184 * simply set to 0 since no data transfer occurs in this case. 1185 * 1186 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1187 * all the information required to perform the subsequent data transfer. In 1188 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1189 * controller performs the entire PING protocol, then starts the data 1190 * transfer. 1191 */ 1192 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1193 struct dwc2_host_chan *chan) 1194 { 1195 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1196 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1197 u32 hcchar; 1198 u32 hctsiz = 0; 1199 u16 num_packets; 1200 u32 ec_mc; 1201 1202 if (dbg_hc(chan)) 1203 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1204 1205 if (chan->do_ping) { 1206 if (!hsotg->params.host_dma) { 1207 if (dbg_hc(chan)) 1208 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1209 dwc2_hc_do_ping(hsotg, chan); 1210 chan->xfer_started = 1; 1211 return; 1212 } 1213 1214 if (dbg_hc(chan)) 1215 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1216 1217 hctsiz |= TSIZ_DOPNG; 1218 } 1219 1220 if (chan->do_split) { 1221 if (dbg_hc(chan)) 1222 dev_vdbg(hsotg->dev, "split\n"); 1223 num_packets = 1; 1224 1225 if (chan->complete_split && !chan->ep_is_in) 1226 /* 1227 * For CSPLIT OUT Transfer, set the size to 0 so the 1228 * core doesn't expect any data written to the FIFO 1229 */ 1230 chan->xfer_len = 0; 1231 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1232 chan->xfer_len = chan->max_packet; 1233 else if (!chan->ep_is_in && chan->xfer_len > 188) 1234 chan->xfer_len = 188; 1235 1236 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1237 TSIZ_XFERSIZE_MASK; 1238 1239 /* For split set ec_mc for immediate retries */ 1240 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1241 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1242 ec_mc = 3; 1243 else 1244 ec_mc = 1; 1245 } else { 1246 if (dbg_hc(chan)) 1247 dev_vdbg(hsotg->dev, "no split\n"); 1248 /* 1249 * Ensure that the transfer length and packet count will fit 1250 * in the widths allocated for them in the HCTSIZn register 1251 */ 1252 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1253 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1254 /* 1255 * Make sure the transfer size is no larger than one 1256 * (micro)frame's worth of data. (A check was done 1257 * when the periodic transfer was accepted to ensure 1258 * that a (micro)frame's worth of data can be 1259 * programmed into a channel.) 1260 */ 1261 u32 max_periodic_len = 1262 chan->multi_count * chan->max_packet; 1263 1264 if (chan->xfer_len > max_periodic_len) 1265 chan->xfer_len = max_periodic_len; 1266 } else if (chan->xfer_len > max_hc_xfer_size) { 1267 /* 1268 * Make sure that xfer_len is a multiple of max packet 1269 * size 1270 */ 1271 chan->xfer_len = 1272 max_hc_xfer_size - chan->max_packet + 1; 1273 } 1274 1275 if (chan->xfer_len > 0) { 1276 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1277 chan->max_packet; 1278 if (num_packets > max_hc_pkt_count) { 1279 num_packets = max_hc_pkt_count; 1280 chan->xfer_len = num_packets * chan->max_packet; 1281 } else if (chan->ep_is_in) { 1282 /* 1283 * Always program an integral # of max packets 1284 * for IN transfers. 1285 * Note: This assumes that the input buffer is 1286 * aligned and sized accordingly. 1287 */ 1288 chan->xfer_len = num_packets * chan->max_packet; 1289 } 1290 } else { 1291 /* Need 1 packet for transfer length of 0 */ 1292 num_packets = 1; 1293 } 1294 1295 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1296 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1297 /* 1298 * Make sure that the multi_count field matches the 1299 * actual transfer length 1300 */ 1301 chan->multi_count = num_packets; 1302 1303 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1304 dwc2_set_pid_isoc(chan); 1305 1306 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1307 TSIZ_XFERSIZE_MASK; 1308 1309 /* The ec_mc gets the multi_count for non-split */ 1310 ec_mc = chan->multi_count; 1311 } 1312 1313 chan->start_pkt_count = num_packets; 1314 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1315 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1316 TSIZ_SC_MC_PID_MASK; 1317 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1318 if (dbg_hc(chan)) { 1319 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1320 hctsiz, chan->hc_num); 1321 1322 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1323 chan->hc_num); 1324 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1325 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1326 TSIZ_XFERSIZE_SHIFT); 1327 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1328 (hctsiz & TSIZ_PKTCNT_MASK) >> 1329 TSIZ_PKTCNT_SHIFT); 1330 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1331 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1332 TSIZ_SC_MC_PID_SHIFT); 1333 } 1334 1335 if (hsotg->params.host_dma) { 1336 dma_addr_t dma_addr; 1337 1338 if (chan->align_buf) { 1339 if (dbg_hc(chan)) 1340 dev_vdbg(hsotg->dev, "align_buf\n"); 1341 dma_addr = chan->align_buf; 1342 } else { 1343 dma_addr = chan->xfer_dma; 1344 } 1345 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num)); 1346 1347 if (dbg_hc(chan)) 1348 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1349 (unsigned long)dma_addr, chan->hc_num); 1350 } 1351 1352 /* Start the split */ 1353 if (chan->do_split) { 1354 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); 1355 1356 hcsplt |= HCSPLT_SPLTENA; 1357 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num)); 1358 } 1359 1360 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1361 hcchar &= ~HCCHAR_MULTICNT_MASK; 1362 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1363 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1364 1365 if (hcchar & HCCHAR_CHDIS) 1366 dev_warn(hsotg->dev, 1367 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1368 __func__, chan->hc_num, hcchar); 1369 1370 /* Set host channel enable after all other setup is complete */ 1371 hcchar |= HCCHAR_CHENA; 1372 hcchar &= ~HCCHAR_CHDIS; 1373 1374 if (dbg_hc(chan)) 1375 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1376 (hcchar & HCCHAR_MULTICNT_MASK) >> 1377 HCCHAR_MULTICNT_SHIFT); 1378 1379 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1380 if (dbg_hc(chan)) 1381 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1382 chan->hc_num); 1383 1384 chan->xfer_started = 1; 1385 chan->requests++; 1386 1387 if (!hsotg->params.host_dma && 1388 !chan->ep_is_in && chan->xfer_len > 0) 1389 /* Load OUT packet into the appropriate Tx FIFO */ 1390 dwc2_hc_write_packet(hsotg, chan); 1391 } 1392 1393 /** 1394 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1395 * host channel and starts the transfer in Descriptor DMA mode 1396 * 1397 * @hsotg: Programming view of DWC_otg controller 1398 * @chan: Information needed to initialize the host channel 1399 * 1400 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1401 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1402 * with micro-frame bitmap. 1403 * 1404 * Initializes HCDMA register with descriptor list address and CTD value then 1405 * starts the transfer via enabling the channel. 1406 */ 1407 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1408 struct dwc2_host_chan *chan) 1409 { 1410 u32 hcchar; 1411 u32 hctsiz = 0; 1412 1413 if (chan->do_ping) 1414 hctsiz |= TSIZ_DOPNG; 1415 1416 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1417 dwc2_set_pid_isoc(chan); 1418 1419 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1420 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1421 TSIZ_SC_MC_PID_MASK; 1422 1423 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1424 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1425 1426 /* Non-zero only for high-speed interrupt endpoints */ 1427 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1428 1429 if (dbg_hc(chan)) { 1430 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1431 chan->hc_num); 1432 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1433 chan->data_pid_start); 1434 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1435 } 1436 1437 dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); 1438 1439 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1440 chan->desc_list_sz, DMA_TO_DEVICE); 1441 1442 dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num)); 1443 1444 if (dbg_hc(chan)) 1445 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1446 &chan->desc_list_addr, chan->hc_num); 1447 1448 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1449 hcchar &= ~HCCHAR_MULTICNT_MASK; 1450 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1451 HCCHAR_MULTICNT_MASK; 1452 1453 if (hcchar & HCCHAR_CHDIS) 1454 dev_warn(hsotg->dev, 1455 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1456 __func__, chan->hc_num, hcchar); 1457 1458 /* Set host channel enable after all other setup is complete */ 1459 hcchar |= HCCHAR_CHENA; 1460 hcchar &= ~HCCHAR_CHDIS; 1461 1462 if (dbg_hc(chan)) 1463 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1464 (hcchar & HCCHAR_MULTICNT_MASK) >> 1465 HCCHAR_MULTICNT_SHIFT); 1466 1467 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1468 if (dbg_hc(chan)) 1469 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1470 chan->hc_num); 1471 1472 chan->xfer_started = 1; 1473 chan->requests++; 1474 } 1475 1476 /** 1477 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1478 * a previous call to dwc2_hc_start_transfer() 1479 * 1480 * @hsotg: Programming view of DWC_otg controller 1481 * @chan: Information needed to initialize the host channel 1482 * 1483 * The caller must ensure there is sufficient space in the request queue and Tx 1484 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1485 * the controller acts autonomously to complete transfers programmed to a host 1486 * channel. 1487 * 1488 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1489 * if there is any data remaining to be queued. For an IN transfer, another 1490 * data packet is always requested. For the SETUP phase of a control transfer, 1491 * this function does nothing. 1492 * 1493 * Return: 1 if a new request is queued, 0 if no more requests are required 1494 * for this transfer 1495 */ 1496 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1497 struct dwc2_host_chan *chan) 1498 { 1499 if (dbg_hc(chan)) 1500 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1501 chan->hc_num); 1502 1503 if (chan->do_split) 1504 /* SPLITs always queue just once per channel */ 1505 return 0; 1506 1507 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1508 /* SETUPs are queued only once since they can't be NAK'd */ 1509 return 0; 1510 1511 if (chan->ep_is_in) { 1512 /* 1513 * Always queue another request for other IN transfers. If 1514 * back-to-back INs are issued and NAKs are received for both, 1515 * the driver may still be processing the first NAK when the 1516 * second NAK is received. When the interrupt handler clears 1517 * the NAK interrupt for the first NAK, the second NAK will 1518 * not be seen. So we can't depend on the NAK interrupt 1519 * handler to requeue a NAK'd request. Instead, IN requests 1520 * are issued each time this function is called. When the 1521 * transfer completes, the extra requests for the channel will 1522 * be flushed. 1523 */ 1524 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); 1525 1526 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1527 hcchar |= HCCHAR_CHENA; 1528 hcchar &= ~HCCHAR_CHDIS; 1529 if (dbg_hc(chan)) 1530 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1531 hcchar); 1532 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); 1533 chan->requests++; 1534 return 1; 1535 } 1536 1537 /* OUT transfers */ 1538 1539 if (chan->xfer_count < chan->xfer_len) { 1540 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1541 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1542 u32 hcchar = dwc2_readl(hsotg, 1543 HCCHAR(chan->hc_num)); 1544 1545 dwc2_hc_set_even_odd_frame(hsotg, chan, 1546 &hcchar); 1547 } 1548 1549 /* Load OUT packet into the appropriate Tx FIFO */ 1550 dwc2_hc_write_packet(hsotg, chan); 1551 chan->requests++; 1552 return 1; 1553 } 1554 1555 return 0; 1556 } 1557 1558 /* 1559 * ========================================================================= 1560 * HCD 1561 * ========================================================================= 1562 */ 1563 1564 /* 1565 * Processes all the URBs in a single list of QHs. Completes them with 1566 * -ETIMEDOUT and frees the QTD. 1567 * 1568 * Must be called with interrupt disabled and spinlock held 1569 */ 1570 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1571 struct list_head *qh_list) 1572 { 1573 struct dwc2_qh *qh, *qh_tmp; 1574 struct dwc2_qtd *qtd, *qtd_tmp; 1575 1576 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1577 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1578 qtd_list_entry) { 1579 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1580 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1581 } 1582 } 1583 } 1584 1585 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1586 struct list_head *qh_list) 1587 { 1588 struct dwc2_qtd *qtd, *qtd_tmp; 1589 struct dwc2_qh *qh, *qh_tmp; 1590 unsigned long flags; 1591 1592 if (!qh_list->next) 1593 /* The list hasn't been initialized yet */ 1594 return; 1595 1596 spin_lock_irqsave(&hsotg->lock, flags); 1597 1598 /* Ensure there are no QTDs or URBs left */ 1599 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1600 1601 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1602 dwc2_hcd_qh_unlink(hsotg, qh); 1603 1604 /* Free each QTD in the QH's QTD list */ 1605 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1606 qtd_list_entry) 1607 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1608 1609 if (qh->channel && qh->channel->qh == qh) 1610 qh->channel->qh = NULL; 1611 1612 spin_unlock_irqrestore(&hsotg->lock, flags); 1613 dwc2_hcd_qh_free(hsotg, qh); 1614 spin_lock_irqsave(&hsotg->lock, flags); 1615 } 1616 1617 spin_unlock_irqrestore(&hsotg->lock, flags); 1618 } 1619 1620 /* 1621 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1622 * and periodic schedules. The QTD associated with each URB is removed from 1623 * the schedule and freed. This function may be called when a disconnect is 1624 * detected or when the HCD is being stopped. 1625 * 1626 * Must be called with interrupt disabled and spinlock held 1627 */ 1628 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1629 { 1630 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1631 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 1632 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1633 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1634 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1635 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1636 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1637 } 1638 1639 /** 1640 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1641 * 1642 * @hsotg: Pointer to struct dwc2_hsotg 1643 */ 1644 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1645 { 1646 u32 hprt0; 1647 1648 if (hsotg->op_state == OTG_STATE_B_HOST) { 1649 /* 1650 * Reset the port. During a HNP mode switch the reset 1651 * needs to occur within 1ms and have a duration of at 1652 * least 50ms. 1653 */ 1654 hprt0 = dwc2_read_hprt0(hsotg); 1655 hprt0 |= HPRT0_RST; 1656 dwc2_writel(hsotg, hprt0, HPRT0); 1657 } 1658 1659 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1660 msecs_to_jiffies(50)); 1661 } 1662 1663 /* Must be called with interrupt disabled and spinlock held */ 1664 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1665 { 1666 int num_channels = hsotg->params.host_channels; 1667 struct dwc2_host_chan *channel; 1668 u32 hcchar; 1669 int i; 1670 1671 if (!hsotg->params.host_dma) { 1672 /* Flush out any channel requests in slave mode */ 1673 for (i = 0; i < num_channels; i++) { 1674 channel = hsotg->hc_ptr_array[i]; 1675 if (!list_empty(&channel->hc_list_entry)) 1676 continue; 1677 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1678 if (hcchar & HCCHAR_CHENA) { 1679 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1680 hcchar |= HCCHAR_CHDIS; 1681 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1682 } 1683 } 1684 } 1685 1686 for (i = 0; i < num_channels; i++) { 1687 channel = hsotg->hc_ptr_array[i]; 1688 if (!list_empty(&channel->hc_list_entry)) 1689 continue; 1690 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 1691 if (hcchar & HCCHAR_CHENA) { 1692 /* Halt the channel */ 1693 hcchar |= HCCHAR_CHDIS; 1694 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 1695 } 1696 1697 dwc2_hc_cleanup(hsotg, channel); 1698 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1699 /* 1700 * Added for Descriptor DMA to prevent channel double cleanup in 1701 * release_channel_ddma(), which is called from ep_disable when 1702 * device disconnects 1703 */ 1704 channel->qh = NULL; 1705 } 1706 /* All channels have been freed, mark them available */ 1707 if (hsotg->params.uframe_sched) { 1708 hsotg->available_host_channels = 1709 hsotg->params.host_channels; 1710 } else { 1711 hsotg->non_periodic_channels = 0; 1712 hsotg->periodic_channels = 0; 1713 } 1714 } 1715 1716 /** 1717 * dwc2_hcd_connect() - Handles connect of the HCD 1718 * 1719 * @hsotg: Pointer to struct dwc2_hsotg 1720 * 1721 * Must be called with interrupt disabled and spinlock held 1722 */ 1723 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1724 { 1725 if (hsotg->lx_state != DWC2_L0) 1726 usb_hcd_resume_root_hub(hsotg->priv); 1727 1728 hsotg->flags.b.port_connect_status_change = 1; 1729 hsotg->flags.b.port_connect_status = 1; 1730 } 1731 1732 /** 1733 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1734 * 1735 * @hsotg: Pointer to struct dwc2_hsotg 1736 * @force: If true, we won't try to reconnect even if we see device connected. 1737 * 1738 * Must be called with interrupt disabled and spinlock held 1739 */ 1740 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1741 { 1742 u32 intr; 1743 u32 hprt0; 1744 1745 /* Set status flags for the hub driver */ 1746 hsotg->flags.b.port_connect_status_change = 1; 1747 hsotg->flags.b.port_connect_status = 0; 1748 1749 /* 1750 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1751 * interrupt mask and status bits and disabling subsequent host 1752 * channel interrupts. 1753 */ 1754 intr = dwc2_readl(hsotg, GINTMSK); 1755 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1756 dwc2_writel(hsotg, intr, GINTMSK); 1757 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1758 dwc2_writel(hsotg, intr, GINTSTS); 1759 1760 /* 1761 * Turn off the vbus power only if the core has transitioned to device 1762 * mode. If still in host mode, need to keep power on to detect a 1763 * reconnection. 1764 */ 1765 if (dwc2_is_device_mode(hsotg)) { 1766 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1767 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1768 dwc2_writel(hsotg, 0, HPRT0); 1769 } 1770 1771 dwc2_disable_host_interrupts(hsotg); 1772 } 1773 1774 /* Respond with an error status to all URBs in the schedule */ 1775 dwc2_kill_all_urbs(hsotg); 1776 1777 if (dwc2_is_host_mode(hsotg)) 1778 /* Clean up any host channels that were in use */ 1779 dwc2_hcd_cleanup_channels(hsotg); 1780 1781 dwc2_host_disconnect(hsotg); 1782 1783 /* 1784 * Add an extra check here to see if we're actually connected but 1785 * we don't have a detection interrupt pending. This can happen if: 1786 * 1. hardware sees connect 1787 * 2. hardware sees disconnect 1788 * 3. hardware sees connect 1789 * 4. dwc2_port_intr() - clears connect interrupt 1790 * 5. dwc2_handle_common_intr() - calls here 1791 * 1792 * Without the extra check here we will end calling disconnect 1793 * and won't get any future interrupts to handle the connect. 1794 */ 1795 if (!force) { 1796 hprt0 = dwc2_readl(hsotg, HPRT0); 1797 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1798 dwc2_hcd_connect(hsotg); 1799 } 1800 } 1801 1802 /** 1803 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1804 * 1805 * @hsotg: Pointer to struct dwc2_hsotg 1806 */ 1807 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1808 { 1809 if (hsotg->bus_suspended) { 1810 hsotg->flags.b.port_suspend_change = 1; 1811 usb_hcd_resume_root_hub(hsotg->priv); 1812 } 1813 1814 if (hsotg->lx_state == DWC2_L1) 1815 hsotg->flags.b.port_l1_change = 1; 1816 } 1817 1818 /** 1819 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1820 * 1821 * @hsotg: Pointer to struct dwc2_hsotg 1822 * 1823 * Must be called with interrupt disabled and spinlock held 1824 */ 1825 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1826 { 1827 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1828 1829 /* 1830 * The root hub should be disconnected before this function is called. 1831 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 1832 * and the QH lists (via ..._hcd_endpoint_disable). 1833 */ 1834 1835 /* Turn off all host-specific interrupts */ 1836 dwc2_disable_host_interrupts(hsotg); 1837 1838 /* Turn off the vbus power */ 1839 dev_dbg(hsotg->dev, "PortPower off\n"); 1840 dwc2_writel(hsotg, 0, HPRT0); 1841 } 1842 1843 /* Caller must hold driver lock */ 1844 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 1845 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 1846 struct dwc2_qtd *qtd) 1847 { 1848 u32 intr_mask; 1849 int retval; 1850 int dev_speed; 1851 1852 if (!hsotg->flags.b.port_connect_status) { 1853 /* No longer connected */ 1854 dev_err(hsotg->dev, "Not connected\n"); 1855 return -ENODEV; 1856 } 1857 1858 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 1859 1860 /* Some configurations cannot support LS traffic on a FS root port */ 1861 if ((dev_speed == USB_SPEED_LOW) && 1862 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 1863 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 1864 u32 hprt0 = dwc2_readl(hsotg, HPRT0); 1865 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1866 1867 if (prtspd == HPRT0_SPD_FULL_SPEED) 1868 return -ENODEV; 1869 } 1870 1871 if (!qtd) 1872 return -EINVAL; 1873 1874 dwc2_hcd_qtd_init(qtd, urb); 1875 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 1876 if (retval) { 1877 dev_err(hsotg->dev, 1878 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 1879 retval); 1880 return retval; 1881 } 1882 1883 intr_mask = dwc2_readl(hsotg, GINTMSK); 1884 if (!(intr_mask & GINTSTS_SOF)) { 1885 enum dwc2_transaction_type tr_type; 1886 1887 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 1888 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 1889 /* 1890 * Do not schedule SG transactions until qtd has 1891 * URB_GIVEBACK_ASAP set 1892 */ 1893 return 0; 1894 1895 tr_type = dwc2_hcd_select_transactions(hsotg); 1896 if (tr_type != DWC2_TRANSACTION_NONE) 1897 dwc2_hcd_queue_transactions(hsotg, tr_type); 1898 } 1899 1900 return 0; 1901 } 1902 1903 /* Must be called with interrupt disabled and spinlock held */ 1904 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 1905 struct dwc2_hcd_urb *urb) 1906 { 1907 struct dwc2_qh *qh; 1908 struct dwc2_qtd *urb_qtd; 1909 1910 urb_qtd = urb->qtd; 1911 if (!urb_qtd) { 1912 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 1913 return -EINVAL; 1914 } 1915 1916 qh = urb_qtd->qh; 1917 if (!qh) { 1918 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 1919 return -EINVAL; 1920 } 1921 1922 urb->priv = NULL; 1923 1924 if (urb_qtd->in_process && qh->channel) { 1925 dwc2_dump_channel_info(hsotg, qh->channel); 1926 1927 /* The QTD is in process (it has been assigned to a channel) */ 1928 if (hsotg->flags.b.port_connect_status) 1929 /* 1930 * If still connected (i.e. in host mode), halt the 1931 * channel so it can be used for other transfers. If 1932 * no longer connected, the host registers can't be 1933 * written to halt the channel since the core is in 1934 * device mode. 1935 */ 1936 dwc2_hc_halt(hsotg, qh->channel, 1937 DWC2_HC_XFER_URB_DEQUEUE); 1938 } 1939 1940 /* 1941 * Free the QTD and clean up the associated QH. Leave the QH in the 1942 * schedule if it has any remaining QTDs. 1943 */ 1944 if (!hsotg->params.dma_desc_enable) { 1945 u8 in_process = urb_qtd->in_process; 1946 1947 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 1948 if (in_process) { 1949 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 1950 qh->channel = NULL; 1951 } else if (list_empty(&qh->qtd_list)) { 1952 dwc2_hcd_qh_unlink(hsotg, qh); 1953 } 1954 } else { 1955 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 1956 } 1957 1958 return 0; 1959 } 1960 1961 /* Must NOT be called with interrupt disabled or spinlock held */ 1962 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 1963 struct usb_host_endpoint *ep, int retry) 1964 { 1965 struct dwc2_qtd *qtd, *qtd_tmp; 1966 struct dwc2_qh *qh; 1967 unsigned long flags; 1968 int rc; 1969 1970 spin_lock_irqsave(&hsotg->lock, flags); 1971 1972 qh = ep->hcpriv; 1973 if (!qh) { 1974 rc = -EINVAL; 1975 goto err; 1976 } 1977 1978 while (!list_empty(&qh->qtd_list) && retry--) { 1979 if (retry == 0) { 1980 dev_err(hsotg->dev, 1981 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 1982 rc = -EBUSY; 1983 goto err; 1984 } 1985 1986 spin_unlock_irqrestore(&hsotg->lock, flags); 1987 msleep(20); 1988 spin_lock_irqsave(&hsotg->lock, flags); 1989 qh = ep->hcpriv; 1990 if (!qh) { 1991 rc = -EINVAL; 1992 goto err; 1993 } 1994 } 1995 1996 dwc2_hcd_qh_unlink(hsotg, qh); 1997 1998 /* Free each QTD in the QH's QTD list */ 1999 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2000 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2001 2002 ep->hcpriv = NULL; 2003 2004 if (qh->channel && qh->channel->qh == qh) 2005 qh->channel->qh = NULL; 2006 2007 spin_unlock_irqrestore(&hsotg->lock, flags); 2008 2009 dwc2_hcd_qh_free(hsotg, qh); 2010 2011 return 0; 2012 2013 err: 2014 ep->hcpriv = NULL; 2015 spin_unlock_irqrestore(&hsotg->lock, flags); 2016 2017 return rc; 2018 } 2019 2020 /* Must be called with interrupt disabled and spinlock held */ 2021 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2022 struct usb_host_endpoint *ep) 2023 { 2024 struct dwc2_qh *qh = ep->hcpriv; 2025 2026 if (!qh) 2027 return -EINVAL; 2028 2029 qh->data_toggle = DWC2_HC_PID_DATA0; 2030 2031 return 0; 2032 } 2033 2034 /** 2035 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2036 * prepares the core for device mode or host mode operation 2037 * 2038 * @hsotg: Programming view of the DWC_otg controller 2039 * @initial_setup: If true then this is the first init for this instance. 2040 */ 2041 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2042 { 2043 u32 usbcfg, otgctl; 2044 int retval; 2045 2046 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2047 2048 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2049 2050 /* Set ULPI External VBUS bit if needed */ 2051 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2052 if (hsotg->params.phy_ulpi_ext_vbus) 2053 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2054 2055 /* Set external TS Dline pulsing bit if needed */ 2056 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2057 if (hsotg->params.ts_dline) 2058 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2059 2060 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2061 2062 /* 2063 * Reset the Controller 2064 * 2065 * We only need to reset the controller if this is a re-init. 2066 * For the first init we know for sure that earlier code reset us (it 2067 * needed to in order to properly detect various parameters). 2068 */ 2069 if (!initial_setup) { 2070 retval = dwc2_core_reset(hsotg, false); 2071 if (retval) { 2072 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2073 __func__); 2074 return retval; 2075 } 2076 } 2077 2078 /* 2079 * This needs to happen in FS mode before any other programming occurs 2080 */ 2081 retval = dwc2_phy_init(hsotg, initial_setup); 2082 if (retval) 2083 return retval; 2084 2085 /* Program the GAHBCFG Register */ 2086 retval = dwc2_gahbcfg_init(hsotg); 2087 if (retval) 2088 return retval; 2089 2090 /* Program the GUSBCFG register */ 2091 dwc2_gusbcfg_init(hsotg); 2092 2093 /* Program the GOTGCTL register */ 2094 otgctl = dwc2_readl(hsotg, GOTGCTL); 2095 otgctl &= ~GOTGCTL_OTGVER; 2096 dwc2_writel(hsotg, otgctl, GOTGCTL); 2097 2098 /* Clear the SRP success bit for FS-I2c */ 2099 hsotg->srp_success = 0; 2100 2101 /* Enable common interrupts */ 2102 dwc2_enable_common_interrupts(hsotg); 2103 2104 /* 2105 * Do device or host initialization based on mode during PCD and 2106 * HCD initialization 2107 */ 2108 if (dwc2_is_host_mode(hsotg)) { 2109 dev_dbg(hsotg->dev, "Host Mode\n"); 2110 hsotg->op_state = OTG_STATE_A_HOST; 2111 } else { 2112 dev_dbg(hsotg->dev, "Device Mode\n"); 2113 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2114 } 2115 2116 return 0; 2117 } 2118 2119 /** 2120 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2121 * Host mode 2122 * 2123 * @hsotg: Programming view of DWC_otg controller 2124 * 2125 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2126 * request queues. Host channels are reset to ensure that they are ready for 2127 * performing transfers. 2128 */ 2129 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2130 { 2131 u32 hcfg, hfir, otgctl, usbcfg; 2132 2133 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2134 2135 /* Set HS/FS Timeout Calibration to 7 (max available value). 2136 * The number of PHY clocks that the application programs in 2137 * this field is added to the high/full speed interpacket timeout 2138 * duration in the core to account for any additional delays 2139 * introduced by the PHY. This can be required, because the delay 2140 * introduced by the PHY in generating the linestate condition 2141 * can vary from one PHY to another. 2142 */ 2143 usbcfg = dwc2_readl(hsotg, GUSBCFG); 2144 usbcfg |= GUSBCFG_TOUTCAL(7); 2145 dwc2_writel(hsotg, usbcfg, GUSBCFG); 2146 2147 /* Restart the Phy Clock */ 2148 dwc2_writel(hsotg, 0, PCGCTL); 2149 2150 /* Initialize Host Configuration Register */ 2151 dwc2_init_fs_ls_pclk_sel(hsotg); 2152 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2153 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2154 hcfg = dwc2_readl(hsotg, HCFG); 2155 hcfg |= HCFG_FSLSSUPP; 2156 dwc2_writel(hsotg, hcfg, HCFG); 2157 } 2158 2159 /* 2160 * This bit allows dynamic reloading of the HFIR register during 2161 * runtime. This bit needs to be programmed during initial configuration 2162 * and its value must not be changed during runtime. 2163 */ 2164 if (hsotg->params.reload_ctl) { 2165 hfir = dwc2_readl(hsotg, HFIR); 2166 hfir |= HFIR_RLDCTRL; 2167 dwc2_writel(hsotg, hfir, HFIR); 2168 } 2169 2170 if (hsotg->params.dma_desc_enable) { 2171 u32 op_mode = hsotg->hw_params.op_mode; 2172 2173 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2174 !hsotg->hw_params.dma_desc_enable || 2175 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2176 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2177 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2178 dev_err(hsotg->dev, 2179 "Hardware does not support descriptor DMA mode -\n"); 2180 dev_err(hsotg->dev, 2181 "falling back to buffer DMA mode.\n"); 2182 hsotg->params.dma_desc_enable = false; 2183 } else { 2184 hcfg = dwc2_readl(hsotg, HCFG); 2185 hcfg |= HCFG_DESCDMA; 2186 dwc2_writel(hsotg, hcfg, HCFG); 2187 } 2188 } 2189 2190 /* Configure data FIFO sizes */ 2191 dwc2_config_fifos(hsotg); 2192 2193 /* TODO - check this */ 2194 /* Clear Host Set HNP Enable in the OTG Control Register */ 2195 otgctl = dwc2_readl(hsotg, GOTGCTL); 2196 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2197 dwc2_writel(hsotg, otgctl, GOTGCTL); 2198 2199 /* Make sure the FIFOs are flushed */ 2200 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2201 dwc2_flush_rx_fifo(hsotg); 2202 2203 /* Clear Host Set HNP Enable in the OTG Control Register */ 2204 otgctl = dwc2_readl(hsotg, GOTGCTL); 2205 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2206 dwc2_writel(hsotg, otgctl, GOTGCTL); 2207 2208 if (!hsotg->params.dma_desc_enable) { 2209 int num_channels, i; 2210 u32 hcchar; 2211 2212 /* Flush out any leftover queued requests */ 2213 num_channels = hsotg->params.host_channels; 2214 for (i = 0; i < num_channels; i++) { 2215 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2216 if (hcchar & HCCHAR_CHENA) { 2217 hcchar &= ~HCCHAR_CHENA; 2218 hcchar |= HCCHAR_CHDIS; 2219 hcchar &= ~HCCHAR_EPDIR; 2220 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2221 } 2222 } 2223 2224 /* Halt all channels to put them into a known state */ 2225 for (i = 0; i < num_channels; i++) { 2226 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 2227 if (hcchar & HCCHAR_CHENA) { 2228 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2229 hcchar &= ~HCCHAR_EPDIR; 2230 dwc2_writel(hsotg, hcchar, HCCHAR(i)); 2231 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2232 __func__, i); 2233 2234 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), 2235 HCCHAR_CHENA, 2236 1000)) { 2237 dev_warn(hsotg->dev, 2238 "Unable to clear enable on channel %d\n", 2239 i); 2240 } 2241 } 2242 } 2243 } 2244 2245 /* Enable ACG feature in host mode, if supported */ 2246 dwc2_enable_acg(hsotg); 2247 2248 /* Turn on the vbus power */ 2249 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2250 if (hsotg->op_state == OTG_STATE_A_HOST) { 2251 u32 hprt0 = dwc2_read_hprt0(hsotg); 2252 2253 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2254 !!(hprt0 & HPRT0_PWR)); 2255 if (!(hprt0 & HPRT0_PWR)) { 2256 hprt0 |= HPRT0_PWR; 2257 dwc2_writel(hsotg, hprt0, HPRT0); 2258 } 2259 } 2260 2261 dwc2_enable_host_interrupts(hsotg); 2262 } 2263 2264 /* 2265 * Initializes dynamic portions of the DWC_otg HCD state 2266 * 2267 * Must be called with interrupt disabled and spinlock held 2268 */ 2269 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2270 { 2271 struct dwc2_host_chan *chan, *chan_tmp; 2272 int num_channels; 2273 int i; 2274 2275 hsotg->flags.d32 = 0; 2276 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2277 2278 if (hsotg->params.uframe_sched) { 2279 hsotg->available_host_channels = 2280 hsotg->params.host_channels; 2281 } else { 2282 hsotg->non_periodic_channels = 0; 2283 hsotg->periodic_channels = 0; 2284 } 2285 2286 /* 2287 * Put all channels in the free channel list and clean up channel 2288 * states 2289 */ 2290 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2291 hc_list_entry) 2292 list_del_init(&chan->hc_list_entry); 2293 2294 num_channels = hsotg->params.host_channels; 2295 for (i = 0; i < num_channels; i++) { 2296 chan = hsotg->hc_ptr_array[i]; 2297 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2298 dwc2_hc_cleanup(hsotg, chan); 2299 } 2300 2301 /* Initialize the DWC core for host mode operation */ 2302 dwc2_core_host_init(hsotg); 2303 } 2304 2305 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2306 struct dwc2_host_chan *chan, 2307 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2308 { 2309 int hub_addr, hub_port; 2310 2311 chan->do_split = 1; 2312 chan->xact_pos = qtd->isoc_split_pos; 2313 chan->complete_split = qtd->complete_split; 2314 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2315 chan->hub_addr = (u8)hub_addr; 2316 chan->hub_port = (u8)hub_port; 2317 } 2318 2319 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2320 struct dwc2_host_chan *chan, 2321 struct dwc2_qtd *qtd) 2322 { 2323 struct dwc2_hcd_urb *urb = qtd->urb; 2324 struct dwc2_hcd_iso_packet_desc *frame_desc; 2325 2326 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2327 case USB_ENDPOINT_XFER_CONTROL: 2328 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2329 2330 switch (qtd->control_phase) { 2331 case DWC2_CONTROL_SETUP: 2332 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2333 chan->do_ping = 0; 2334 chan->ep_is_in = 0; 2335 chan->data_pid_start = DWC2_HC_PID_SETUP; 2336 if (hsotg->params.host_dma) 2337 chan->xfer_dma = urb->setup_dma; 2338 else 2339 chan->xfer_buf = urb->setup_packet; 2340 chan->xfer_len = 8; 2341 break; 2342 2343 case DWC2_CONTROL_DATA: 2344 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2345 chan->data_pid_start = qtd->data_toggle; 2346 break; 2347 2348 case DWC2_CONTROL_STATUS: 2349 /* 2350 * Direction is opposite of data direction or IN if no 2351 * data 2352 */ 2353 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2354 if (urb->length == 0) 2355 chan->ep_is_in = 1; 2356 else 2357 chan->ep_is_in = 2358 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2359 if (chan->ep_is_in) 2360 chan->do_ping = 0; 2361 chan->data_pid_start = DWC2_HC_PID_DATA1; 2362 chan->xfer_len = 0; 2363 if (hsotg->params.host_dma) 2364 chan->xfer_dma = hsotg->status_buf_dma; 2365 else 2366 chan->xfer_buf = hsotg->status_buf; 2367 break; 2368 } 2369 break; 2370 2371 case USB_ENDPOINT_XFER_BULK: 2372 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2373 break; 2374 2375 case USB_ENDPOINT_XFER_INT: 2376 chan->ep_type = USB_ENDPOINT_XFER_INT; 2377 break; 2378 2379 case USB_ENDPOINT_XFER_ISOC: 2380 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2381 if (hsotg->params.dma_desc_enable) 2382 break; 2383 2384 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2385 frame_desc->status = 0; 2386 2387 if (hsotg->params.host_dma) { 2388 chan->xfer_dma = urb->dma; 2389 chan->xfer_dma += frame_desc->offset + 2390 qtd->isoc_split_offset; 2391 } else { 2392 chan->xfer_buf = urb->buf; 2393 chan->xfer_buf += frame_desc->offset + 2394 qtd->isoc_split_offset; 2395 } 2396 2397 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2398 2399 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2400 if (chan->xfer_len <= 188) 2401 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2402 else 2403 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2404 } 2405 break; 2406 } 2407 } 2408 2409 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg, 2410 struct dwc2_qh *qh, 2411 struct dwc2_host_chan *chan) 2412 { 2413 if (!hsotg->unaligned_cache || 2414 chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE) 2415 return -ENOMEM; 2416 2417 if (!qh->dw_align_buf) { 2418 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache, 2419 GFP_ATOMIC | GFP_DMA); 2420 if (!qh->dw_align_buf) 2421 return -ENOMEM; 2422 } 2423 2424 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf, 2425 DWC2_KMEM_UNALIGNED_BUF_SIZE, 2426 DMA_FROM_DEVICE); 2427 2428 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 2429 dev_err(hsotg->dev, "can't map align_buf\n"); 2430 chan->align_buf = 0; 2431 return -EINVAL; 2432 } 2433 2434 chan->align_buf = qh->dw_align_buf_dma; 2435 return 0; 2436 } 2437 2438 #define DWC2_USB_DMA_ALIGN 4 2439 2440 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2441 { 2442 void *stored_xfer_buffer; 2443 size_t length; 2444 2445 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2446 return; 2447 2448 /* Restore urb->transfer_buffer from the end of the allocated area */ 2449 memcpy(&stored_xfer_buffer, 2450 PTR_ALIGN(urb->transfer_buffer + urb->transfer_buffer_length, 2451 dma_get_cache_alignment()), 2452 sizeof(urb->transfer_buffer)); 2453 2454 if (usb_urb_dir_in(urb)) { 2455 if (usb_pipeisoc(urb->pipe)) 2456 length = urb->transfer_buffer_length; 2457 else 2458 length = urb->actual_length; 2459 2460 memcpy(stored_xfer_buffer, urb->transfer_buffer, length); 2461 } 2462 kfree(urb->transfer_buffer); 2463 urb->transfer_buffer = stored_xfer_buffer; 2464 2465 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2466 } 2467 2468 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2469 { 2470 void *kmalloc_ptr; 2471 size_t kmalloc_size; 2472 2473 if (urb->num_sgs || urb->sg || 2474 urb->transfer_buffer_length == 0 || 2475 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2476 return 0; 2477 2478 /* 2479 * Allocate a buffer with enough padding for original transfer_buffer 2480 * pointer. This allocation is guaranteed to be aligned properly for 2481 * DMA 2482 */ 2483 kmalloc_size = urb->transfer_buffer_length + 2484 (dma_get_cache_alignment() - 1) + 2485 sizeof(urb->transfer_buffer); 2486 2487 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2488 if (!kmalloc_ptr) 2489 return -ENOMEM; 2490 2491 /* 2492 * Position value of original urb->transfer_buffer pointer to the end 2493 * of allocation for later referencing 2494 */ 2495 memcpy(PTR_ALIGN(kmalloc_ptr + urb->transfer_buffer_length, 2496 dma_get_cache_alignment()), 2497 &urb->transfer_buffer, sizeof(urb->transfer_buffer)); 2498 2499 if (usb_urb_dir_out(urb)) 2500 memcpy(kmalloc_ptr, urb->transfer_buffer, 2501 urb->transfer_buffer_length); 2502 urb->transfer_buffer = kmalloc_ptr; 2503 2504 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2505 2506 return 0; 2507 } 2508 2509 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2510 gfp_t mem_flags) 2511 { 2512 int ret; 2513 2514 /* We assume setup_dma is always aligned; warn if not */ 2515 WARN_ON_ONCE(urb->setup_dma && 2516 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2517 2518 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2519 if (ret) 2520 return ret; 2521 2522 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2523 if (ret) 2524 dwc2_free_dma_aligned_buffer(urb); 2525 2526 return ret; 2527 } 2528 2529 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2530 { 2531 usb_hcd_unmap_urb_for_dma(hcd, urb); 2532 dwc2_free_dma_aligned_buffer(urb); 2533 } 2534 2535 /** 2536 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2537 * channel and initializes the host channel to perform the transactions. The 2538 * host channel is removed from the free list. 2539 * 2540 * @hsotg: The HCD state structure 2541 * @qh: Transactions from the first QTD for this QH are selected and assigned 2542 * to a free host channel 2543 */ 2544 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2545 { 2546 struct dwc2_host_chan *chan; 2547 struct dwc2_hcd_urb *urb; 2548 struct dwc2_qtd *qtd; 2549 2550 if (dbg_qh(qh)) 2551 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2552 2553 if (list_empty(&qh->qtd_list)) { 2554 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2555 return -ENOMEM; 2556 } 2557 2558 if (list_empty(&hsotg->free_hc_list)) { 2559 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2560 return -ENOMEM; 2561 } 2562 2563 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2564 hc_list_entry); 2565 2566 /* Remove host channel from free list */ 2567 list_del_init(&chan->hc_list_entry); 2568 2569 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2570 urb = qtd->urb; 2571 qh->channel = chan; 2572 qtd->in_process = 1; 2573 2574 /* 2575 * Use usb_pipedevice to determine device address. This address is 2576 * 0 before the SET_ADDRESS command and the correct address afterward. 2577 */ 2578 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2579 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2580 chan->speed = qh->dev_speed; 2581 chan->max_packet = qh->maxp; 2582 2583 chan->xfer_started = 0; 2584 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2585 chan->error_state = (qtd->error_count > 0); 2586 chan->halt_on_queue = 0; 2587 chan->halt_pending = 0; 2588 chan->requests = 0; 2589 2590 /* 2591 * The following values may be modified in the transfer type section 2592 * below. The xfer_len value may be reduced when the transfer is 2593 * started to accommodate the max widths of the XferSize and PktCnt 2594 * fields in the HCTSIZn register. 2595 */ 2596 2597 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2598 if (chan->ep_is_in) 2599 chan->do_ping = 0; 2600 else 2601 chan->do_ping = qh->ping_state; 2602 2603 chan->data_pid_start = qh->data_toggle; 2604 chan->multi_count = 1; 2605 2606 if (urb->actual_length > urb->length && 2607 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2608 urb->actual_length = urb->length; 2609 2610 if (hsotg->params.host_dma) 2611 chan->xfer_dma = urb->dma + urb->actual_length; 2612 else 2613 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2614 2615 chan->xfer_len = urb->length - urb->actual_length; 2616 chan->xfer_count = 0; 2617 2618 /* Set the split attributes if required */ 2619 if (qh->do_split) 2620 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2621 else 2622 chan->do_split = 0; 2623 2624 /* Set the transfer attributes */ 2625 dwc2_hc_init_xfer(hsotg, chan, qtd); 2626 2627 /* For non-dword aligned buffers */ 2628 if (hsotg->params.host_dma && qh->do_split && 2629 chan->ep_is_in && (chan->xfer_dma & 0x3)) { 2630 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 2631 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) { 2632 dev_err(hsotg->dev, 2633 "Failed to allocate memory to handle non-aligned buffer\n"); 2634 /* Add channel back to free list */ 2635 chan->align_buf = 0; 2636 chan->multi_count = 0; 2637 list_add_tail(&chan->hc_list_entry, 2638 &hsotg->free_hc_list); 2639 qtd->in_process = 0; 2640 qh->channel = NULL; 2641 return -ENOMEM; 2642 } 2643 } else { 2644 /* 2645 * We assume that DMA is always aligned in non-split 2646 * case or split out case. Warn if not. 2647 */ 2648 WARN_ON_ONCE(hsotg->params.host_dma && 2649 (chan->xfer_dma & 0x3)); 2650 chan->align_buf = 0; 2651 } 2652 2653 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2654 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2655 /* 2656 * This value may be modified when the transfer is started 2657 * to reflect the actual transfer length 2658 */ 2659 chan->multi_count = qh->maxp_mult; 2660 2661 if (hsotg->params.dma_desc_enable) { 2662 chan->desc_list_addr = qh->desc_list_dma; 2663 chan->desc_list_sz = qh->desc_list_sz; 2664 } 2665 2666 dwc2_hc_init(hsotg, chan); 2667 chan->qh = qh; 2668 2669 return 0; 2670 } 2671 2672 /** 2673 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2674 * schedule and assigns them to available host channels. Called from the HCD 2675 * interrupt handler functions. 2676 * 2677 * @hsotg: The HCD state structure 2678 * 2679 * Return: The types of new transactions that were assigned to host channels 2680 */ 2681 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2682 struct dwc2_hsotg *hsotg) 2683 { 2684 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2685 struct list_head *qh_ptr; 2686 struct dwc2_qh *qh; 2687 int num_channels; 2688 2689 #ifdef DWC2_DEBUG_SOF 2690 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2691 #endif 2692 2693 /* Process entries in the periodic ready list */ 2694 qh_ptr = hsotg->periodic_sched_ready.next; 2695 while (qh_ptr != &hsotg->periodic_sched_ready) { 2696 if (list_empty(&hsotg->free_hc_list)) 2697 break; 2698 if (hsotg->params.uframe_sched) { 2699 if (hsotg->available_host_channels <= 1) 2700 break; 2701 hsotg->available_host_channels--; 2702 } 2703 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2704 if (dwc2_assign_and_init_hc(hsotg, qh)) 2705 break; 2706 2707 /* 2708 * Move the QH from the periodic ready schedule to the 2709 * periodic assigned schedule 2710 */ 2711 qh_ptr = qh_ptr->next; 2712 list_move_tail(&qh->qh_list_entry, 2713 &hsotg->periodic_sched_assigned); 2714 ret_val = DWC2_TRANSACTION_PERIODIC; 2715 } 2716 2717 /* 2718 * Process entries in the inactive portion of the non-periodic 2719 * schedule. Some free host channels may not be used if they are 2720 * reserved for periodic transfers. 2721 */ 2722 num_channels = hsotg->params.host_channels; 2723 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2724 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2725 if (!hsotg->params.uframe_sched && 2726 hsotg->non_periodic_channels >= num_channels - 2727 hsotg->periodic_channels) 2728 break; 2729 if (list_empty(&hsotg->free_hc_list)) 2730 break; 2731 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2732 if (hsotg->params.uframe_sched) { 2733 if (hsotg->available_host_channels < 1) 2734 break; 2735 hsotg->available_host_channels--; 2736 } 2737 2738 if (dwc2_assign_and_init_hc(hsotg, qh)) 2739 break; 2740 2741 /* 2742 * Move the QH from the non-periodic inactive schedule to the 2743 * non-periodic active schedule 2744 */ 2745 qh_ptr = qh_ptr->next; 2746 list_move_tail(&qh->qh_list_entry, 2747 &hsotg->non_periodic_sched_active); 2748 2749 if (ret_val == DWC2_TRANSACTION_NONE) 2750 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2751 else 2752 ret_val = DWC2_TRANSACTION_ALL; 2753 2754 if (!hsotg->params.uframe_sched) 2755 hsotg->non_periodic_channels++; 2756 } 2757 2758 return ret_val; 2759 } 2760 2761 /** 2762 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2763 * a host channel associated with either a periodic or non-periodic transfer 2764 * 2765 * @hsotg: The HCD state structure 2766 * @chan: Host channel descriptor associated with either a periodic or 2767 * non-periodic transfer 2768 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2769 * for periodic transfers or the non-periodic Tx FIFO 2770 * for non-periodic transfers 2771 * 2772 * Return: 1 if a request is queued and more requests may be needed to 2773 * complete the transfer, 0 if no more requests are required for this 2774 * transfer, -1 if there is insufficient space in the Tx FIFO 2775 * 2776 * This function assumes that there is space available in the appropriate 2777 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2778 * it checks whether space is available in the appropriate Tx FIFO. 2779 * 2780 * Must be called with interrupt disabled and spinlock held 2781 */ 2782 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2783 struct dwc2_host_chan *chan, 2784 u16 fifo_dwords_avail) 2785 { 2786 int retval = 0; 2787 2788 if (chan->do_split) 2789 /* Put ourselves on the list to keep order straight */ 2790 list_move_tail(&chan->split_order_list_entry, 2791 &hsotg->split_order); 2792 2793 if (hsotg->params.host_dma && chan->qh) { 2794 if (hsotg->params.dma_desc_enable) { 2795 if (!chan->xfer_started || 2796 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2797 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2798 chan->qh->ping_state = 0; 2799 } 2800 } else if (!chan->xfer_started) { 2801 dwc2_hc_start_transfer(hsotg, chan); 2802 chan->qh->ping_state = 0; 2803 } 2804 } else if (chan->halt_pending) { 2805 /* Don't queue a request if the channel has been halted */ 2806 } else if (chan->halt_on_queue) { 2807 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2808 } else if (chan->do_ping) { 2809 if (!chan->xfer_started) 2810 dwc2_hc_start_transfer(hsotg, chan); 2811 } else if (!chan->ep_is_in || 2812 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2813 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2814 if (!chan->xfer_started) { 2815 dwc2_hc_start_transfer(hsotg, chan); 2816 retval = 1; 2817 } else { 2818 retval = dwc2_hc_continue_transfer(hsotg, chan); 2819 } 2820 } else { 2821 retval = -1; 2822 } 2823 } else { 2824 if (!chan->xfer_started) { 2825 dwc2_hc_start_transfer(hsotg, chan); 2826 retval = 1; 2827 } else { 2828 retval = dwc2_hc_continue_transfer(hsotg, chan); 2829 } 2830 } 2831 2832 return retval; 2833 } 2834 2835 /* 2836 * Processes periodic channels for the next frame and queues transactions for 2837 * these channels to the DWC_otg controller. After queueing transactions, the 2838 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2839 * to queue as Periodic Tx FIFO or request queue space becomes available. 2840 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2841 * 2842 * Must be called with interrupt disabled and spinlock held 2843 */ 2844 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2845 { 2846 struct list_head *qh_ptr; 2847 struct dwc2_qh *qh; 2848 u32 tx_status; 2849 u32 fspcavail; 2850 u32 gintmsk; 2851 int status; 2852 bool no_queue_space = false; 2853 bool no_fifo_space = false; 2854 u32 qspcavail; 2855 2856 /* If empty list then just adjust interrupt enables */ 2857 if (list_empty(&hsotg->periodic_sched_assigned)) 2858 goto exit; 2859 2860 if (dbg_perio()) 2861 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2862 2863 tx_status = dwc2_readl(hsotg, HPTXSTS); 2864 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2865 TXSTS_QSPCAVAIL_SHIFT; 2866 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2867 TXSTS_FSPCAVAIL_SHIFT; 2868 2869 if (dbg_perio()) { 2870 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2871 qspcavail); 2872 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2873 fspcavail); 2874 } 2875 2876 qh_ptr = hsotg->periodic_sched_assigned.next; 2877 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2878 tx_status = dwc2_readl(hsotg, HPTXSTS); 2879 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2880 TXSTS_QSPCAVAIL_SHIFT; 2881 if (qspcavail == 0) { 2882 no_queue_space = true; 2883 break; 2884 } 2885 2886 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2887 if (!qh->channel) { 2888 qh_ptr = qh_ptr->next; 2889 continue; 2890 } 2891 2892 /* Make sure EP's TT buffer is clean before queueing qtds */ 2893 if (qh->tt_buffer_dirty) { 2894 qh_ptr = qh_ptr->next; 2895 continue; 2896 } 2897 2898 /* 2899 * Set a flag if we're queuing high-bandwidth in slave mode. 2900 * The flag prevents any halts to get into the request queue in 2901 * the middle of multiple high-bandwidth packets getting queued. 2902 */ 2903 if (!hsotg->params.host_dma && 2904 qh->channel->multi_count > 1) 2905 hsotg->queuing_high_bandwidth = 1; 2906 2907 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2908 TXSTS_FSPCAVAIL_SHIFT; 2909 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2910 if (status < 0) { 2911 no_fifo_space = true; 2912 break; 2913 } 2914 2915 /* 2916 * In Slave mode, stay on the current transfer until there is 2917 * nothing more to do or the high-bandwidth request count is 2918 * reached. In DMA mode, only need to queue one request. The 2919 * controller automatically handles multiple packets for 2920 * high-bandwidth transfers. 2921 */ 2922 if (hsotg->params.host_dma || status == 0 || 2923 qh->channel->requests == qh->channel->multi_count) { 2924 qh_ptr = qh_ptr->next; 2925 /* 2926 * Move the QH from the periodic assigned schedule to 2927 * the periodic queued schedule 2928 */ 2929 list_move_tail(&qh->qh_list_entry, 2930 &hsotg->periodic_sched_queued); 2931 2932 /* done queuing high bandwidth */ 2933 hsotg->queuing_high_bandwidth = 0; 2934 } 2935 } 2936 2937 exit: 2938 if (no_queue_space || no_fifo_space || 2939 (!hsotg->params.host_dma && 2940 !list_empty(&hsotg->periodic_sched_assigned))) { 2941 /* 2942 * May need to queue more transactions as the request 2943 * queue or Tx FIFO empties. Enable the periodic Tx 2944 * FIFO empty interrupt. (Always use the half-empty 2945 * level to ensure that new requests are loaded as 2946 * soon as possible.) 2947 */ 2948 gintmsk = dwc2_readl(hsotg, GINTMSK); 2949 if (!(gintmsk & GINTSTS_PTXFEMP)) { 2950 gintmsk |= GINTSTS_PTXFEMP; 2951 dwc2_writel(hsotg, gintmsk, GINTMSK); 2952 } 2953 } else { 2954 /* 2955 * Disable the Tx FIFO empty interrupt since there are 2956 * no more transactions that need to be queued right 2957 * now. This function is called from interrupt 2958 * handlers to queue more transactions as transfer 2959 * states change. 2960 */ 2961 gintmsk = dwc2_readl(hsotg, GINTMSK); 2962 if (gintmsk & GINTSTS_PTXFEMP) { 2963 gintmsk &= ~GINTSTS_PTXFEMP; 2964 dwc2_writel(hsotg, gintmsk, GINTMSK); 2965 } 2966 } 2967 } 2968 2969 /* 2970 * Processes active non-periodic channels and queues transactions for these 2971 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 2972 * FIFO Empty interrupt is enabled if there are more transactions to queue as 2973 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 2974 * FIFO Empty interrupt is disabled. 2975 * 2976 * Must be called with interrupt disabled and spinlock held 2977 */ 2978 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 2979 { 2980 struct list_head *orig_qh_ptr; 2981 struct dwc2_qh *qh; 2982 u32 tx_status; 2983 u32 qspcavail; 2984 u32 fspcavail; 2985 u32 gintmsk; 2986 int status; 2987 int no_queue_space = 0; 2988 int no_fifo_space = 0; 2989 int more_to_do = 0; 2990 2991 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 2992 2993 tx_status = dwc2_readl(hsotg, GNPTXSTS); 2994 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2995 TXSTS_QSPCAVAIL_SHIFT; 2996 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2997 TXSTS_FSPCAVAIL_SHIFT; 2998 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 2999 qspcavail); 3000 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3001 fspcavail); 3002 3003 /* 3004 * Keep track of the starting point. Skip over the start-of-list 3005 * entry. 3006 */ 3007 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3008 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3009 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3010 3011 /* 3012 * Process once through the active list or until no more space is 3013 * available in the request queue or the Tx FIFO 3014 */ 3015 do { 3016 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3017 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3018 TXSTS_QSPCAVAIL_SHIFT; 3019 if (!hsotg->params.host_dma && qspcavail == 0) { 3020 no_queue_space = 1; 3021 break; 3022 } 3023 3024 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3025 qh_list_entry); 3026 if (!qh->channel) 3027 goto next; 3028 3029 /* Make sure EP's TT buffer is clean before queueing qtds */ 3030 if (qh->tt_buffer_dirty) 3031 goto next; 3032 3033 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3034 TXSTS_FSPCAVAIL_SHIFT; 3035 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3036 3037 if (status > 0) { 3038 more_to_do = 1; 3039 } else if (status < 0) { 3040 no_fifo_space = 1; 3041 break; 3042 } 3043 next: 3044 /* Advance to next QH, skipping start-of-list entry */ 3045 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3046 if (hsotg->non_periodic_qh_ptr == 3047 &hsotg->non_periodic_sched_active) 3048 hsotg->non_periodic_qh_ptr = 3049 hsotg->non_periodic_qh_ptr->next; 3050 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3051 3052 if (!hsotg->params.host_dma) { 3053 tx_status = dwc2_readl(hsotg, GNPTXSTS); 3054 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3055 TXSTS_QSPCAVAIL_SHIFT; 3056 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3057 TXSTS_FSPCAVAIL_SHIFT; 3058 dev_vdbg(hsotg->dev, 3059 " NP Tx Req Queue Space Avail (after queue): %d\n", 3060 qspcavail); 3061 dev_vdbg(hsotg->dev, 3062 " NP Tx FIFO Space Avail (after queue): %d\n", 3063 fspcavail); 3064 3065 if (more_to_do || no_queue_space || no_fifo_space) { 3066 /* 3067 * May need to queue more transactions as the request 3068 * queue or Tx FIFO empties. Enable the non-periodic 3069 * Tx FIFO empty interrupt. (Always use the half-empty 3070 * level to ensure that new requests are loaded as 3071 * soon as possible.) 3072 */ 3073 gintmsk = dwc2_readl(hsotg, GINTMSK); 3074 gintmsk |= GINTSTS_NPTXFEMP; 3075 dwc2_writel(hsotg, gintmsk, GINTMSK); 3076 } else { 3077 /* 3078 * Disable the Tx FIFO empty interrupt since there are 3079 * no more transactions that need to be queued right 3080 * now. This function is called from interrupt 3081 * handlers to queue more transactions as transfer 3082 * states change. 3083 */ 3084 gintmsk = dwc2_readl(hsotg, GINTMSK); 3085 gintmsk &= ~GINTSTS_NPTXFEMP; 3086 dwc2_writel(hsotg, gintmsk, GINTMSK); 3087 } 3088 } 3089 } 3090 3091 /** 3092 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3093 * and queues transactions for these channels to the DWC_otg controller. Called 3094 * from the HCD interrupt handler functions. 3095 * 3096 * @hsotg: The HCD state structure 3097 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3098 * or both) 3099 * 3100 * Must be called with interrupt disabled and spinlock held 3101 */ 3102 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3103 enum dwc2_transaction_type tr_type) 3104 { 3105 #ifdef DWC2_DEBUG_SOF 3106 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3107 #endif 3108 /* Process host channels associated with periodic transfers */ 3109 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3110 tr_type == DWC2_TRANSACTION_ALL) 3111 dwc2_process_periodic_channels(hsotg); 3112 3113 /* Process host channels associated with non-periodic transfers */ 3114 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3115 tr_type == DWC2_TRANSACTION_ALL) { 3116 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3117 dwc2_process_non_periodic_channels(hsotg); 3118 } else { 3119 /* 3120 * Ensure NP Tx FIFO empty interrupt is disabled when 3121 * there are no non-periodic transfers to process 3122 */ 3123 u32 gintmsk = dwc2_readl(hsotg, GINTMSK); 3124 3125 gintmsk &= ~GINTSTS_NPTXFEMP; 3126 dwc2_writel(hsotg, gintmsk, GINTMSK); 3127 } 3128 } 3129 } 3130 3131 static void dwc2_conn_id_status_change(struct work_struct *work) 3132 { 3133 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3134 wf_otg); 3135 u32 count = 0; 3136 u32 gotgctl; 3137 unsigned long flags; 3138 3139 dev_dbg(hsotg->dev, "%s()\n", __func__); 3140 3141 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3142 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3143 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3144 !!(gotgctl & GOTGCTL_CONID_B)); 3145 3146 /* B-Device connector (Device Mode) */ 3147 if (gotgctl & GOTGCTL_CONID_B) { 3148 dwc2_vbus_supply_exit(hsotg); 3149 /* Wait for switch to device mode */ 3150 dev_dbg(hsotg->dev, "connId B\n"); 3151 if (hsotg->bus_suspended) { 3152 dev_info(hsotg->dev, 3153 "Do port resume before switching to device mode\n"); 3154 dwc2_port_resume(hsotg); 3155 } 3156 while (!dwc2_is_device_mode(hsotg)) { 3157 dev_info(hsotg->dev, 3158 "Waiting for Peripheral Mode, Mode=%s\n", 3159 dwc2_is_host_mode(hsotg) ? "Host" : 3160 "Peripheral"); 3161 msleep(20); 3162 /* 3163 * Sometimes the initial GOTGCTRL read is wrong, so 3164 * check it again and jump to host mode if that was 3165 * the case. 3166 */ 3167 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3168 if (!(gotgctl & GOTGCTL_CONID_B)) 3169 goto host; 3170 if (++count > 250) 3171 break; 3172 } 3173 if (count > 250) 3174 dev_err(hsotg->dev, 3175 "Connection id status change timed out\n"); 3176 3177 /* 3178 * Exit Partial Power Down without restoring registers. 3179 * No need to check the return value as registers 3180 * are not being restored. 3181 */ 3182 if (hsotg->in_ppd && hsotg->lx_state == DWC2_L2) 3183 dwc2_exit_partial_power_down(hsotg, 0, false); 3184 3185 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3186 dwc2_core_init(hsotg, false); 3187 dwc2_enable_global_interrupts(hsotg); 3188 spin_lock_irqsave(&hsotg->lock, flags); 3189 dwc2_hsotg_core_init_disconnected(hsotg, false); 3190 spin_unlock_irqrestore(&hsotg->lock, flags); 3191 /* Enable ACG feature in device mode,if supported */ 3192 dwc2_enable_acg(hsotg); 3193 dwc2_hsotg_core_connect(hsotg); 3194 } else { 3195 host: 3196 /* A-Device connector (Host Mode) */ 3197 dev_dbg(hsotg->dev, "connId A\n"); 3198 while (!dwc2_is_host_mode(hsotg)) { 3199 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3200 dwc2_is_host_mode(hsotg) ? 3201 "Host" : "Peripheral"); 3202 msleep(20); 3203 if (++count > 250) 3204 break; 3205 } 3206 if (count > 250) 3207 dev_err(hsotg->dev, 3208 "Connection id status change timed out\n"); 3209 3210 spin_lock_irqsave(&hsotg->lock, flags); 3211 dwc2_hsotg_disconnect(hsotg); 3212 spin_unlock_irqrestore(&hsotg->lock, flags); 3213 3214 hsotg->op_state = OTG_STATE_A_HOST; 3215 /* Initialize the Core for Host mode */ 3216 dwc2_core_init(hsotg, false); 3217 dwc2_enable_global_interrupts(hsotg); 3218 dwc2_hcd_start(hsotg); 3219 } 3220 } 3221 3222 static void dwc2_wakeup_detected(struct timer_list *t) 3223 { 3224 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); 3225 u32 hprt0; 3226 3227 dev_dbg(hsotg->dev, "%s()\n", __func__); 3228 3229 /* 3230 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3231 * so that OPT tests pass with all PHYs.) 3232 */ 3233 hprt0 = dwc2_read_hprt0(hsotg); 3234 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3235 hprt0 &= ~HPRT0_RES; 3236 dwc2_writel(hsotg, hprt0, HPRT0); 3237 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3238 dwc2_readl(hsotg, HPRT0)); 3239 3240 dwc2_hcd_rem_wakeup(hsotg); 3241 hsotg->bus_suspended = false; 3242 3243 /* Change to L0 state */ 3244 hsotg->lx_state = DWC2_L0; 3245 } 3246 3247 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3248 { 3249 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3250 3251 return hcd->self.b_hnp_enable; 3252 } 3253 3254 /** 3255 * dwc2_port_suspend() - Put controller in suspend mode for host. 3256 * 3257 * @hsotg: Programming view of the DWC_otg controller 3258 * @windex: The control request wIndex field 3259 * 3260 * Return: non-zero if failed to enter suspend mode for host. 3261 * 3262 * This function is for entering Host mode suspend. 3263 * Must NOT be called with interrupt disabled or spinlock held. 3264 */ 3265 int dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3266 { 3267 unsigned long flags; 3268 u32 pcgctl; 3269 u32 gotgctl; 3270 int ret = 0; 3271 3272 dev_dbg(hsotg->dev, "%s()\n", __func__); 3273 3274 spin_lock_irqsave(&hsotg->lock, flags); 3275 3276 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3277 gotgctl = dwc2_readl(hsotg, GOTGCTL); 3278 gotgctl |= GOTGCTL_HSTSETHNPEN; 3279 dwc2_writel(hsotg, gotgctl, GOTGCTL); 3280 hsotg->op_state = OTG_STATE_A_SUSPEND; 3281 } 3282 3283 switch (hsotg->params.power_down) { 3284 case DWC2_POWER_DOWN_PARAM_PARTIAL: 3285 ret = dwc2_enter_partial_power_down(hsotg); 3286 if (ret) 3287 dev_err(hsotg->dev, 3288 "enter partial_power_down failed.\n"); 3289 break; 3290 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 3291 /* 3292 * Perform spin unlock and lock because in 3293 * "dwc2_host_enter_hibernation()" function there is a spinlock 3294 * logic which prevents servicing of any IRQ during entering 3295 * hibernation. 3296 */ 3297 spin_unlock_irqrestore(&hsotg->lock, flags); 3298 ret = dwc2_enter_hibernation(hsotg, 1); 3299 if (ret) 3300 dev_err(hsotg->dev, "enter hibernation failed.\n"); 3301 spin_lock_irqsave(&hsotg->lock, flags); 3302 break; 3303 case DWC2_POWER_DOWN_PARAM_NONE: 3304 /* 3305 * If not hibernation nor partial power down are supported, 3306 * clock gating is used to save power. 3307 */ 3308 if (!hsotg->params.no_clock_gating) 3309 dwc2_host_enter_clock_gating(hsotg); 3310 break; 3311 } 3312 3313 /* For HNP the bus must be suspended for at least 200ms */ 3314 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3315 pcgctl = dwc2_readl(hsotg, PCGCTL); 3316 pcgctl &= ~PCGCTL_STOPPCLK; 3317 dwc2_writel(hsotg, pcgctl, PCGCTL); 3318 3319 spin_unlock_irqrestore(&hsotg->lock, flags); 3320 3321 msleep(200); 3322 } else { 3323 spin_unlock_irqrestore(&hsotg->lock, flags); 3324 } 3325 3326 return ret; 3327 } 3328 3329 /** 3330 * dwc2_port_resume() - Exit controller from suspend mode for host. 3331 * 3332 * @hsotg: Programming view of the DWC_otg controller 3333 * 3334 * Return: non-zero if failed to exit suspend mode for host. 3335 * 3336 * This function is for exiting Host mode suspend. 3337 * Must NOT be called with interrupt disabled or spinlock held. 3338 */ 3339 int dwc2_port_resume(struct dwc2_hsotg *hsotg) 3340 { 3341 unsigned long flags; 3342 int ret = 0; 3343 3344 spin_lock_irqsave(&hsotg->lock, flags); 3345 3346 switch (hsotg->params.power_down) { 3347 case DWC2_POWER_DOWN_PARAM_PARTIAL: 3348 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 3349 if (ret) 3350 dev_err(hsotg->dev, 3351 "exit partial_power_down failed.\n"); 3352 break; 3353 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 3354 /* Exit host hibernation. */ 3355 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 3356 if (ret) 3357 dev_err(hsotg->dev, "exit hibernation failed.\n"); 3358 break; 3359 case DWC2_POWER_DOWN_PARAM_NONE: 3360 /* 3361 * If not hibernation nor partial power down are supported, 3362 * port resume is done using the clock gating programming flow. 3363 */ 3364 spin_unlock_irqrestore(&hsotg->lock, flags); 3365 dwc2_host_exit_clock_gating(hsotg, 0); 3366 spin_lock_irqsave(&hsotg->lock, flags); 3367 break; 3368 } 3369 3370 spin_unlock_irqrestore(&hsotg->lock, flags); 3371 3372 return ret; 3373 } 3374 3375 /* Handles hub class-specific requests */ 3376 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3377 u16 wvalue, u16 windex, char *buf, u16 wlength) 3378 { 3379 struct usb_hub_descriptor *hub_desc; 3380 int retval = 0; 3381 u32 hprt0; 3382 u32 port_status; 3383 u32 speed; 3384 u32 pcgctl; 3385 u32 pwr; 3386 3387 switch (typereq) { 3388 case ClearHubFeature: 3389 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3390 3391 switch (wvalue) { 3392 case C_HUB_LOCAL_POWER: 3393 case C_HUB_OVER_CURRENT: 3394 /* Nothing required here */ 3395 break; 3396 3397 default: 3398 retval = -EINVAL; 3399 dev_err(hsotg->dev, 3400 "ClearHubFeature request %1xh unknown\n", 3401 wvalue); 3402 } 3403 break; 3404 3405 case ClearPortFeature: 3406 if (wvalue != USB_PORT_FEAT_L1) 3407 if (!windex || windex > 1) 3408 goto error; 3409 switch (wvalue) { 3410 case USB_PORT_FEAT_ENABLE: 3411 dev_dbg(hsotg->dev, 3412 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3413 hprt0 = dwc2_read_hprt0(hsotg); 3414 hprt0 |= HPRT0_ENA; 3415 dwc2_writel(hsotg, hprt0, HPRT0); 3416 break; 3417 3418 case USB_PORT_FEAT_SUSPEND: 3419 dev_dbg(hsotg->dev, 3420 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3421 3422 if (hsotg->bus_suspended) 3423 retval = dwc2_port_resume(hsotg); 3424 break; 3425 3426 case USB_PORT_FEAT_POWER: 3427 dev_dbg(hsotg->dev, 3428 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3429 hprt0 = dwc2_read_hprt0(hsotg); 3430 pwr = hprt0 & HPRT0_PWR; 3431 hprt0 &= ~HPRT0_PWR; 3432 dwc2_writel(hsotg, hprt0, HPRT0); 3433 if (pwr) 3434 dwc2_vbus_supply_exit(hsotg); 3435 break; 3436 3437 case USB_PORT_FEAT_INDICATOR: 3438 dev_dbg(hsotg->dev, 3439 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3440 /* Port indicator not supported */ 3441 break; 3442 3443 case USB_PORT_FEAT_C_CONNECTION: 3444 /* 3445 * Clears driver's internal Connect Status Change flag 3446 */ 3447 dev_dbg(hsotg->dev, 3448 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3449 hsotg->flags.b.port_connect_status_change = 0; 3450 break; 3451 3452 case USB_PORT_FEAT_C_RESET: 3453 /* Clears driver's internal Port Reset Change flag */ 3454 dev_dbg(hsotg->dev, 3455 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3456 hsotg->flags.b.port_reset_change = 0; 3457 break; 3458 3459 case USB_PORT_FEAT_C_ENABLE: 3460 /* 3461 * Clears the driver's internal Port Enable/Disable 3462 * Change flag 3463 */ 3464 dev_dbg(hsotg->dev, 3465 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3466 hsotg->flags.b.port_enable_change = 0; 3467 break; 3468 3469 case USB_PORT_FEAT_C_SUSPEND: 3470 /* 3471 * Clears the driver's internal Port Suspend Change 3472 * flag, which is set when resume signaling on the host 3473 * port is complete 3474 */ 3475 dev_dbg(hsotg->dev, 3476 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3477 hsotg->flags.b.port_suspend_change = 0; 3478 break; 3479 3480 case USB_PORT_FEAT_C_PORT_L1: 3481 dev_dbg(hsotg->dev, 3482 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3483 hsotg->flags.b.port_l1_change = 0; 3484 break; 3485 3486 case USB_PORT_FEAT_C_OVER_CURRENT: 3487 dev_dbg(hsotg->dev, 3488 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3489 hsotg->flags.b.port_over_current_change = 0; 3490 break; 3491 3492 default: 3493 retval = -EINVAL; 3494 dev_err(hsotg->dev, 3495 "ClearPortFeature request %1xh unknown or unsupported\n", 3496 wvalue); 3497 } 3498 break; 3499 3500 case GetHubDescriptor: 3501 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3502 hub_desc = (struct usb_hub_descriptor *)buf; 3503 hub_desc->bDescLength = 9; 3504 hub_desc->bDescriptorType = USB_DT_HUB; 3505 hub_desc->bNbrPorts = 1; 3506 hub_desc->wHubCharacteristics = 3507 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3508 HUB_CHAR_INDV_PORT_OCPM); 3509 hub_desc->bPwrOn2PwrGood = 1; 3510 hub_desc->bHubContrCurrent = 0; 3511 hub_desc->u.hs.DeviceRemovable[0] = 0; 3512 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3513 break; 3514 3515 case GetHubStatus: 3516 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3517 memset(buf, 0, 4); 3518 break; 3519 3520 case GetPortStatus: 3521 dev_vdbg(hsotg->dev, 3522 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3523 hsotg->flags.d32); 3524 if (!windex || windex > 1) 3525 goto error; 3526 3527 port_status = 0; 3528 if (hsotg->flags.b.port_connect_status_change) 3529 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3530 if (hsotg->flags.b.port_enable_change) 3531 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3532 if (hsotg->flags.b.port_suspend_change) 3533 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3534 if (hsotg->flags.b.port_l1_change) 3535 port_status |= USB_PORT_STAT_C_L1 << 16; 3536 if (hsotg->flags.b.port_reset_change) 3537 port_status |= USB_PORT_STAT_C_RESET << 16; 3538 if (hsotg->flags.b.port_over_current_change) { 3539 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3540 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3541 } 3542 3543 if (!hsotg->flags.b.port_connect_status) { 3544 /* 3545 * The port is disconnected, which means the core is 3546 * either in device mode or it soon will be. Just 3547 * return 0's for the remainder of the port status 3548 * since the port register can't be read if the core 3549 * is in device mode. 3550 */ 3551 *(__le32 *)buf = cpu_to_le32(port_status); 3552 break; 3553 } 3554 3555 hprt0 = dwc2_readl(hsotg, HPRT0); 3556 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3557 3558 if (hprt0 & HPRT0_CONNSTS) 3559 port_status |= USB_PORT_STAT_CONNECTION; 3560 if (hprt0 & HPRT0_ENA) 3561 port_status |= USB_PORT_STAT_ENABLE; 3562 if (hprt0 & HPRT0_SUSP) 3563 port_status |= USB_PORT_STAT_SUSPEND; 3564 if (hprt0 & HPRT0_OVRCURRACT) 3565 port_status |= USB_PORT_STAT_OVERCURRENT; 3566 if (hprt0 & HPRT0_RST) 3567 port_status |= USB_PORT_STAT_RESET; 3568 if (hprt0 & HPRT0_PWR) 3569 port_status |= USB_PORT_STAT_POWER; 3570 3571 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3572 if (speed == HPRT0_SPD_HIGH_SPEED) 3573 port_status |= USB_PORT_STAT_HIGH_SPEED; 3574 else if (speed == HPRT0_SPD_LOW_SPEED) 3575 port_status |= USB_PORT_STAT_LOW_SPEED; 3576 3577 if (hprt0 & HPRT0_TSTCTL_MASK) 3578 port_status |= USB_PORT_STAT_TEST; 3579 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3580 3581 if (hsotg->params.dma_desc_fs_enable) { 3582 /* 3583 * Enable descriptor DMA only if a full speed 3584 * device is connected. 3585 */ 3586 if (hsotg->new_connection && 3587 ((port_status & 3588 (USB_PORT_STAT_CONNECTION | 3589 USB_PORT_STAT_HIGH_SPEED | 3590 USB_PORT_STAT_LOW_SPEED)) == 3591 USB_PORT_STAT_CONNECTION)) { 3592 u32 hcfg; 3593 3594 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3595 hsotg->params.dma_desc_enable = true; 3596 hcfg = dwc2_readl(hsotg, HCFG); 3597 hcfg |= HCFG_DESCDMA; 3598 dwc2_writel(hsotg, hcfg, HCFG); 3599 hsotg->new_connection = false; 3600 } 3601 } 3602 3603 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3604 *(__le32 *)buf = cpu_to_le32(port_status); 3605 break; 3606 3607 case SetHubFeature: 3608 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3609 /* No HUB features supported */ 3610 break; 3611 3612 case SetPortFeature: 3613 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3614 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3615 goto error; 3616 3617 if (!hsotg->flags.b.port_connect_status) { 3618 /* 3619 * The port is disconnected, which means the core is 3620 * either in device mode or it soon will be. Just 3621 * return without doing anything since the port 3622 * register can't be written if the core is in device 3623 * mode. 3624 */ 3625 break; 3626 } 3627 3628 switch (wvalue) { 3629 case USB_PORT_FEAT_SUSPEND: 3630 dev_dbg(hsotg->dev, 3631 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3632 if (windex != hsotg->otg_port) 3633 goto error; 3634 if (!hsotg->bus_suspended) 3635 retval = dwc2_port_suspend(hsotg, windex); 3636 break; 3637 3638 case USB_PORT_FEAT_POWER: 3639 dev_dbg(hsotg->dev, 3640 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3641 hprt0 = dwc2_read_hprt0(hsotg); 3642 pwr = hprt0 & HPRT0_PWR; 3643 hprt0 |= HPRT0_PWR; 3644 dwc2_writel(hsotg, hprt0, HPRT0); 3645 if (!pwr) 3646 dwc2_vbus_supply_init(hsotg); 3647 break; 3648 3649 case USB_PORT_FEAT_RESET: 3650 dev_dbg(hsotg->dev, 3651 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3652 3653 hprt0 = dwc2_read_hprt0(hsotg); 3654 3655 if (hsotg->hibernated) { 3656 retval = dwc2_exit_hibernation(hsotg, 0, 1, 1); 3657 if (retval) 3658 dev_err(hsotg->dev, 3659 "exit hibernation failed\n"); 3660 } 3661 3662 if (hsotg->in_ppd) { 3663 retval = dwc2_exit_partial_power_down(hsotg, 1, 3664 true); 3665 if (retval) 3666 dev_err(hsotg->dev, 3667 "exit partial_power_down failed\n"); 3668 } 3669 3670 if (hsotg->params.power_down == 3671 DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended) 3672 dwc2_host_exit_clock_gating(hsotg, 0); 3673 3674 pcgctl = dwc2_readl(hsotg, PCGCTL); 3675 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3676 dwc2_writel(hsotg, pcgctl, PCGCTL); 3677 /* ??? Original driver does this */ 3678 dwc2_writel(hsotg, 0, PCGCTL); 3679 3680 hprt0 = dwc2_read_hprt0(hsotg); 3681 pwr = hprt0 & HPRT0_PWR; 3682 /* Clear suspend bit if resetting from suspend state */ 3683 hprt0 &= ~HPRT0_SUSP; 3684 3685 /* 3686 * When B-Host the Port reset bit is set in the Start 3687 * HCD Callback function, so that the reset is started 3688 * within 1ms of the HNP success interrupt 3689 */ 3690 if (!dwc2_hcd_is_b_host(hsotg)) { 3691 hprt0 |= HPRT0_PWR | HPRT0_RST; 3692 dev_dbg(hsotg->dev, 3693 "In host mode, hprt0=%08x\n", hprt0); 3694 dwc2_writel(hsotg, hprt0, HPRT0); 3695 if (!pwr) 3696 dwc2_vbus_supply_init(hsotg); 3697 } 3698 3699 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3700 msleep(50); 3701 hprt0 &= ~HPRT0_RST; 3702 dwc2_writel(hsotg, hprt0, HPRT0); 3703 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3704 break; 3705 3706 case USB_PORT_FEAT_INDICATOR: 3707 dev_dbg(hsotg->dev, 3708 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3709 /* Not supported */ 3710 break; 3711 3712 case USB_PORT_FEAT_TEST: 3713 hprt0 = dwc2_read_hprt0(hsotg); 3714 dev_dbg(hsotg->dev, 3715 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3716 hprt0 &= ~HPRT0_TSTCTL_MASK; 3717 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3718 dwc2_writel(hsotg, hprt0, HPRT0); 3719 break; 3720 3721 default: 3722 retval = -EINVAL; 3723 dev_err(hsotg->dev, 3724 "SetPortFeature %1xh unknown or unsupported\n", 3725 wvalue); 3726 break; 3727 } 3728 break; 3729 3730 default: 3731 error: 3732 retval = -EINVAL; 3733 dev_dbg(hsotg->dev, 3734 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3735 typereq, windex, wvalue); 3736 break; 3737 } 3738 3739 return retval; 3740 } 3741 3742 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3743 { 3744 int retval; 3745 3746 if (port != 1) 3747 return -EINVAL; 3748 3749 retval = (hsotg->flags.b.port_connect_status_change || 3750 hsotg->flags.b.port_reset_change || 3751 hsotg->flags.b.port_enable_change || 3752 hsotg->flags.b.port_suspend_change || 3753 hsotg->flags.b.port_over_current_change); 3754 3755 if (retval) { 3756 dev_dbg(hsotg->dev, 3757 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3758 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3759 hsotg->flags.b.port_connect_status_change); 3760 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3761 hsotg->flags.b.port_reset_change); 3762 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3763 hsotg->flags.b.port_enable_change); 3764 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3765 hsotg->flags.b.port_suspend_change); 3766 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3767 hsotg->flags.b.port_over_current_change); 3768 } 3769 3770 return retval; 3771 } 3772 3773 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3774 { 3775 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3776 3777 #ifdef DWC2_DEBUG_SOF 3778 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3779 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3780 #endif 3781 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3782 } 3783 3784 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3785 { 3786 u32 hprt = dwc2_readl(hsotg, HPRT0); 3787 u32 hfir = dwc2_readl(hsotg, HFIR); 3788 u32 hfnum = dwc2_readl(hsotg, HFNUM); 3789 unsigned int us_per_frame; 3790 unsigned int frame_number; 3791 unsigned int remaining; 3792 unsigned int interval; 3793 unsigned int phy_clks; 3794 3795 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3796 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3797 3798 /* Extract fields */ 3799 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3800 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3801 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3802 3803 /* 3804 * Number of phy clocks since the last tick of the frame number after 3805 * "us" has passed. 3806 */ 3807 phy_clks = (interval - remaining) + 3808 DIV_ROUND_UP(interval * us, us_per_frame); 3809 3810 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3811 } 3812 3813 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3814 { 3815 return hsotg->op_state == OTG_STATE_B_HOST; 3816 } 3817 3818 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3819 int iso_desc_count, 3820 gfp_t mem_flags) 3821 { 3822 struct dwc2_hcd_urb *urb; 3823 3824 urb = kzalloc(struct_size(urb, iso_descs, iso_desc_count), mem_flags); 3825 if (urb) 3826 urb->packet_count = iso_desc_count; 3827 return urb; 3828 } 3829 3830 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3831 struct dwc2_hcd_urb *urb, u8 dev_addr, 3832 u8 ep_num, u8 ep_type, u8 ep_dir, 3833 u16 maxp, u16 maxp_mult) 3834 { 3835 if (dbg_perio() || 3836 ep_type == USB_ENDPOINT_XFER_BULK || 3837 ep_type == USB_ENDPOINT_XFER_CONTROL) 3838 dev_vdbg(hsotg->dev, 3839 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, maxp=%d (%d mult)\n", 3840 dev_addr, ep_num, ep_dir, ep_type, maxp, maxp_mult); 3841 urb->pipe_info.dev_addr = dev_addr; 3842 urb->pipe_info.ep_num = ep_num; 3843 urb->pipe_info.pipe_type = ep_type; 3844 urb->pipe_info.pipe_dir = ep_dir; 3845 urb->pipe_info.maxp = maxp; 3846 urb->pipe_info.maxp_mult = maxp_mult; 3847 } 3848 3849 /* 3850 * NOTE: This function will be removed once the peripheral controller code 3851 * is integrated and the driver is stable 3852 */ 3853 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3854 { 3855 #ifdef DEBUG 3856 struct dwc2_host_chan *chan; 3857 struct dwc2_hcd_urb *urb; 3858 struct dwc2_qtd *qtd; 3859 int num_channels; 3860 u32 np_tx_status; 3861 u32 p_tx_status; 3862 int i; 3863 3864 num_channels = hsotg->params.host_channels; 3865 dev_dbg(hsotg->dev, "\n"); 3866 dev_dbg(hsotg->dev, 3867 "************************************************************\n"); 3868 dev_dbg(hsotg->dev, "HCD State:\n"); 3869 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3870 3871 for (i = 0; i < num_channels; i++) { 3872 chan = hsotg->hc_ptr_array[i]; 3873 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3874 dev_dbg(hsotg->dev, 3875 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3876 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3877 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3878 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3879 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3880 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3881 chan->data_pid_start); 3882 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3883 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3884 chan->xfer_started); 3885 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3886 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3887 (unsigned long)chan->xfer_dma); 3888 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3889 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3890 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3891 chan->halt_on_queue); 3892 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3893 chan->halt_pending); 3894 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3895 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3896 dev_dbg(hsotg->dev, " complete_split: %d\n", 3897 chan->complete_split); 3898 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3899 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3900 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3901 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3902 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3903 3904 if (chan->xfer_started) { 3905 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3906 3907 hfnum = dwc2_readl(hsotg, HFNUM); 3908 hcchar = dwc2_readl(hsotg, HCCHAR(i)); 3909 hctsiz = dwc2_readl(hsotg, HCTSIZ(i)); 3910 hcint = dwc2_readl(hsotg, HCINT(i)); 3911 hcintmsk = dwc2_readl(hsotg, HCINTMSK(i)); 3912 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3913 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3914 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3915 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3916 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3917 } 3918 3919 if (!(chan->xfer_started && chan->qh)) 3920 continue; 3921 3922 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3923 if (!qtd->in_process) 3924 break; 3925 urb = qtd->urb; 3926 dev_dbg(hsotg->dev, " URB Info:\n"); 3927 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3928 qtd, urb); 3929 if (urb) { 3930 dev_dbg(hsotg->dev, 3931 " Dev: %d, EP: %d %s\n", 3932 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3933 dwc2_hcd_get_ep_num(&urb->pipe_info), 3934 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3935 "IN" : "OUT"); 3936 dev_dbg(hsotg->dev, 3937 " Max packet size: %d (%d mult)\n", 3938 dwc2_hcd_get_maxp(&urb->pipe_info), 3939 dwc2_hcd_get_maxp_mult(&urb->pipe_info)); 3940 dev_dbg(hsotg->dev, 3941 " transfer_buffer: %p\n", 3942 urb->buf); 3943 dev_dbg(hsotg->dev, 3944 " transfer_dma: %08lx\n", 3945 (unsigned long)urb->dma); 3946 dev_dbg(hsotg->dev, 3947 " transfer_buffer_length: %d\n", 3948 urb->length); 3949 dev_dbg(hsotg->dev, " actual_length: %d\n", 3950 urb->actual_length); 3951 } 3952 } 3953 } 3954 3955 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3956 hsotg->non_periodic_channels); 3957 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3958 hsotg->periodic_channels); 3959 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3960 np_tx_status = dwc2_readl(hsotg, GNPTXSTS); 3961 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3962 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3963 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3964 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3965 p_tx_status = dwc2_readl(hsotg, HPTXSTS); 3966 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3967 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3968 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3969 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3970 dwc2_dump_global_registers(hsotg); 3971 dwc2_dump_host_registers(hsotg); 3972 dev_dbg(hsotg->dev, 3973 "************************************************************\n"); 3974 dev_dbg(hsotg->dev, "\n"); 3975 #endif 3976 } 3977 3978 struct wrapper_priv_data { 3979 struct dwc2_hsotg *hsotg; 3980 }; 3981 3982 /* Gets the dwc2_hsotg from a usb_hcd */ 3983 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 3984 { 3985 struct wrapper_priv_data *p; 3986 3987 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 3988 return p->hsotg; 3989 } 3990 3991 /** 3992 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 3993 * 3994 * This will get the dwc2_tt structure (and ttport) associated with the given 3995 * context (which is really just a struct urb pointer). 3996 * 3997 * The first time this is called for a given TT we allocate memory for our 3998 * structure. When everyone is done and has called dwc2_host_put_tt_info() 3999 * then the refcount for the structure will go to 0 and we'll free it. 4000 * 4001 * @hsotg: The HCD state structure for the DWC OTG controller. 4002 * @context: The priv pointer from a struct dwc2_hcd_urb. 4003 * @mem_flags: Flags for allocating memory. 4004 * @ttport: We'll return this device's port number here. That's used to 4005 * reference into the bitmap if we're on a multi_tt hub. 4006 * 4007 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4008 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4009 */ 4010 4011 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4012 gfp_t mem_flags, int *ttport) 4013 { 4014 struct urb *urb = context; 4015 struct dwc2_tt *dwc_tt = NULL; 4016 4017 if (urb->dev->tt) { 4018 *ttport = urb->dev->ttport; 4019 4020 dwc_tt = urb->dev->tt->hcpriv; 4021 if (!dwc_tt) { 4022 size_t bitmap_size; 4023 4024 /* 4025 * For single_tt we need one schedule. For multi_tt 4026 * we need one per port. 4027 */ 4028 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4029 sizeof(dwc_tt->periodic_bitmaps[0]); 4030 if (urb->dev->tt->multi) 4031 bitmap_size *= urb->dev->tt->hub->maxchild; 4032 4033 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4034 mem_flags); 4035 if (!dwc_tt) 4036 return NULL; 4037 4038 dwc_tt->usb_tt = urb->dev->tt; 4039 dwc_tt->usb_tt->hcpriv = dwc_tt; 4040 } 4041 4042 dwc_tt->refcount++; 4043 } 4044 4045 return dwc_tt; 4046 } 4047 4048 /** 4049 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4050 * 4051 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4052 * of the structure are done. 4053 * 4054 * It's OK to call this with NULL. 4055 * 4056 * @hsotg: The HCD state structure for the DWC OTG controller. 4057 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4058 */ 4059 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4060 { 4061 /* Model kfree and make put of NULL a no-op */ 4062 if (!dwc_tt) 4063 return; 4064 4065 WARN_ON(dwc_tt->refcount < 1); 4066 4067 dwc_tt->refcount--; 4068 if (!dwc_tt->refcount) { 4069 dwc_tt->usb_tt->hcpriv = NULL; 4070 kfree(dwc_tt); 4071 } 4072 } 4073 4074 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4075 { 4076 struct urb *urb = context; 4077 4078 return urb->dev->speed; 4079 } 4080 4081 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4082 struct urb *urb) 4083 { 4084 struct usb_bus *bus = hcd_to_bus(hcd); 4085 4086 if (urb->interval) 4087 bus->bandwidth_allocated += bw / urb->interval; 4088 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4089 bus->bandwidth_isoc_reqs++; 4090 else 4091 bus->bandwidth_int_reqs++; 4092 } 4093 4094 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4095 struct urb *urb) 4096 { 4097 struct usb_bus *bus = hcd_to_bus(hcd); 4098 4099 if (urb->interval) 4100 bus->bandwidth_allocated -= bw / urb->interval; 4101 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4102 bus->bandwidth_isoc_reqs--; 4103 else 4104 bus->bandwidth_int_reqs--; 4105 } 4106 4107 /* 4108 * Sets the final status of an URB and returns it to the upper layer. Any 4109 * required cleanup of the URB is performed. 4110 * 4111 * Must be called with interrupt disabled and spinlock held 4112 */ 4113 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4114 int status) 4115 { 4116 struct urb *urb; 4117 int i; 4118 4119 if (!qtd) { 4120 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4121 return; 4122 } 4123 4124 if (!qtd->urb) { 4125 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4126 return; 4127 } 4128 4129 urb = qtd->urb->priv; 4130 if (!urb) { 4131 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4132 return; 4133 } 4134 4135 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4136 4137 if (dbg_urb(urb)) 4138 dev_vdbg(hsotg->dev, 4139 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4140 __func__, urb, usb_pipedevice(urb->pipe), 4141 usb_pipeendpoint(urb->pipe), 4142 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4143 urb->actual_length); 4144 4145 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4146 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4147 for (i = 0; i < urb->number_of_packets; ++i) { 4148 urb->iso_frame_desc[i].actual_length = 4149 dwc2_hcd_urb_get_iso_desc_actual_length( 4150 qtd->urb, i); 4151 urb->iso_frame_desc[i].status = 4152 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4153 } 4154 } 4155 4156 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4157 for (i = 0; i < urb->number_of_packets; i++) 4158 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4159 i, urb->iso_frame_desc[i].status); 4160 } 4161 4162 urb->status = status; 4163 if (!status) { 4164 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4165 urb->actual_length < urb->transfer_buffer_length) 4166 urb->status = -EREMOTEIO; 4167 } 4168 4169 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4170 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4171 struct usb_host_endpoint *ep = urb->ep; 4172 4173 if (ep) 4174 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4175 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4176 urb); 4177 } 4178 4179 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4180 urb->hcpriv = NULL; 4181 kfree(qtd->urb); 4182 qtd->urb = NULL; 4183 4184 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4185 } 4186 4187 /* 4188 * Work queue function for starting the HCD when A-Cable is connected 4189 */ 4190 static void dwc2_hcd_start_func(struct work_struct *work) 4191 { 4192 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4193 start_work.work); 4194 4195 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4196 dwc2_host_start(hsotg); 4197 } 4198 4199 /* 4200 * Reset work queue function 4201 */ 4202 static void dwc2_hcd_reset_func(struct work_struct *work) 4203 { 4204 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4205 reset_work.work); 4206 unsigned long flags; 4207 u32 hprt0; 4208 4209 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4210 4211 spin_lock_irqsave(&hsotg->lock, flags); 4212 4213 hprt0 = dwc2_read_hprt0(hsotg); 4214 hprt0 &= ~HPRT0_RST; 4215 dwc2_writel(hsotg, hprt0, HPRT0); 4216 hsotg->flags.b.port_reset_change = 1; 4217 4218 spin_unlock_irqrestore(&hsotg->lock, flags); 4219 } 4220 4221 static void dwc2_hcd_phy_reset_func(struct work_struct *work) 4222 { 4223 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4224 phy_reset_work); 4225 int ret; 4226 4227 ret = phy_reset(hsotg->phy); 4228 if (ret) 4229 dev_warn(hsotg->dev, "PHY reset failed\n"); 4230 } 4231 4232 /* 4233 * ========================================================================= 4234 * Linux HC Driver Functions 4235 * ========================================================================= 4236 */ 4237 4238 /* 4239 * Initializes the DWC_otg controller and its root hub and prepares it for host 4240 * mode operation. Activates the root port. Returns 0 on success and a negative 4241 * error code on failure. 4242 */ 4243 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4244 { 4245 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4246 struct usb_bus *bus = hcd_to_bus(hcd); 4247 unsigned long flags; 4248 u32 hprt0; 4249 int ret; 4250 4251 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4252 4253 spin_lock_irqsave(&hsotg->lock, flags); 4254 hsotg->lx_state = DWC2_L0; 4255 hcd->state = HC_STATE_RUNNING; 4256 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4257 4258 if (dwc2_is_device_mode(hsotg)) { 4259 spin_unlock_irqrestore(&hsotg->lock, flags); 4260 return 0; /* why 0 ?? */ 4261 } 4262 4263 dwc2_hcd_reinit(hsotg); 4264 4265 hprt0 = dwc2_read_hprt0(hsotg); 4266 /* Has vbus power been turned on in dwc2_core_host_init ? */ 4267 if (hprt0 & HPRT0_PWR) { 4268 /* Enable external vbus supply before resuming root hub */ 4269 spin_unlock_irqrestore(&hsotg->lock, flags); 4270 ret = dwc2_vbus_supply_init(hsotg); 4271 if (ret) 4272 return ret; 4273 spin_lock_irqsave(&hsotg->lock, flags); 4274 } 4275 4276 /* Initialize and connect root hub if one is not already attached */ 4277 if (bus->root_hub) { 4278 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4279 /* Inform the HUB driver to resume */ 4280 usb_hcd_resume_root_hub(hcd); 4281 } 4282 4283 spin_unlock_irqrestore(&hsotg->lock, flags); 4284 4285 return 0; 4286 } 4287 4288 /* 4289 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4290 * stopped. 4291 */ 4292 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4293 { 4294 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4295 unsigned long flags; 4296 u32 hprt0; 4297 4298 /* Turn off all host-specific interrupts */ 4299 dwc2_disable_host_interrupts(hsotg); 4300 4301 /* Wait for interrupt processing to finish */ 4302 synchronize_irq(hcd->irq); 4303 4304 spin_lock_irqsave(&hsotg->lock, flags); 4305 hprt0 = dwc2_read_hprt0(hsotg); 4306 /* Ensure hcd is disconnected */ 4307 dwc2_hcd_disconnect(hsotg, true); 4308 dwc2_hcd_stop(hsotg); 4309 hsotg->lx_state = DWC2_L3; 4310 hcd->state = HC_STATE_HALT; 4311 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4312 spin_unlock_irqrestore(&hsotg->lock, flags); 4313 4314 /* keep balanced supply init/exit by checking HPRT0_PWR */ 4315 if (hprt0 & HPRT0_PWR) 4316 dwc2_vbus_supply_exit(hsotg); 4317 4318 usleep_range(1000, 3000); 4319 } 4320 4321 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4322 { 4323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4324 unsigned long flags; 4325 int ret = 0; 4326 4327 spin_lock_irqsave(&hsotg->lock, flags); 4328 4329 if (dwc2_is_device_mode(hsotg)) 4330 goto unlock; 4331 4332 if (hsotg->lx_state != DWC2_L0) 4333 goto unlock; 4334 4335 if (!HCD_HW_ACCESSIBLE(hcd)) 4336 goto unlock; 4337 4338 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4339 goto unlock; 4340 4341 if (hsotg->bus_suspended) 4342 goto skip_power_saving; 4343 4344 if (hsotg->flags.b.port_connect_status == 0) 4345 goto skip_power_saving; 4346 4347 switch (hsotg->params.power_down) { 4348 case DWC2_POWER_DOWN_PARAM_PARTIAL: 4349 /* Enter partial_power_down */ 4350 ret = dwc2_enter_partial_power_down(hsotg); 4351 if (ret) 4352 dev_err(hsotg->dev, 4353 "enter partial_power_down failed\n"); 4354 /* After entering suspend, hardware is not accessible */ 4355 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4356 break; 4357 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 4358 /* Enter hibernation */ 4359 spin_unlock_irqrestore(&hsotg->lock, flags); 4360 ret = dwc2_enter_hibernation(hsotg, 1); 4361 if (ret) 4362 dev_err(hsotg->dev, "enter hibernation failed\n"); 4363 spin_lock_irqsave(&hsotg->lock, flags); 4364 4365 /* After entering suspend, hardware is not accessible */ 4366 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4367 break; 4368 case DWC2_POWER_DOWN_PARAM_NONE: 4369 /* 4370 * If not hibernation nor partial power down are supported, 4371 * clock gating is used to save power. 4372 */ 4373 if (!hsotg->params.no_clock_gating) { 4374 dwc2_host_enter_clock_gating(hsotg); 4375 4376 /* After entering suspend, hardware is not accessible */ 4377 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4378 } 4379 break; 4380 default: 4381 goto skip_power_saving; 4382 } 4383 4384 spin_unlock_irqrestore(&hsotg->lock, flags); 4385 dwc2_vbus_supply_exit(hsotg); 4386 spin_lock_irqsave(&hsotg->lock, flags); 4387 4388 /* Ask phy to be suspended */ 4389 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4390 spin_unlock_irqrestore(&hsotg->lock, flags); 4391 usb_phy_set_suspend(hsotg->uphy, true); 4392 spin_lock_irqsave(&hsotg->lock, flags); 4393 } 4394 4395 skip_power_saving: 4396 hsotg->lx_state = DWC2_L2; 4397 unlock: 4398 spin_unlock_irqrestore(&hsotg->lock, flags); 4399 4400 return ret; 4401 } 4402 4403 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4404 { 4405 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4406 unsigned long flags; 4407 u32 hprt0; 4408 int ret = 0; 4409 4410 spin_lock_irqsave(&hsotg->lock, flags); 4411 4412 if (dwc2_is_device_mode(hsotg)) 4413 goto unlock; 4414 4415 if (hsotg->lx_state != DWC2_L2) 4416 goto unlock; 4417 4418 hprt0 = dwc2_read_hprt0(hsotg); 4419 4420 /* 4421 * Added port connection status checking which prevents exiting from 4422 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial 4423 * Power Down mode. 4424 */ 4425 if (hprt0 & HPRT0_CONNSTS) { 4426 hsotg->lx_state = DWC2_L0; 4427 goto unlock; 4428 } 4429 4430 switch (hsotg->params.power_down) { 4431 case DWC2_POWER_DOWN_PARAM_PARTIAL: 4432 ret = dwc2_exit_partial_power_down(hsotg, 0, true); 4433 if (ret) 4434 dev_err(hsotg->dev, 4435 "exit partial_power_down failed\n"); 4436 /* 4437 * Set HW accessible bit before powering on the controller 4438 * since an interrupt may rise. 4439 */ 4440 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4441 break; 4442 case DWC2_POWER_DOWN_PARAM_HIBERNATION: 4443 ret = dwc2_exit_hibernation(hsotg, 0, 0, 1); 4444 if (ret) 4445 dev_err(hsotg->dev, "exit hibernation failed.\n"); 4446 4447 /* 4448 * Set HW accessible bit before powering on the controller 4449 * since an interrupt may rise. 4450 */ 4451 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4452 break; 4453 case DWC2_POWER_DOWN_PARAM_NONE: 4454 /* 4455 * If not hibernation nor partial power down are supported, 4456 * port resume is done using the clock gating programming flow. 4457 */ 4458 spin_unlock_irqrestore(&hsotg->lock, flags); 4459 dwc2_host_exit_clock_gating(hsotg, 0); 4460 4461 /* 4462 * Initialize the Core for Host mode, as after system resume 4463 * the global interrupts are disabled. 4464 */ 4465 dwc2_core_init(hsotg, false); 4466 dwc2_enable_global_interrupts(hsotg); 4467 dwc2_hcd_reinit(hsotg); 4468 spin_lock_irqsave(&hsotg->lock, flags); 4469 4470 /* 4471 * Set HW accessible bit before powering on the controller 4472 * since an interrupt may rise. 4473 */ 4474 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4475 break; 4476 default: 4477 hsotg->lx_state = DWC2_L0; 4478 goto unlock; 4479 } 4480 4481 /* Change Root port status, as port status change occurred after resume.*/ 4482 hsotg->flags.b.port_suspend_change = 1; 4483 4484 /* 4485 * Enable power if not already done. 4486 * This must not be spinlocked since duration 4487 * of this call is unknown. 4488 */ 4489 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4490 spin_unlock_irqrestore(&hsotg->lock, flags); 4491 usb_phy_set_suspend(hsotg->uphy, false); 4492 spin_lock_irqsave(&hsotg->lock, flags); 4493 } 4494 4495 /* Enable external vbus supply after resuming the port. */ 4496 spin_unlock_irqrestore(&hsotg->lock, flags); 4497 dwc2_vbus_supply_init(hsotg); 4498 4499 /* Wait for controller to correctly update D+/D- level */ 4500 usleep_range(3000, 5000); 4501 spin_lock_irqsave(&hsotg->lock, flags); 4502 4503 /* 4504 * Clear Port Enable and Port Status changes. 4505 * Enable Port Power. 4506 */ 4507 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET | 4508 HPRT0_ENACHG, HPRT0); 4509 4510 /* Wait for controller to detect Port Connect */ 4511 spin_unlock_irqrestore(&hsotg->lock, flags); 4512 usleep_range(5000, 7000); 4513 spin_lock_irqsave(&hsotg->lock, flags); 4514 unlock: 4515 spin_unlock_irqrestore(&hsotg->lock, flags); 4516 4517 return ret; 4518 } 4519 4520 /* Returns the current frame number */ 4521 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4522 { 4523 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4524 4525 return dwc2_hcd_get_frame_number(hsotg); 4526 } 4527 4528 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4529 char *fn_name) 4530 { 4531 #ifdef VERBOSE_DEBUG 4532 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4533 char *pipetype = NULL; 4534 char *speed = NULL; 4535 4536 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4537 dev_vdbg(hsotg->dev, " Device address: %d\n", 4538 usb_pipedevice(urb->pipe)); 4539 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4540 usb_pipeendpoint(urb->pipe), 4541 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4542 4543 switch (usb_pipetype(urb->pipe)) { 4544 case PIPE_CONTROL: 4545 pipetype = "CONTROL"; 4546 break; 4547 case PIPE_BULK: 4548 pipetype = "BULK"; 4549 break; 4550 case PIPE_INTERRUPT: 4551 pipetype = "INTERRUPT"; 4552 break; 4553 case PIPE_ISOCHRONOUS: 4554 pipetype = "ISOCHRONOUS"; 4555 break; 4556 } 4557 4558 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4559 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4560 "IN" : "OUT"); 4561 4562 switch (urb->dev->speed) { 4563 case USB_SPEED_HIGH: 4564 speed = "HIGH"; 4565 break; 4566 case USB_SPEED_FULL: 4567 speed = "FULL"; 4568 break; 4569 case USB_SPEED_LOW: 4570 speed = "LOW"; 4571 break; 4572 default: 4573 speed = "UNKNOWN"; 4574 break; 4575 } 4576 4577 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4578 dev_vdbg(hsotg->dev, " Max packet size: %d (%d mult)\n", 4579 usb_endpoint_maxp(&urb->ep->desc), 4580 usb_endpoint_maxp_mult(&urb->ep->desc)); 4581 4582 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4583 urb->transfer_buffer_length); 4584 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4585 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4586 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4587 urb->setup_packet, (unsigned long)urb->setup_dma); 4588 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4589 4590 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4591 int i; 4592 4593 for (i = 0; i < urb->number_of_packets; i++) { 4594 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4595 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4596 urb->iso_frame_desc[i].offset, 4597 urb->iso_frame_desc[i].length); 4598 } 4599 } 4600 #endif 4601 } 4602 4603 /* 4604 * Starts processing a USB transfer request specified by a USB Request Block 4605 * (URB). mem_flags indicates the type of memory allocation to use while 4606 * processing this URB. 4607 */ 4608 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4609 gfp_t mem_flags) 4610 { 4611 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4612 struct usb_host_endpoint *ep = urb->ep; 4613 struct dwc2_hcd_urb *dwc2_urb; 4614 int i; 4615 int retval; 4616 int alloc_bandwidth = 0; 4617 u8 ep_type = 0; 4618 u32 tflags = 0; 4619 void *buf; 4620 unsigned long flags; 4621 struct dwc2_qh *qh; 4622 bool qh_allocated = false; 4623 struct dwc2_qtd *qtd; 4624 struct dwc2_gregs_backup *gr; 4625 4626 gr = &hsotg->gr_backup; 4627 4628 if (dbg_urb(urb)) { 4629 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4630 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4631 } 4632 4633 if (hsotg->hibernated) { 4634 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 4635 retval = dwc2_exit_hibernation(hsotg, 0, 0, 1); 4636 else 4637 retval = dwc2_exit_hibernation(hsotg, 0, 0, 0); 4638 4639 if (retval) 4640 dev_err(hsotg->dev, 4641 "exit hibernation failed.\n"); 4642 } 4643 4644 if (hsotg->in_ppd) { 4645 retval = dwc2_exit_partial_power_down(hsotg, 0, true); 4646 if (retval) 4647 dev_err(hsotg->dev, 4648 "exit partial_power_down failed\n"); 4649 } 4650 4651 if (hsotg->params.power_down == DWC2_POWER_DOWN_PARAM_NONE && 4652 hsotg->bus_suspended) { 4653 if (dwc2_is_device_mode(hsotg)) 4654 dwc2_gadget_exit_clock_gating(hsotg, 0); 4655 else 4656 dwc2_host_exit_clock_gating(hsotg, 0); 4657 } 4658 4659 if (!ep) 4660 return -EINVAL; 4661 4662 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4663 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4664 spin_lock_irqsave(&hsotg->lock, flags); 4665 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4666 alloc_bandwidth = 1; 4667 spin_unlock_irqrestore(&hsotg->lock, flags); 4668 } 4669 4670 switch (usb_pipetype(urb->pipe)) { 4671 case PIPE_CONTROL: 4672 ep_type = USB_ENDPOINT_XFER_CONTROL; 4673 break; 4674 case PIPE_ISOCHRONOUS: 4675 ep_type = USB_ENDPOINT_XFER_ISOC; 4676 break; 4677 case PIPE_BULK: 4678 ep_type = USB_ENDPOINT_XFER_BULK; 4679 break; 4680 case PIPE_INTERRUPT: 4681 ep_type = USB_ENDPOINT_XFER_INT; 4682 break; 4683 } 4684 4685 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4686 mem_flags); 4687 if (!dwc2_urb) 4688 return -ENOMEM; 4689 4690 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4691 usb_pipeendpoint(urb->pipe), ep_type, 4692 usb_pipein(urb->pipe), 4693 usb_endpoint_maxp(&ep->desc), 4694 usb_endpoint_maxp_mult(&ep->desc)); 4695 4696 buf = urb->transfer_buffer; 4697 4698 if (hcd_uses_dma(hcd)) { 4699 if (!buf && (urb->transfer_dma & 3)) { 4700 dev_err(hsotg->dev, 4701 "%s: unaligned transfer with no transfer_buffer", 4702 __func__); 4703 retval = -EINVAL; 4704 goto fail0; 4705 } 4706 } 4707 4708 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4709 tflags |= URB_GIVEBACK_ASAP; 4710 if (urb->transfer_flags & URB_ZERO_PACKET) 4711 tflags |= URB_SEND_ZERO_PACKET; 4712 4713 dwc2_urb->priv = urb; 4714 dwc2_urb->buf = buf; 4715 dwc2_urb->dma = urb->transfer_dma; 4716 dwc2_urb->length = urb->transfer_buffer_length; 4717 dwc2_urb->setup_packet = urb->setup_packet; 4718 dwc2_urb->setup_dma = urb->setup_dma; 4719 dwc2_urb->flags = tflags; 4720 dwc2_urb->interval = urb->interval; 4721 dwc2_urb->status = -EINPROGRESS; 4722 4723 for (i = 0; i < urb->number_of_packets; ++i) 4724 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4725 urb->iso_frame_desc[i].offset, 4726 urb->iso_frame_desc[i].length); 4727 4728 urb->hcpriv = dwc2_urb; 4729 qh = (struct dwc2_qh *)ep->hcpriv; 4730 /* Create QH for the endpoint if it doesn't exist */ 4731 if (!qh) { 4732 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4733 if (!qh) { 4734 retval = -ENOMEM; 4735 goto fail0; 4736 } 4737 ep->hcpriv = qh; 4738 qh_allocated = true; 4739 } 4740 4741 qtd = kzalloc(sizeof(*qtd), mem_flags); 4742 if (!qtd) { 4743 retval = -ENOMEM; 4744 goto fail1; 4745 } 4746 4747 spin_lock_irqsave(&hsotg->lock, flags); 4748 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4749 if (retval) 4750 goto fail2; 4751 4752 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4753 if (retval) 4754 goto fail3; 4755 4756 if (alloc_bandwidth) { 4757 dwc2_allocate_bus_bandwidth(hcd, 4758 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4759 urb); 4760 } 4761 4762 spin_unlock_irqrestore(&hsotg->lock, flags); 4763 4764 return 0; 4765 4766 fail3: 4767 dwc2_urb->priv = NULL; 4768 usb_hcd_unlink_urb_from_ep(hcd, urb); 4769 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4770 qh->channel->qh = NULL; 4771 fail2: 4772 urb->hcpriv = NULL; 4773 spin_unlock_irqrestore(&hsotg->lock, flags); 4774 kfree(qtd); 4775 fail1: 4776 if (qh_allocated) { 4777 struct dwc2_qtd *qtd2, *qtd2_tmp; 4778 4779 ep->hcpriv = NULL; 4780 dwc2_hcd_qh_unlink(hsotg, qh); 4781 /* Free each QTD in the QH's QTD list */ 4782 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4783 qtd_list_entry) 4784 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4785 dwc2_hcd_qh_free(hsotg, qh); 4786 } 4787 fail0: 4788 kfree(dwc2_urb); 4789 4790 return retval; 4791 } 4792 4793 /* 4794 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4795 */ 4796 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4797 int status) 4798 { 4799 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4800 int rc; 4801 unsigned long flags; 4802 4803 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4804 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4805 4806 spin_lock_irqsave(&hsotg->lock, flags); 4807 4808 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4809 if (rc) 4810 goto out; 4811 4812 if (!urb->hcpriv) { 4813 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4814 goto out; 4815 } 4816 4817 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4818 4819 usb_hcd_unlink_urb_from_ep(hcd, urb); 4820 4821 kfree(urb->hcpriv); 4822 urb->hcpriv = NULL; 4823 4824 /* Higher layer software sets URB status */ 4825 spin_unlock(&hsotg->lock); 4826 usb_hcd_giveback_urb(hcd, urb, status); 4827 spin_lock(&hsotg->lock); 4828 4829 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4830 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4831 out: 4832 spin_unlock_irqrestore(&hsotg->lock, flags); 4833 4834 return rc; 4835 } 4836 4837 /* 4838 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4839 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4840 * must already be dequeued. 4841 */ 4842 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4843 struct usb_host_endpoint *ep) 4844 { 4845 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4846 4847 dev_dbg(hsotg->dev, 4848 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4849 ep->desc.bEndpointAddress, ep->hcpriv); 4850 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4851 } 4852 4853 /* 4854 * Resets endpoint specific parameter values, in current version used to reset 4855 * the data toggle (as a WA). This function can be called from usb_clear_halt 4856 * routine. 4857 */ 4858 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4859 struct usb_host_endpoint *ep) 4860 { 4861 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4862 unsigned long flags; 4863 4864 dev_dbg(hsotg->dev, 4865 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4866 ep->desc.bEndpointAddress); 4867 4868 spin_lock_irqsave(&hsotg->lock, flags); 4869 dwc2_hcd_endpoint_reset(hsotg, ep); 4870 spin_unlock_irqrestore(&hsotg->lock, flags); 4871 } 4872 4873 /* 4874 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4875 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4876 * interrupt. 4877 * 4878 * This function is called by the USB core when an interrupt occurs 4879 */ 4880 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4881 { 4882 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4883 4884 return dwc2_handle_hcd_intr(hsotg); 4885 } 4886 4887 /* 4888 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4889 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4890 * is the status change indicator for the single root port. Returns 1 if either 4891 * change indicator is 1, otherwise returns 0. 4892 */ 4893 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4894 { 4895 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4896 4897 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4898 return buf[0] != 0; 4899 } 4900 4901 /* Handles hub class-specific requests */ 4902 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4903 u16 windex, char *buf, u16 wlength) 4904 { 4905 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4906 wvalue, windex, buf, wlength); 4907 return retval; 4908 } 4909 4910 /* Handles hub TT buffer clear completions */ 4911 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4912 struct usb_host_endpoint *ep) 4913 { 4914 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4915 struct dwc2_qh *qh; 4916 unsigned long flags; 4917 4918 qh = ep->hcpriv; 4919 if (!qh) 4920 return; 4921 4922 spin_lock_irqsave(&hsotg->lock, flags); 4923 qh->tt_buffer_dirty = 0; 4924 4925 if (hsotg->flags.b.port_connect_status) 4926 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4927 4928 spin_unlock_irqrestore(&hsotg->lock, flags); 4929 } 4930 4931 /* 4932 * HPRT0_SPD_HIGH_SPEED: high speed 4933 * HPRT0_SPD_FULL_SPEED: full speed 4934 */ 4935 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4936 { 4937 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4938 4939 if (hsotg->params.speed == speed) 4940 return; 4941 4942 hsotg->params.speed = speed; 4943 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4944 } 4945 4946 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4947 { 4948 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4949 4950 if (!hsotg->params.change_speed_quirk) 4951 return; 4952 4953 /* 4954 * On removal, set speed to default high-speed. 4955 */ 4956 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4957 udev->parent->speed < USB_SPEED_HIGH) { 4958 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4959 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4960 } 4961 } 4962 4963 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 4964 { 4965 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4966 4967 if (!hsotg->params.change_speed_quirk) 4968 return 0; 4969 4970 if (udev->speed == USB_SPEED_HIGH) { 4971 dev_info(hsotg->dev, "Set speed to high-speed\n"); 4972 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4973 } else if ((udev->speed == USB_SPEED_FULL || 4974 udev->speed == USB_SPEED_LOW)) { 4975 /* 4976 * Change speed setting to full-speed if there's 4977 * a full-speed or low-speed device plugged in. 4978 */ 4979 dev_info(hsotg->dev, "Set speed to full-speed\n"); 4980 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 4981 } 4982 4983 return 0; 4984 } 4985 4986 static struct hc_driver dwc2_hc_driver = { 4987 .description = "dwc2_hsotg", 4988 .product_desc = "DWC OTG Controller", 4989 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4990 4991 .irq = _dwc2_hcd_irq, 4992 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4993 4994 .start = _dwc2_hcd_start, 4995 .stop = _dwc2_hcd_stop, 4996 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4997 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4998 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4999 .endpoint_reset = _dwc2_hcd_endpoint_reset, 5000 .get_frame_number = _dwc2_hcd_get_frame_number, 5001 5002 .hub_status_data = _dwc2_hcd_hub_status_data, 5003 .hub_control = _dwc2_hcd_hub_control, 5004 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 5005 5006 .bus_suspend = _dwc2_hcd_suspend, 5007 .bus_resume = _dwc2_hcd_resume, 5008 5009 .map_urb_for_dma = dwc2_map_urb_for_dma, 5010 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 5011 }; 5012 5013 /* 5014 * Frees secondary storage associated with the dwc2_hsotg structure contained 5015 * in the struct usb_hcd field 5016 */ 5017 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 5018 { 5019 u32 ahbcfg; 5020 u32 dctl; 5021 int i; 5022 5023 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 5024 5025 /* Free memory for QH/QTD lists */ 5026 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 5027 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 5028 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 5029 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 5030 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 5031 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 5032 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 5033 5034 /* Free memory for the host channels */ 5035 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 5036 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 5037 5038 if (chan) { 5039 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 5040 i, chan); 5041 hsotg->hc_ptr_array[i] = NULL; 5042 kfree(chan); 5043 } 5044 } 5045 5046 if (hsotg->params.host_dma) { 5047 if (hsotg->status_buf) { 5048 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 5049 hsotg->status_buf, 5050 hsotg->status_buf_dma); 5051 hsotg->status_buf = NULL; 5052 } 5053 } else { 5054 kfree(hsotg->status_buf); 5055 hsotg->status_buf = NULL; 5056 } 5057 5058 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 5059 5060 /* Disable all interrupts */ 5061 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5062 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 5063 dwc2_writel(hsotg, 0, GINTMSK); 5064 5065 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5066 dctl = dwc2_readl(hsotg, DCTL); 5067 dctl |= DCTL_SFTDISCON; 5068 dwc2_writel(hsotg, dctl, DCTL); 5069 } 5070 5071 if (hsotg->wq_otg) { 5072 if (!cancel_work_sync(&hsotg->wf_otg)) 5073 flush_workqueue(hsotg->wq_otg); 5074 destroy_workqueue(hsotg->wq_otg); 5075 } 5076 5077 cancel_work_sync(&hsotg->phy_reset_work); 5078 5079 del_timer(&hsotg->wkp_timer); 5080 } 5081 5082 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5083 { 5084 /* Turn off all host-specific interrupts */ 5085 dwc2_disable_host_interrupts(hsotg); 5086 5087 dwc2_hcd_free(hsotg); 5088 } 5089 5090 /* 5091 * Initializes the HCD. This function allocates memory for and initializes the 5092 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5093 * USB bus with the core and calls the hc_driver->start() function. It returns 5094 * a negative error on failure. 5095 */ 5096 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5097 { 5098 struct platform_device *pdev = to_platform_device(hsotg->dev); 5099 struct resource *res; 5100 struct usb_hcd *hcd; 5101 struct dwc2_host_chan *channel; 5102 u32 hcfg; 5103 int i, num_channels; 5104 int retval; 5105 5106 if (usb_disabled()) 5107 return -ENODEV; 5108 5109 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5110 5111 retval = -ENOMEM; 5112 5113 hcfg = dwc2_readl(hsotg, HCFG); 5114 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5115 5116 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5117 hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE, 5118 sizeof(*hsotg->frame_num_array), 5119 GFP_KERNEL); 5120 if (!hsotg->frame_num_array) 5121 goto error1; 5122 hsotg->last_frame_num_array = 5123 kcalloc(FRAME_NUM_ARRAY_SIZE, 5124 sizeof(*hsotg->last_frame_num_array), GFP_KERNEL); 5125 if (!hsotg->last_frame_num_array) 5126 goto error1; 5127 #endif 5128 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5129 5130 /* Check if the bus driver or platform code has setup a dma_mask */ 5131 if (hsotg->params.host_dma && 5132 !hsotg->dev->dma_mask) { 5133 dev_warn(hsotg->dev, 5134 "dma_mask not set, disabling DMA\n"); 5135 hsotg->params.host_dma = false; 5136 hsotg->params.dma_desc_enable = false; 5137 } 5138 5139 /* Set device flags indicating whether the HCD supports DMA */ 5140 if (hsotg->params.host_dma) { 5141 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5142 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5143 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5144 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5145 } 5146 5147 if (hsotg->params.change_speed_quirk) { 5148 dwc2_hc_driver.free_dev = dwc2_free_dev; 5149 dwc2_hc_driver.reset_device = dwc2_reset_device; 5150 } 5151 5152 if (hsotg->params.host_dma) 5153 dwc2_hc_driver.flags |= HCD_DMA; 5154 5155 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5156 if (!hcd) 5157 goto error1; 5158 5159 hcd->has_tt = 1; 5160 5161 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5162 if (!res) { 5163 retval = -EINVAL; 5164 goto error2; 5165 } 5166 hcd->rsrc_start = res->start; 5167 hcd->rsrc_len = resource_size(res); 5168 5169 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5170 hsotg->priv = hcd; 5171 5172 /* 5173 * Disable the global interrupt until all the interrupt handlers are 5174 * installed 5175 */ 5176 dwc2_disable_global_interrupts(hsotg); 5177 5178 /* Initialize the DWC_otg core, and select the Phy type */ 5179 retval = dwc2_core_init(hsotg, true); 5180 if (retval) 5181 goto error2; 5182 5183 /* Create new workqueue and init work */ 5184 retval = -ENOMEM; 5185 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5186 if (!hsotg->wq_otg) { 5187 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5188 goto error2; 5189 } 5190 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5191 5192 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); 5193 5194 /* Initialize the non-periodic schedule */ 5195 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5196 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 5197 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5198 5199 /* Initialize the periodic schedule */ 5200 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5201 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5202 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5203 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5204 5205 INIT_LIST_HEAD(&hsotg->split_order); 5206 5207 /* 5208 * Create a host channel descriptor for each host channel implemented 5209 * in the controller. Initialize the channel descriptor array. 5210 */ 5211 INIT_LIST_HEAD(&hsotg->free_hc_list); 5212 num_channels = hsotg->params.host_channels; 5213 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5214 5215 for (i = 0; i < num_channels; i++) { 5216 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5217 if (!channel) 5218 goto error3; 5219 channel->hc_num = i; 5220 INIT_LIST_HEAD(&channel->split_order_list_entry); 5221 hsotg->hc_ptr_array[i] = channel; 5222 } 5223 5224 /* Initialize work */ 5225 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5226 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5227 INIT_WORK(&hsotg->phy_reset_work, dwc2_hcd_phy_reset_func); 5228 5229 /* 5230 * Allocate space for storing data on status transactions. Normally no 5231 * data is sent, but this space acts as a bit bucket. This must be 5232 * done after usb_add_hcd since that function allocates the DMA buffer 5233 * pool. 5234 */ 5235 if (hsotg->params.host_dma) 5236 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5237 DWC2_HCD_STATUS_BUF_SIZE, 5238 &hsotg->status_buf_dma, GFP_KERNEL); 5239 else 5240 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5241 GFP_KERNEL); 5242 5243 if (!hsotg->status_buf) 5244 goto error3; 5245 5246 /* 5247 * Create kmem caches to handle descriptor buffers in descriptor 5248 * DMA mode. 5249 * Alignment must be set to 512 bytes. 5250 */ 5251 if (hsotg->params.dma_desc_enable || 5252 hsotg->params.dma_desc_fs_enable) { 5253 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5254 sizeof(struct dwc2_dma_desc) * 5255 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5256 NULL); 5257 if (!hsotg->desc_gen_cache) { 5258 dev_err(hsotg->dev, 5259 "unable to create dwc2 generic desc cache\n"); 5260 5261 /* 5262 * Disable descriptor dma mode since it will not be 5263 * usable. 5264 */ 5265 hsotg->params.dma_desc_enable = false; 5266 hsotg->params.dma_desc_fs_enable = false; 5267 } 5268 5269 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5270 sizeof(struct dwc2_dma_desc) * 5271 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5272 if (!hsotg->desc_hsisoc_cache) { 5273 dev_err(hsotg->dev, 5274 "unable to create dwc2 hs isoc desc cache\n"); 5275 5276 kmem_cache_destroy(hsotg->desc_gen_cache); 5277 5278 /* 5279 * Disable descriptor dma mode since it will not be 5280 * usable. 5281 */ 5282 hsotg->params.dma_desc_enable = false; 5283 hsotg->params.dma_desc_fs_enable = false; 5284 } 5285 } 5286 5287 if (hsotg->params.host_dma) { 5288 /* 5289 * Create kmem caches to handle non-aligned buffer 5290 * in Buffer DMA mode. 5291 */ 5292 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma", 5293 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4, 5294 SLAB_CACHE_DMA, NULL); 5295 if (!hsotg->unaligned_cache) 5296 dev_err(hsotg->dev, 5297 "unable to create dwc2 unaligned cache\n"); 5298 } 5299 5300 hsotg->otg_port = 1; 5301 hsotg->frame_list = NULL; 5302 hsotg->frame_list_dma = 0; 5303 hsotg->periodic_qh_count = 0; 5304 5305 /* Initiate lx_state to L3 disconnected state */ 5306 hsotg->lx_state = DWC2_L3; 5307 5308 hcd->self.otg_port = hsotg->otg_port; 5309 5310 /* Don't support SG list at this point */ 5311 hcd->self.sg_tablesize = 0; 5312 5313 hcd->tpl_support = of_usb_host_tpl_support(hsotg->dev->of_node); 5314 5315 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5316 otg_set_host(hsotg->uphy->otg, &hcd->self); 5317 5318 /* 5319 * Finish generic HCD initialization and start the HCD. This function 5320 * allocates the DMA buffer pool, registers the USB bus, requests the 5321 * IRQ line, and calls hcd_start method. 5322 */ 5323 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5324 if (retval < 0) 5325 goto error4; 5326 5327 device_wakeup_enable(hcd->self.controller); 5328 5329 dwc2_hcd_dump_state(hsotg); 5330 5331 dwc2_enable_global_interrupts(hsotg); 5332 5333 return 0; 5334 5335 error4: 5336 kmem_cache_destroy(hsotg->unaligned_cache); 5337 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5338 kmem_cache_destroy(hsotg->desc_gen_cache); 5339 error3: 5340 dwc2_hcd_release(hsotg); 5341 error2: 5342 usb_put_hcd(hcd); 5343 error1: 5344 5345 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5346 kfree(hsotg->last_frame_num_array); 5347 kfree(hsotg->frame_num_array); 5348 #endif 5349 5350 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5351 return retval; 5352 } 5353 5354 /* 5355 * Removes the HCD. 5356 * Frees memory and resources associated with the HCD and deregisters the bus. 5357 */ 5358 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5359 { 5360 struct usb_hcd *hcd; 5361 5362 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5363 5364 hcd = dwc2_hsotg_to_hcd(hsotg); 5365 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5366 5367 if (!hcd) { 5368 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5369 __func__); 5370 return; 5371 } 5372 5373 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5374 otg_set_host(hsotg->uphy->otg, NULL); 5375 5376 usb_remove_hcd(hcd); 5377 hsotg->priv = NULL; 5378 5379 kmem_cache_destroy(hsotg->unaligned_cache); 5380 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5381 kmem_cache_destroy(hsotg->desc_gen_cache); 5382 5383 dwc2_hcd_release(hsotg); 5384 usb_put_hcd(hcd); 5385 5386 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5387 kfree(hsotg->last_frame_num_array); 5388 kfree(hsotg->frame_num_array); 5389 #endif 5390 } 5391 5392 /** 5393 * dwc2_backup_host_registers() - Backup controller host registers. 5394 * When suspending usb bus, registers needs to be backuped 5395 * if controller power is disabled once suspended. 5396 * 5397 * @hsotg: Programming view of the DWC_otg controller 5398 */ 5399 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5400 { 5401 struct dwc2_hregs_backup *hr; 5402 int i; 5403 5404 dev_dbg(hsotg->dev, "%s\n", __func__); 5405 5406 /* Backup Host regs */ 5407 hr = &hsotg->hr_backup; 5408 hr->hcfg = dwc2_readl(hsotg, HCFG); 5409 hr->haintmsk = dwc2_readl(hsotg, HAINTMSK); 5410 for (i = 0; i < hsotg->params.host_channels; ++i) 5411 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i)); 5412 5413 hr->hprt0 = dwc2_read_hprt0(hsotg); 5414 hr->hfir = dwc2_readl(hsotg, HFIR); 5415 hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); 5416 hr->valid = true; 5417 5418 return 0; 5419 } 5420 5421 /** 5422 * dwc2_restore_host_registers() - Restore controller host registers. 5423 * When resuming usb bus, device registers needs to be restored 5424 * if controller power were disabled. 5425 * 5426 * @hsotg: Programming view of the DWC_otg controller 5427 */ 5428 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5429 { 5430 struct dwc2_hregs_backup *hr; 5431 int i; 5432 5433 dev_dbg(hsotg->dev, "%s\n", __func__); 5434 5435 /* Restore host regs */ 5436 hr = &hsotg->hr_backup; 5437 if (!hr->valid) { 5438 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5439 __func__); 5440 return -EINVAL; 5441 } 5442 hr->valid = false; 5443 5444 dwc2_writel(hsotg, hr->hcfg, HCFG); 5445 dwc2_writel(hsotg, hr->haintmsk, HAINTMSK); 5446 5447 for (i = 0; i < hsotg->params.host_channels; ++i) 5448 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i)); 5449 5450 dwc2_writel(hsotg, hr->hprt0, HPRT0); 5451 dwc2_writel(hsotg, hr->hfir, HFIR); 5452 dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ); 5453 hsotg->frame_number = 0; 5454 5455 return 0; 5456 } 5457 5458 /** 5459 * dwc2_host_enter_hibernation() - Put controller in Hibernation. 5460 * 5461 * @hsotg: Programming view of the DWC_otg controller 5462 */ 5463 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) 5464 { 5465 unsigned long flags; 5466 int ret = 0; 5467 u32 hprt0; 5468 u32 pcgcctl; 5469 u32 gusbcfg; 5470 u32 gpwrdn; 5471 5472 dev_dbg(hsotg->dev, "Preparing host for hibernation\n"); 5473 ret = dwc2_backup_global_registers(hsotg); 5474 if (ret) { 5475 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5476 __func__); 5477 return ret; 5478 } 5479 ret = dwc2_backup_host_registers(hsotg); 5480 if (ret) { 5481 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 5482 __func__); 5483 return ret; 5484 } 5485 5486 /* Enter USB Suspend Mode */ 5487 hprt0 = dwc2_readl(hsotg, HPRT0); 5488 hprt0 |= HPRT0_SUSP; 5489 hprt0 &= ~HPRT0_ENA; 5490 dwc2_writel(hsotg, hprt0, HPRT0); 5491 5492 /* Wait for the HPRT0.PrtSusp register field to be set */ 5493 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 5000)) 5494 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); 5495 5496 /* 5497 * We need to disable interrupts to prevent servicing of any IRQ 5498 * during going to hibernation 5499 */ 5500 spin_lock_irqsave(&hsotg->lock, flags); 5501 hsotg->lx_state = DWC2_L2; 5502 5503 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 5504 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { 5505 /* ULPI interface */ 5506 /* Suspend the Phy Clock */ 5507 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5508 pcgcctl |= PCGCTL_STOPPCLK; 5509 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5510 udelay(10); 5511 5512 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5513 gpwrdn |= GPWRDN_PMUACTV; 5514 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5515 udelay(10); 5516 } else { 5517 /* UTMI+ Interface */ 5518 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5519 gpwrdn |= GPWRDN_PMUACTV; 5520 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5521 udelay(10); 5522 5523 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5524 pcgcctl |= PCGCTL_STOPPCLK; 5525 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5526 udelay(10); 5527 } 5528 5529 /* Enable interrupts from wake up logic */ 5530 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5531 gpwrdn |= GPWRDN_PMUINTSEL; 5532 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5533 udelay(10); 5534 5535 /* Unmask host mode interrupts in GPWRDN */ 5536 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5537 gpwrdn |= GPWRDN_DISCONN_DET_MSK; 5538 gpwrdn |= GPWRDN_LNSTSCHG_MSK; 5539 gpwrdn |= GPWRDN_STS_CHGINT_MSK; 5540 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5541 udelay(10); 5542 5543 /* Enable Power Down Clamp */ 5544 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5545 gpwrdn |= GPWRDN_PWRDNCLMP; 5546 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5547 udelay(10); 5548 5549 /* Switch off VDD */ 5550 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5551 gpwrdn |= GPWRDN_PWRDNSWTCH; 5552 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5553 5554 hsotg->hibernated = 1; 5555 hsotg->bus_suspended = 1; 5556 dev_dbg(hsotg->dev, "Host hibernation completed\n"); 5557 spin_unlock_irqrestore(&hsotg->lock, flags); 5558 return ret; 5559 } 5560 5561 /* 5562 * dwc2_host_exit_hibernation() 5563 * 5564 * @hsotg: Programming view of the DWC_otg controller 5565 * @rem_wakeup: indicates whether resume is initiated by Device or Host. 5566 * @param reset: indicates whether resume is initiated by Reset. 5567 * 5568 * Return: non-zero if failed to enter to hibernation. 5569 * 5570 * This function is for exiting from Host mode hibernation by 5571 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. 5572 */ 5573 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 5574 int reset) 5575 { 5576 u32 gpwrdn; 5577 u32 hprt0; 5578 int ret = 0; 5579 struct dwc2_gregs_backup *gr; 5580 struct dwc2_hregs_backup *hr; 5581 5582 gr = &hsotg->gr_backup; 5583 hr = &hsotg->hr_backup; 5584 5585 dev_dbg(hsotg->dev, 5586 "%s: called with rem_wakeup = %d reset = %d\n", 5587 __func__, rem_wakeup, reset); 5588 5589 dwc2_hib_restore_common(hsotg, rem_wakeup, 1); 5590 hsotg->hibernated = 0; 5591 5592 /* 5593 * This step is not described in functional spec but if not wait for 5594 * this delay, mismatch interrupts occurred because just after restore 5595 * core is in Device mode(gintsts.curmode == 0) 5596 */ 5597 mdelay(100); 5598 5599 /* Clear all pending interupts */ 5600 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5601 5602 /* De-assert Restore */ 5603 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5604 gpwrdn &= ~GPWRDN_RESTORE; 5605 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5606 udelay(10); 5607 5608 /* Restore GUSBCFG, HCFG */ 5609 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 5610 dwc2_writel(hsotg, hr->hcfg, HCFG); 5611 5612 /* De-assert Wakeup Logic */ 5613 gpwrdn = dwc2_readl(hsotg, GPWRDN); 5614 gpwrdn &= ~GPWRDN_PMUACTV; 5615 dwc2_writel(hsotg, gpwrdn, GPWRDN); 5616 udelay(10); 5617 5618 hprt0 = hr->hprt0; 5619 hprt0 |= HPRT0_PWR; 5620 hprt0 &= ~HPRT0_ENA; 5621 hprt0 &= ~HPRT0_SUSP; 5622 dwc2_writel(hsotg, hprt0, HPRT0); 5623 5624 hprt0 = hr->hprt0; 5625 hprt0 |= HPRT0_PWR; 5626 hprt0 &= ~HPRT0_ENA; 5627 hprt0 &= ~HPRT0_SUSP; 5628 5629 if (reset) { 5630 hprt0 |= HPRT0_RST; 5631 dwc2_writel(hsotg, hprt0, HPRT0); 5632 5633 /* Wait for Resume time and then program HPRT again */ 5634 mdelay(60); 5635 hprt0 &= ~HPRT0_RST; 5636 dwc2_writel(hsotg, hprt0, HPRT0); 5637 } else { 5638 hprt0 |= HPRT0_RES; 5639 dwc2_writel(hsotg, hprt0, HPRT0); 5640 5641 /* Wait for Resume time and then program HPRT again */ 5642 mdelay(100); 5643 hprt0 &= ~HPRT0_RES; 5644 dwc2_writel(hsotg, hprt0, HPRT0); 5645 } 5646 /* Clear all interrupt status */ 5647 hprt0 = dwc2_readl(hsotg, HPRT0); 5648 hprt0 |= HPRT0_CONNDET; 5649 hprt0 |= HPRT0_ENACHG; 5650 hprt0 &= ~HPRT0_ENA; 5651 dwc2_writel(hsotg, hprt0, HPRT0); 5652 5653 hprt0 = dwc2_readl(hsotg, HPRT0); 5654 5655 /* Clear all pending interupts */ 5656 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5657 5658 /* Restore global registers */ 5659 ret = dwc2_restore_global_registers(hsotg); 5660 if (ret) { 5661 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5662 __func__); 5663 return ret; 5664 } 5665 5666 /* Restore host registers */ 5667 ret = dwc2_restore_host_registers(hsotg); 5668 if (ret) { 5669 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 5670 __func__); 5671 return ret; 5672 } 5673 5674 if (rem_wakeup) { 5675 dwc2_hcd_rem_wakeup(hsotg); 5676 /* 5677 * Change "port_connect_status_change" flag to re-enumerate, 5678 * because after exit from hibernation port connection status 5679 * is not detected. 5680 */ 5681 hsotg->flags.b.port_connect_status_change = 1; 5682 } 5683 5684 hsotg->hibernated = 0; 5685 hsotg->bus_suspended = 0; 5686 hsotg->lx_state = DWC2_L0; 5687 dev_dbg(hsotg->dev, "Host hibernation restore complete\n"); 5688 return ret; 5689 } 5690 5691 bool dwc2_host_can_poweroff_phy(struct dwc2_hsotg *dwc2) 5692 { 5693 struct usb_device *root_hub = dwc2_hsotg_to_hcd(dwc2)->self.root_hub; 5694 5695 /* If the controller isn't allowed to wakeup then we can power off. */ 5696 if (!device_may_wakeup(dwc2->dev)) 5697 return true; 5698 5699 /* 5700 * We don't want to power off the PHY if something under the 5701 * root hub has wakeup enabled. 5702 */ 5703 if (usb_wakeup_enabled_descendants(root_hub)) 5704 return false; 5705 5706 /* No reason to keep the PHY powered, so allow poweroff */ 5707 return true; 5708 } 5709 5710 /** 5711 * dwc2_host_enter_partial_power_down() - Put controller in partial 5712 * power down. 5713 * 5714 * @hsotg: Programming view of the DWC_otg controller 5715 * 5716 * Return: non-zero if failed to enter host partial power down. 5717 * 5718 * This function is for entering Host mode partial power down. 5719 */ 5720 int dwc2_host_enter_partial_power_down(struct dwc2_hsotg *hsotg) 5721 { 5722 u32 pcgcctl; 5723 u32 hprt0; 5724 int ret = 0; 5725 5726 dev_dbg(hsotg->dev, "Entering host partial power down started.\n"); 5727 5728 /* Put this port in suspend mode. */ 5729 hprt0 = dwc2_read_hprt0(hsotg); 5730 hprt0 |= HPRT0_SUSP; 5731 dwc2_writel(hsotg, hprt0, HPRT0); 5732 udelay(5); 5733 5734 /* Wait for the HPRT0.PrtSusp register field to be set */ 5735 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) 5736 dev_warn(hsotg->dev, "Suspend wasn't generated\n"); 5737 5738 /* Backup all registers */ 5739 ret = dwc2_backup_global_registers(hsotg); 5740 if (ret) { 5741 dev_err(hsotg->dev, "%s: failed to backup global registers\n", 5742 __func__); 5743 return ret; 5744 } 5745 5746 ret = dwc2_backup_host_registers(hsotg); 5747 if (ret) { 5748 dev_err(hsotg->dev, "%s: failed to backup host registers\n", 5749 __func__); 5750 return ret; 5751 } 5752 5753 /* 5754 * Clear any pending interrupts since dwc2 will not be able to 5755 * clear them after entering partial_power_down. 5756 */ 5757 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 5758 5759 /* Put the controller in low power state */ 5760 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5761 5762 pcgcctl |= PCGCTL_PWRCLMP; 5763 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5764 udelay(5); 5765 5766 pcgcctl |= PCGCTL_RSTPDWNMODULE; 5767 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5768 udelay(5); 5769 5770 pcgcctl |= PCGCTL_STOPPCLK; 5771 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5772 5773 /* Set in_ppd flag to 1 as here core enters suspend. */ 5774 hsotg->in_ppd = 1; 5775 hsotg->lx_state = DWC2_L2; 5776 hsotg->bus_suspended = true; 5777 5778 dev_dbg(hsotg->dev, "Entering host partial power down completed.\n"); 5779 5780 return ret; 5781 } 5782 5783 /* 5784 * dwc2_host_exit_partial_power_down() - Exit controller from host partial 5785 * power down. 5786 * 5787 * @hsotg: Programming view of the DWC_otg controller 5788 * @rem_wakeup: indicates whether resume is initiated by Reset. 5789 * @restore: indicates whether need to restore the registers or not. 5790 * 5791 * Return: non-zero if failed to exit host partial power down. 5792 * 5793 * This function is for exiting from Host mode partial power down. 5794 */ 5795 int dwc2_host_exit_partial_power_down(struct dwc2_hsotg *hsotg, 5796 int rem_wakeup, bool restore) 5797 { 5798 u32 pcgcctl; 5799 int ret = 0; 5800 u32 hprt0; 5801 5802 dev_dbg(hsotg->dev, "Exiting host partial power down started.\n"); 5803 5804 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5805 pcgcctl &= ~PCGCTL_STOPPCLK; 5806 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5807 udelay(5); 5808 5809 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5810 pcgcctl &= ~PCGCTL_PWRCLMP; 5811 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5812 udelay(5); 5813 5814 pcgcctl = dwc2_readl(hsotg, PCGCTL); 5815 pcgcctl &= ~PCGCTL_RSTPDWNMODULE; 5816 dwc2_writel(hsotg, pcgcctl, PCGCTL); 5817 5818 udelay(100); 5819 if (restore) { 5820 ret = dwc2_restore_global_registers(hsotg); 5821 if (ret) { 5822 dev_err(hsotg->dev, "%s: failed to restore registers\n", 5823 __func__); 5824 return ret; 5825 } 5826 5827 ret = dwc2_restore_host_registers(hsotg); 5828 if (ret) { 5829 dev_err(hsotg->dev, "%s: failed to restore host registers\n", 5830 __func__); 5831 return ret; 5832 } 5833 } 5834 5835 /* Drive resume signaling and exit suspend mode on the port. */ 5836 hprt0 = dwc2_read_hprt0(hsotg); 5837 hprt0 |= HPRT0_RES; 5838 hprt0 &= ~HPRT0_SUSP; 5839 dwc2_writel(hsotg, hprt0, HPRT0); 5840 udelay(5); 5841 5842 if (!rem_wakeup) { 5843 /* Stop driveing resume signaling on the port. */ 5844 hprt0 = dwc2_read_hprt0(hsotg); 5845 hprt0 &= ~HPRT0_RES; 5846 dwc2_writel(hsotg, hprt0, HPRT0); 5847 5848 hsotg->bus_suspended = false; 5849 } else { 5850 /* Turn on the port power bit. */ 5851 hprt0 = dwc2_read_hprt0(hsotg); 5852 hprt0 |= HPRT0_PWR; 5853 dwc2_writel(hsotg, hprt0, HPRT0); 5854 5855 /* Connect hcd. */ 5856 dwc2_hcd_connect(hsotg); 5857 5858 mod_timer(&hsotg->wkp_timer, 5859 jiffies + msecs_to_jiffies(71)); 5860 } 5861 5862 /* Set lx_state to and in_ppd to 0 as here core exits from suspend. */ 5863 hsotg->in_ppd = 0; 5864 hsotg->lx_state = DWC2_L0; 5865 5866 dev_dbg(hsotg->dev, "Exiting host partial power down completed.\n"); 5867 return ret; 5868 } 5869 5870 /** 5871 * dwc2_host_enter_clock_gating() - Put controller in clock gating. 5872 * 5873 * @hsotg: Programming view of the DWC_otg controller 5874 * 5875 * This function is for entering Host mode clock gating. 5876 */ 5877 void dwc2_host_enter_clock_gating(struct dwc2_hsotg *hsotg) 5878 { 5879 u32 hprt0; 5880 u32 pcgctl; 5881 5882 dev_dbg(hsotg->dev, "Entering host clock gating.\n"); 5883 5884 /* Put this port in suspend mode. */ 5885 hprt0 = dwc2_read_hprt0(hsotg); 5886 hprt0 |= HPRT0_SUSP; 5887 dwc2_writel(hsotg, hprt0, HPRT0); 5888 5889 /* Set the Phy Clock bit as suspend is received. */ 5890 pcgctl = dwc2_readl(hsotg, PCGCTL); 5891 pcgctl |= PCGCTL_STOPPCLK; 5892 dwc2_writel(hsotg, pcgctl, PCGCTL); 5893 udelay(5); 5894 5895 /* Set the Gate hclk as suspend is received. */ 5896 pcgctl = dwc2_readl(hsotg, PCGCTL); 5897 pcgctl |= PCGCTL_GATEHCLK; 5898 dwc2_writel(hsotg, pcgctl, PCGCTL); 5899 udelay(5); 5900 5901 hsotg->bus_suspended = true; 5902 hsotg->lx_state = DWC2_L2; 5903 } 5904 5905 /** 5906 * dwc2_host_exit_clock_gating() - Exit controller from clock gating. 5907 * 5908 * @hsotg: Programming view of the DWC_otg controller 5909 * @rem_wakeup: indicates whether resume is initiated by remote wakeup 5910 * 5911 * This function is for exiting Host mode clock gating. 5912 */ 5913 void dwc2_host_exit_clock_gating(struct dwc2_hsotg *hsotg, int rem_wakeup) 5914 { 5915 u32 hprt0; 5916 u32 pcgctl; 5917 5918 dev_dbg(hsotg->dev, "Exiting host clock gating.\n"); 5919 5920 /* Clear the Gate hclk. */ 5921 pcgctl = dwc2_readl(hsotg, PCGCTL); 5922 pcgctl &= ~PCGCTL_GATEHCLK; 5923 dwc2_writel(hsotg, pcgctl, PCGCTL); 5924 udelay(5); 5925 5926 /* Phy Clock bit. */ 5927 pcgctl = dwc2_readl(hsotg, PCGCTL); 5928 pcgctl &= ~PCGCTL_STOPPCLK; 5929 dwc2_writel(hsotg, pcgctl, PCGCTL); 5930 udelay(5); 5931 5932 /* Drive resume signaling and exit suspend mode on the port. */ 5933 hprt0 = dwc2_read_hprt0(hsotg); 5934 hprt0 |= HPRT0_RES; 5935 hprt0 &= ~HPRT0_SUSP; 5936 dwc2_writel(hsotg, hprt0, HPRT0); 5937 udelay(5); 5938 5939 if (!rem_wakeup) { 5940 /* In case of port resume need to wait for 40 ms */ 5941 msleep(USB_RESUME_TIMEOUT); 5942 5943 /* Stop driveing resume signaling on the port. */ 5944 hprt0 = dwc2_read_hprt0(hsotg); 5945 hprt0 &= ~HPRT0_RES; 5946 dwc2_writel(hsotg, hprt0, HPRT0); 5947 5948 hsotg->bus_suspended = false; 5949 hsotg->lx_state = DWC2_L0; 5950 } else { 5951 mod_timer(&hsotg->wkp_timer, 5952 jiffies + msecs_to_jiffies(71)); 5953 } 5954 } 5955