1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 58 59 /* 60 * ========================================================================= 61 * Host Core Layer Functions 62 * ========================================================================= 63 */ 64 65 /** 66 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 67 * used in both device and host modes 68 * 69 * @hsotg: Programming view of the DWC_otg controller 70 */ 71 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 72 { 73 u32 intmsk; 74 75 /* Clear any pending OTG Interrupts */ 76 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 77 78 /* Clear any pending interrupts */ 79 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 80 81 /* Enable the interrupts in the GINTMSK */ 82 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 83 84 if (!hsotg->params.host_dma) 85 intmsk |= GINTSTS_RXFLVL; 86 if (!hsotg->params.external_id_pin_ctl) 87 intmsk |= GINTSTS_CONIDSTSCHNG; 88 89 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 90 GINTSTS_SESSREQINT; 91 92 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 93 } 94 95 /* 96 * Initializes the FSLSPClkSel field of the HCFG register depending on the 97 * PHY type 98 */ 99 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 100 { 101 u32 hcfg, val; 102 103 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 104 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 105 hsotg->params.ulpi_fs_ls) || 106 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 107 /* Full speed PHY */ 108 val = HCFG_FSLSPCLKSEL_48_MHZ; 109 } else { 110 /* High speed PHY running at full speed or high speed */ 111 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 112 } 113 114 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 115 hcfg = dwc2_readl(hsotg->regs + HCFG); 116 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 117 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 118 dwc2_writel(hcfg, hsotg->regs + HCFG); 119 } 120 121 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 122 { 123 u32 usbcfg, i2cctl; 124 int retval = 0; 125 126 /* 127 * core_init() is now called on every switch so only call the 128 * following for the first time through 129 */ 130 if (select_phy) { 131 dev_dbg(hsotg->dev, "FS PHY selected\n"); 132 133 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 134 if (!(usbcfg & GUSBCFG_PHYSEL)) { 135 usbcfg |= GUSBCFG_PHYSEL; 136 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 137 138 /* Reset after a PHY select */ 139 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 140 141 if (retval) { 142 dev_err(hsotg->dev, 143 "%s: Reset failed, aborting", __func__); 144 return retval; 145 } 146 } 147 } 148 149 /* 150 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 151 * do this on HNP Dev/Host mode switches (done in dev_init and 152 * host_init). 153 */ 154 if (dwc2_is_host_mode(hsotg)) 155 dwc2_init_fs_ls_pclk_sel(hsotg); 156 157 if (hsotg->params.i2c_enable) { 158 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 159 160 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 161 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 162 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 163 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 164 165 /* Program GI2CCTL.I2CEn */ 166 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 167 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 168 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 169 i2cctl &= ~GI2CCTL_I2CEN; 170 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 171 i2cctl |= GI2CCTL_I2CEN; 172 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 173 } 174 175 return retval; 176 } 177 178 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 179 { 180 u32 usbcfg, usbcfg_old; 181 int retval = 0; 182 183 if (!select_phy) 184 return 0; 185 186 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 187 usbcfg_old = usbcfg; 188 189 /* 190 * HS PHY parameters. These parameters are preserved during soft reset 191 * so only program the first time. Do a soft reset immediately after 192 * setting phyif. 193 */ 194 switch (hsotg->params.phy_type) { 195 case DWC2_PHY_TYPE_PARAM_ULPI: 196 /* ULPI interface */ 197 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 198 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 199 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 200 if (hsotg->params.phy_ulpi_ddr) 201 usbcfg |= GUSBCFG_DDRSEL; 202 break; 203 case DWC2_PHY_TYPE_PARAM_UTMI: 204 /* UTMI+ interface */ 205 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 206 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 207 if (hsotg->params.phy_utmi_width == 16) 208 usbcfg |= GUSBCFG_PHYIF16; 209 break; 210 default: 211 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 212 break; 213 } 214 215 if (usbcfg != usbcfg_old) { 216 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 217 218 /* Reset after setting the PHY parameters */ 219 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 220 if (retval) { 221 dev_err(hsotg->dev, 222 "%s: Reset failed, aborting", __func__); 223 return retval; 224 } 225 } 226 227 return retval; 228 } 229 230 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 231 { 232 u32 usbcfg; 233 int retval = 0; 234 235 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 236 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 237 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 238 /* If FS/LS mode with FS/LS PHY */ 239 retval = dwc2_fs_phy_init(hsotg, select_phy); 240 if (retval) 241 return retval; 242 } else { 243 /* High speed PHY */ 244 retval = dwc2_hs_phy_init(hsotg, select_phy); 245 if (retval) 246 return retval; 247 } 248 249 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 250 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 251 hsotg->params.ulpi_fs_ls) { 252 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 253 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 254 usbcfg |= GUSBCFG_ULPI_FS_LS; 255 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 256 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 257 } else { 258 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 259 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 260 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 261 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 262 } 263 264 return retval; 265 } 266 267 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 268 { 269 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 270 271 switch (hsotg->hw_params.arch) { 272 case GHWCFG2_EXT_DMA_ARCH: 273 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 274 return -EINVAL; 275 276 case GHWCFG2_INT_DMA_ARCH: 277 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 278 if (hsotg->params.ahbcfg != -1) { 279 ahbcfg &= GAHBCFG_CTRL_MASK; 280 ahbcfg |= hsotg->params.ahbcfg & 281 ~GAHBCFG_CTRL_MASK; 282 } 283 break; 284 285 case GHWCFG2_SLAVE_ONLY_ARCH: 286 default: 287 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 288 break; 289 } 290 291 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n", 292 hsotg->params.host_dma, 293 hsotg->params.dma_desc_enable); 294 295 if (hsotg->params.host_dma) { 296 if (hsotg->params.dma_desc_enable) 297 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 298 else 299 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 300 } else { 301 dev_dbg(hsotg->dev, "Using Slave mode\n"); 302 hsotg->params.dma_desc_enable = false; 303 } 304 305 if (hsotg->params.host_dma) 306 ahbcfg |= GAHBCFG_DMA_EN; 307 308 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 309 310 return 0; 311 } 312 313 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 314 { 315 u32 usbcfg; 316 317 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 318 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 319 320 switch (hsotg->hw_params.op_mode) { 321 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 322 if (hsotg->params.otg_cap == 323 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 324 usbcfg |= GUSBCFG_HNPCAP; 325 if (hsotg->params.otg_cap != 326 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 327 usbcfg |= GUSBCFG_SRPCAP; 328 break; 329 330 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 331 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 332 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 333 if (hsotg->params.otg_cap != 334 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 335 usbcfg |= GUSBCFG_SRPCAP; 336 break; 337 338 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 339 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 340 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 341 default: 342 break; 343 } 344 345 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 346 } 347 348 /** 349 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 350 * 351 * @hsotg: Programming view of DWC_otg controller 352 */ 353 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 354 { 355 u32 intmsk; 356 357 dev_dbg(hsotg->dev, "%s()\n", __func__); 358 359 /* Disable all interrupts */ 360 dwc2_writel(0, hsotg->regs + GINTMSK); 361 dwc2_writel(0, hsotg->regs + HAINTMSK); 362 363 /* Enable the common interrupts */ 364 dwc2_enable_common_interrupts(hsotg); 365 366 /* Enable host mode interrupts without disturbing common interrupts */ 367 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 368 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 369 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 370 } 371 372 /** 373 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 374 * 375 * @hsotg: Programming view of DWC_otg controller 376 */ 377 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 378 { 379 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 380 381 /* Disable host mode interrupts without disturbing common interrupts */ 382 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 383 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 384 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 385 } 386 387 /* 388 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 389 * For system that have a total fifo depth that is smaller than the default 390 * RX + TX fifo size. 391 * 392 * @hsotg: Programming view of DWC_otg controller 393 */ 394 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 395 { 396 struct dwc2_core_params *params = &hsotg->params; 397 struct dwc2_hw_params *hw = &hsotg->hw_params; 398 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 399 400 total_fifo_size = hw->total_fifo_size; 401 rxfsiz = params->host_rx_fifo_size; 402 nptxfsiz = params->host_nperio_tx_fifo_size; 403 ptxfsiz = params->host_perio_tx_fifo_size; 404 405 /* 406 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 407 * allocation with support for high bandwidth endpoints. Synopsys 408 * defines MPS(Max Packet size) for a periodic EP=1024, and for 409 * non-periodic as 512. 410 */ 411 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 412 /* 413 * For Buffer DMA mode/Scatter Gather DMA mode 414 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 415 * with n = number of host channel. 416 * 2 * ((1024/4) + 2) = 516 417 */ 418 rxfsiz = 516 + hw->host_channels; 419 420 /* 421 * min non-periodic tx fifo depth 422 * 2 * (largest non-periodic USB packet used / 4) 423 * 2 * (512/4) = 256 424 */ 425 nptxfsiz = 256; 426 427 /* 428 * min periodic tx fifo depth 429 * (largest packet size*MC)/4 430 * (1024 * 3)/4 = 768 431 */ 432 ptxfsiz = 768; 433 434 params->host_rx_fifo_size = rxfsiz; 435 params->host_nperio_tx_fifo_size = nptxfsiz; 436 params->host_perio_tx_fifo_size = ptxfsiz; 437 } 438 439 /* 440 * If the summation of RX, NPTX and PTX fifo sizes is still 441 * bigger than the total_fifo_size, then we have a problem. 442 * 443 * We won't be able to allocate as many endpoints. Right now, 444 * we're just printing an error message, but ideally this FIFO 445 * allocation algorithm would be improved in the future. 446 * 447 * FIXME improve this FIFO allocation algorithm. 448 */ 449 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 450 dev_err(hsotg->dev, "invalid fifo sizes\n"); 451 } 452 453 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 454 { 455 struct dwc2_core_params *params = &hsotg->params; 456 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 457 458 if (!params->enable_dynamic_fifo) 459 return; 460 461 dwc2_calculate_dynamic_fifo(hsotg); 462 463 /* Rx FIFO */ 464 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 465 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 466 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 467 grxfsiz |= params->host_rx_fifo_size << 468 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 469 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 470 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 471 dwc2_readl(hsotg->regs + GRXFSIZ)); 472 473 /* Non-periodic Tx FIFO */ 474 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 475 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 476 nptxfsiz = params->host_nperio_tx_fifo_size << 477 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 478 nptxfsiz |= params->host_rx_fifo_size << 479 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 480 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 481 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 482 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 483 484 /* Periodic Tx FIFO */ 485 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 486 dwc2_readl(hsotg->regs + HPTXFSIZ)); 487 hptxfsiz = params->host_perio_tx_fifo_size << 488 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 489 hptxfsiz |= (params->host_rx_fifo_size + 490 params->host_nperio_tx_fifo_size) << 491 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 492 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 493 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 494 dwc2_readl(hsotg->regs + HPTXFSIZ)); 495 496 if (hsotg->params.en_multiple_tx_fifo && 497 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { 498 /* 499 * Global DFIFOCFG calculation for Host mode - 500 * include RxFIFO, NPTXFIFO and HPTXFIFO 501 */ 502 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 503 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 504 dfifocfg |= (params->host_rx_fifo_size + 505 params->host_nperio_tx_fifo_size + 506 params->host_perio_tx_fifo_size) << 507 GDFIFOCFG_EPINFOBASE_SHIFT & 508 GDFIFOCFG_EPINFOBASE_MASK; 509 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 510 } 511 } 512 513 /** 514 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 515 * the HFIR register according to PHY type and speed 516 * 517 * @hsotg: Programming view of DWC_otg controller 518 * 519 * NOTE: The caller can modify the value of the HFIR register only after the 520 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 521 * has been set 522 */ 523 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 524 { 525 u32 usbcfg; 526 u32 hprt0; 527 int clock = 60; /* default value */ 528 529 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 530 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 531 532 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 533 !(usbcfg & GUSBCFG_PHYIF16)) 534 clock = 60; 535 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 536 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 537 clock = 48; 538 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 539 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 540 clock = 30; 541 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 542 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 543 clock = 60; 544 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 545 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 546 clock = 48; 547 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 548 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 549 clock = 48; 550 if ((usbcfg & GUSBCFG_PHYSEL) && 551 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 552 clock = 48; 553 554 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 555 /* High speed case */ 556 return 125 * clock - 1; 557 558 /* FS/LS case */ 559 return 1000 * clock - 1; 560 } 561 562 /** 563 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 564 * buffer 565 * 566 * @core_if: Programming view of DWC_otg controller 567 * @dest: Destination buffer for the packet 568 * @bytes: Number of bytes to copy to the destination 569 */ 570 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 571 { 572 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 573 u32 *data_buf = (u32 *)dest; 574 int word_count = (bytes + 3) / 4; 575 int i; 576 577 /* 578 * Todo: Account for the case where dest is not dword aligned. This 579 * requires reading data from the FIFO into a u32 temp buffer, then 580 * moving it into the data buffer. 581 */ 582 583 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 584 585 for (i = 0; i < word_count; i++, data_buf++) 586 *data_buf = dwc2_readl(fifo); 587 } 588 589 /** 590 * dwc2_dump_channel_info() - Prints the state of a host channel 591 * 592 * @hsotg: Programming view of DWC_otg controller 593 * @chan: Pointer to the channel to dump 594 * 595 * Must be called with interrupt disabled and spinlock held 596 * 597 * NOTE: This function will be removed once the peripheral controller code 598 * is integrated and the driver is stable 599 */ 600 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 601 struct dwc2_host_chan *chan) 602 { 603 #ifdef VERBOSE_DEBUG 604 int num_channels = hsotg->params.host_channels; 605 struct dwc2_qh *qh; 606 u32 hcchar; 607 u32 hcsplt; 608 u32 hctsiz; 609 u32 hc_dma; 610 int i; 611 612 if (!chan) 613 return; 614 615 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 616 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 617 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 618 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 619 620 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 621 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 622 hcchar, hcsplt); 623 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 624 hctsiz, hc_dma); 625 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 626 chan->dev_addr, chan->ep_num, chan->ep_is_in); 627 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 628 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 629 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 630 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 631 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 632 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 633 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 634 (unsigned long)chan->xfer_dma); 635 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 636 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 637 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 638 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 639 qh_list_entry) 640 dev_dbg(hsotg->dev, " %p\n", qh); 641 dev_dbg(hsotg->dev, " NP active sched:\n"); 642 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 643 qh_list_entry) 644 dev_dbg(hsotg->dev, " %p\n", qh); 645 dev_dbg(hsotg->dev, " Channels:\n"); 646 for (i = 0; i < num_channels; i++) { 647 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 648 649 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 650 } 651 #endif /* VERBOSE_DEBUG */ 652 } 653 654 static int _dwc2_hcd_start(struct usb_hcd *hcd); 655 656 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 657 { 658 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 659 660 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 661 _dwc2_hcd_start(hcd); 662 } 663 664 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 665 { 666 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 667 668 hcd->self.is_b_host = 0; 669 } 670 671 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 672 int *hub_addr, int *hub_port) 673 { 674 struct urb *urb = context; 675 676 if (urb->dev->tt) 677 *hub_addr = urb->dev->tt->hub->devnum; 678 else 679 *hub_addr = 0; 680 *hub_port = urb->dev->ttport; 681 } 682 683 /* 684 * ========================================================================= 685 * Low Level Host Channel Access Functions 686 * ========================================================================= 687 */ 688 689 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 690 struct dwc2_host_chan *chan) 691 { 692 u32 hcintmsk = HCINTMSK_CHHLTD; 693 694 switch (chan->ep_type) { 695 case USB_ENDPOINT_XFER_CONTROL: 696 case USB_ENDPOINT_XFER_BULK: 697 dev_vdbg(hsotg->dev, "control/bulk\n"); 698 hcintmsk |= HCINTMSK_XFERCOMPL; 699 hcintmsk |= HCINTMSK_STALL; 700 hcintmsk |= HCINTMSK_XACTERR; 701 hcintmsk |= HCINTMSK_DATATGLERR; 702 if (chan->ep_is_in) { 703 hcintmsk |= HCINTMSK_BBLERR; 704 } else { 705 hcintmsk |= HCINTMSK_NAK; 706 hcintmsk |= HCINTMSK_NYET; 707 if (chan->do_ping) 708 hcintmsk |= HCINTMSK_ACK; 709 } 710 711 if (chan->do_split) { 712 hcintmsk |= HCINTMSK_NAK; 713 if (chan->complete_split) 714 hcintmsk |= HCINTMSK_NYET; 715 else 716 hcintmsk |= HCINTMSK_ACK; 717 } 718 719 if (chan->error_state) 720 hcintmsk |= HCINTMSK_ACK; 721 break; 722 723 case USB_ENDPOINT_XFER_INT: 724 if (dbg_perio()) 725 dev_vdbg(hsotg->dev, "intr\n"); 726 hcintmsk |= HCINTMSK_XFERCOMPL; 727 hcintmsk |= HCINTMSK_NAK; 728 hcintmsk |= HCINTMSK_STALL; 729 hcintmsk |= HCINTMSK_XACTERR; 730 hcintmsk |= HCINTMSK_DATATGLERR; 731 hcintmsk |= HCINTMSK_FRMOVRUN; 732 733 if (chan->ep_is_in) 734 hcintmsk |= HCINTMSK_BBLERR; 735 if (chan->error_state) 736 hcintmsk |= HCINTMSK_ACK; 737 if (chan->do_split) { 738 if (chan->complete_split) 739 hcintmsk |= HCINTMSK_NYET; 740 else 741 hcintmsk |= HCINTMSK_ACK; 742 } 743 break; 744 745 case USB_ENDPOINT_XFER_ISOC: 746 if (dbg_perio()) 747 dev_vdbg(hsotg->dev, "isoc\n"); 748 hcintmsk |= HCINTMSK_XFERCOMPL; 749 hcintmsk |= HCINTMSK_FRMOVRUN; 750 hcintmsk |= HCINTMSK_ACK; 751 752 if (chan->ep_is_in) { 753 hcintmsk |= HCINTMSK_XACTERR; 754 hcintmsk |= HCINTMSK_BBLERR; 755 } 756 break; 757 default: 758 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 759 break; 760 } 761 762 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 763 if (dbg_hc(chan)) 764 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 765 } 766 767 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 768 struct dwc2_host_chan *chan) 769 { 770 u32 hcintmsk = HCINTMSK_CHHLTD; 771 772 /* 773 * For Descriptor DMA mode core halts the channel on AHB error. 774 * Interrupt is not required. 775 */ 776 if (!hsotg->params.dma_desc_enable) { 777 if (dbg_hc(chan)) 778 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 779 hcintmsk |= HCINTMSK_AHBERR; 780 } else { 781 if (dbg_hc(chan)) 782 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 783 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 784 hcintmsk |= HCINTMSK_XFERCOMPL; 785 } 786 787 if (chan->error_state && !chan->do_split && 788 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 789 if (dbg_hc(chan)) 790 dev_vdbg(hsotg->dev, "setting ACK\n"); 791 hcintmsk |= HCINTMSK_ACK; 792 if (chan->ep_is_in) { 793 hcintmsk |= HCINTMSK_DATATGLERR; 794 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 795 hcintmsk |= HCINTMSK_NAK; 796 } 797 } 798 799 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 800 if (dbg_hc(chan)) 801 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 802 } 803 804 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 805 struct dwc2_host_chan *chan) 806 { 807 u32 intmsk; 808 809 if (hsotg->params.host_dma) { 810 if (dbg_hc(chan)) 811 dev_vdbg(hsotg->dev, "DMA enabled\n"); 812 dwc2_hc_enable_dma_ints(hsotg, chan); 813 } else { 814 if (dbg_hc(chan)) 815 dev_vdbg(hsotg->dev, "DMA disabled\n"); 816 dwc2_hc_enable_slave_ints(hsotg, chan); 817 } 818 819 /* Enable the top level host channel interrupt */ 820 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 821 intmsk |= 1 << chan->hc_num; 822 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 823 if (dbg_hc(chan)) 824 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 825 826 /* Make sure host channel interrupts are enabled */ 827 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 828 intmsk |= GINTSTS_HCHINT; 829 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 830 if (dbg_hc(chan)) 831 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 832 } 833 834 /** 835 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 836 * a specific endpoint 837 * 838 * @hsotg: Programming view of DWC_otg controller 839 * @chan: Information needed to initialize the host channel 840 * 841 * The HCCHARn register is set up with the characteristics specified in chan. 842 * Host channel interrupts that may need to be serviced while this transfer is 843 * in progress are enabled. 844 */ 845 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 846 { 847 u8 hc_num = chan->hc_num; 848 u32 hcintmsk; 849 u32 hcchar; 850 u32 hcsplt = 0; 851 852 if (dbg_hc(chan)) 853 dev_vdbg(hsotg->dev, "%s()\n", __func__); 854 855 /* Clear old interrupt conditions for this host channel */ 856 hcintmsk = 0xffffffff; 857 hcintmsk &= ~HCINTMSK_RESERVED14_31; 858 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 859 860 /* Enable channel interrupts required for this transfer */ 861 dwc2_hc_enable_ints(hsotg, chan); 862 863 /* 864 * Program the HCCHARn register with the endpoint characteristics for 865 * the current transfer 866 */ 867 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 868 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 869 if (chan->ep_is_in) 870 hcchar |= HCCHAR_EPDIR; 871 if (chan->speed == USB_SPEED_LOW) 872 hcchar |= HCCHAR_LSPDDEV; 873 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 874 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 875 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 876 if (dbg_hc(chan)) { 877 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 878 hc_num, hcchar); 879 880 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 881 __func__, hc_num); 882 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 883 chan->dev_addr); 884 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 885 chan->ep_num); 886 dev_vdbg(hsotg->dev, " Is In: %d\n", 887 chan->ep_is_in); 888 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 889 chan->speed == USB_SPEED_LOW); 890 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 891 chan->ep_type); 892 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 893 chan->max_packet); 894 } 895 896 /* Program the HCSPLT register for SPLITs */ 897 if (chan->do_split) { 898 if (dbg_hc(chan)) 899 dev_vdbg(hsotg->dev, 900 "Programming HC %d with split --> %s\n", 901 hc_num, 902 chan->complete_split ? "CSPLIT" : "SSPLIT"); 903 if (chan->complete_split) 904 hcsplt |= HCSPLT_COMPSPLT; 905 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 906 HCSPLT_XACTPOS_MASK; 907 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 908 HCSPLT_HUBADDR_MASK; 909 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 910 HCSPLT_PRTADDR_MASK; 911 if (dbg_hc(chan)) { 912 dev_vdbg(hsotg->dev, " comp split %d\n", 913 chan->complete_split); 914 dev_vdbg(hsotg->dev, " xact pos %d\n", 915 chan->xact_pos); 916 dev_vdbg(hsotg->dev, " hub addr %d\n", 917 chan->hub_addr); 918 dev_vdbg(hsotg->dev, " hub port %d\n", 919 chan->hub_port); 920 dev_vdbg(hsotg->dev, " is_in %d\n", 921 chan->ep_is_in); 922 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 923 chan->max_packet); 924 dev_vdbg(hsotg->dev, " xferlen %d\n", 925 chan->xfer_len); 926 } 927 } 928 929 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 930 } 931 932 /** 933 * dwc2_hc_halt() - Attempts to halt a host channel 934 * 935 * @hsotg: Controller register interface 936 * @chan: Host channel to halt 937 * @halt_status: Reason for halting the channel 938 * 939 * This function should only be called in Slave mode or to abort a transfer in 940 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 941 * controller halts the channel when the transfer is complete or a condition 942 * occurs that requires application intervention. 943 * 944 * In slave mode, checks for a free request queue entry, then sets the Channel 945 * Enable and Channel Disable bits of the Host Channel Characteristics 946 * register of the specified channel to intiate the halt. If there is no free 947 * request queue entry, sets only the Channel Disable bit of the HCCHARn 948 * register to flush requests for this channel. In the latter case, sets a 949 * flag to indicate that the host channel needs to be halted when a request 950 * queue slot is open. 951 * 952 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 953 * HCCHARn register. The controller ensures there is space in the request 954 * queue before submitting the halt request. 955 * 956 * Some time may elapse before the core flushes any posted requests for this 957 * host channel and halts. The Channel Halted interrupt handler completes the 958 * deactivation of the host channel. 959 */ 960 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 961 enum dwc2_halt_status halt_status) 962 { 963 u32 nptxsts, hptxsts, hcchar; 964 965 if (dbg_hc(chan)) 966 dev_vdbg(hsotg->dev, "%s()\n", __func__); 967 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 968 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 969 970 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 971 halt_status == DWC2_HC_XFER_AHB_ERR) { 972 /* 973 * Disable all channel interrupts except Ch Halted. The QTD 974 * and QH state associated with this transfer has been cleared 975 * (in the case of URB_DEQUEUE), so the channel needs to be 976 * shut down carefully to prevent crashes. 977 */ 978 u32 hcintmsk = HCINTMSK_CHHLTD; 979 980 dev_vdbg(hsotg->dev, "dequeue/error\n"); 981 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 982 983 /* 984 * Make sure no other interrupts besides halt are currently 985 * pending. Handling another interrupt could cause a crash due 986 * to the QTD and QH state. 987 */ 988 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 989 990 /* 991 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 992 * even if the channel was already halted for some other 993 * reason 994 */ 995 chan->halt_status = halt_status; 996 997 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 998 if (!(hcchar & HCCHAR_CHENA)) { 999 /* 1000 * The channel is either already halted or it hasn't 1001 * started yet. In DMA mode, the transfer may halt if 1002 * it finishes normally or a condition occurs that 1003 * requires driver intervention. Don't want to halt 1004 * the channel again. In either Slave or DMA mode, 1005 * it's possible that the transfer has been assigned 1006 * to a channel, but not started yet when an URB is 1007 * dequeued. Don't want to halt a channel that hasn't 1008 * started yet. 1009 */ 1010 return; 1011 } 1012 } 1013 if (chan->halt_pending) { 1014 /* 1015 * A halt has already been issued for this channel. This might 1016 * happen when a transfer is aborted by a higher level in 1017 * the stack. 1018 */ 1019 dev_vdbg(hsotg->dev, 1020 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1021 __func__, chan->hc_num); 1022 return; 1023 } 1024 1025 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1026 1027 /* No need to set the bit in DDMA for disabling the channel */ 1028 /* TODO check it everywhere channel is disabled */ 1029 if (!hsotg->params.dma_desc_enable) { 1030 if (dbg_hc(chan)) 1031 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1032 hcchar |= HCCHAR_CHENA; 1033 } else { 1034 if (dbg_hc(chan)) 1035 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1036 } 1037 hcchar |= HCCHAR_CHDIS; 1038 1039 if (!hsotg->params.host_dma) { 1040 if (dbg_hc(chan)) 1041 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1042 hcchar |= HCCHAR_CHENA; 1043 1044 /* Check for space in the request queue to issue the halt */ 1045 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1046 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1047 dev_vdbg(hsotg->dev, "control/bulk\n"); 1048 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1049 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1050 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1051 hcchar &= ~HCCHAR_CHENA; 1052 } 1053 } else { 1054 if (dbg_perio()) 1055 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1056 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1057 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1058 hsotg->queuing_high_bandwidth) { 1059 if (dbg_perio()) 1060 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1061 hcchar &= ~HCCHAR_CHENA; 1062 } 1063 } 1064 } else { 1065 if (dbg_hc(chan)) 1066 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1067 } 1068 1069 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1070 chan->halt_status = halt_status; 1071 1072 if (hcchar & HCCHAR_CHENA) { 1073 if (dbg_hc(chan)) 1074 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1075 chan->halt_pending = 1; 1076 chan->halt_on_queue = 0; 1077 } else { 1078 if (dbg_hc(chan)) 1079 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1080 chan->halt_on_queue = 1; 1081 } 1082 1083 if (dbg_hc(chan)) { 1084 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1085 chan->hc_num); 1086 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1087 hcchar); 1088 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1089 chan->halt_pending); 1090 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1091 chan->halt_on_queue); 1092 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1093 chan->halt_status); 1094 } 1095 } 1096 1097 /** 1098 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1099 * 1100 * @hsotg: Programming view of DWC_otg controller 1101 * @chan: Identifies the host channel to clean up 1102 * 1103 * This function is normally called after a transfer is done and the host 1104 * channel is being released 1105 */ 1106 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1107 { 1108 u32 hcintmsk; 1109 1110 chan->xfer_started = 0; 1111 1112 list_del_init(&chan->split_order_list_entry); 1113 1114 /* 1115 * Clear channel interrupt enables and any unhandled channel interrupt 1116 * conditions 1117 */ 1118 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1119 hcintmsk = 0xffffffff; 1120 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1121 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1122 } 1123 1124 /** 1125 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1126 * which frame a periodic transfer should occur 1127 * 1128 * @hsotg: Programming view of DWC_otg controller 1129 * @chan: Identifies the host channel to set up and its properties 1130 * @hcchar: Current value of the HCCHAR register for the specified host channel 1131 * 1132 * This function has no effect on non-periodic transfers 1133 */ 1134 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1135 struct dwc2_host_chan *chan, u32 *hcchar) 1136 { 1137 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1138 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1139 int host_speed; 1140 int xfer_ns; 1141 int xfer_us; 1142 int bytes_in_fifo; 1143 u16 fifo_space; 1144 u16 frame_number; 1145 u16 wire_frame; 1146 1147 /* 1148 * Try to figure out if we're an even or odd frame. If we set 1149 * even and the current frame number is even the the transfer 1150 * will happen immediately. Similar if both are odd. If one is 1151 * even and the other is odd then the transfer will happen when 1152 * the frame number ticks. 1153 * 1154 * There's a bit of a balancing act to get this right. 1155 * Sometimes we may want to send data in the current frame (AK 1156 * right away). We might want to do this if the frame number 1157 * _just_ ticked, but we might also want to do this in order 1158 * to continue a split transaction that happened late in a 1159 * microframe (so we didn't know to queue the next transfer 1160 * until the frame number had ticked). The problem is that we 1161 * need a lot of knowledge to know if there's actually still 1162 * time to send things or if it would be better to wait until 1163 * the next frame. 1164 * 1165 * We can look at how much time is left in the current frame 1166 * and make a guess about whether we'll have time to transfer. 1167 * We'll do that. 1168 */ 1169 1170 /* Get speed host is running at */ 1171 host_speed = (chan->speed != USB_SPEED_HIGH && 1172 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1173 1174 /* See how many bytes are in the periodic FIFO right now */ 1175 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1176 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1177 bytes_in_fifo = sizeof(u32) * 1178 (hsotg->params.host_perio_tx_fifo_size - 1179 fifo_space); 1180 1181 /* 1182 * Roughly estimate bus time for everything in the periodic 1183 * queue + our new transfer. This is "rough" because we're 1184 * using a function that makes takes into account IN/OUT 1185 * and INT/ISO and we're just slamming in one value for all 1186 * transfers. This should be an over-estimate and that should 1187 * be OK, but we can probably tighten it. 1188 */ 1189 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1190 chan->xfer_len + bytes_in_fifo); 1191 xfer_us = NS_TO_US(xfer_ns); 1192 1193 /* See what frame number we'll be at by the time we finish */ 1194 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1195 1196 /* This is when we were scheduled to be on the wire */ 1197 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1198 1199 /* 1200 * If we'd finish _after_ the frame we're scheduled in then 1201 * it's hopeless. Just schedule right away and hope for the 1202 * best. Note that it _might_ be wise to call back into the 1203 * scheduler to pick a better frame, but this is better than 1204 * nothing. 1205 */ 1206 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1207 dwc2_sch_vdbg(hsotg, 1208 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1209 chan->qh, wire_frame, frame_number, 1210 dwc2_frame_num_dec(frame_number, 1211 wire_frame)); 1212 wire_frame = frame_number; 1213 1214 /* 1215 * We picked a different frame number; communicate this 1216 * back to the scheduler so it doesn't try to schedule 1217 * another in the same frame. 1218 * 1219 * Remember that next_active_frame is 1 before the wire 1220 * frame. 1221 */ 1222 chan->qh->next_active_frame = 1223 dwc2_frame_num_dec(frame_number, 1); 1224 } 1225 1226 if (wire_frame & 1) 1227 *hcchar |= HCCHAR_ODDFRM; 1228 else 1229 *hcchar &= ~HCCHAR_ODDFRM; 1230 } 1231 } 1232 1233 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1234 { 1235 /* Set up the initial PID for the transfer */ 1236 if (chan->speed == USB_SPEED_HIGH) { 1237 if (chan->ep_is_in) { 1238 if (chan->multi_count == 1) 1239 chan->data_pid_start = DWC2_HC_PID_DATA0; 1240 else if (chan->multi_count == 2) 1241 chan->data_pid_start = DWC2_HC_PID_DATA1; 1242 else 1243 chan->data_pid_start = DWC2_HC_PID_DATA2; 1244 } else { 1245 if (chan->multi_count == 1) 1246 chan->data_pid_start = DWC2_HC_PID_DATA0; 1247 else 1248 chan->data_pid_start = DWC2_HC_PID_MDATA; 1249 } 1250 } else { 1251 chan->data_pid_start = DWC2_HC_PID_DATA0; 1252 } 1253 } 1254 1255 /** 1256 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1257 * the Host Channel 1258 * 1259 * @hsotg: Programming view of DWC_otg controller 1260 * @chan: Information needed to initialize the host channel 1261 * 1262 * This function should only be called in Slave mode. For a channel associated 1263 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1264 * associated with a periodic EP, the periodic Tx FIFO is written. 1265 * 1266 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1267 * the number of bytes written to the Tx FIFO. 1268 */ 1269 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1270 struct dwc2_host_chan *chan) 1271 { 1272 u32 i; 1273 u32 remaining_count; 1274 u32 byte_count; 1275 u32 dword_count; 1276 u32 __iomem *data_fifo; 1277 u32 *data_buf = (u32 *)chan->xfer_buf; 1278 1279 if (dbg_hc(chan)) 1280 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1281 1282 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1283 1284 remaining_count = chan->xfer_len - chan->xfer_count; 1285 if (remaining_count > chan->max_packet) 1286 byte_count = chan->max_packet; 1287 else 1288 byte_count = remaining_count; 1289 1290 dword_count = (byte_count + 3) / 4; 1291 1292 if (((unsigned long)data_buf & 0x3) == 0) { 1293 /* xfer_buf is DWORD aligned */ 1294 for (i = 0; i < dword_count; i++, data_buf++) 1295 dwc2_writel(*data_buf, data_fifo); 1296 } else { 1297 /* xfer_buf is not DWORD aligned */ 1298 for (i = 0; i < dword_count; i++, data_buf++) { 1299 u32 data = data_buf[0] | data_buf[1] << 8 | 1300 data_buf[2] << 16 | data_buf[3] << 24; 1301 dwc2_writel(data, data_fifo); 1302 } 1303 } 1304 1305 chan->xfer_count += byte_count; 1306 chan->xfer_buf += byte_count; 1307 } 1308 1309 /** 1310 * dwc2_hc_do_ping() - Starts a PING transfer 1311 * 1312 * @hsotg: Programming view of DWC_otg controller 1313 * @chan: Information needed to initialize the host channel 1314 * 1315 * This function should only be called in Slave mode. The Do Ping bit is set in 1316 * the HCTSIZ register, then the channel is enabled. 1317 */ 1318 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1319 struct dwc2_host_chan *chan) 1320 { 1321 u32 hcchar; 1322 u32 hctsiz; 1323 1324 if (dbg_hc(chan)) 1325 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1326 chan->hc_num); 1327 1328 hctsiz = TSIZ_DOPNG; 1329 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1330 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1331 1332 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1333 hcchar |= HCCHAR_CHENA; 1334 hcchar &= ~HCCHAR_CHDIS; 1335 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1336 } 1337 1338 /** 1339 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1340 * channel and starts the transfer 1341 * 1342 * @hsotg: Programming view of DWC_otg controller 1343 * @chan: Information needed to initialize the host channel. The xfer_len value 1344 * may be reduced to accommodate the max widths of the XferSize and 1345 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1346 * changed to reflect the final xfer_len value. 1347 * 1348 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1349 * the caller must ensure that there is sufficient space in the request queue 1350 * and Tx Data FIFO. 1351 * 1352 * For an OUT transfer in Slave mode, it loads a data packet into the 1353 * appropriate FIFO. If necessary, additional data packets are loaded in the 1354 * Host ISR. 1355 * 1356 * For an IN transfer in Slave mode, a data packet is requested. The data 1357 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1358 * additional data packets are requested in the Host ISR. 1359 * 1360 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1361 * register along with a packet count of 1 and the channel is enabled. This 1362 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1363 * simply set to 0 since no data transfer occurs in this case. 1364 * 1365 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1366 * all the information required to perform the subsequent data transfer. In 1367 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1368 * controller performs the entire PING protocol, then starts the data 1369 * transfer. 1370 */ 1371 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1372 struct dwc2_host_chan *chan) 1373 { 1374 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1375 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1376 u32 hcchar; 1377 u32 hctsiz = 0; 1378 u16 num_packets; 1379 u32 ec_mc; 1380 1381 if (dbg_hc(chan)) 1382 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1383 1384 if (chan->do_ping) { 1385 if (!hsotg->params.host_dma) { 1386 if (dbg_hc(chan)) 1387 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1388 dwc2_hc_do_ping(hsotg, chan); 1389 chan->xfer_started = 1; 1390 return; 1391 } 1392 1393 if (dbg_hc(chan)) 1394 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1395 1396 hctsiz |= TSIZ_DOPNG; 1397 } 1398 1399 if (chan->do_split) { 1400 if (dbg_hc(chan)) 1401 dev_vdbg(hsotg->dev, "split\n"); 1402 num_packets = 1; 1403 1404 if (chan->complete_split && !chan->ep_is_in) 1405 /* 1406 * For CSPLIT OUT Transfer, set the size to 0 so the 1407 * core doesn't expect any data written to the FIFO 1408 */ 1409 chan->xfer_len = 0; 1410 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1411 chan->xfer_len = chan->max_packet; 1412 else if (!chan->ep_is_in && chan->xfer_len > 188) 1413 chan->xfer_len = 188; 1414 1415 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1416 TSIZ_XFERSIZE_MASK; 1417 1418 /* For split set ec_mc for immediate retries */ 1419 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1420 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1421 ec_mc = 3; 1422 else 1423 ec_mc = 1; 1424 } else { 1425 if (dbg_hc(chan)) 1426 dev_vdbg(hsotg->dev, "no split\n"); 1427 /* 1428 * Ensure that the transfer length and packet count will fit 1429 * in the widths allocated for them in the HCTSIZn register 1430 */ 1431 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1432 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1433 /* 1434 * Make sure the transfer size is no larger than one 1435 * (micro)frame's worth of data. (A check was done 1436 * when the periodic transfer was accepted to ensure 1437 * that a (micro)frame's worth of data can be 1438 * programmed into a channel.) 1439 */ 1440 u32 max_periodic_len = 1441 chan->multi_count * chan->max_packet; 1442 1443 if (chan->xfer_len > max_periodic_len) 1444 chan->xfer_len = max_periodic_len; 1445 } else if (chan->xfer_len > max_hc_xfer_size) { 1446 /* 1447 * Make sure that xfer_len is a multiple of max packet 1448 * size 1449 */ 1450 chan->xfer_len = 1451 max_hc_xfer_size - chan->max_packet + 1; 1452 } 1453 1454 if (chan->xfer_len > 0) { 1455 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1456 chan->max_packet; 1457 if (num_packets > max_hc_pkt_count) { 1458 num_packets = max_hc_pkt_count; 1459 chan->xfer_len = num_packets * chan->max_packet; 1460 } 1461 } else { 1462 /* Need 1 packet for transfer length of 0 */ 1463 num_packets = 1; 1464 } 1465 1466 if (chan->ep_is_in) 1467 /* 1468 * Always program an integral # of max packets for IN 1469 * transfers 1470 */ 1471 chan->xfer_len = num_packets * chan->max_packet; 1472 1473 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1474 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1475 /* 1476 * Make sure that the multi_count field matches the 1477 * actual transfer length 1478 */ 1479 chan->multi_count = num_packets; 1480 1481 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1482 dwc2_set_pid_isoc(chan); 1483 1484 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1485 TSIZ_XFERSIZE_MASK; 1486 1487 /* The ec_mc gets the multi_count for non-split */ 1488 ec_mc = chan->multi_count; 1489 } 1490 1491 chan->start_pkt_count = num_packets; 1492 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1493 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1494 TSIZ_SC_MC_PID_MASK; 1495 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1496 if (dbg_hc(chan)) { 1497 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1498 hctsiz, chan->hc_num); 1499 1500 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1501 chan->hc_num); 1502 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1503 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1504 TSIZ_XFERSIZE_SHIFT); 1505 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1506 (hctsiz & TSIZ_PKTCNT_MASK) >> 1507 TSIZ_PKTCNT_SHIFT); 1508 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1509 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1510 TSIZ_SC_MC_PID_SHIFT); 1511 } 1512 1513 if (hsotg->params.host_dma) { 1514 dwc2_writel((u32)chan->xfer_dma, 1515 hsotg->regs + HCDMA(chan->hc_num)); 1516 if (dbg_hc(chan)) 1517 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1518 (unsigned long)chan->xfer_dma, chan->hc_num); 1519 } 1520 1521 /* Start the split */ 1522 if (chan->do_split) { 1523 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1524 1525 hcsplt |= HCSPLT_SPLTENA; 1526 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1527 } 1528 1529 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1530 hcchar &= ~HCCHAR_MULTICNT_MASK; 1531 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1532 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1533 1534 if (hcchar & HCCHAR_CHDIS) 1535 dev_warn(hsotg->dev, 1536 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1537 __func__, chan->hc_num, hcchar); 1538 1539 /* Set host channel enable after all other setup is complete */ 1540 hcchar |= HCCHAR_CHENA; 1541 hcchar &= ~HCCHAR_CHDIS; 1542 1543 if (dbg_hc(chan)) 1544 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1545 (hcchar & HCCHAR_MULTICNT_MASK) >> 1546 HCCHAR_MULTICNT_SHIFT); 1547 1548 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1549 if (dbg_hc(chan)) 1550 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1551 chan->hc_num); 1552 1553 chan->xfer_started = 1; 1554 chan->requests++; 1555 1556 if (!hsotg->params.host_dma && 1557 !chan->ep_is_in && chan->xfer_len > 0) 1558 /* Load OUT packet into the appropriate Tx FIFO */ 1559 dwc2_hc_write_packet(hsotg, chan); 1560 } 1561 1562 /** 1563 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1564 * host channel and starts the transfer in Descriptor DMA mode 1565 * 1566 * @hsotg: Programming view of DWC_otg controller 1567 * @chan: Information needed to initialize the host channel 1568 * 1569 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1570 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1571 * with micro-frame bitmap. 1572 * 1573 * Initializes HCDMA register with descriptor list address and CTD value then 1574 * starts the transfer via enabling the channel. 1575 */ 1576 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1577 struct dwc2_host_chan *chan) 1578 { 1579 u32 hcchar; 1580 u32 hctsiz = 0; 1581 1582 if (chan->do_ping) 1583 hctsiz |= TSIZ_DOPNG; 1584 1585 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1586 dwc2_set_pid_isoc(chan); 1587 1588 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1589 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1590 TSIZ_SC_MC_PID_MASK; 1591 1592 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1593 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1594 1595 /* Non-zero only for high-speed interrupt endpoints */ 1596 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1597 1598 if (dbg_hc(chan)) { 1599 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1600 chan->hc_num); 1601 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1602 chan->data_pid_start); 1603 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1604 } 1605 1606 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1607 1608 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1609 chan->desc_list_sz, DMA_TO_DEVICE); 1610 1611 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1612 1613 if (dbg_hc(chan)) 1614 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1615 &chan->desc_list_addr, chan->hc_num); 1616 1617 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1618 hcchar &= ~HCCHAR_MULTICNT_MASK; 1619 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1620 HCCHAR_MULTICNT_MASK; 1621 1622 if (hcchar & HCCHAR_CHDIS) 1623 dev_warn(hsotg->dev, 1624 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1625 __func__, chan->hc_num, hcchar); 1626 1627 /* Set host channel enable after all other setup is complete */ 1628 hcchar |= HCCHAR_CHENA; 1629 hcchar &= ~HCCHAR_CHDIS; 1630 1631 if (dbg_hc(chan)) 1632 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1633 (hcchar & HCCHAR_MULTICNT_MASK) >> 1634 HCCHAR_MULTICNT_SHIFT); 1635 1636 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1637 if (dbg_hc(chan)) 1638 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1639 chan->hc_num); 1640 1641 chan->xfer_started = 1; 1642 chan->requests++; 1643 } 1644 1645 /** 1646 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1647 * a previous call to dwc2_hc_start_transfer() 1648 * 1649 * @hsotg: Programming view of DWC_otg controller 1650 * @chan: Information needed to initialize the host channel 1651 * 1652 * The caller must ensure there is sufficient space in the request queue and Tx 1653 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1654 * the controller acts autonomously to complete transfers programmed to a host 1655 * channel. 1656 * 1657 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1658 * if there is any data remaining to be queued. For an IN transfer, another 1659 * data packet is always requested. For the SETUP phase of a control transfer, 1660 * this function does nothing. 1661 * 1662 * Return: 1 if a new request is queued, 0 if no more requests are required 1663 * for this transfer 1664 */ 1665 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1666 struct dwc2_host_chan *chan) 1667 { 1668 if (dbg_hc(chan)) 1669 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1670 chan->hc_num); 1671 1672 if (chan->do_split) 1673 /* SPLITs always queue just once per channel */ 1674 return 0; 1675 1676 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1677 /* SETUPs are queued only once since they can't be NAK'd */ 1678 return 0; 1679 1680 if (chan->ep_is_in) { 1681 /* 1682 * Always queue another request for other IN transfers. If 1683 * back-to-back INs are issued and NAKs are received for both, 1684 * the driver may still be processing the first NAK when the 1685 * second NAK is received. When the interrupt handler clears 1686 * the NAK interrupt for the first NAK, the second NAK will 1687 * not be seen. So we can't depend on the NAK interrupt 1688 * handler to requeue a NAK'd request. Instead, IN requests 1689 * are issued each time this function is called. When the 1690 * transfer completes, the extra requests for the channel will 1691 * be flushed. 1692 */ 1693 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1694 1695 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1696 hcchar |= HCCHAR_CHENA; 1697 hcchar &= ~HCCHAR_CHDIS; 1698 if (dbg_hc(chan)) 1699 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1700 hcchar); 1701 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1702 chan->requests++; 1703 return 1; 1704 } 1705 1706 /* OUT transfers */ 1707 1708 if (chan->xfer_count < chan->xfer_len) { 1709 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1710 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1711 u32 hcchar = dwc2_readl(hsotg->regs + 1712 HCCHAR(chan->hc_num)); 1713 1714 dwc2_hc_set_even_odd_frame(hsotg, chan, 1715 &hcchar); 1716 } 1717 1718 /* Load OUT packet into the appropriate Tx FIFO */ 1719 dwc2_hc_write_packet(hsotg, chan); 1720 chan->requests++; 1721 return 1; 1722 } 1723 1724 return 0; 1725 } 1726 1727 /* 1728 * ========================================================================= 1729 * HCD 1730 * ========================================================================= 1731 */ 1732 1733 /* 1734 * Processes all the URBs in a single list of QHs. Completes them with 1735 * -ETIMEDOUT and frees the QTD. 1736 * 1737 * Must be called with interrupt disabled and spinlock held 1738 */ 1739 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1740 struct list_head *qh_list) 1741 { 1742 struct dwc2_qh *qh, *qh_tmp; 1743 struct dwc2_qtd *qtd, *qtd_tmp; 1744 1745 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1746 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1747 qtd_list_entry) { 1748 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1749 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1750 } 1751 } 1752 } 1753 1754 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1755 struct list_head *qh_list) 1756 { 1757 struct dwc2_qtd *qtd, *qtd_tmp; 1758 struct dwc2_qh *qh, *qh_tmp; 1759 unsigned long flags; 1760 1761 if (!qh_list->next) 1762 /* The list hasn't been initialized yet */ 1763 return; 1764 1765 spin_lock_irqsave(&hsotg->lock, flags); 1766 1767 /* Ensure there are no QTDs or URBs left */ 1768 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1769 1770 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1771 dwc2_hcd_qh_unlink(hsotg, qh); 1772 1773 /* Free each QTD in the QH's QTD list */ 1774 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1775 qtd_list_entry) 1776 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1777 1778 if (qh->channel && qh->channel->qh == qh) 1779 qh->channel->qh = NULL; 1780 1781 spin_unlock_irqrestore(&hsotg->lock, flags); 1782 dwc2_hcd_qh_free(hsotg, qh); 1783 spin_lock_irqsave(&hsotg->lock, flags); 1784 } 1785 1786 spin_unlock_irqrestore(&hsotg->lock, flags); 1787 } 1788 1789 /* 1790 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1791 * and periodic schedules. The QTD associated with each URB is removed from 1792 * the schedule and freed. This function may be called when a disconnect is 1793 * detected or when the HCD is being stopped. 1794 * 1795 * Must be called with interrupt disabled and spinlock held 1796 */ 1797 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1798 { 1799 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1800 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1801 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1802 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1803 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1804 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1805 } 1806 1807 /** 1808 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1809 * 1810 * @hsotg: Pointer to struct dwc2_hsotg 1811 */ 1812 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1813 { 1814 u32 hprt0; 1815 1816 if (hsotg->op_state == OTG_STATE_B_HOST) { 1817 /* 1818 * Reset the port. During a HNP mode switch the reset 1819 * needs to occur within 1ms and have a duration of at 1820 * least 50ms. 1821 */ 1822 hprt0 = dwc2_read_hprt0(hsotg); 1823 hprt0 |= HPRT0_RST; 1824 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1825 } 1826 1827 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1828 msecs_to_jiffies(50)); 1829 } 1830 1831 /* Must be called with interrupt disabled and spinlock held */ 1832 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1833 { 1834 int num_channels = hsotg->params.host_channels; 1835 struct dwc2_host_chan *channel; 1836 u32 hcchar; 1837 int i; 1838 1839 if (!hsotg->params.host_dma) { 1840 /* Flush out any channel requests in slave mode */ 1841 for (i = 0; i < num_channels; i++) { 1842 channel = hsotg->hc_ptr_array[i]; 1843 if (!list_empty(&channel->hc_list_entry)) 1844 continue; 1845 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1846 if (hcchar & HCCHAR_CHENA) { 1847 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1848 hcchar |= HCCHAR_CHDIS; 1849 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1850 } 1851 } 1852 } 1853 1854 for (i = 0; i < num_channels; i++) { 1855 channel = hsotg->hc_ptr_array[i]; 1856 if (!list_empty(&channel->hc_list_entry)) 1857 continue; 1858 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1859 if (hcchar & HCCHAR_CHENA) { 1860 /* Halt the channel */ 1861 hcchar |= HCCHAR_CHDIS; 1862 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1863 } 1864 1865 dwc2_hc_cleanup(hsotg, channel); 1866 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1867 /* 1868 * Added for Descriptor DMA to prevent channel double cleanup in 1869 * release_channel_ddma(), which is called from ep_disable when 1870 * device disconnects 1871 */ 1872 channel->qh = NULL; 1873 } 1874 /* All channels have been freed, mark them available */ 1875 if (hsotg->params.uframe_sched) { 1876 hsotg->available_host_channels = 1877 hsotg->params.host_channels; 1878 } else { 1879 hsotg->non_periodic_channels = 0; 1880 hsotg->periodic_channels = 0; 1881 } 1882 } 1883 1884 /** 1885 * dwc2_hcd_connect() - Handles connect of the HCD 1886 * 1887 * @hsotg: Pointer to struct dwc2_hsotg 1888 * 1889 * Must be called with interrupt disabled and spinlock held 1890 */ 1891 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1892 { 1893 if (hsotg->lx_state != DWC2_L0) 1894 usb_hcd_resume_root_hub(hsotg->priv); 1895 1896 hsotg->flags.b.port_connect_status_change = 1; 1897 hsotg->flags.b.port_connect_status = 1; 1898 } 1899 1900 /** 1901 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1902 * 1903 * @hsotg: Pointer to struct dwc2_hsotg 1904 * @force: If true, we won't try to reconnect even if we see device connected. 1905 * 1906 * Must be called with interrupt disabled and spinlock held 1907 */ 1908 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1909 { 1910 u32 intr; 1911 u32 hprt0; 1912 1913 /* Set status flags for the hub driver */ 1914 hsotg->flags.b.port_connect_status_change = 1; 1915 hsotg->flags.b.port_connect_status = 0; 1916 1917 /* 1918 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1919 * interrupt mask and status bits and disabling subsequent host 1920 * channel interrupts. 1921 */ 1922 intr = dwc2_readl(hsotg->regs + GINTMSK); 1923 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1924 dwc2_writel(intr, hsotg->regs + GINTMSK); 1925 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1926 dwc2_writel(intr, hsotg->regs + GINTSTS); 1927 1928 /* 1929 * Turn off the vbus power only if the core has transitioned to device 1930 * mode. If still in host mode, need to keep power on to detect a 1931 * reconnection. 1932 */ 1933 if (dwc2_is_device_mode(hsotg)) { 1934 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1935 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1936 dwc2_writel(0, hsotg->regs + HPRT0); 1937 } 1938 1939 dwc2_disable_host_interrupts(hsotg); 1940 } 1941 1942 /* Respond with an error status to all URBs in the schedule */ 1943 dwc2_kill_all_urbs(hsotg); 1944 1945 if (dwc2_is_host_mode(hsotg)) 1946 /* Clean up any host channels that were in use */ 1947 dwc2_hcd_cleanup_channels(hsotg); 1948 1949 dwc2_host_disconnect(hsotg); 1950 1951 /* 1952 * Add an extra check here to see if we're actually connected but 1953 * we don't have a detection interrupt pending. This can happen if: 1954 * 1. hardware sees connect 1955 * 2. hardware sees disconnect 1956 * 3. hardware sees connect 1957 * 4. dwc2_port_intr() - clears connect interrupt 1958 * 5. dwc2_handle_common_intr() - calls here 1959 * 1960 * Without the extra check here we will end calling disconnect 1961 * and won't get any future interrupts to handle the connect. 1962 */ 1963 if (!force) { 1964 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1965 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1966 dwc2_hcd_connect(hsotg); 1967 } 1968 } 1969 1970 /** 1971 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1972 * 1973 * @hsotg: Pointer to struct dwc2_hsotg 1974 */ 1975 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1976 { 1977 if (hsotg->bus_suspended) { 1978 hsotg->flags.b.port_suspend_change = 1; 1979 usb_hcd_resume_root_hub(hsotg->priv); 1980 } 1981 1982 if (hsotg->lx_state == DWC2_L1) 1983 hsotg->flags.b.port_l1_change = 1; 1984 } 1985 1986 /** 1987 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 1988 * 1989 * @hsotg: Pointer to struct dwc2_hsotg 1990 * 1991 * Must be called with interrupt disabled and spinlock held 1992 */ 1993 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 1994 { 1995 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 1996 1997 /* 1998 * The root hub should be disconnected before this function is called. 1999 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2000 * and the QH lists (via ..._hcd_endpoint_disable). 2001 */ 2002 2003 /* Turn off all host-specific interrupts */ 2004 dwc2_disable_host_interrupts(hsotg); 2005 2006 /* Turn off the vbus power */ 2007 dev_dbg(hsotg->dev, "PortPower off\n"); 2008 dwc2_writel(0, hsotg->regs + HPRT0); 2009 } 2010 2011 /* Caller must hold driver lock */ 2012 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2013 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2014 struct dwc2_qtd *qtd) 2015 { 2016 u32 intr_mask; 2017 int retval; 2018 int dev_speed; 2019 2020 if (!hsotg->flags.b.port_connect_status) { 2021 /* No longer connected */ 2022 dev_err(hsotg->dev, "Not connected\n"); 2023 return -ENODEV; 2024 } 2025 2026 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2027 2028 /* Some configurations cannot support LS traffic on a FS root port */ 2029 if ((dev_speed == USB_SPEED_LOW) && 2030 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2031 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2032 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2033 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2034 2035 if (prtspd == HPRT0_SPD_FULL_SPEED) 2036 return -ENODEV; 2037 } 2038 2039 if (!qtd) 2040 return -EINVAL; 2041 2042 dwc2_hcd_qtd_init(qtd, urb); 2043 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2044 if (retval) { 2045 dev_err(hsotg->dev, 2046 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2047 retval); 2048 return retval; 2049 } 2050 2051 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2052 if (!(intr_mask & GINTSTS_SOF)) { 2053 enum dwc2_transaction_type tr_type; 2054 2055 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2056 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2057 /* 2058 * Do not schedule SG transactions until qtd has 2059 * URB_GIVEBACK_ASAP set 2060 */ 2061 return 0; 2062 2063 tr_type = dwc2_hcd_select_transactions(hsotg); 2064 if (tr_type != DWC2_TRANSACTION_NONE) 2065 dwc2_hcd_queue_transactions(hsotg, tr_type); 2066 } 2067 2068 return 0; 2069 } 2070 2071 /* Must be called with interrupt disabled and spinlock held */ 2072 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2073 struct dwc2_hcd_urb *urb) 2074 { 2075 struct dwc2_qh *qh; 2076 struct dwc2_qtd *urb_qtd; 2077 2078 urb_qtd = urb->qtd; 2079 if (!urb_qtd) { 2080 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2081 return -EINVAL; 2082 } 2083 2084 qh = urb_qtd->qh; 2085 if (!qh) { 2086 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2087 return -EINVAL; 2088 } 2089 2090 urb->priv = NULL; 2091 2092 if (urb_qtd->in_process && qh->channel) { 2093 dwc2_dump_channel_info(hsotg, qh->channel); 2094 2095 /* The QTD is in process (it has been assigned to a channel) */ 2096 if (hsotg->flags.b.port_connect_status) 2097 /* 2098 * If still connected (i.e. in host mode), halt the 2099 * channel so it can be used for other transfers. If 2100 * no longer connected, the host registers can't be 2101 * written to halt the channel since the core is in 2102 * device mode. 2103 */ 2104 dwc2_hc_halt(hsotg, qh->channel, 2105 DWC2_HC_XFER_URB_DEQUEUE); 2106 } 2107 2108 /* 2109 * Free the QTD and clean up the associated QH. Leave the QH in the 2110 * schedule if it has any remaining QTDs. 2111 */ 2112 if (!hsotg->params.dma_desc_enable) { 2113 u8 in_process = urb_qtd->in_process; 2114 2115 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2116 if (in_process) { 2117 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2118 qh->channel = NULL; 2119 } else if (list_empty(&qh->qtd_list)) { 2120 dwc2_hcd_qh_unlink(hsotg, qh); 2121 } 2122 } else { 2123 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2124 } 2125 2126 return 0; 2127 } 2128 2129 /* Must NOT be called with interrupt disabled or spinlock held */ 2130 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2131 struct usb_host_endpoint *ep, int retry) 2132 { 2133 struct dwc2_qtd *qtd, *qtd_tmp; 2134 struct dwc2_qh *qh; 2135 unsigned long flags; 2136 int rc; 2137 2138 spin_lock_irqsave(&hsotg->lock, flags); 2139 2140 qh = ep->hcpriv; 2141 if (!qh) { 2142 rc = -EINVAL; 2143 goto err; 2144 } 2145 2146 while (!list_empty(&qh->qtd_list) && retry--) { 2147 if (retry == 0) { 2148 dev_err(hsotg->dev, 2149 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2150 rc = -EBUSY; 2151 goto err; 2152 } 2153 2154 spin_unlock_irqrestore(&hsotg->lock, flags); 2155 msleep(20); 2156 spin_lock_irqsave(&hsotg->lock, flags); 2157 qh = ep->hcpriv; 2158 if (!qh) { 2159 rc = -EINVAL; 2160 goto err; 2161 } 2162 } 2163 2164 dwc2_hcd_qh_unlink(hsotg, qh); 2165 2166 /* Free each QTD in the QH's QTD list */ 2167 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2168 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2169 2170 ep->hcpriv = NULL; 2171 2172 if (qh->channel && qh->channel->qh == qh) 2173 qh->channel->qh = NULL; 2174 2175 spin_unlock_irqrestore(&hsotg->lock, flags); 2176 2177 dwc2_hcd_qh_free(hsotg, qh); 2178 2179 return 0; 2180 2181 err: 2182 ep->hcpriv = NULL; 2183 spin_unlock_irqrestore(&hsotg->lock, flags); 2184 2185 return rc; 2186 } 2187 2188 /* Must be called with interrupt disabled and spinlock held */ 2189 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2190 struct usb_host_endpoint *ep) 2191 { 2192 struct dwc2_qh *qh = ep->hcpriv; 2193 2194 if (!qh) 2195 return -EINVAL; 2196 2197 qh->data_toggle = DWC2_HC_PID_DATA0; 2198 2199 return 0; 2200 } 2201 2202 /** 2203 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2204 * prepares the core for device mode or host mode operation 2205 * 2206 * @hsotg: Programming view of the DWC_otg controller 2207 * @initial_setup: If true then this is the first init for this instance. 2208 */ 2209 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2210 { 2211 u32 usbcfg, otgctl; 2212 int retval; 2213 2214 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2215 2216 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2217 2218 /* Set ULPI External VBUS bit if needed */ 2219 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2220 if (hsotg->params.phy_ulpi_ext_vbus) 2221 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2222 2223 /* Set external TS Dline pulsing bit if needed */ 2224 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2225 if (hsotg->params.ts_dline) 2226 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2227 2228 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2229 2230 /* 2231 * Reset the Controller 2232 * 2233 * We only need to reset the controller if this is a re-init. 2234 * For the first init we know for sure that earlier code reset us (it 2235 * needed to in order to properly detect various parameters). 2236 */ 2237 if (!initial_setup) { 2238 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2239 if (retval) { 2240 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2241 __func__); 2242 return retval; 2243 } 2244 } 2245 2246 /* 2247 * This needs to happen in FS mode before any other programming occurs 2248 */ 2249 retval = dwc2_phy_init(hsotg, initial_setup); 2250 if (retval) 2251 return retval; 2252 2253 /* Program the GAHBCFG Register */ 2254 retval = dwc2_gahbcfg_init(hsotg); 2255 if (retval) 2256 return retval; 2257 2258 /* Program the GUSBCFG register */ 2259 dwc2_gusbcfg_init(hsotg); 2260 2261 /* Program the GOTGCTL register */ 2262 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2263 otgctl &= ~GOTGCTL_OTGVER; 2264 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2265 2266 /* Clear the SRP success bit for FS-I2c */ 2267 hsotg->srp_success = 0; 2268 2269 /* Enable common interrupts */ 2270 dwc2_enable_common_interrupts(hsotg); 2271 2272 /* 2273 * Do device or host initialization based on mode during PCD and 2274 * HCD initialization 2275 */ 2276 if (dwc2_is_host_mode(hsotg)) { 2277 dev_dbg(hsotg->dev, "Host Mode\n"); 2278 hsotg->op_state = OTG_STATE_A_HOST; 2279 } else { 2280 dev_dbg(hsotg->dev, "Device Mode\n"); 2281 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2282 } 2283 2284 return 0; 2285 } 2286 2287 /** 2288 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2289 * Host mode 2290 * 2291 * @hsotg: Programming view of DWC_otg controller 2292 * 2293 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2294 * request queues. Host channels are reset to ensure that they are ready for 2295 * performing transfers. 2296 */ 2297 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2298 { 2299 u32 hcfg, hfir, otgctl; 2300 2301 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2302 2303 /* Restart the Phy Clock */ 2304 dwc2_writel(0, hsotg->regs + PCGCTL); 2305 2306 /* Initialize Host Configuration Register */ 2307 dwc2_init_fs_ls_pclk_sel(hsotg); 2308 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2309 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2310 hcfg = dwc2_readl(hsotg->regs + HCFG); 2311 hcfg |= HCFG_FSLSSUPP; 2312 dwc2_writel(hcfg, hsotg->regs + HCFG); 2313 } 2314 2315 /* 2316 * This bit allows dynamic reloading of the HFIR register during 2317 * runtime. This bit needs to be programmed during initial configuration 2318 * and its value must not be changed during runtime. 2319 */ 2320 if (hsotg->params.reload_ctl) { 2321 hfir = dwc2_readl(hsotg->regs + HFIR); 2322 hfir |= HFIR_RLDCTRL; 2323 dwc2_writel(hfir, hsotg->regs + HFIR); 2324 } 2325 2326 if (hsotg->params.dma_desc_enable) { 2327 u32 op_mode = hsotg->hw_params.op_mode; 2328 2329 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2330 !hsotg->hw_params.dma_desc_enable || 2331 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2332 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2333 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2334 dev_err(hsotg->dev, 2335 "Hardware does not support descriptor DMA mode -\n"); 2336 dev_err(hsotg->dev, 2337 "falling back to buffer DMA mode.\n"); 2338 hsotg->params.dma_desc_enable = false; 2339 } else { 2340 hcfg = dwc2_readl(hsotg->regs + HCFG); 2341 hcfg |= HCFG_DESCDMA; 2342 dwc2_writel(hcfg, hsotg->regs + HCFG); 2343 } 2344 } 2345 2346 /* Configure data FIFO sizes */ 2347 dwc2_config_fifos(hsotg); 2348 2349 /* TODO - check this */ 2350 /* Clear Host Set HNP Enable in the OTG Control Register */ 2351 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2352 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2353 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2354 2355 /* Make sure the FIFOs are flushed */ 2356 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2357 dwc2_flush_rx_fifo(hsotg); 2358 2359 /* Clear Host Set HNP Enable in the OTG Control Register */ 2360 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2361 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2362 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2363 2364 if (!hsotg->params.dma_desc_enable) { 2365 int num_channels, i; 2366 u32 hcchar; 2367 2368 /* Flush out any leftover queued requests */ 2369 num_channels = hsotg->params.host_channels; 2370 for (i = 0; i < num_channels; i++) { 2371 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2372 hcchar &= ~HCCHAR_CHENA; 2373 hcchar |= HCCHAR_CHDIS; 2374 hcchar &= ~HCCHAR_EPDIR; 2375 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2376 } 2377 2378 /* Halt all channels to put them into a known state */ 2379 for (i = 0; i < num_channels; i++) { 2380 int count = 0; 2381 2382 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2383 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2384 hcchar &= ~HCCHAR_EPDIR; 2385 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2386 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2387 __func__, i); 2388 do { 2389 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2390 if (++count > 1000) { 2391 dev_err(hsotg->dev, 2392 "Unable to clear enable on channel %d\n", 2393 i); 2394 break; 2395 } 2396 udelay(1); 2397 } while (hcchar & HCCHAR_CHENA); 2398 } 2399 } 2400 2401 /* Turn on the vbus power */ 2402 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2403 if (hsotg->op_state == OTG_STATE_A_HOST) { 2404 u32 hprt0 = dwc2_read_hprt0(hsotg); 2405 2406 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2407 !!(hprt0 & HPRT0_PWR)); 2408 if (!(hprt0 & HPRT0_PWR)) { 2409 hprt0 |= HPRT0_PWR; 2410 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2411 } 2412 } 2413 2414 dwc2_enable_host_interrupts(hsotg); 2415 } 2416 2417 /* 2418 * Initializes dynamic portions of the DWC_otg HCD state 2419 * 2420 * Must be called with interrupt disabled and spinlock held 2421 */ 2422 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2423 { 2424 struct dwc2_host_chan *chan, *chan_tmp; 2425 int num_channels; 2426 int i; 2427 2428 hsotg->flags.d32 = 0; 2429 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2430 2431 if (hsotg->params.uframe_sched) { 2432 hsotg->available_host_channels = 2433 hsotg->params.host_channels; 2434 } else { 2435 hsotg->non_periodic_channels = 0; 2436 hsotg->periodic_channels = 0; 2437 } 2438 2439 /* 2440 * Put all channels in the free channel list and clean up channel 2441 * states 2442 */ 2443 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2444 hc_list_entry) 2445 list_del_init(&chan->hc_list_entry); 2446 2447 num_channels = hsotg->params.host_channels; 2448 for (i = 0; i < num_channels; i++) { 2449 chan = hsotg->hc_ptr_array[i]; 2450 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2451 dwc2_hc_cleanup(hsotg, chan); 2452 } 2453 2454 /* Initialize the DWC core for host mode operation */ 2455 dwc2_core_host_init(hsotg); 2456 } 2457 2458 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2459 struct dwc2_host_chan *chan, 2460 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2461 { 2462 int hub_addr, hub_port; 2463 2464 chan->do_split = 1; 2465 chan->xact_pos = qtd->isoc_split_pos; 2466 chan->complete_split = qtd->complete_split; 2467 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2468 chan->hub_addr = (u8)hub_addr; 2469 chan->hub_port = (u8)hub_port; 2470 } 2471 2472 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2473 struct dwc2_host_chan *chan, 2474 struct dwc2_qtd *qtd) 2475 { 2476 struct dwc2_hcd_urb *urb = qtd->urb; 2477 struct dwc2_hcd_iso_packet_desc *frame_desc; 2478 2479 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2480 case USB_ENDPOINT_XFER_CONTROL: 2481 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2482 2483 switch (qtd->control_phase) { 2484 case DWC2_CONTROL_SETUP: 2485 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2486 chan->do_ping = 0; 2487 chan->ep_is_in = 0; 2488 chan->data_pid_start = DWC2_HC_PID_SETUP; 2489 if (hsotg->params.host_dma) 2490 chan->xfer_dma = urb->setup_dma; 2491 else 2492 chan->xfer_buf = urb->setup_packet; 2493 chan->xfer_len = 8; 2494 break; 2495 2496 case DWC2_CONTROL_DATA: 2497 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2498 chan->data_pid_start = qtd->data_toggle; 2499 break; 2500 2501 case DWC2_CONTROL_STATUS: 2502 /* 2503 * Direction is opposite of data direction or IN if no 2504 * data 2505 */ 2506 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2507 if (urb->length == 0) 2508 chan->ep_is_in = 1; 2509 else 2510 chan->ep_is_in = 2511 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2512 if (chan->ep_is_in) 2513 chan->do_ping = 0; 2514 chan->data_pid_start = DWC2_HC_PID_DATA1; 2515 chan->xfer_len = 0; 2516 if (hsotg->params.host_dma) 2517 chan->xfer_dma = hsotg->status_buf_dma; 2518 else 2519 chan->xfer_buf = hsotg->status_buf; 2520 break; 2521 } 2522 break; 2523 2524 case USB_ENDPOINT_XFER_BULK: 2525 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2526 break; 2527 2528 case USB_ENDPOINT_XFER_INT: 2529 chan->ep_type = USB_ENDPOINT_XFER_INT; 2530 break; 2531 2532 case USB_ENDPOINT_XFER_ISOC: 2533 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2534 if (hsotg->params.dma_desc_enable) 2535 break; 2536 2537 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2538 frame_desc->status = 0; 2539 2540 if (hsotg->params.host_dma) { 2541 chan->xfer_dma = urb->dma; 2542 chan->xfer_dma += frame_desc->offset + 2543 qtd->isoc_split_offset; 2544 } else { 2545 chan->xfer_buf = urb->buf; 2546 chan->xfer_buf += frame_desc->offset + 2547 qtd->isoc_split_offset; 2548 } 2549 2550 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2551 2552 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2553 if (chan->xfer_len <= 188) 2554 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2555 else 2556 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2557 } 2558 break; 2559 } 2560 } 2561 2562 #define DWC2_USB_DMA_ALIGN 4 2563 2564 struct dma_aligned_buffer { 2565 void *kmalloc_ptr; 2566 void *old_xfer_buffer; 2567 u8 data[0]; 2568 }; 2569 2570 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2571 { 2572 struct dma_aligned_buffer *temp; 2573 2574 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2575 return; 2576 2577 temp = container_of(urb->transfer_buffer, 2578 struct dma_aligned_buffer, data); 2579 2580 if (usb_urb_dir_in(urb)) 2581 memcpy(temp->old_xfer_buffer, temp->data, 2582 urb->transfer_buffer_length); 2583 urb->transfer_buffer = temp->old_xfer_buffer; 2584 kfree(temp->kmalloc_ptr); 2585 2586 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2587 } 2588 2589 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2590 { 2591 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2592 size_t kmalloc_size; 2593 2594 if (urb->num_sgs || urb->sg || 2595 urb->transfer_buffer_length == 0 || 2596 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2597 return 0; 2598 2599 /* Allocate a buffer with enough padding for alignment */ 2600 kmalloc_size = urb->transfer_buffer_length + 2601 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2602 2603 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2604 if (!kmalloc_ptr) 2605 return -ENOMEM; 2606 2607 /* Position our struct dma_aligned_buffer such that data is aligned */ 2608 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2609 temp->kmalloc_ptr = kmalloc_ptr; 2610 temp->old_xfer_buffer = urb->transfer_buffer; 2611 if (usb_urb_dir_out(urb)) 2612 memcpy(temp->data, urb->transfer_buffer, 2613 urb->transfer_buffer_length); 2614 urb->transfer_buffer = temp->data; 2615 2616 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2617 2618 return 0; 2619 } 2620 2621 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2622 gfp_t mem_flags) 2623 { 2624 int ret; 2625 2626 /* We assume setup_dma is always aligned; warn if not */ 2627 WARN_ON_ONCE(urb->setup_dma && 2628 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2629 2630 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2631 if (ret) 2632 return ret; 2633 2634 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2635 if (ret) 2636 dwc2_free_dma_aligned_buffer(urb); 2637 2638 return ret; 2639 } 2640 2641 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2642 { 2643 usb_hcd_unmap_urb_for_dma(hcd, urb); 2644 dwc2_free_dma_aligned_buffer(urb); 2645 } 2646 2647 /** 2648 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2649 * channel and initializes the host channel to perform the transactions. The 2650 * host channel is removed from the free list. 2651 * 2652 * @hsotg: The HCD state structure 2653 * @qh: Transactions from the first QTD for this QH are selected and assigned 2654 * to a free host channel 2655 */ 2656 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2657 { 2658 struct dwc2_host_chan *chan; 2659 struct dwc2_hcd_urb *urb; 2660 struct dwc2_qtd *qtd; 2661 2662 if (dbg_qh(qh)) 2663 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2664 2665 if (list_empty(&qh->qtd_list)) { 2666 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2667 return -ENOMEM; 2668 } 2669 2670 if (list_empty(&hsotg->free_hc_list)) { 2671 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2672 return -ENOMEM; 2673 } 2674 2675 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2676 hc_list_entry); 2677 2678 /* Remove host channel from free list */ 2679 list_del_init(&chan->hc_list_entry); 2680 2681 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2682 urb = qtd->urb; 2683 qh->channel = chan; 2684 qtd->in_process = 1; 2685 2686 /* 2687 * Use usb_pipedevice to determine device address. This address is 2688 * 0 before the SET_ADDRESS command and the correct address afterward. 2689 */ 2690 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2691 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2692 chan->speed = qh->dev_speed; 2693 chan->max_packet = dwc2_max_packet(qh->maxp); 2694 2695 chan->xfer_started = 0; 2696 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2697 chan->error_state = (qtd->error_count > 0); 2698 chan->halt_on_queue = 0; 2699 chan->halt_pending = 0; 2700 chan->requests = 0; 2701 2702 /* 2703 * The following values may be modified in the transfer type section 2704 * below. The xfer_len value may be reduced when the transfer is 2705 * started to accommodate the max widths of the XferSize and PktCnt 2706 * fields in the HCTSIZn register. 2707 */ 2708 2709 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2710 if (chan->ep_is_in) 2711 chan->do_ping = 0; 2712 else 2713 chan->do_ping = qh->ping_state; 2714 2715 chan->data_pid_start = qh->data_toggle; 2716 chan->multi_count = 1; 2717 2718 if (urb->actual_length > urb->length && 2719 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2720 urb->actual_length = urb->length; 2721 2722 if (hsotg->params.host_dma) 2723 chan->xfer_dma = urb->dma + urb->actual_length; 2724 else 2725 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2726 2727 chan->xfer_len = urb->length - urb->actual_length; 2728 chan->xfer_count = 0; 2729 2730 /* Set the split attributes if required */ 2731 if (qh->do_split) 2732 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2733 else 2734 chan->do_split = 0; 2735 2736 /* Set the transfer attributes */ 2737 dwc2_hc_init_xfer(hsotg, chan, qtd); 2738 2739 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2740 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2741 /* 2742 * This value may be modified when the transfer is started 2743 * to reflect the actual transfer length 2744 */ 2745 chan->multi_count = dwc2_hb_mult(qh->maxp); 2746 2747 if (hsotg->params.dma_desc_enable) { 2748 chan->desc_list_addr = qh->desc_list_dma; 2749 chan->desc_list_sz = qh->desc_list_sz; 2750 } 2751 2752 dwc2_hc_init(hsotg, chan); 2753 chan->qh = qh; 2754 2755 return 0; 2756 } 2757 2758 /** 2759 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2760 * schedule and assigns them to available host channels. Called from the HCD 2761 * interrupt handler functions. 2762 * 2763 * @hsotg: The HCD state structure 2764 * 2765 * Return: The types of new transactions that were assigned to host channels 2766 */ 2767 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2768 struct dwc2_hsotg *hsotg) 2769 { 2770 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2771 struct list_head *qh_ptr; 2772 struct dwc2_qh *qh; 2773 int num_channels; 2774 2775 #ifdef DWC2_DEBUG_SOF 2776 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2777 #endif 2778 2779 /* Process entries in the periodic ready list */ 2780 qh_ptr = hsotg->periodic_sched_ready.next; 2781 while (qh_ptr != &hsotg->periodic_sched_ready) { 2782 if (list_empty(&hsotg->free_hc_list)) 2783 break; 2784 if (hsotg->params.uframe_sched) { 2785 if (hsotg->available_host_channels <= 1) 2786 break; 2787 hsotg->available_host_channels--; 2788 } 2789 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2790 if (dwc2_assign_and_init_hc(hsotg, qh)) 2791 break; 2792 2793 /* 2794 * Move the QH from the periodic ready schedule to the 2795 * periodic assigned schedule 2796 */ 2797 qh_ptr = qh_ptr->next; 2798 list_move_tail(&qh->qh_list_entry, 2799 &hsotg->periodic_sched_assigned); 2800 ret_val = DWC2_TRANSACTION_PERIODIC; 2801 } 2802 2803 /* 2804 * Process entries in the inactive portion of the non-periodic 2805 * schedule. Some free host channels may not be used if they are 2806 * reserved for periodic transfers. 2807 */ 2808 num_channels = hsotg->params.host_channels; 2809 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2810 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2811 if (!hsotg->params.uframe_sched && 2812 hsotg->non_periodic_channels >= num_channels - 2813 hsotg->periodic_channels) 2814 break; 2815 if (list_empty(&hsotg->free_hc_list)) 2816 break; 2817 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2818 if (hsotg->params.uframe_sched) { 2819 if (hsotg->available_host_channels < 1) 2820 break; 2821 hsotg->available_host_channels--; 2822 } 2823 2824 if (dwc2_assign_and_init_hc(hsotg, qh)) 2825 break; 2826 2827 /* 2828 * Move the QH from the non-periodic inactive schedule to the 2829 * non-periodic active schedule 2830 */ 2831 qh_ptr = qh_ptr->next; 2832 list_move_tail(&qh->qh_list_entry, 2833 &hsotg->non_periodic_sched_active); 2834 2835 if (ret_val == DWC2_TRANSACTION_NONE) 2836 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2837 else 2838 ret_val = DWC2_TRANSACTION_ALL; 2839 2840 if (!hsotg->params.uframe_sched) 2841 hsotg->non_periodic_channels++; 2842 } 2843 2844 return ret_val; 2845 } 2846 2847 /** 2848 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2849 * a host channel associated with either a periodic or non-periodic transfer 2850 * 2851 * @hsotg: The HCD state structure 2852 * @chan: Host channel descriptor associated with either a periodic or 2853 * non-periodic transfer 2854 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2855 * for periodic transfers or the non-periodic Tx FIFO 2856 * for non-periodic transfers 2857 * 2858 * Return: 1 if a request is queued and more requests may be needed to 2859 * complete the transfer, 0 if no more requests are required for this 2860 * transfer, -1 if there is insufficient space in the Tx FIFO 2861 * 2862 * This function assumes that there is space available in the appropriate 2863 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2864 * it checks whether space is available in the appropriate Tx FIFO. 2865 * 2866 * Must be called with interrupt disabled and spinlock held 2867 */ 2868 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2869 struct dwc2_host_chan *chan, 2870 u16 fifo_dwords_avail) 2871 { 2872 int retval = 0; 2873 2874 if (chan->do_split) 2875 /* Put ourselves on the list to keep order straight */ 2876 list_move_tail(&chan->split_order_list_entry, 2877 &hsotg->split_order); 2878 2879 if (hsotg->params.host_dma) { 2880 if (hsotg->params.dma_desc_enable) { 2881 if (!chan->xfer_started || 2882 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2883 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2884 chan->qh->ping_state = 0; 2885 } 2886 } else if (!chan->xfer_started) { 2887 dwc2_hc_start_transfer(hsotg, chan); 2888 chan->qh->ping_state = 0; 2889 } 2890 } else if (chan->halt_pending) { 2891 /* Don't queue a request if the channel has been halted */ 2892 } else if (chan->halt_on_queue) { 2893 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2894 } else if (chan->do_ping) { 2895 if (!chan->xfer_started) 2896 dwc2_hc_start_transfer(hsotg, chan); 2897 } else if (!chan->ep_is_in || 2898 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2899 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2900 if (!chan->xfer_started) { 2901 dwc2_hc_start_transfer(hsotg, chan); 2902 retval = 1; 2903 } else { 2904 retval = dwc2_hc_continue_transfer(hsotg, chan); 2905 } 2906 } else { 2907 retval = -1; 2908 } 2909 } else { 2910 if (!chan->xfer_started) { 2911 dwc2_hc_start_transfer(hsotg, chan); 2912 retval = 1; 2913 } else { 2914 retval = dwc2_hc_continue_transfer(hsotg, chan); 2915 } 2916 } 2917 2918 return retval; 2919 } 2920 2921 /* 2922 * Processes periodic channels for the next frame and queues transactions for 2923 * these channels to the DWC_otg controller. After queueing transactions, the 2924 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2925 * to queue as Periodic Tx FIFO or request queue space becomes available. 2926 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2927 * 2928 * Must be called with interrupt disabled and spinlock held 2929 */ 2930 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2931 { 2932 struct list_head *qh_ptr; 2933 struct dwc2_qh *qh; 2934 u32 tx_status; 2935 u32 fspcavail; 2936 u32 gintmsk; 2937 int status; 2938 bool no_queue_space = false; 2939 bool no_fifo_space = false; 2940 u32 qspcavail; 2941 2942 /* If empty list then just adjust interrupt enables */ 2943 if (list_empty(&hsotg->periodic_sched_assigned)) 2944 goto exit; 2945 2946 if (dbg_perio()) 2947 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2948 2949 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2950 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2951 TXSTS_QSPCAVAIL_SHIFT; 2952 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2953 TXSTS_FSPCAVAIL_SHIFT; 2954 2955 if (dbg_perio()) { 2956 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2957 qspcavail); 2958 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2959 fspcavail); 2960 } 2961 2962 qh_ptr = hsotg->periodic_sched_assigned.next; 2963 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2964 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2965 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2966 TXSTS_QSPCAVAIL_SHIFT; 2967 if (qspcavail == 0) { 2968 no_queue_space = true; 2969 break; 2970 } 2971 2972 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2973 if (!qh->channel) { 2974 qh_ptr = qh_ptr->next; 2975 continue; 2976 } 2977 2978 /* Make sure EP's TT buffer is clean before queueing qtds */ 2979 if (qh->tt_buffer_dirty) { 2980 qh_ptr = qh_ptr->next; 2981 continue; 2982 } 2983 2984 /* 2985 * Set a flag if we're queuing high-bandwidth in slave mode. 2986 * The flag prevents any halts to get into the request queue in 2987 * the middle of multiple high-bandwidth packets getting queued. 2988 */ 2989 if (!hsotg->params.host_dma && 2990 qh->channel->multi_count > 1) 2991 hsotg->queuing_high_bandwidth = 1; 2992 2993 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2994 TXSTS_FSPCAVAIL_SHIFT; 2995 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 2996 if (status < 0) { 2997 no_fifo_space = true; 2998 break; 2999 } 3000 3001 /* 3002 * In Slave mode, stay on the current transfer until there is 3003 * nothing more to do or the high-bandwidth request count is 3004 * reached. In DMA mode, only need to queue one request. The 3005 * controller automatically handles multiple packets for 3006 * high-bandwidth transfers. 3007 */ 3008 if (hsotg->params.host_dma || status == 0 || 3009 qh->channel->requests == qh->channel->multi_count) { 3010 qh_ptr = qh_ptr->next; 3011 /* 3012 * Move the QH from the periodic assigned schedule to 3013 * the periodic queued schedule 3014 */ 3015 list_move_tail(&qh->qh_list_entry, 3016 &hsotg->periodic_sched_queued); 3017 3018 /* done queuing high bandwidth */ 3019 hsotg->queuing_high_bandwidth = 0; 3020 } 3021 } 3022 3023 exit: 3024 if (no_queue_space || no_fifo_space || 3025 (!hsotg->params.host_dma && 3026 !list_empty(&hsotg->periodic_sched_assigned))) { 3027 /* 3028 * May need to queue more transactions as the request 3029 * queue or Tx FIFO empties. Enable the periodic Tx 3030 * FIFO empty interrupt. (Always use the half-empty 3031 * level to ensure that new requests are loaded as 3032 * soon as possible.) 3033 */ 3034 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3035 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3036 gintmsk |= GINTSTS_PTXFEMP; 3037 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3038 } 3039 } else { 3040 /* 3041 * Disable the Tx FIFO empty interrupt since there are 3042 * no more transactions that need to be queued right 3043 * now. This function is called from interrupt 3044 * handlers to queue more transactions as transfer 3045 * states change. 3046 */ 3047 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3048 if (gintmsk & GINTSTS_PTXFEMP) { 3049 gintmsk &= ~GINTSTS_PTXFEMP; 3050 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3051 } 3052 } 3053 } 3054 3055 /* 3056 * Processes active non-periodic channels and queues transactions for these 3057 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3058 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3059 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3060 * FIFO Empty interrupt is disabled. 3061 * 3062 * Must be called with interrupt disabled and spinlock held 3063 */ 3064 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3065 { 3066 struct list_head *orig_qh_ptr; 3067 struct dwc2_qh *qh; 3068 u32 tx_status; 3069 u32 qspcavail; 3070 u32 fspcavail; 3071 u32 gintmsk; 3072 int status; 3073 int no_queue_space = 0; 3074 int no_fifo_space = 0; 3075 int more_to_do = 0; 3076 3077 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3078 3079 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3080 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3081 TXSTS_QSPCAVAIL_SHIFT; 3082 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3083 TXSTS_FSPCAVAIL_SHIFT; 3084 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3085 qspcavail); 3086 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3087 fspcavail); 3088 3089 /* 3090 * Keep track of the starting point. Skip over the start-of-list 3091 * entry. 3092 */ 3093 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3094 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3095 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3096 3097 /* 3098 * Process once through the active list or until no more space is 3099 * available in the request queue or the Tx FIFO 3100 */ 3101 do { 3102 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3103 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3104 TXSTS_QSPCAVAIL_SHIFT; 3105 if (!hsotg->params.host_dma && qspcavail == 0) { 3106 no_queue_space = 1; 3107 break; 3108 } 3109 3110 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3111 qh_list_entry); 3112 if (!qh->channel) 3113 goto next; 3114 3115 /* Make sure EP's TT buffer is clean before queueing qtds */ 3116 if (qh->tt_buffer_dirty) 3117 goto next; 3118 3119 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3120 TXSTS_FSPCAVAIL_SHIFT; 3121 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3122 3123 if (status > 0) { 3124 more_to_do = 1; 3125 } else if (status < 0) { 3126 no_fifo_space = 1; 3127 break; 3128 } 3129 next: 3130 /* Advance to next QH, skipping start-of-list entry */ 3131 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3132 if (hsotg->non_periodic_qh_ptr == 3133 &hsotg->non_periodic_sched_active) 3134 hsotg->non_periodic_qh_ptr = 3135 hsotg->non_periodic_qh_ptr->next; 3136 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3137 3138 if (!hsotg->params.host_dma) { 3139 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3140 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3141 TXSTS_QSPCAVAIL_SHIFT; 3142 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3143 TXSTS_FSPCAVAIL_SHIFT; 3144 dev_vdbg(hsotg->dev, 3145 " NP Tx Req Queue Space Avail (after queue): %d\n", 3146 qspcavail); 3147 dev_vdbg(hsotg->dev, 3148 " NP Tx FIFO Space Avail (after queue): %d\n", 3149 fspcavail); 3150 3151 if (more_to_do || no_queue_space || no_fifo_space) { 3152 /* 3153 * May need to queue more transactions as the request 3154 * queue or Tx FIFO empties. Enable the non-periodic 3155 * Tx FIFO empty interrupt. (Always use the half-empty 3156 * level to ensure that new requests are loaded as 3157 * soon as possible.) 3158 */ 3159 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3160 gintmsk |= GINTSTS_NPTXFEMP; 3161 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3162 } else { 3163 /* 3164 * Disable the Tx FIFO empty interrupt since there are 3165 * no more transactions that need to be queued right 3166 * now. This function is called from interrupt 3167 * handlers to queue more transactions as transfer 3168 * states change. 3169 */ 3170 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3171 gintmsk &= ~GINTSTS_NPTXFEMP; 3172 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3173 } 3174 } 3175 } 3176 3177 /** 3178 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3179 * and queues transactions for these channels to the DWC_otg controller. Called 3180 * from the HCD interrupt handler functions. 3181 * 3182 * @hsotg: The HCD state structure 3183 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3184 * or both) 3185 * 3186 * Must be called with interrupt disabled and spinlock held 3187 */ 3188 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3189 enum dwc2_transaction_type tr_type) 3190 { 3191 #ifdef DWC2_DEBUG_SOF 3192 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3193 #endif 3194 /* Process host channels associated with periodic transfers */ 3195 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3196 tr_type == DWC2_TRANSACTION_ALL) 3197 dwc2_process_periodic_channels(hsotg); 3198 3199 /* Process host channels associated with non-periodic transfers */ 3200 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3201 tr_type == DWC2_TRANSACTION_ALL) { 3202 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3203 dwc2_process_non_periodic_channels(hsotg); 3204 } else { 3205 /* 3206 * Ensure NP Tx FIFO empty interrupt is disabled when 3207 * there are no non-periodic transfers to process 3208 */ 3209 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3210 3211 gintmsk &= ~GINTSTS_NPTXFEMP; 3212 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3213 } 3214 } 3215 } 3216 3217 static void dwc2_conn_id_status_change(struct work_struct *work) 3218 { 3219 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3220 wf_otg); 3221 u32 count = 0; 3222 u32 gotgctl; 3223 unsigned long flags; 3224 3225 dev_dbg(hsotg->dev, "%s()\n", __func__); 3226 3227 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3228 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3229 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3230 !!(gotgctl & GOTGCTL_CONID_B)); 3231 3232 /* B-Device connector (Device Mode) */ 3233 if (gotgctl & GOTGCTL_CONID_B) { 3234 /* Wait for switch to device mode */ 3235 dev_dbg(hsotg->dev, "connId B\n"); 3236 if (hsotg->bus_suspended) { 3237 dev_info(hsotg->dev, 3238 "Do port resume before switching to device mode\n"); 3239 dwc2_port_resume(hsotg); 3240 } 3241 while (!dwc2_is_device_mode(hsotg)) { 3242 dev_info(hsotg->dev, 3243 "Waiting for Peripheral Mode, Mode=%s\n", 3244 dwc2_is_host_mode(hsotg) ? "Host" : 3245 "Peripheral"); 3246 msleep(20); 3247 /* 3248 * Sometimes the initial GOTGCTRL read is wrong, so 3249 * check it again and jump to host mode if that was 3250 * the case. 3251 */ 3252 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3253 if (!(gotgctl & GOTGCTL_CONID_B)) 3254 goto host; 3255 if (++count > 250) 3256 break; 3257 } 3258 if (count > 250) 3259 dev_err(hsotg->dev, 3260 "Connection id status change timed out\n"); 3261 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3262 dwc2_core_init(hsotg, false); 3263 dwc2_enable_global_interrupts(hsotg); 3264 spin_lock_irqsave(&hsotg->lock, flags); 3265 dwc2_hsotg_core_init_disconnected(hsotg, false); 3266 spin_unlock_irqrestore(&hsotg->lock, flags); 3267 dwc2_hsotg_core_connect(hsotg); 3268 } else { 3269 host: 3270 /* A-Device connector (Host Mode) */ 3271 dev_dbg(hsotg->dev, "connId A\n"); 3272 while (!dwc2_is_host_mode(hsotg)) { 3273 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3274 dwc2_is_host_mode(hsotg) ? 3275 "Host" : "Peripheral"); 3276 msleep(20); 3277 if (++count > 250) 3278 break; 3279 } 3280 if (count > 250) 3281 dev_err(hsotg->dev, 3282 "Connection id status change timed out\n"); 3283 hsotg->op_state = OTG_STATE_A_HOST; 3284 3285 /* Initialize the Core for Host mode */ 3286 dwc2_core_init(hsotg, false); 3287 dwc2_enable_global_interrupts(hsotg); 3288 dwc2_hcd_start(hsotg); 3289 } 3290 } 3291 3292 static void dwc2_wakeup_detected(unsigned long data) 3293 { 3294 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 3295 u32 hprt0; 3296 3297 dev_dbg(hsotg->dev, "%s()\n", __func__); 3298 3299 /* 3300 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3301 * so that OPT tests pass with all PHYs.) 3302 */ 3303 hprt0 = dwc2_read_hprt0(hsotg); 3304 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3305 hprt0 &= ~HPRT0_RES; 3306 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3307 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3308 dwc2_readl(hsotg->regs + HPRT0)); 3309 3310 dwc2_hcd_rem_wakeup(hsotg); 3311 hsotg->bus_suspended = false; 3312 3313 /* Change to L0 state */ 3314 hsotg->lx_state = DWC2_L0; 3315 } 3316 3317 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3318 { 3319 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3320 3321 return hcd->self.b_hnp_enable; 3322 } 3323 3324 /* Must NOT be called with interrupt disabled or spinlock held */ 3325 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3326 { 3327 unsigned long flags; 3328 u32 hprt0; 3329 u32 pcgctl; 3330 u32 gotgctl; 3331 3332 dev_dbg(hsotg->dev, "%s()\n", __func__); 3333 3334 spin_lock_irqsave(&hsotg->lock, flags); 3335 3336 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3337 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3338 gotgctl |= GOTGCTL_HSTSETHNPEN; 3339 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3340 hsotg->op_state = OTG_STATE_A_SUSPEND; 3341 } 3342 3343 hprt0 = dwc2_read_hprt0(hsotg); 3344 hprt0 |= HPRT0_SUSP; 3345 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3346 3347 hsotg->bus_suspended = true; 3348 3349 /* 3350 * If hibernation is supported, Phy clock will be suspended 3351 * after registers are backuped. 3352 */ 3353 if (!hsotg->params.hibernation) { 3354 /* Suspend the Phy Clock */ 3355 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3356 pcgctl |= PCGCTL_STOPPCLK; 3357 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3358 udelay(10); 3359 } 3360 3361 /* For HNP the bus must be suspended for at least 200ms */ 3362 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3363 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3364 pcgctl &= ~PCGCTL_STOPPCLK; 3365 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3366 3367 spin_unlock_irqrestore(&hsotg->lock, flags); 3368 3369 msleep(200); 3370 } else { 3371 spin_unlock_irqrestore(&hsotg->lock, flags); 3372 } 3373 } 3374 3375 /* Must NOT be called with interrupt disabled or spinlock held */ 3376 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3377 { 3378 unsigned long flags; 3379 u32 hprt0; 3380 u32 pcgctl; 3381 3382 spin_lock_irqsave(&hsotg->lock, flags); 3383 3384 /* 3385 * If hibernation is supported, Phy clock is already resumed 3386 * after registers restore. 3387 */ 3388 if (!hsotg->params.hibernation) { 3389 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3390 pcgctl &= ~PCGCTL_STOPPCLK; 3391 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3392 spin_unlock_irqrestore(&hsotg->lock, flags); 3393 msleep(20); 3394 spin_lock_irqsave(&hsotg->lock, flags); 3395 } 3396 3397 hprt0 = dwc2_read_hprt0(hsotg); 3398 hprt0 |= HPRT0_RES; 3399 hprt0 &= ~HPRT0_SUSP; 3400 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3401 spin_unlock_irqrestore(&hsotg->lock, flags); 3402 3403 msleep(USB_RESUME_TIMEOUT); 3404 3405 spin_lock_irqsave(&hsotg->lock, flags); 3406 hprt0 = dwc2_read_hprt0(hsotg); 3407 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3408 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3409 hsotg->bus_suspended = false; 3410 spin_unlock_irqrestore(&hsotg->lock, flags); 3411 } 3412 3413 /* Handles hub class-specific requests */ 3414 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3415 u16 wvalue, u16 windex, char *buf, u16 wlength) 3416 { 3417 struct usb_hub_descriptor *hub_desc; 3418 int retval = 0; 3419 u32 hprt0; 3420 u32 port_status; 3421 u32 speed; 3422 u32 pcgctl; 3423 3424 switch (typereq) { 3425 case ClearHubFeature: 3426 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3427 3428 switch (wvalue) { 3429 case C_HUB_LOCAL_POWER: 3430 case C_HUB_OVER_CURRENT: 3431 /* Nothing required here */ 3432 break; 3433 3434 default: 3435 retval = -EINVAL; 3436 dev_err(hsotg->dev, 3437 "ClearHubFeature request %1xh unknown\n", 3438 wvalue); 3439 } 3440 break; 3441 3442 case ClearPortFeature: 3443 if (wvalue != USB_PORT_FEAT_L1) 3444 if (!windex || windex > 1) 3445 goto error; 3446 switch (wvalue) { 3447 case USB_PORT_FEAT_ENABLE: 3448 dev_dbg(hsotg->dev, 3449 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3450 hprt0 = dwc2_read_hprt0(hsotg); 3451 hprt0 |= HPRT0_ENA; 3452 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3453 break; 3454 3455 case USB_PORT_FEAT_SUSPEND: 3456 dev_dbg(hsotg->dev, 3457 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3458 3459 if (hsotg->bus_suspended) 3460 dwc2_port_resume(hsotg); 3461 break; 3462 3463 case USB_PORT_FEAT_POWER: 3464 dev_dbg(hsotg->dev, 3465 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3466 hprt0 = dwc2_read_hprt0(hsotg); 3467 hprt0 &= ~HPRT0_PWR; 3468 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3469 break; 3470 3471 case USB_PORT_FEAT_INDICATOR: 3472 dev_dbg(hsotg->dev, 3473 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3474 /* Port indicator not supported */ 3475 break; 3476 3477 case USB_PORT_FEAT_C_CONNECTION: 3478 /* 3479 * Clears driver's internal Connect Status Change flag 3480 */ 3481 dev_dbg(hsotg->dev, 3482 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3483 hsotg->flags.b.port_connect_status_change = 0; 3484 break; 3485 3486 case USB_PORT_FEAT_C_RESET: 3487 /* Clears driver's internal Port Reset Change flag */ 3488 dev_dbg(hsotg->dev, 3489 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3490 hsotg->flags.b.port_reset_change = 0; 3491 break; 3492 3493 case USB_PORT_FEAT_C_ENABLE: 3494 /* 3495 * Clears the driver's internal Port Enable/Disable 3496 * Change flag 3497 */ 3498 dev_dbg(hsotg->dev, 3499 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3500 hsotg->flags.b.port_enable_change = 0; 3501 break; 3502 3503 case USB_PORT_FEAT_C_SUSPEND: 3504 /* 3505 * Clears the driver's internal Port Suspend Change 3506 * flag, which is set when resume signaling on the host 3507 * port is complete 3508 */ 3509 dev_dbg(hsotg->dev, 3510 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3511 hsotg->flags.b.port_suspend_change = 0; 3512 break; 3513 3514 case USB_PORT_FEAT_C_PORT_L1: 3515 dev_dbg(hsotg->dev, 3516 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3517 hsotg->flags.b.port_l1_change = 0; 3518 break; 3519 3520 case USB_PORT_FEAT_C_OVER_CURRENT: 3521 dev_dbg(hsotg->dev, 3522 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3523 hsotg->flags.b.port_over_current_change = 0; 3524 break; 3525 3526 default: 3527 retval = -EINVAL; 3528 dev_err(hsotg->dev, 3529 "ClearPortFeature request %1xh unknown or unsupported\n", 3530 wvalue); 3531 } 3532 break; 3533 3534 case GetHubDescriptor: 3535 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3536 hub_desc = (struct usb_hub_descriptor *)buf; 3537 hub_desc->bDescLength = 9; 3538 hub_desc->bDescriptorType = USB_DT_HUB; 3539 hub_desc->bNbrPorts = 1; 3540 hub_desc->wHubCharacteristics = 3541 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3542 HUB_CHAR_INDV_PORT_OCPM); 3543 hub_desc->bPwrOn2PwrGood = 1; 3544 hub_desc->bHubContrCurrent = 0; 3545 hub_desc->u.hs.DeviceRemovable[0] = 0; 3546 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3547 break; 3548 3549 case GetHubStatus: 3550 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3551 memset(buf, 0, 4); 3552 break; 3553 3554 case GetPortStatus: 3555 dev_vdbg(hsotg->dev, 3556 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3557 hsotg->flags.d32); 3558 if (!windex || windex > 1) 3559 goto error; 3560 3561 port_status = 0; 3562 if (hsotg->flags.b.port_connect_status_change) 3563 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3564 if (hsotg->flags.b.port_enable_change) 3565 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3566 if (hsotg->flags.b.port_suspend_change) 3567 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3568 if (hsotg->flags.b.port_l1_change) 3569 port_status |= USB_PORT_STAT_C_L1 << 16; 3570 if (hsotg->flags.b.port_reset_change) 3571 port_status |= USB_PORT_STAT_C_RESET << 16; 3572 if (hsotg->flags.b.port_over_current_change) { 3573 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3574 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3575 } 3576 3577 if (!hsotg->flags.b.port_connect_status) { 3578 /* 3579 * The port is disconnected, which means the core is 3580 * either in device mode or it soon will be. Just 3581 * return 0's for the remainder of the port status 3582 * since the port register can't be read if the core 3583 * is in device mode. 3584 */ 3585 *(__le32 *)buf = cpu_to_le32(port_status); 3586 break; 3587 } 3588 3589 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3590 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3591 3592 if (hprt0 & HPRT0_CONNSTS) 3593 port_status |= USB_PORT_STAT_CONNECTION; 3594 if (hprt0 & HPRT0_ENA) 3595 port_status |= USB_PORT_STAT_ENABLE; 3596 if (hprt0 & HPRT0_SUSP) 3597 port_status |= USB_PORT_STAT_SUSPEND; 3598 if (hprt0 & HPRT0_OVRCURRACT) 3599 port_status |= USB_PORT_STAT_OVERCURRENT; 3600 if (hprt0 & HPRT0_RST) 3601 port_status |= USB_PORT_STAT_RESET; 3602 if (hprt0 & HPRT0_PWR) 3603 port_status |= USB_PORT_STAT_POWER; 3604 3605 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3606 if (speed == HPRT0_SPD_HIGH_SPEED) 3607 port_status |= USB_PORT_STAT_HIGH_SPEED; 3608 else if (speed == HPRT0_SPD_LOW_SPEED) 3609 port_status |= USB_PORT_STAT_LOW_SPEED; 3610 3611 if (hprt0 & HPRT0_TSTCTL_MASK) 3612 port_status |= USB_PORT_STAT_TEST; 3613 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3614 3615 if (hsotg->params.dma_desc_fs_enable) { 3616 /* 3617 * Enable descriptor DMA only if a full speed 3618 * device is connected. 3619 */ 3620 if (hsotg->new_connection && 3621 ((port_status & 3622 (USB_PORT_STAT_CONNECTION | 3623 USB_PORT_STAT_HIGH_SPEED | 3624 USB_PORT_STAT_LOW_SPEED)) == 3625 USB_PORT_STAT_CONNECTION)) { 3626 u32 hcfg; 3627 3628 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3629 hsotg->params.dma_desc_enable = true; 3630 hcfg = dwc2_readl(hsotg->regs + HCFG); 3631 hcfg |= HCFG_DESCDMA; 3632 dwc2_writel(hcfg, hsotg->regs + HCFG); 3633 hsotg->new_connection = false; 3634 } 3635 } 3636 3637 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3638 *(__le32 *)buf = cpu_to_le32(port_status); 3639 break; 3640 3641 case SetHubFeature: 3642 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3643 /* No HUB features supported */ 3644 break; 3645 3646 case SetPortFeature: 3647 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3648 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3649 goto error; 3650 3651 if (!hsotg->flags.b.port_connect_status) { 3652 /* 3653 * The port is disconnected, which means the core is 3654 * either in device mode or it soon will be. Just 3655 * return without doing anything since the port 3656 * register can't be written if the core is in device 3657 * mode. 3658 */ 3659 break; 3660 } 3661 3662 switch (wvalue) { 3663 case USB_PORT_FEAT_SUSPEND: 3664 dev_dbg(hsotg->dev, 3665 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3666 if (windex != hsotg->otg_port) 3667 goto error; 3668 dwc2_port_suspend(hsotg, windex); 3669 break; 3670 3671 case USB_PORT_FEAT_POWER: 3672 dev_dbg(hsotg->dev, 3673 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3674 hprt0 = dwc2_read_hprt0(hsotg); 3675 hprt0 |= HPRT0_PWR; 3676 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3677 break; 3678 3679 case USB_PORT_FEAT_RESET: 3680 hprt0 = dwc2_read_hprt0(hsotg); 3681 dev_dbg(hsotg->dev, 3682 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3683 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3684 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3685 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3686 /* ??? Original driver does this */ 3687 dwc2_writel(0, hsotg->regs + PCGCTL); 3688 3689 hprt0 = dwc2_read_hprt0(hsotg); 3690 /* Clear suspend bit if resetting from suspend state */ 3691 hprt0 &= ~HPRT0_SUSP; 3692 3693 /* 3694 * When B-Host the Port reset bit is set in the Start 3695 * HCD Callback function, so that the reset is started 3696 * within 1ms of the HNP success interrupt 3697 */ 3698 if (!dwc2_hcd_is_b_host(hsotg)) { 3699 hprt0 |= HPRT0_PWR | HPRT0_RST; 3700 dev_dbg(hsotg->dev, 3701 "In host mode, hprt0=%08x\n", hprt0); 3702 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3703 } 3704 3705 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3706 msleep(50); 3707 hprt0 &= ~HPRT0_RST; 3708 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3709 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3710 break; 3711 3712 case USB_PORT_FEAT_INDICATOR: 3713 dev_dbg(hsotg->dev, 3714 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3715 /* Not supported */ 3716 break; 3717 3718 case USB_PORT_FEAT_TEST: 3719 hprt0 = dwc2_read_hprt0(hsotg); 3720 dev_dbg(hsotg->dev, 3721 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3722 hprt0 &= ~HPRT0_TSTCTL_MASK; 3723 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3724 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3725 break; 3726 3727 default: 3728 retval = -EINVAL; 3729 dev_err(hsotg->dev, 3730 "SetPortFeature %1xh unknown or unsupported\n", 3731 wvalue); 3732 break; 3733 } 3734 break; 3735 3736 default: 3737 error: 3738 retval = -EINVAL; 3739 dev_dbg(hsotg->dev, 3740 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3741 typereq, windex, wvalue); 3742 break; 3743 } 3744 3745 return retval; 3746 } 3747 3748 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3749 { 3750 int retval; 3751 3752 if (port != 1) 3753 return -EINVAL; 3754 3755 retval = (hsotg->flags.b.port_connect_status_change || 3756 hsotg->flags.b.port_reset_change || 3757 hsotg->flags.b.port_enable_change || 3758 hsotg->flags.b.port_suspend_change || 3759 hsotg->flags.b.port_over_current_change); 3760 3761 if (retval) { 3762 dev_dbg(hsotg->dev, 3763 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3764 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3765 hsotg->flags.b.port_connect_status_change); 3766 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3767 hsotg->flags.b.port_reset_change); 3768 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3769 hsotg->flags.b.port_enable_change); 3770 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3771 hsotg->flags.b.port_suspend_change); 3772 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3773 hsotg->flags.b.port_over_current_change); 3774 } 3775 3776 return retval; 3777 } 3778 3779 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3780 { 3781 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3782 3783 #ifdef DWC2_DEBUG_SOF 3784 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3785 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3786 #endif 3787 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3788 } 3789 3790 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3791 { 3792 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3793 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3794 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3795 unsigned int us_per_frame; 3796 unsigned int frame_number; 3797 unsigned int remaining; 3798 unsigned int interval; 3799 unsigned int phy_clks; 3800 3801 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3802 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3803 3804 /* Extract fields */ 3805 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3806 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3807 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3808 3809 /* 3810 * Number of phy clocks since the last tick of the frame number after 3811 * "us" has passed. 3812 */ 3813 phy_clks = (interval - remaining) + 3814 DIV_ROUND_UP(interval * us, us_per_frame); 3815 3816 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3817 } 3818 3819 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3820 { 3821 return hsotg->op_state == OTG_STATE_B_HOST; 3822 } 3823 3824 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3825 int iso_desc_count, 3826 gfp_t mem_flags) 3827 { 3828 struct dwc2_hcd_urb *urb; 3829 u32 size = sizeof(*urb) + iso_desc_count * 3830 sizeof(struct dwc2_hcd_iso_packet_desc); 3831 3832 urb = kzalloc(size, mem_flags); 3833 if (urb) 3834 urb->packet_count = iso_desc_count; 3835 return urb; 3836 } 3837 3838 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3839 struct dwc2_hcd_urb *urb, u8 dev_addr, 3840 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3841 { 3842 if (dbg_perio() || 3843 ep_type == USB_ENDPOINT_XFER_BULK || 3844 ep_type == USB_ENDPOINT_XFER_CONTROL) 3845 dev_vdbg(hsotg->dev, 3846 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3847 dev_addr, ep_num, ep_dir, ep_type, mps); 3848 urb->pipe_info.dev_addr = dev_addr; 3849 urb->pipe_info.ep_num = ep_num; 3850 urb->pipe_info.pipe_type = ep_type; 3851 urb->pipe_info.pipe_dir = ep_dir; 3852 urb->pipe_info.mps = mps; 3853 } 3854 3855 /* 3856 * NOTE: This function will be removed once the peripheral controller code 3857 * is integrated and the driver is stable 3858 */ 3859 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3860 { 3861 #ifdef DEBUG 3862 struct dwc2_host_chan *chan; 3863 struct dwc2_hcd_urb *urb; 3864 struct dwc2_qtd *qtd; 3865 int num_channels; 3866 u32 np_tx_status; 3867 u32 p_tx_status; 3868 int i; 3869 3870 num_channels = hsotg->params.host_channels; 3871 dev_dbg(hsotg->dev, "\n"); 3872 dev_dbg(hsotg->dev, 3873 "************************************************************\n"); 3874 dev_dbg(hsotg->dev, "HCD State:\n"); 3875 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3876 3877 for (i = 0; i < num_channels; i++) { 3878 chan = hsotg->hc_ptr_array[i]; 3879 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3880 dev_dbg(hsotg->dev, 3881 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3882 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3883 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3884 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3885 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3886 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3887 chan->data_pid_start); 3888 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3889 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3890 chan->xfer_started); 3891 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3892 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3893 (unsigned long)chan->xfer_dma); 3894 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3895 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3896 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3897 chan->halt_on_queue); 3898 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3899 chan->halt_pending); 3900 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3901 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3902 dev_dbg(hsotg->dev, " complete_split: %d\n", 3903 chan->complete_split); 3904 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3905 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3906 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3907 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3908 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3909 3910 if (chan->xfer_started) { 3911 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3912 3913 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3914 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3915 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3916 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3917 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3918 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3919 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3920 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3921 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3922 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3923 } 3924 3925 if (!(chan->xfer_started && chan->qh)) 3926 continue; 3927 3928 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3929 if (!qtd->in_process) 3930 break; 3931 urb = qtd->urb; 3932 dev_dbg(hsotg->dev, " URB Info:\n"); 3933 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3934 qtd, urb); 3935 if (urb) { 3936 dev_dbg(hsotg->dev, 3937 " Dev: %d, EP: %d %s\n", 3938 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3939 dwc2_hcd_get_ep_num(&urb->pipe_info), 3940 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3941 "IN" : "OUT"); 3942 dev_dbg(hsotg->dev, 3943 " Max packet size: %d\n", 3944 dwc2_hcd_get_mps(&urb->pipe_info)); 3945 dev_dbg(hsotg->dev, 3946 " transfer_buffer: %p\n", 3947 urb->buf); 3948 dev_dbg(hsotg->dev, 3949 " transfer_dma: %08lx\n", 3950 (unsigned long)urb->dma); 3951 dev_dbg(hsotg->dev, 3952 " transfer_buffer_length: %d\n", 3953 urb->length); 3954 dev_dbg(hsotg->dev, " actual_length: %d\n", 3955 urb->actual_length); 3956 } 3957 } 3958 } 3959 3960 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3961 hsotg->non_periodic_channels); 3962 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3963 hsotg->periodic_channels); 3964 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3965 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3966 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3967 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3968 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3969 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3970 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3971 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3972 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3973 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3974 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3975 dwc2_hcd_dump_frrem(hsotg); 3976 dwc2_dump_global_registers(hsotg); 3977 dwc2_dump_host_registers(hsotg); 3978 dev_dbg(hsotg->dev, 3979 "************************************************************\n"); 3980 dev_dbg(hsotg->dev, "\n"); 3981 #endif 3982 } 3983 3984 /* 3985 * NOTE: This function will be removed once the peripheral controller code 3986 * is integrated and the driver is stable 3987 */ 3988 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 3989 { 3990 #ifdef DWC2_DUMP_FRREM 3991 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 3992 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3993 hsotg->frrem_samples, hsotg->frrem_accum, 3994 hsotg->frrem_samples > 0 ? 3995 hsotg->frrem_accum / hsotg->frrem_samples : 0); 3996 dev_dbg(hsotg->dev, "\n"); 3997 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 3998 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 3999 hsotg->hfnum_7_samples, 4000 hsotg->hfnum_7_frrem_accum, 4001 hsotg->hfnum_7_samples > 0 ? 4002 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 4003 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 4004 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4005 hsotg->hfnum_0_samples, 4006 hsotg->hfnum_0_frrem_accum, 4007 hsotg->hfnum_0_samples > 0 ? 4008 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 4009 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 4010 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4011 hsotg->hfnum_other_samples, 4012 hsotg->hfnum_other_frrem_accum, 4013 hsotg->hfnum_other_samples > 0 ? 4014 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 4015 0); 4016 dev_dbg(hsotg->dev, "\n"); 4017 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 4018 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4019 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 4020 hsotg->hfnum_7_samples_a > 0 ? 4021 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 4022 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 4023 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4024 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 4025 hsotg->hfnum_0_samples_a > 0 ? 4026 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 4027 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 4028 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4029 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 4030 hsotg->hfnum_other_samples_a > 0 ? 4031 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 4032 : 0); 4033 dev_dbg(hsotg->dev, "\n"); 4034 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 4035 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4036 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 4037 hsotg->hfnum_7_samples_b > 0 ? 4038 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 4039 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 4040 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4041 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 4042 (hsotg->hfnum_0_samples_b > 0) ? 4043 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4044 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4045 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4046 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4047 (hsotg->hfnum_other_samples_b > 0) ? 4048 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4049 : 0); 4050 #endif 4051 } 4052 4053 struct wrapper_priv_data { 4054 struct dwc2_hsotg *hsotg; 4055 }; 4056 4057 /* Gets the dwc2_hsotg from a usb_hcd */ 4058 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4059 { 4060 struct wrapper_priv_data *p; 4061 4062 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4063 return p->hsotg; 4064 } 4065 4066 /** 4067 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4068 * 4069 * This will get the dwc2_tt structure (and ttport) associated with the given 4070 * context (which is really just a struct urb pointer). 4071 * 4072 * The first time this is called for a given TT we allocate memory for our 4073 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4074 * then the refcount for the structure will go to 0 and we'll free it. 4075 * 4076 * @hsotg: The HCD state structure for the DWC OTG controller. 4077 * @qh: The QH structure. 4078 * @context: The priv pointer from a struct dwc2_hcd_urb. 4079 * @mem_flags: Flags for allocating memory. 4080 * @ttport: We'll return this device's port number here. That's used to 4081 * reference into the bitmap if we're on a multi_tt hub. 4082 * 4083 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4084 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4085 */ 4086 4087 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4088 gfp_t mem_flags, int *ttport) 4089 { 4090 struct urb *urb = context; 4091 struct dwc2_tt *dwc_tt = NULL; 4092 4093 if (urb->dev->tt) { 4094 *ttport = urb->dev->ttport; 4095 4096 dwc_tt = urb->dev->tt->hcpriv; 4097 if (!dwc_tt) { 4098 size_t bitmap_size; 4099 4100 /* 4101 * For single_tt we need one schedule. For multi_tt 4102 * we need one per port. 4103 */ 4104 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4105 sizeof(dwc_tt->periodic_bitmaps[0]); 4106 if (urb->dev->tt->multi) 4107 bitmap_size *= urb->dev->tt->hub->maxchild; 4108 4109 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4110 mem_flags); 4111 if (!dwc_tt) 4112 return NULL; 4113 4114 dwc_tt->usb_tt = urb->dev->tt; 4115 dwc_tt->usb_tt->hcpriv = dwc_tt; 4116 } 4117 4118 dwc_tt->refcount++; 4119 } 4120 4121 return dwc_tt; 4122 } 4123 4124 /** 4125 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4126 * 4127 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4128 * of the structure are done. 4129 * 4130 * It's OK to call this with NULL. 4131 * 4132 * @hsotg: The HCD state structure for the DWC OTG controller. 4133 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4134 */ 4135 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4136 { 4137 /* Model kfree and make put of NULL a no-op */ 4138 if (!dwc_tt) 4139 return; 4140 4141 WARN_ON(dwc_tt->refcount < 1); 4142 4143 dwc_tt->refcount--; 4144 if (!dwc_tt->refcount) { 4145 dwc_tt->usb_tt->hcpriv = NULL; 4146 kfree(dwc_tt); 4147 } 4148 } 4149 4150 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4151 { 4152 struct urb *urb = context; 4153 4154 return urb->dev->speed; 4155 } 4156 4157 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4158 struct urb *urb) 4159 { 4160 struct usb_bus *bus = hcd_to_bus(hcd); 4161 4162 if (urb->interval) 4163 bus->bandwidth_allocated += bw / urb->interval; 4164 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4165 bus->bandwidth_isoc_reqs++; 4166 else 4167 bus->bandwidth_int_reqs++; 4168 } 4169 4170 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4171 struct urb *urb) 4172 { 4173 struct usb_bus *bus = hcd_to_bus(hcd); 4174 4175 if (urb->interval) 4176 bus->bandwidth_allocated -= bw / urb->interval; 4177 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4178 bus->bandwidth_isoc_reqs--; 4179 else 4180 bus->bandwidth_int_reqs--; 4181 } 4182 4183 /* 4184 * Sets the final status of an URB and returns it to the upper layer. Any 4185 * required cleanup of the URB is performed. 4186 * 4187 * Must be called with interrupt disabled and spinlock held 4188 */ 4189 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4190 int status) 4191 { 4192 struct urb *urb; 4193 int i; 4194 4195 if (!qtd) { 4196 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4197 return; 4198 } 4199 4200 if (!qtd->urb) { 4201 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4202 return; 4203 } 4204 4205 urb = qtd->urb->priv; 4206 if (!urb) { 4207 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4208 return; 4209 } 4210 4211 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4212 4213 if (dbg_urb(urb)) 4214 dev_vdbg(hsotg->dev, 4215 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4216 __func__, urb, usb_pipedevice(urb->pipe), 4217 usb_pipeendpoint(urb->pipe), 4218 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4219 urb->actual_length); 4220 4221 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4222 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4223 for (i = 0; i < urb->number_of_packets; ++i) { 4224 urb->iso_frame_desc[i].actual_length = 4225 dwc2_hcd_urb_get_iso_desc_actual_length( 4226 qtd->urb, i); 4227 urb->iso_frame_desc[i].status = 4228 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4229 } 4230 } 4231 4232 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4233 for (i = 0; i < urb->number_of_packets; i++) 4234 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4235 i, urb->iso_frame_desc[i].status); 4236 } 4237 4238 urb->status = status; 4239 if (!status) { 4240 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4241 urb->actual_length < urb->transfer_buffer_length) 4242 urb->status = -EREMOTEIO; 4243 } 4244 4245 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4246 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4247 struct usb_host_endpoint *ep = urb->ep; 4248 4249 if (ep) 4250 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4251 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4252 urb); 4253 } 4254 4255 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4256 urb->hcpriv = NULL; 4257 kfree(qtd->urb); 4258 qtd->urb = NULL; 4259 4260 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4261 } 4262 4263 /* 4264 * Work queue function for starting the HCD when A-Cable is connected 4265 */ 4266 static void dwc2_hcd_start_func(struct work_struct *work) 4267 { 4268 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4269 start_work.work); 4270 4271 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4272 dwc2_host_start(hsotg); 4273 } 4274 4275 /* 4276 * Reset work queue function 4277 */ 4278 static void dwc2_hcd_reset_func(struct work_struct *work) 4279 { 4280 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4281 reset_work.work); 4282 unsigned long flags; 4283 u32 hprt0; 4284 4285 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4286 4287 spin_lock_irqsave(&hsotg->lock, flags); 4288 4289 hprt0 = dwc2_read_hprt0(hsotg); 4290 hprt0 &= ~HPRT0_RST; 4291 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4292 hsotg->flags.b.port_reset_change = 1; 4293 4294 spin_unlock_irqrestore(&hsotg->lock, flags); 4295 } 4296 4297 /* 4298 * ========================================================================= 4299 * Linux HC Driver Functions 4300 * ========================================================================= 4301 */ 4302 4303 /* 4304 * Initializes the DWC_otg controller and its root hub and prepares it for host 4305 * mode operation. Activates the root port. Returns 0 on success and a negative 4306 * error code on failure. 4307 */ 4308 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4309 { 4310 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4311 struct usb_bus *bus = hcd_to_bus(hcd); 4312 unsigned long flags; 4313 4314 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4315 4316 spin_lock_irqsave(&hsotg->lock, flags); 4317 hsotg->lx_state = DWC2_L0; 4318 hcd->state = HC_STATE_RUNNING; 4319 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4320 4321 if (dwc2_is_device_mode(hsotg)) { 4322 spin_unlock_irqrestore(&hsotg->lock, flags); 4323 return 0; /* why 0 ?? */ 4324 } 4325 4326 dwc2_hcd_reinit(hsotg); 4327 4328 /* Initialize and connect root hub if one is not already attached */ 4329 if (bus->root_hub) { 4330 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4331 /* Inform the HUB driver to resume */ 4332 usb_hcd_resume_root_hub(hcd); 4333 } 4334 4335 spin_unlock_irqrestore(&hsotg->lock, flags); 4336 return 0; 4337 } 4338 4339 /* 4340 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4341 * stopped. 4342 */ 4343 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4344 { 4345 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4346 unsigned long flags; 4347 4348 /* Turn off all host-specific interrupts */ 4349 dwc2_disable_host_interrupts(hsotg); 4350 4351 /* Wait for interrupt processing to finish */ 4352 synchronize_irq(hcd->irq); 4353 4354 spin_lock_irqsave(&hsotg->lock, flags); 4355 /* Ensure hcd is disconnected */ 4356 dwc2_hcd_disconnect(hsotg, true); 4357 dwc2_hcd_stop(hsotg); 4358 hsotg->lx_state = DWC2_L3; 4359 hcd->state = HC_STATE_HALT; 4360 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4361 spin_unlock_irqrestore(&hsotg->lock, flags); 4362 4363 usleep_range(1000, 3000); 4364 } 4365 4366 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4367 { 4368 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4369 unsigned long flags; 4370 int ret = 0; 4371 u32 hprt0; 4372 4373 spin_lock_irqsave(&hsotg->lock, flags); 4374 4375 if (hsotg->lx_state != DWC2_L0) 4376 goto unlock; 4377 4378 if (!HCD_HW_ACCESSIBLE(hcd)) 4379 goto unlock; 4380 4381 if (!hsotg->params.hibernation) 4382 goto skip_power_saving; 4383 4384 /* 4385 * Drive USB suspend and disable port Power 4386 * if usb bus is not suspended. 4387 */ 4388 if (!hsotg->bus_suspended) { 4389 hprt0 = dwc2_read_hprt0(hsotg); 4390 hprt0 |= HPRT0_SUSP; 4391 hprt0 &= ~HPRT0_PWR; 4392 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4393 } 4394 4395 /* Enter hibernation */ 4396 ret = dwc2_enter_hibernation(hsotg); 4397 if (ret) { 4398 if (ret != -ENOTSUPP) 4399 dev_err(hsotg->dev, 4400 "enter hibernation failed\n"); 4401 goto skip_power_saving; 4402 } 4403 4404 /* Ask phy to be suspended */ 4405 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4406 spin_unlock_irqrestore(&hsotg->lock, flags); 4407 usb_phy_set_suspend(hsotg->uphy, true); 4408 spin_lock_irqsave(&hsotg->lock, flags); 4409 } 4410 4411 /* After entering hibernation, hardware is no more accessible */ 4412 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4413 4414 skip_power_saving: 4415 hsotg->lx_state = DWC2_L2; 4416 unlock: 4417 spin_unlock_irqrestore(&hsotg->lock, flags); 4418 4419 return ret; 4420 } 4421 4422 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4423 { 4424 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4425 unsigned long flags; 4426 int ret = 0; 4427 4428 spin_lock_irqsave(&hsotg->lock, flags); 4429 4430 if (hsotg->lx_state != DWC2_L2) 4431 goto unlock; 4432 4433 if (!hsotg->params.hibernation) { 4434 hsotg->lx_state = DWC2_L0; 4435 goto unlock; 4436 } 4437 4438 /* 4439 * Set HW accessible bit before powering on the controller 4440 * since an interrupt may rise. 4441 */ 4442 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4443 4444 /* 4445 * Enable power if not already done. 4446 * This must not be spinlocked since duration 4447 * of this call is unknown. 4448 */ 4449 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4450 spin_unlock_irqrestore(&hsotg->lock, flags); 4451 usb_phy_set_suspend(hsotg->uphy, false); 4452 spin_lock_irqsave(&hsotg->lock, flags); 4453 } 4454 4455 /* Exit hibernation */ 4456 ret = dwc2_exit_hibernation(hsotg, true); 4457 if (ret && (ret != -ENOTSUPP)) 4458 dev_err(hsotg->dev, "exit hibernation failed\n"); 4459 4460 hsotg->lx_state = DWC2_L0; 4461 4462 spin_unlock_irqrestore(&hsotg->lock, flags); 4463 4464 if (hsotg->bus_suspended) { 4465 spin_lock_irqsave(&hsotg->lock, flags); 4466 hsotg->flags.b.port_suspend_change = 1; 4467 spin_unlock_irqrestore(&hsotg->lock, flags); 4468 dwc2_port_resume(hsotg); 4469 } else { 4470 /* Wait for controller to correctly update D+/D- level */ 4471 usleep_range(3000, 5000); 4472 4473 /* 4474 * Clear Port Enable and Port Status changes. 4475 * Enable Port Power. 4476 */ 4477 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4478 HPRT0_ENACHG, hsotg->regs + HPRT0); 4479 /* Wait for controller to detect Port Connect */ 4480 usleep_range(5000, 7000); 4481 } 4482 4483 return ret; 4484 unlock: 4485 spin_unlock_irqrestore(&hsotg->lock, flags); 4486 4487 return ret; 4488 } 4489 4490 /* Returns the current frame number */ 4491 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4492 { 4493 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4494 4495 return dwc2_hcd_get_frame_number(hsotg); 4496 } 4497 4498 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4499 char *fn_name) 4500 { 4501 #ifdef VERBOSE_DEBUG 4502 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4503 char *pipetype; 4504 char *speed; 4505 4506 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4507 dev_vdbg(hsotg->dev, " Device address: %d\n", 4508 usb_pipedevice(urb->pipe)); 4509 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4510 usb_pipeendpoint(urb->pipe), 4511 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4512 4513 switch (usb_pipetype(urb->pipe)) { 4514 case PIPE_CONTROL: 4515 pipetype = "CONTROL"; 4516 break; 4517 case PIPE_BULK: 4518 pipetype = "BULK"; 4519 break; 4520 case PIPE_INTERRUPT: 4521 pipetype = "INTERRUPT"; 4522 break; 4523 case PIPE_ISOCHRONOUS: 4524 pipetype = "ISOCHRONOUS"; 4525 break; 4526 } 4527 4528 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4529 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4530 "IN" : "OUT"); 4531 4532 switch (urb->dev->speed) { 4533 case USB_SPEED_HIGH: 4534 speed = "HIGH"; 4535 break; 4536 case USB_SPEED_FULL: 4537 speed = "FULL"; 4538 break; 4539 case USB_SPEED_LOW: 4540 speed = "LOW"; 4541 break; 4542 default: 4543 speed = "UNKNOWN"; 4544 break; 4545 } 4546 4547 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4548 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4549 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4550 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4551 urb->transfer_buffer_length); 4552 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4553 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4554 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4555 urb->setup_packet, (unsigned long)urb->setup_dma); 4556 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4557 4558 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4559 int i; 4560 4561 for (i = 0; i < urb->number_of_packets; i++) { 4562 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4563 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4564 urb->iso_frame_desc[i].offset, 4565 urb->iso_frame_desc[i].length); 4566 } 4567 } 4568 #endif 4569 } 4570 4571 /* 4572 * Starts processing a USB transfer request specified by a USB Request Block 4573 * (URB). mem_flags indicates the type of memory allocation to use while 4574 * processing this URB. 4575 */ 4576 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4577 gfp_t mem_flags) 4578 { 4579 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4580 struct usb_host_endpoint *ep = urb->ep; 4581 struct dwc2_hcd_urb *dwc2_urb; 4582 int i; 4583 int retval; 4584 int alloc_bandwidth = 0; 4585 u8 ep_type = 0; 4586 u32 tflags = 0; 4587 void *buf; 4588 unsigned long flags; 4589 struct dwc2_qh *qh; 4590 bool qh_allocated = false; 4591 struct dwc2_qtd *qtd; 4592 4593 if (dbg_urb(urb)) { 4594 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4595 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4596 } 4597 4598 if (!ep) 4599 return -EINVAL; 4600 4601 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4602 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4603 spin_lock_irqsave(&hsotg->lock, flags); 4604 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4605 alloc_bandwidth = 1; 4606 spin_unlock_irqrestore(&hsotg->lock, flags); 4607 } 4608 4609 switch (usb_pipetype(urb->pipe)) { 4610 case PIPE_CONTROL: 4611 ep_type = USB_ENDPOINT_XFER_CONTROL; 4612 break; 4613 case PIPE_ISOCHRONOUS: 4614 ep_type = USB_ENDPOINT_XFER_ISOC; 4615 break; 4616 case PIPE_BULK: 4617 ep_type = USB_ENDPOINT_XFER_BULK; 4618 break; 4619 case PIPE_INTERRUPT: 4620 ep_type = USB_ENDPOINT_XFER_INT; 4621 break; 4622 } 4623 4624 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4625 mem_flags); 4626 if (!dwc2_urb) 4627 return -ENOMEM; 4628 4629 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4630 usb_pipeendpoint(urb->pipe), ep_type, 4631 usb_pipein(urb->pipe), 4632 usb_maxpacket(urb->dev, urb->pipe, 4633 !(usb_pipein(urb->pipe)))); 4634 4635 buf = urb->transfer_buffer; 4636 4637 if (hcd->self.uses_dma) { 4638 if (!buf && (urb->transfer_dma & 3)) { 4639 dev_err(hsotg->dev, 4640 "%s: unaligned transfer with no transfer_buffer", 4641 __func__); 4642 retval = -EINVAL; 4643 goto fail0; 4644 } 4645 } 4646 4647 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4648 tflags |= URB_GIVEBACK_ASAP; 4649 if (urb->transfer_flags & URB_ZERO_PACKET) 4650 tflags |= URB_SEND_ZERO_PACKET; 4651 4652 dwc2_urb->priv = urb; 4653 dwc2_urb->buf = buf; 4654 dwc2_urb->dma = urb->transfer_dma; 4655 dwc2_urb->length = urb->transfer_buffer_length; 4656 dwc2_urb->setup_packet = urb->setup_packet; 4657 dwc2_urb->setup_dma = urb->setup_dma; 4658 dwc2_urb->flags = tflags; 4659 dwc2_urb->interval = urb->interval; 4660 dwc2_urb->status = -EINPROGRESS; 4661 4662 for (i = 0; i < urb->number_of_packets; ++i) 4663 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4664 urb->iso_frame_desc[i].offset, 4665 urb->iso_frame_desc[i].length); 4666 4667 urb->hcpriv = dwc2_urb; 4668 qh = (struct dwc2_qh *)ep->hcpriv; 4669 /* Create QH for the endpoint if it doesn't exist */ 4670 if (!qh) { 4671 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4672 if (!qh) { 4673 retval = -ENOMEM; 4674 goto fail0; 4675 } 4676 ep->hcpriv = qh; 4677 qh_allocated = true; 4678 } 4679 4680 qtd = kzalloc(sizeof(*qtd), mem_flags); 4681 if (!qtd) { 4682 retval = -ENOMEM; 4683 goto fail1; 4684 } 4685 4686 spin_lock_irqsave(&hsotg->lock, flags); 4687 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4688 if (retval) 4689 goto fail2; 4690 4691 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4692 if (retval) 4693 goto fail3; 4694 4695 if (alloc_bandwidth) { 4696 dwc2_allocate_bus_bandwidth(hcd, 4697 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4698 urb); 4699 } 4700 4701 spin_unlock_irqrestore(&hsotg->lock, flags); 4702 4703 return 0; 4704 4705 fail3: 4706 dwc2_urb->priv = NULL; 4707 usb_hcd_unlink_urb_from_ep(hcd, urb); 4708 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4709 qh->channel->qh = NULL; 4710 fail2: 4711 spin_unlock_irqrestore(&hsotg->lock, flags); 4712 urb->hcpriv = NULL; 4713 kfree(qtd); 4714 qtd = NULL; 4715 fail1: 4716 if (qh_allocated) { 4717 struct dwc2_qtd *qtd2, *qtd2_tmp; 4718 4719 ep->hcpriv = NULL; 4720 dwc2_hcd_qh_unlink(hsotg, qh); 4721 /* Free each QTD in the QH's QTD list */ 4722 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4723 qtd_list_entry) 4724 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4725 dwc2_hcd_qh_free(hsotg, qh); 4726 } 4727 fail0: 4728 kfree(dwc2_urb); 4729 4730 return retval; 4731 } 4732 4733 /* 4734 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4735 */ 4736 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4737 int status) 4738 { 4739 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4740 int rc; 4741 unsigned long flags; 4742 4743 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4744 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4745 4746 spin_lock_irqsave(&hsotg->lock, flags); 4747 4748 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4749 if (rc) 4750 goto out; 4751 4752 if (!urb->hcpriv) { 4753 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4754 goto out; 4755 } 4756 4757 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4758 4759 usb_hcd_unlink_urb_from_ep(hcd, urb); 4760 4761 kfree(urb->hcpriv); 4762 urb->hcpriv = NULL; 4763 4764 /* Higher layer software sets URB status */ 4765 spin_unlock(&hsotg->lock); 4766 usb_hcd_giveback_urb(hcd, urb, status); 4767 spin_lock(&hsotg->lock); 4768 4769 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4770 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4771 out: 4772 spin_unlock_irqrestore(&hsotg->lock, flags); 4773 4774 return rc; 4775 } 4776 4777 /* 4778 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4779 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4780 * must already be dequeued. 4781 */ 4782 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4783 struct usb_host_endpoint *ep) 4784 { 4785 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4786 4787 dev_dbg(hsotg->dev, 4788 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4789 ep->desc.bEndpointAddress, ep->hcpriv); 4790 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4791 } 4792 4793 /* 4794 * Resets endpoint specific parameter values, in current version used to reset 4795 * the data toggle (as a WA). This function can be called from usb_clear_halt 4796 * routine. 4797 */ 4798 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4799 struct usb_host_endpoint *ep) 4800 { 4801 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4802 unsigned long flags; 4803 4804 dev_dbg(hsotg->dev, 4805 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4806 ep->desc.bEndpointAddress); 4807 4808 spin_lock_irqsave(&hsotg->lock, flags); 4809 dwc2_hcd_endpoint_reset(hsotg, ep); 4810 spin_unlock_irqrestore(&hsotg->lock, flags); 4811 } 4812 4813 /* 4814 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4815 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4816 * interrupt. 4817 * 4818 * This function is called by the USB core when an interrupt occurs 4819 */ 4820 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4821 { 4822 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4823 4824 return dwc2_handle_hcd_intr(hsotg); 4825 } 4826 4827 /* 4828 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4829 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4830 * is the status change indicator for the single root port. Returns 1 if either 4831 * change indicator is 1, otherwise returns 0. 4832 */ 4833 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4834 { 4835 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4836 4837 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4838 return buf[0] != 0; 4839 } 4840 4841 /* Handles hub class-specific requests */ 4842 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4843 u16 windex, char *buf, u16 wlength) 4844 { 4845 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4846 wvalue, windex, buf, wlength); 4847 return retval; 4848 } 4849 4850 /* Handles hub TT buffer clear completions */ 4851 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4852 struct usb_host_endpoint *ep) 4853 { 4854 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4855 struct dwc2_qh *qh; 4856 unsigned long flags; 4857 4858 qh = ep->hcpriv; 4859 if (!qh) 4860 return; 4861 4862 spin_lock_irqsave(&hsotg->lock, flags); 4863 qh->tt_buffer_dirty = 0; 4864 4865 if (hsotg->flags.b.port_connect_status) 4866 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4867 4868 spin_unlock_irqrestore(&hsotg->lock, flags); 4869 } 4870 4871 static struct hc_driver dwc2_hc_driver = { 4872 .description = "dwc2_hsotg", 4873 .product_desc = "DWC OTG Controller", 4874 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4875 4876 .irq = _dwc2_hcd_irq, 4877 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4878 4879 .start = _dwc2_hcd_start, 4880 .stop = _dwc2_hcd_stop, 4881 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4882 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4883 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4884 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4885 .get_frame_number = _dwc2_hcd_get_frame_number, 4886 4887 .hub_status_data = _dwc2_hcd_hub_status_data, 4888 .hub_control = _dwc2_hcd_hub_control, 4889 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4890 4891 .bus_suspend = _dwc2_hcd_suspend, 4892 .bus_resume = _dwc2_hcd_resume, 4893 4894 .map_urb_for_dma = dwc2_map_urb_for_dma, 4895 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4896 }; 4897 4898 /* 4899 * Frees secondary storage associated with the dwc2_hsotg structure contained 4900 * in the struct usb_hcd field 4901 */ 4902 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4903 { 4904 u32 ahbcfg; 4905 u32 dctl; 4906 int i; 4907 4908 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4909 4910 /* Free memory for QH/QTD lists */ 4911 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4912 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4913 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4914 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4915 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4916 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4917 4918 /* Free memory for the host channels */ 4919 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4920 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4921 4922 if (chan) { 4923 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4924 i, chan); 4925 hsotg->hc_ptr_array[i] = NULL; 4926 kfree(chan); 4927 } 4928 } 4929 4930 if (hsotg->params.host_dma) { 4931 if (hsotg->status_buf) { 4932 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 4933 hsotg->status_buf, 4934 hsotg->status_buf_dma); 4935 hsotg->status_buf = NULL; 4936 } 4937 } else { 4938 kfree(hsotg->status_buf); 4939 hsotg->status_buf = NULL; 4940 } 4941 4942 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 4943 4944 /* Disable all interrupts */ 4945 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 4946 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 4947 dwc2_writel(0, hsotg->regs + GINTMSK); 4948 4949 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 4950 dctl = dwc2_readl(hsotg->regs + DCTL); 4951 dctl |= DCTL_SFTDISCON; 4952 dwc2_writel(dctl, hsotg->regs + DCTL); 4953 } 4954 4955 if (hsotg->wq_otg) { 4956 if (!cancel_work_sync(&hsotg->wf_otg)) 4957 flush_workqueue(hsotg->wq_otg); 4958 destroy_workqueue(hsotg->wq_otg); 4959 } 4960 4961 del_timer(&hsotg->wkp_timer); 4962 } 4963 4964 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 4965 { 4966 /* Turn off all host-specific interrupts */ 4967 dwc2_disable_host_interrupts(hsotg); 4968 4969 dwc2_hcd_free(hsotg); 4970 } 4971 4972 /* 4973 * Initializes the HCD. This function allocates memory for and initializes the 4974 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 4975 * USB bus with the core and calls the hc_driver->start() function. It returns 4976 * a negative error on failure. 4977 */ 4978 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 4979 { 4980 struct usb_hcd *hcd; 4981 struct dwc2_host_chan *channel; 4982 u32 hcfg; 4983 int i, num_channels; 4984 int retval; 4985 4986 if (usb_disabled()) 4987 return -ENODEV; 4988 4989 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 4990 4991 retval = -ENOMEM; 4992 4993 hcfg = dwc2_readl(hsotg->regs + HCFG); 4994 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 4995 4996 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 4997 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 4998 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 4999 if (!hsotg->frame_num_array) 5000 goto error1; 5001 hsotg->last_frame_num_array = kzalloc( 5002 sizeof(*hsotg->last_frame_num_array) * 5003 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5004 if (!hsotg->last_frame_num_array) 5005 goto error1; 5006 #endif 5007 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5008 5009 /* Check if the bus driver or platform code has setup a dma_mask */ 5010 if (hsotg->params.host_dma && 5011 !hsotg->dev->dma_mask) { 5012 dev_warn(hsotg->dev, 5013 "dma_mask not set, disabling DMA\n"); 5014 hsotg->params.host_dma = false; 5015 hsotg->params.dma_desc_enable = false; 5016 } 5017 5018 /* Set device flags indicating whether the HCD supports DMA */ 5019 if (hsotg->params.host_dma) { 5020 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5021 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5022 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5023 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5024 } 5025 5026 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5027 if (!hcd) 5028 goto error1; 5029 5030 if (!hsotg->params.host_dma) 5031 hcd->self.uses_dma = 0; 5032 5033 hcd->has_tt = 1; 5034 5035 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5036 hsotg->priv = hcd; 5037 5038 /* 5039 * Disable the global interrupt until all the interrupt handlers are 5040 * installed 5041 */ 5042 dwc2_disable_global_interrupts(hsotg); 5043 5044 /* Initialize the DWC_otg core, and select the Phy type */ 5045 retval = dwc2_core_init(hsotg, true); 5046 if (retval) 5047 goto error2; 5048 5049 /* Create new workqueue and init work */ 5050 retval = -ENOMEM; 5051 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5052 if (!hsotg->wq_otg) { 5053 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5054 goto error2; 5055 } 5056 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5057 5058 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 5059 (unsigned long)hsotg); 5060 5061 /* Initialize the non-periodic schedule */ 5062 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5063 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5064 5065 /* Initialize the periodic schedule */ 5066 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5067 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5068 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5069 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5070 5071 INIT_LIST_HEAD(&hsotg->split_order); 5072 5073 /* 5074 * Create a host channel descriptor for each host channel implemented 5075 * in the controller. Initialize the channel descriptor array. 5076 */ 5077 INIT_LIST_HEAD(&hsotg->free_hc_list); 5078 num_channels = hsotg->params.host_channels; 5079 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5080 5081 for (i = 0; i < num_channels; i++) { 5082 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5083 if (!channel) 5084 goto error3; 5085 channel->hc_num = i; 5086 INIT_LIST_HEAD(&channel->split_order_list_entry); 5087 hsotg->hc_ptr_array[i] = channel; 5088 } 5089 5090 /* Initialize hsotg start work */ 5091 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5092 5093 /* Initialize port reset work */ 5094 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5095 5096 /* 5097 * Allocate space for storing data on status transactions. Normally no 5098 * data is sent, but this space acts as a bit bucket. This must be 5099 * done after usb_add_hcd since that function allocates the DMA buffer 5100 * pool. 5101 */ 5102 if (hsotg->params.host_dma) 5103 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5104 DWC2_HCD_STATUS_BUF_SIZE, 5105 &hsotg->status_buf_dma, GFP_KERNEL); 5106 else 5107 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5108 GFP_KERNEL); 5109 5110 if (!hsotg->status_buf) 5111 goto error3; 5112 5113 /* 5114 * Create kmem caches to handle descriptor buffers in descriptor 5115 * DMA mode. 5116 * Alignment must be set to 512 bytes. 5117 */ 5118 if (hsotg->params.dma_desc_enable || 5119 hsotg->params.dma_desc_fs_enable) { 5120 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5121 sizeof(struct dwc2_dma_desc) * 5122 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5123 NULL); 5124 if (!hsotg->desc_gen_cache) { 5125 dev_err(hsotg->dev, 5126 "unable to create dwc2 generic desc cache\n"); 5127 5128 /* 5129 * Disable descriptor dma mode since it will not be 5130 * usable. 5131 */ 5132 hsotg->params.dma_desc_enable = false; 5133 hsotg->params.dma_desc_fs_enable = false; 5134 } 5135 5136 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5137 sizeof(struct dwc2_dma_desc) * 5138 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5139 if (!hsotg->desc_hsisoc_cache) { 5140 dev_err(hsotg->dev, 5141 "unable to create dwc2 hs isoc desc cache\n"); 5142 5143 kmem_cache_destroy(hsotg->desc_gen_cache); 5144 5145 /* 5146 * Disable descriptor dma mode since it will not be 5147 * usable. 5148 */ 5149 hsotg->params.dma_desc_enable = false; 5150 hsotg->params.dma_desc_fs_enable = false; 5151 } 5152 } 5153 5154 hsotg->otg_port = 1; 5155 hsotg->frame_list = NULL; 5156 hsotg->frame_list_dma = 0; 5157 hsotg->periodic_qh_count = 0; 5158 5159 /* Initiate lx_state to L3 disconnected state */ 5160 hsotg->lx_state = DWC2_L3; 5161 5162 hcd->self.otg_port = hsotg->otg_port; 5163 5164 /* Don't support SG list at this point */ 5165 hcd->self.sg_tablesize = 0; 5166 5167 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5168 otg_set_host(hsotg->uphy->otg, &hcd->self); 5169 5170 /* 5171 * Finish generic HCD initialization and start the HCD. This function 5172 * allocates the DMA buffer pool, registers the USB bus, requests the 5173 * IRQ line, and calls hcd_start method. 5174 */ 5175 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 5176 if (retval < 0) 5177 goto error4; 5178 5179 device_wakeup_enable(hcd->self.controller); 5180 5181 dwc2_hcd_dump_state(hsotg); 5182 5183 dwc2_enable_global_interrupts(hsotg); 5184 5185 return 0; 5186 5187 error4: 5188 kmem_cache_destroy(hsotg->desc_gen_cache); 5189 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5190 error3: 5191 dwc2_hcd_release(hsotg); 5192 error2: 5193 usb_put_hcd(hcd); 5194 error1: 5195 5196 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5197 kfree(hsotg->last_frame_num_array); 5198 kfree(hsotg->frame_num_array); 5199 #endif 5200 5201 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5202 return retval; 5203 } 5204 5205 /* 5206 * Removes the HCD. 5207 * Frees memory and resources associated with the HCD and deregisters the bus. 5208 */ 5209 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5210 { 5211 struct usb_hcd *hcd; 5212 5213 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5214 5215 hcd = dwc2_hsotg_to_hcd(hsotg); 5216 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5217 5218 if (!hcd) { 5219 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5220 __func__); 5221 return; 5222 } 5223 5224 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5225 otg_set_host(hsotg->uphy->otg, NULL); 5226 5227 usb_remove_hcd(hcd); 5228 hsotg->priv = NULL; 5229 5230 kmem_cache_destroy(hsotg->desc_gen_cache); 5231 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5232 5233 dwc2_hcd_release(hsotg); 5234 usb_put_hcd(hcd); 5235 5236 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5237 kfree(hsotg->last_frame_num_array); 5238 kfree(hsotg->frame_num_array); 5239 #endif 5240 } 5241 5242 /** 5243 * dwc2_backup_host_registers() - Backup controller host registers. 5244 * When suspending usb bus, registers needs to be backuped 5245 * if controller power is disabled once suspended. 5246 * 5247 * @hsotg: Programming view of the DWC_otg controller 5248 */ 5249 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5250 { 5251 struct dwc2_hregs_backup *hr; 5252 int i; 5253 5254 dev_dbg(hsotg->dev, "%s\n", __func__); 5255 5256 /* Backup Host regs */ 5257 hr = &hsotg->hr_backup; 5258 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5259 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5260 for (i = 0; i < hsotg->params.host_channels; ++i) 5261 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5262 5263 hr->hprt0 = dwc2_read_hprt0(hsotg); 5264 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5265 hr->valid = true; 5266 5267 return 0; 5268 } 5269 5270 /** 5271 * dwc2_restore_host_registers() - Restore controller host registers. 5272 * When resuming usb bus, device registers needs to be restored 5273 * if controller power were disabled. 5274 * 5275 * @hsotg: Programming view of the DWC_otg controller 5276 */ 5277 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5278 { 5279 struct dwc2_hregs_backup *hr; 5280 int i; 5281 5282 dev_dbg(hsotg->dev, "%s\n", __func__); 5283 5284 /* Restore host regs */ 5285 hr = &hsotg->hr_backup; 5286 if (!hr->valid) { 5287 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5288 __func__); 5289 return -EINVAL; 5290 } 5291 hr->valid = false; 5292 5293 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5294 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5295 5296 for (i = 0; i < hsotg->params.host_channels; ++i) 5297 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5298 5299 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5300 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5301 hsotg->frame_number = 0; 5302 5303 return 0; 5304 } 5305