1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.c - DesignWare HS OTG Controller host-mode routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * This file contains the core HCD code, and implements the Linux hc_driver 40 * API 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/platform_device.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 60 61 /* 62 * ========================================================================= 63 * Host Core Layer Functions 64 * ========================================================================= 65 */ 66 67 /** 68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 69 * used in both device and host modes 70 * 71 * @hsotg: Programming view of the DWC_otg controller 72 */ 73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 74 { 75 u32 intmsk; 76 77 /* Clear any pending OTG Interrupts */ 78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 79 80 /* Clear any pending interrupts */ 81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 82 83 /* Enable the interrupts in the GINTMSK */ 84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 85 86 if (!hsotg->params.host_dma) 87 intmsk |= GINTSTS_RXFLVL; 88 if (!hsotg->params.external_id_pin_ctl) 89 intmsk |= GINTSTS_CONIDSTSCHNG; 90 91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 92 GINTSTS_SESSREQINT; 93 94 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 95 } 96 97 /* 98 * Initializes the FSLSPClkSel field of the HCFG register depending on the 99 * PHY type 100 */ 101 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 102 { 103 u32 hcfg, val; 104 105 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 106 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 107 hsotg->params.ulpi_fs_ls) || 108 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 109 /* Full speed PHY */ 110 val = HCFG_FSLSPCLKSEL_48_MHZ; 111 } else { 112 /* High speed PHY running at full speed or high speed */ 113 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 114 } 115 116 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 117 hcfg = dwc2_readl(hsotg->regs + HCFG); 118 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 119 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 120 dwc2_writel(hcfg, hsotg->regs + HCFG); 121 } 122 123 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 124 { 125 u32 usbcfg, ggpio, i2cctl; 126 int retval = 0; 127 128 /* 129 * core_init() is now called on every switch so only call the 130 * following for the first time through 131 */ 132 if (select_phy) { 133 dev_dbg(hsotg->dev, "FS PHY selected\n"); 134 135 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 136 if (!(usbcfg & GUSBCFG_PHYSEL)) { 137 usbcfg |= GUSBCFG_PHYSEL; 138 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 139 140 /* Reset after a PHY select */ 141 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 142 143 if (retval) { 144 dev_err(hsotg->dev, 145 "%s: Reset failed, aborting", __func__); 146 return retval; 147 } 148 } 149 150 if (hsotg->params.activate_stm_fs_transceiver) { 151 ggpio = dwc2_readl(hsotg->regs + GGPIO); 152 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 153 dev_dbg(hsotg->dev, "Activating transceiver\n"); 154 /* 155 * STM32F4x9 uses the GGPIO register as general 156 * core configuration register. 157 */ 158 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 159 dwc2_writel(ggpio, hsotg->regs + GGPIO); 160 } 161 } 162 } 163 164 /* 165 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 166 * do this on HNP Dev/Host mode switches (done in dev_init and 167 * host_init). 168 */ 169 if (dwc2_is_host_mode(hsotg)) 170 dwc2_init_fs_ls_pclk_sel(hsotg); 171 172 if (hsotg->params.i2c_enable) { 173 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 174 175 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 176 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 177 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 178 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 179 180 /* Program GI2CCTL.I2CEn */ 181 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 182 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 183 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 184 i2cctl &= ~GI2CCTL_I2CEN; 185 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 186 i2cctl |= GI2CCTL_I2CEN; 187 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 188 } 189 190 return retval; 191 } 192 193 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 194 { 195 u32 usbcfg, usbcfg_old; 196 int retval = 0; 197 198 if (!select_phy) 199 return 0; 200 201 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 202 usbcfg_old = usbcfg; 203 204 /* 205 * HS PHY parameters. These parameters are preserved during soft reset 206 * so only program the first time. Do a soft reset immediately after 207 * setting phyif. 208 */ 209 switch (hsotg->params.phy_type) { 210 case DWC2_PHY_TYPE_PARAM_ULPI: 211 /* ULPI interface */ 212 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 213 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 214 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 215 if (hsotg->params.phy_ulpi_ddr) 216 usbcfg |= GUSBCFG_DDRSEL; 217 218 /* Set external VBUS indicator as needed. */ 219 if (hsotg->params.oc_disable) 220 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 221 GUSBCFG_INDICATORPASSTHROUGH); 222 break; 223 case DWC2_PHY_TYPE_PARAM_UTMI: 224 /* UTMI+ interface */ 225 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 226 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 227 if (hsotg->params.phy_utmi_width == 16) 228 usbcfg |= GUSBCFG_PHYIF16; 229 break; 230 default: 231 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 232 break; 233 } 234 235 if (usbcfg != usbcfg_old) { 236 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 237 238 /* Reset after setting the PHY parameters */ 239 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 240 if (retval) { 241 dev_err(hsotg->dev, 242 "%s: Reset failed, aborting", __func__); 243 return retval; 244 } 245 } 246 247 return retval; 248 } 249 250 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 251 { 252 u32 usbcfg; 253 int retval = 0; 254 255 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 256 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 257 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 258 /* If FS/LS mode with FS/LS PHY */ 259 retval = dwc2_fs_phy_init(hsotg, select_phy); 260 if (retval) 261 return retval; 262 } else { 263 /* High speed PHY */ 264 retval = dwc2_hs_phy_init(hsotg, select_phy); 265 if (retval) 266 return retval; 267 } 268 269 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 270 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 271 hsotg->params.ulpi_fs_ls) { 272 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 273 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 274 usbcfg |= GUSBCFG_ULPI_FS_LS; 275 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 276 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 277 } else { 278 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 279 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 280 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 281 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 282 } 283 284 return retval; 285 } 286 287 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 288 { 289 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 290 291 switch (hsotg->hw_params.arch) { 292 case GHWCFG2_EXT_DMA_ARCH: 293 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 294 return -EINVAL; 295 296 case GHWCFG2_INT_DMA_ARCH: 297 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 298 if (hsotg->params.ahbcfg != -1) { 299 ahbcfg &= GAHBCFG_CTRL_MASK; 300 ahbcfg |= hsotg->params.ahbcfg & 301 ~GAHBCFG_CTRL_MASK; 302 } 303 break; 304 305 case GHWCFG2_SLAVE_ONLY_ARCH: 306 default: 307 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 308 break; 309 } 310 311 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n", 312 hsotg->params.host_dma, 313 hsotg->params.dma_desc_enable); 314 315 if (hsotg->params.host_dma) { 316 if (hsotg->params.dma_desc_enable) 317 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n"); 318 else 319 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n"); 320 } else { 321 dev_dbg(hsotg->dev, "Using Slave mode\n"); 322 hsotg->params.dma_desc_enable = false; 323 } 324 325 if (hsotg->params.host_dma) 326 ahbcfg |= GAHBCFG_DMA_EN; 327 328 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 329 330 return 0; 331 } 332 333 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 334 { 335 u32 usbcfg; 336 337 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 338 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 339 340 switch (hsotg->hw_params.op_mode) { 341 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 342 if (hsotg->params.otg_cap == 343 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 344 usbcfg |= GUSBCFG_HNPCAP; 345 if (hsotg->params.otg_cap != 346 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 347 usbcfg |= GUSBCFG_SRPCAP; 348 break; 349 350 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 351 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 352 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 353 if (hsotg->params.otg_cap != 354 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 355 usbcfg |= GUSBCFG_SRPCAP; 356 break; 357 358 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 359 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 360 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 361 default: 362 break; 363 } 364 365 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 366 } 367 368 /** 369 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 370 * 371 * @hsotg: Programming view of DWC_otg controller 372 */ 373 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 374 { 375 u32 intmsk; 376 377 dev_dbg(hsotg->dev, "%s()\n", __func__); 378 379 /* Disable all interrupts */ 380 dwc2_writel(0, hsotg->regs + GINTMSK); 381 dwc2_writel(0, hsotg->regs + HAINTMSK); 382 383 /* Enable the common interrupts */ 384 dwc2_enable_common_interrupts(hsotg); 385 386 /* Enable host mode interrupts without disturbing common interrupts */ 387 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 388 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 389 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 390 } 391 392 /** 393 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 394 * 395 * @hsotg: Programming view of DWC_otg controller 396 */ 397 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 398 { 399 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 400 401 /* Disable host mode interrupts without disturbing common interrupts */ 402 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 403 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 404 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 405 } 406 407 /* 408 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 409 * For system that have a total fifo depth that is smaller than the default 410 * RX + TX fifo size. 411 * 412 * @hsotg: Programming view of DWC_otg controller 413 */ 414 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 415 { 416 struct dwc2_core_params *params = &hsotg->params; 417 struct dwc2_hw_params *hw = &hsotg->hw_params; 418 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 419 420 total_fifo_size = hw->total_fifo_size; 421 rxfsiz = params->host_rx_fifo_size; 422 nptxfsiz = params->host_nperio_tx_fifo_size; 423 ptxfsiz = params->host_perio_tx_fifo_size; 424 425 /* 426 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 427 * allocation with support for high bandwidth endpoints. Synopsys 428 * defines MPS(Max Packet size) for a periodic EP=1024, and for 429 * non-periodic as 512. 430 */ 431 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 432 /* 433 * For Buffer DMA mode/Scatter Gather DMA mode 434 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 435 * with n = number of host channel. 436 * 2 * ((1024/4) + 2) = 516 437 */ 438 rxfsiz = 516 + hw->host_channels; 439 440 /* 441 * min non-periodic tx fifo depth 442 * 2 * (largest non-periodic USB packet used / 4) 443 * 2 * (512/4) = 256 444 */ 445 nptxfsiz = 256; 446 447 /* 448 * min periodic tx fifo depth 449 * (largest packet size*MC)/4 450 * (1024 * 3)/4 = 768 451 */ 452 ptxfsiz = 768; 453 454 params->host_rx_fifo_size = rxfsiz; 455 params->host_nperio_tx_fifo_size = nptxfsiz; 456 params->host_perio_tx_fifo_size = ptxfsiz; 457 } 458 459 /* 460 * If the summation of RX, NPTX and PTX fifo sizes is still 461 * bigger than the total_fifo_size, then we have a problem. 462 * 463 * We won't be able to allocate as many endpoints. Right now, 464 * we're just printing an error message, but ideally this FIFO 465 * allocation algorithm would be improved in the future. 466 * 467 * FIXME improve this FIFO allocation algorithm. 468 */ 469 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 470 dev_err(hsotg->dev, "invalid fifo sizes\n"); 471 } 472 473 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 474 { 475 struct dwc2_core_params *params = &hsotg->params; 476 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 477 478 if (!params->enable_dynamic_fifo) 479 return; 480 481 dwc2_calculate_dynamic_fifo(hsotg); 482 483 /* Rx FIFO */ 484 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 485 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 486 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 487 grxfsiz |= params->host_rx_fifo_size << 488 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 489 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 490 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 491 dwc2_readl(hsotg->regs + GRXFSIZ)); 492 493 /* Non-periodic Tx FIFO */ 494 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 495 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 496 nptxfsiz = params->host_nperio_tx_fifo_size << 497 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 498 nptxfsiz |= params->host_rx_fifo_size << 499 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 500 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 501 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 502 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 503 504 /* Periodic Tx FIFO */ 505 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 506 dwc2_readl(hsotg->regs + HPTXFSIZ)); 507 hptxfsiz = params->host_perio_tx_fifo_size << 508 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 509 hptxfsiz |= (params->host_rx_fifo_size + 510 params->host_nperio_tx_fifo_size) << 511 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 512 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 513 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 514 dwc2_readl(hsotg->regs + HPTXFSIZ)); 515 516 if (hsotg->params.en_multiple_tx_fifo && 517 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 518 /* 519 * This feature was implemented in 2.91a version 520 * Global DFIFOCFG calculation for Host mode - 521 * include RxFIFO, NPTXFIFO and HPTXFIFO 522 */ 523 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 524 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 525 dfifocfg |= (params->host_rx_fifo_size + 526 params->host_nperio_tx_fifo_size + 527 params->host_perio_tx_fifo_size) << 528 GDFIFOCFG_EPINFOBASE_SHIFT & 529 GDFIFOCFG_EPINFOBASE_MASK; 530 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 531 } 532 } 533 534 /** 535 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 536 * the HFIR register according to PHY type and speed 537 * 538 * @hsotg: Programming view of DWC_otg controller 539 * 540 * NOTE: The caller can modify the value of the HFIR register only after the 541 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 542 * has been set 543 */ 544 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 545 { 546 u32 usbcfg; 547 u32 hprt0; 548 int clock = 60; /* default value */ 549 550 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 551 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 552 553 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 554 !(usbcfg & GUSBCFG_PHYIF16)) 555 clock = 60; 556 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 557 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 558 clock = 48; 559 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 560 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 561 clock = 30; 562 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 563 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 564 clock = 60; 565 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 566 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 567 clock = 48; 568 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 569 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 570 clock = 48; 571 if ((usbcfg & GUSBCFG_PHYSEL) && 572 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 573 clock = 48; 574 575 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 576 /* High speed case */ 577 return 125 * clock - 1; 578 579 /* FS/LS case */ 580 return 1000 * clock - 1; 581 } 582 583 /** 584 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 585 * buffer 586 * 587 * @core_if: Programming view of DWC_otg controller 588 * @dest: Destination buffer for the packet 589 * @bytes: Number of bytes to copy to the destination 590 */ 591 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 592 { 593 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 594 u32 *data_buf = (u32 *)dest; 595 int word_count = (bytes + 3) / 4; 596 int i; 597 598 /* 599 * Todo: Account for the case where dest is not dword aligned. This 600 * requires reading data from the FIFO into a u32 temp buffer, then 601 * moving it into the data buffer. 602 */ 603 604 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 605 606 for (i = 0; i < word_count; i++, data_buf++) 607 *data_buf = dwc2_readl(fifo); 608 } 609 610 /** 611 * dwc2_dump_channel_info() - Prints the state of a host channel 612 * 613 * @hsotg: Programming view of DWC_otg controller 614 * @chan: Pointer to the channel to dump 615 * 616 * Must be called with interrupt disabled and spinlock held 617 * 618 * NOTE: This function will be removed once the peripheral controller code 619 * is integrated and the driver is stable 620 */ 621 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 622 struct dwc2_host_chan *chan) 623 { 624 #ifdef VERBOSE_DEBUG 625 int num_channels = hsotg->params.host_channels; 626 struct dwc2_qh *qh; 627 u32 hcchar; 628 u32 hcsplt; 629 u32 hctsiz; 630 u32 hc_dma; 631 int i; 632 633 if (!chan) 634 return; 635 636 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 637 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 638 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 639 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 640 641 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 642 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 643 hcchar, hcsplt); 644 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 645 hctsiz, hc_dma); 646 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 647 chan->dev_addr, chan->ep_num, chan->ep_is_in); 648 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 649 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 650 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 651 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 652 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 653 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 654 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 655 (unsigned long)chan->xfer_dma); 656 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 657 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 658 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 659 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 660 qh_list_entry) 661 dev_dbg(hsotg->dev, " %p\n", qh); 662 dev_dbg(hsotg->dev, " NP active sched:\n"); 663 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 664 qh_list_entry) 665 dev_dbg(hsotg->dev, " %p\n", qh); 666 dev_dbg(hsotg->dev, " Channels:\n"); 667 for (i = 0; i < num_channels; i++) { 668 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 669 670 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 671 } 672 #endif /* VERBOSE_DEBUG */ 673 } 674 675 static int _dwc2_hcd_start(struct usb_hcd *hcd); 676 677 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 678 { 679 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 680 681 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 682 _dwc2_hcd_start(hcd); 683 } 684 685 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 686 { 687 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 688 689 hcd->self.is_b_host = 0; 690 } 691 692 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 693 int *hub_addr, int *hub_port) 694 { 695 struct urb *urb = context; 696 697 if (urb->dev->tt) 698 *hub_addr = urb->dev->tt->hub->devnum; 699 else 700 *hub_addr = 0; 701 *hub_port = urb->dev->ttport; 702 } 703 704 /* 705 * ========================================================================= 706 * Low Level Host Channel Access Functions 707 * ========================================================================= 708 */ 709 710 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 711 struct dwc2_host_chan *chan) 712 { 713 u32 hcintmsk = HCINTMSK_CHHLTD; 714 715 switch (chan->ep_type) { 716 case USB_ENDPOINT_XFER_CONTROL: 717 case USB_ENDPOINT_XFER_BULK: 718 dev_vdbg(hsotg->dev, "control/bulk\n"); 719 hcintmsk |= HCINTMSK_XFERCOMPL; 720 hcintmsk |= HCINTMSK_STALL; 721 hcintmsk |= HCINTMSK_XACTERR; 722 hcintmsk |= HCINTMSK_DATATGLERR; 723 if (chan->ep_is_in) { 724 hcintmsk |= HCINTMSK_BBLERR; 725 } else { 726 hcintmsk |= HCINTMSK_NAK; 727 hcintmsk |= HCINTMSK_NYET; 728 if (chan->do_ping) 729 hcintmsk |= HCINTMSK_ACK; 730 } 731 732 if (chan->do_split) { 733 hcintmsk |= HCINTMSK_NAK; 734 if (chan->complete_split) 735 hcintmsk |= HCINTMSK_NYET; 736 else 737 hcintmsk |= HCINTMSK_ACK; 738 } 739 740 if (chan->error_state) 741 hcintmsk |= HCINTMSK_ACK; 742 break; 743 744 case USB_ENDPOINT_XFER_INT: 745 if (dbg_perio()) 746 dev_vdbg(hsotg->dev, "intr\n"); 747 hcintmsk |= HCINTMSK_XFERCOMPL; 748 hcintmsk |= HCINTMSK_NAK; 749 hcintmsk |= HCINTMSK_STALL; 750 hcintmsk |= HCINTMSK_XACTERR; 751 hcintmsk |= HCINTMSK_DATATGLERR; 752 hcintmsk |= HCINTMSK_FRMOVRUN; 753 754 if (chan->ep_is_in) 755 hcintmsk |= HCINTMSK_BBLERR; 756 if (chan->error_state) 757 hcintmsk |= HCINTMSK_ACK; 758 if (chan->do_split) { 759 if (chan->complete_split) 760 hcintmsk |= HCINTMSK_NYET; 761 else 762 hcintmsk |= HCINTMSK_ACK; 763 } 764 break; 765 766 case USB_ENDPOINT_XFER_ISOC: 767 if (dbg_perio()) 768 dev_vdbg(hsotg->dev, "isoc\n"); 769 hcintmsk |= HCINTMSK_XFERCOMPL; 770 hcintmsk |= HCINTMSK_FRMOVRUN; 771 hcintmsk |= HCINTMSK_ACK; 772 773 if (chan->ep_is_in) { 774 hcintmsk |= HCINTMSK_XACTERR; 775 hcintmsk |= HCINTMSK_BBLERR; 776 } 777 break; 778 default: 779 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 780 break; 781 } 782 783 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 784 if (dbg_hc(chan)) 785 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 786 } 787 788 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 789 struct dwc2_host_chan *chan) 790 { 791 u32 hcintmsk = HCINTMSK_CHHLTD; 792 793 /* 794 * For Descriptor DMA mode core halts the channel on AHB error. 795 * Interrupt is not required. 796 */ 797 if (!hsotg->params.dma_desc_enable) { 798 if (dbg_hc(chan)) 799 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 800 hcintmsk |= HCINTMSK_AHBERR; 801 } else { 802 if (dbg_hc(chan)) 803 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 804 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 805 hcintmsk |= HCINTMSK_XFERCOMPL; 806 } 807 808 if (chan->error_state && !chan->do_split && 809 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 810 if (dbg_hc(chan)) 811 dev_vdbg(hsotg->dev, "setting ACK\n"); 812 hcintmsk |= HCINTMSK_ACK; 813 if (chan->ep_is_in) { 814 hcintmsk |= HCINTMSK_DATATGLERR; 815 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 816 hcintmsk |= HCINTMSK_NAK; 817 } 818 } 819 820 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 821 if (dbg_hc(chan)) 822 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 823 } 824 825 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 826 struct dwc2_host_chan *chan) 827 { 828 u32 intmsk; 829 830 if (hsotg->params.host_dma) { 831 if (dbg_hc(chan)) 832 dev_vdbg(hsotg->dev, "DMA enabled\n"); 833 dwc2_hc_enable_dma_ints(hsotg, chan); 834 } else { 835 if (dbg_hc(chan)) 836 dev_vdbg(hsotg->dev, "DMA disabled\n"); 837 dwc2_hc_enable_slave_ints(hsotg, chan); 838 } 839 840 /* Enable the top level host channel interrupt */ 841 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 842 intmsk |= 1 << chan->hc_num; 843 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 844 if (dbg_hc(chan)) 845 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 846 847 /* Make sure host channel interrupts are enabled */ 848 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 849 intmsk |= GINTSTS_HCHINT; 850 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 851 if (dbg_hc(chan)) 852 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 853 } 854 855 /** 856 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 857 * a specific endpoint 858 * 859 * @hsotg: Programming view of DWC_otg controller 860 * @chan: Information needed to initialize the host channel 861 * 862 * The HCCHARn register is set up with the characteristics specified in chan. 863 * Host channel interrupts that may need to be serviced while this transfer is 864 * in progress are enabled. 865 */ 866 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 867 { 868 u8 hc_num = chan->hc_num; 869 u32 hcintmsk; 870 u32 hcchar; 871 u32 hcsplt = 0; 872 873 if (dbg_hc(chan)) 874 dev_vdbg(hsotg->dev, "%s()\n", __func__); 875 876 /* Clear old interrupt conditions for this host channel */ 877 hcintmsk = 0xffffffff; 878 hcintmsk &= ~HCINTMSK_RESERVED14_31; 879 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 880 881 /* Enable channel interrupts required for this transfer */ 882 dwc2_hc_enable_ints(hsotg, chan); 883 884 /* 885 * Program the HCCHARn register with the endpoint characteristics for 886 * the current transfer 887 */ 888 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 889 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 890 if (chan->ep_is_in) 891 hcchar |= HCCHAR_EPDIR; 892 if (chan->speed == USB_SPEED_LOW) 893 hcchar |= HCCHAR_LSPDDEV; 894 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 895 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 896 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 897 if (dbg_hc(chan)) { 898 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 899 hc_num, hcchar); 900 901 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 902 __func__, hc_num); 903 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 904 chan->dev_addr); 905 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 906 chan->ep_num); 907 dev_vdbg(hsotg->dev, " Is In: %d\n", 908 chan->ep_is_in); 909 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 910 chan->speed == USB_SPEED_LOW); 911 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 912 chan->ep_type); 913 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 914 chan->max_packet); 915 } 916 917 /* Program the HCSPLT register for SPLITs */ 918 if (chan->do_split) { 919 if (dbg_hc(chan)) 920 dev_vdbg(hsotg->dev, 921 "Programming HC %d with split --> %s\n", 922 hc_num, 923 chan->complete_split ? "CSPLIT" : "SSPLIT"); 924 if (chan->complete_split) 925 hcsplt |= HCSPLT_COMPSPLT; 926 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 927 HCSPLT_XACTPOS_MASK; 928 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 929 HCSPLT_HUBADDR_MASK; 930 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 931 HCSPLT_PRTADDR_MASK; 932 if (dbg_hc(chan)) { 933 dev_vdbg(hsotg->dev, " comp split %d\n", 934 chan->complete_split); 935 dev_vdbg(hsotg->dev, " xact pos %d\n", 936 chan->xact_pos); 937 dev_vdbg(hsotg->dev, " hub addr %d\n", 938 chan->hub_addr); 939 dev_vdbg(hsotg->dev, " hub port %d\n", 940 chan->hub_port); 941 dev_vdbg(hsotg->dev, " is_in %d\n", 942 chan->ep_is_in); 943 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 944 chan->max_packet); 945 dev_vdbg(hsotg->dev, " xferlen %d\n", 946 chan->xfer_len); 947 } 948 } 949 950 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 951 } 952 953 /** 954 * dwc2_hc_halt() - Attempts to halt a host channel 955 * 956 * @hsotg: Controller register interface 957 * @chan: Host channel to halt 958 * @halt_status: Reason for halting the channel 959 * 960 * This function should only be called in Slave mode or to abort a transfer in 961 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 962 * controller halts the channel when the transfer is complete or a condition 963 * occurs that requires application intervention. 964 * 965 * In slave mode, checks for a free request queue entry, then sets the Channel 966 * Enable and Channel Disable bits of the Host Channel Characteristics 967 * register of the specified channel to intiate the halt. If there is no free 968 * request queue entry, sets only the Channel Disable bit of the HCCHARn 969 * register to flush requests for this channel. In the latter case, sets a 970 * flag to indicate that the host channel needs to be halted when a request 971 * queue slot is open. 972 * 973 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 974 * HCCHARn register. The controller ensures there is space in the request 975 * queue before submitting the halt request. 976 * 977 * Some time may elapse before the core flushes any posted requests for this 978 * host channel and halts. The Channel Halted interrupt handler completes the 979 * deactivation of the host channel. 980 */ 981 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 982 enum dwc2_halt_status halt_status) 983 { 984 u32 nptxsts, hptxsts, hcchar; 985 986 if (dbg_hc(chan)) 987 dev_vdbg(hsotg->dev, "%s()\n", __func__); 988 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 989 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 990 991 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 992 halt_status == DWC2_HC_XFER_AHB_ERR) { 993 /* 994 * Disable all channel interrupts except Ch Halted. The QTD 995 * and QH state associated with this transfer has been cleared 996 * (in the case of URB_DEQUEUE), so the channel needs to be 997 * shut down carefully to prevent crashes. 998 */ 999 u32 hcintmsk = HCINTMSK_CHHLTD; 1000 1001 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1002 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1003 1004 /* 1005 * Make sure no other interrupts besides halt are currently 1006 * pending. Handling another interrupt could cause a crash due 1007 * to the QTD and QH state. 1008 */ 1009 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1010 1011 /* 1012 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1013 * even if the channel was already halted for some other 1014 * reason 1015 */ 1016 chan->halt_status = halt_status; 1017 1018 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1019 if (!(hcchar & HCCHAR_CHENA)) { 1020 /* 1021 * The channel is either already halted or it hasn't 1022 * started yet. In DMA mode, the transfer may halt if 1023 * it finishes normally or a condition occurs that 1024 * requires driver intervention. Don't want to halt 1025 * the channel again. In either Slave or DMA mode, 1026 * it's possible that the transfer has been assigned 1027 * to a channel, but not started yet when an URB is 1028 * dequeued. Don't want to halt a channel that hasn't 1029 * started yet. 1030 */ 1031 return; 1032 } 1033 } 1034 if (chan->halt_pending) { 1035 /* 1036 * A halt has already been issued for this channel. This might 1037 * happen when a transfer is aborted by a higher level in 1038 * the stack. 1039 */ 1040 dev_vdbg(hsotg->dev, 1041 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1042 __func__, chan->hc_num); 1043 return; 1044 } 1045 1046 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1047 1048 /* No need to set the bit in DDMA for disabling the channel */ 1049 /* TODO check it everywhere channel is disabled */ 1050 if (!hsotg->params.dma_desc_enable) { 1051 if (dbg_hc(chan)) 1052 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1053 hcchar |= HCCHAR_CHENA; 1054 } else { 1055 if (dbg_hc(chan)) 1056 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1057 } 1058 hcchar |= HCCHAR_CHDIS; 1059 1060 if (!hsotg->params.host_dma) { 1061 if (dbg_hc(chan)) 1062 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1063 hcchar |= HCCHAR_CHENA; 1064 1065 /* Check for space in the request queue to issue the halt */ 1066 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1067 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1068 dev_vdbg(hsotg->dev, "control/bulk\n"); 1069 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1070 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1071 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1072 hcchar &= ~HCCHAR_CHENA; 1073 } 1074 } else { 1075 if (dbg_perio()) 1076 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1077 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1078 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1079 hsotg->queuing_high_bandwidth) { 1080 if (dbg_perio()) 1081 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1082 hcchar &= ~HCCHAR_CHENA; 1083 } 1084 } 1085 } else { 1086 if (dbg_hc(chan)) 1087 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1088 } 1089 1090 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1091 chan->halt_status = halt_status; 1092 1093 if (hcchar & HCCHAR_CHENA) { 1094 if (dbg_hc(chan)) 1095 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1096 chan->halt_pending = 1; 1097 chan->halt_on_queue = 0; 1098 } else { 1099 if (dbg_hc(chan)) 1100 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1101 chan->halt_on_queue = 1; 1102 } 1103 1104 if (dbg_hc(chan)) { 1105 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1106 chan->hc_num); 1107 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1108 hcchar); 1109 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1110 chan->halt_pending); 1111 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1112 chan->halt_on_queue); 1113 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1114 chan->halt_status); 1115 } 1116 } 1117 1118 /** 1119 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1120 * 1121 * @hsotg: Programming view of DWC_otg controller 1122 * @chan: Identifies the host channel to clean up 1123 * 1124 * This function is normally called after a transfer is done and the host 1125 * channel is being released 1126 */ 1127 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1128 { 1129 u32 hcintmsk; 1130 1131 chan->xfer_started = 0; 1132 1133 list_del_init(&chan->split_order_list_entry); 1134 1135 /* 1136 * Clear channel interrupt enables and any unhandled channel interrupt 1137 * conditions 1138 */ 1139 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1140 hcintmsk = 0xffffffff; 1141 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1142 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1143 } 1144 1145 /** 1146 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1147 * which frame a periodic transfer should occur 1148 * 1149 * @hsotg: Programming view of DWC_otg controller 1150 * @chan: Identifies the host channel to set up and its properties 1151 * @hcchar: Current value of the HCCHAR register for the specified host channel 1152 * 1153 * This function has no effect on non-periodic transfers 1154 */ 1155 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1156 struct dwc2_host_chan *chan, u32 *hcchar) 1157 { 1158 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1159 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1160 int host_speed; 1161 int xfer_ns; 1162 int xfer_us; 1163 int bytes_in_fifo; 1164 u16 fifo_space; 1165 u16 frame_number; 1166 u16 wire_frame; 1167 1168 /* 1169 * Try to figure out if we're an even or odd frame. If we set 1170 * even and the current frame number is even the the transfer 1171 * will happen immediately. Similar if both are odd. If one is 1172 * even and the other is odd then the transfer will happen when 1173 * the frame number ticks. 1174 * 1175 * There's a bit of a balancing act to get this right. 1176 * Sometimes we may want to send data in the current frame (AK 1177 * right away). We might want to do this if the frame number 1178 * _just_ ticked, but we might also want to do this in order 1179 * to continue a split transaction that happened late in a 1180 * microframe (so we didn't know to queue the next transfer 1181 * until the frame number had ticked). The problem is that we 1182 * need a lot of knowledge to know if there's actually still 1183 * time to send things or if it would be better to wait until 1184 * the next frame. 1185 * 1186 * We can look at how much time is left in the current frame 1187 * and make a guess about whether we'll have time to transfer. 1188 * We'll do that. 1189 */ 1190 1191 /* Get speed host is running at */ 1192 host_speed = (chan->speed != USB_SPEED_HIGH && 1193 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1194 1195 /* See how many bytes are in the periodic FIFO right now */ 1196 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1197 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1198 bytes_in_fifo = sizeof(u32) * 1199 (hsotg->params.host_perio_tx_fifo_size - 1200 fifo_space); 1201 1202 /* 1203 * Roughly estimate bus time for everything in the periodic 1204 * queue + our new transfer. This is "rough" because we're 1205 * using a function that makes takes into account IN/OUT 1206 * and INT/ISO and we're just slamming in one value for all 1207 * transfers. This should be an over-estimate and that should 1208 * be OK, but we can probably tighten it. 1209 */ 1210 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1211 chan->xfer_len + bytes_in_fifo); 1212 xfer_us = NS_TO_US(xfer_ns); 1213 1214 /* See what frame number we'll be at by the time we finish */ 1215 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1216 1217 /* This is when we were scheduled to be on the wire */ 1218 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1219 1220 /* 1221 * If we'd finish _after_ the frame we're scheduled in then 1222 * it's hopeless. Just schedule right away and hope for the 1223 * best. Note that it _might_ be wise to call back into the 1224 * scheduler to pick a better frame, but this is better than 1225 * nothing. 1226 */ 1227 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1228 dwc2_sch_vdbg(hsotg, 1229 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1230 chan->qh, wire_frame, frame_number, 1231 dwc2_frame_num_dec(frame_number, 1232 wire_frame)); 1233 wire_frame = frame_number; 1234 1235 /* 1236 * We picked a different frame number; communicate this 1237 * back to the scheduler so it doesn't try to schedule 1238 * another in the same frame. 1239 * 1240 * Remember that next_active_frame is 1 before the wire 1241 * frame. 1242 */ 1243 chan->qh->next_active_frame = 1244 dwc2_frame_num_dec(frame_number, 1); 1245 } 1246 1247 if (wire_frame & 1) 1248 *hcchar |= HCCHAR_ODDFRM; 1249 else 1250 *hcchar &= ~HCCHAR_ODDFRM; 1251 } 1252 } 1253 1254 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1255 { 1256 /* Set up the initial PID for the transfer */ 1257 if (chan->speed == USB_SPEED_HIGH) { 1258 if (chan->ep_is_in) { 1259 if (chan->multi_count == 1) 1260 chan->data_pid_start = DWC2_HC_PID_DATA0; 1261 else if (chan->multi_count == 2) 1262 chan->data_pid_start = DWC2_HC_PID_DATA1; 1263 else 1264 chan->data_pid_start = DWC2_HC_PID_DATA2; 1265 } else { 1266 if (chan->multi_count == 1) 1267 chan->data_pid_start = DWC2_HC_PID_DATA0; 1268 else 1269 chan->data_pid_start = DWC2_HC_PID_MDATA; 1270 } 1271 } else { 1272 chan->data_pid_start = DWC2_HC_PID_DATA0; 1273 } 1274 } 1275 1276 /** 1277 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1278 * the Host Channel 1279 * 1280 * @hsotg: Programming view of DWC_otg controller 1281 * @chan: Information needed to initialize the host channel 1282 * 1283 * This function should only be called in Slave mode. For a channel associated 1284 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1285 * associated with a periodic EP, the periodic Tx FIFO is written. 1286 * 1287 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1288 * the number of bytes written to the Tx FIFO. 1289 */ 1290 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1291 struct dwc2_host_chan *chan) 1292 { 1293 u32 i; 1294 u32 remaining_count; 1295 u32 byte_count; 1296 u32 dword_count; 1297 u32 __iomem *data_fifo; 1298 u32 *data_buf = (u32 *)chan->xfer_buf; 1299 1300 if (dbg_hc(chan)) 1301 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1302 1303 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1304 1305 remaining_count = chan->xfer_len - chan->xfer_count; 1306 if (remaining_count > chan->max_packet) 1307 byte_count = chan->max_packet; 1308 else 1309 byte_count = remaining_count; 1310 1311 dword_count = (byte_count + 3) / 4; 1312 1313 if (((unsigned long)data_buf & 0x3) == 0) { 1314 /* xfer_buf is DWORD aligned */ 1315 for (i = 0; i < dword_count; i++, data_buf++) 1316 dwc2_writel(*data_buf, data_fifo); 1317 } else { 1318 /* xfer_buf is not DWORD aligned */ 1319 for (i = 0; i < dword_count; i++, data_buf++) { 1320 u32 data = data_buf[0] | data_buf[1] << 8 | 1321 data_buf[2] << 16 | data_buf[3] << 24; 1322 dwc2_writel(data, data_fifo); 1323 } 1324 } 1325 1326 chan->xfer_count += byte_count; 1327 chan->xfer_buf += byte_count; 1328 } 1329 1330 /** 1331 * dwc2_hc_do_ping() - Starts a PING transfer 1332 * 1333 * @hsotg: Programming view of DWC_otg controller 1334 * @chan: Information needed to initialize the host channel 1335 * 1336 * This function should only be called in Slave mode. The Do Ping bit is set in 1337 * the HCTSIZ register, then the channel is enabled. 1338 */ 1339 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1340 struct dwc2_host_chan *chan) 1341 { 1342 u32 hcchar; 1343 u32 hctsiz; 1344 1345 if (dbg_hc(chan)) 1346 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1347 chan->hc_num); 1348 1349 hctsiz = TSIZ_DOPNG; 1350 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1351 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1352 1353 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1354 hcchar |= HCCHAR_CHENA; 1355 hcchar &= ~HCCHAR_CHDIS; 1356 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1357 } 1358 1359 /** 1360 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1361 * channel and starts the transfer 1362 * 1363 * @hsotg: Programming view of DWC_otg controller 1364 * @chan: Information needed to initialize the host channel. The xfer_len value 1365 * may be reduced to accommodate the max widths of the XferSize and 1366 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1367 * changed to reflect the final xfer_len value. 1368 * 1369 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1370 * the caller must ensure that there is sufficient space in the request queue 1371 * and Tx Data FIFO. 1372 * 1373 * For an OUT transfer in Slave mode, it loads a data packet into the 1374 * appropriate FIFO. If necessary, additional data packets are loaded in the 1375 * Host ISR. 1376 * 1377 * For an IN transfer in Slave mode, a data packet is requested. The data 1378 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1379 * additional data packets are requested in the Host ISR. 1380 * 1381 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1382 * register along with a packet count of 1 and the channel is enabled. This 1383 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1384 * simply set to 0 since no data transfer occurs in this case. 1385 * 1386 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1387 * all the information required to perform the subsequent data transfer. In 1388 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1389 * controller performs the entire PING protocol, then starts the data 1390 * transfer. 1391 */ 1392 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1393 struct dwc2_host_chan *chan) 1394 { 1395 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1396 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1397 u32 hcchar; 1398 u32 hctsiz = 0; 1399 u16 num_packets; 1400 u32 ec_mc; 1401 1402 if (dbg_hc(chan)) 1403 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1404 1405 if (chan->do_ping) { 1406 if (!hsotg->params.host_dma) { 1407 if (dbg_hc(chan)) 1408 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1409 dwc2_hc_do_ping(hsotg, chan); 1410 chan->xfer_started = 1; 1411 return; 1412 } 1413 1414 if (dbg_hc(chan)) 1415 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1416 1417 hctsiz |= TSIZ_DOPNG; 1418 } 1419 1420 if (chan->do_split) { 1421 if (dbg_hc(chan)) 1422 dev_vdbg(hsotg->dev, "split\n"); 1423 num_packets = 1; 1424 1425 if (chan->complete_split && !chan->ep_is_in) 1426 /* 1427 * For CSPLIT OUT Transfer, set the size to 0 so the 1428 * core doesn't expect any data written to the FIFO 1429 */ 1430 chan->xfer_len = 0; 1431 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1432 chan->xfer_len = chan->max_packet; 1433 else if (!chan->ep_is_in && chan->xfer_len > 188) 1434 chan->xfer_len = 188; 1435 1436 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1437 TSIZ_XFERSIZE_MASK; 1438 1439 /* For split set ec_mc for immediate retries */ 1440 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1441 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1442 ec_mc = 3; 1443 else 1444 ec_mc = 1; 1445 } else { 1446 if (dbg_hc(chan)) 1447 dev_vdbg(hsotg->dev, "no split\n"); 1448 /* 1449 * Ensure that the transfer length and packet count will fit 1450 * in the widths allocated for them in the HCTSIZn register 1451 */ 1452 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1453 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1454 /* 1455 * Make sure the transfer size is no larger than one 1456 * (micro)frame's worth of data. (A check was done 1457 * when the periodic transfer was accepted to ensure 1458 * that a (micro)frame's worth of data can be 1459 * programmed into a channel.) 1460 */ 1461 u32 max_periodic_len = 1462 chan->multi_count * chan->max_packet; 1463 1464 if (chan->xfer_len > max_periodic_len) 1465 chan->xfer_len = max_periodic_len; 1466 } else if (chan->xfer_len > max_hc_xfer_size) { 1467 /* 1468 * Make sure that xfer_len is a multiple of max packet 1469 * size 1470 */ 1471 chan->xfer_len = 1472 max_hc_xfer_size - chan->max_packet + 1; 1473 } 1474 1475 if (chan->xfer_len > 0) { 1476 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1477 chan->max_packet; 1478 if (num_packets > max_hc_pkt_count) { 1479 num_packets = max_hc_pkt_count; 1480 chan->xfer_len = num_packets * chan->max_packet; 1481 } 1482 } else { 1483 /* Need 1 packet for transfer length of 0 */ 1484 num_packets = 1; 1485 } 1486 1487 if (chan->ep_is_in) 1488 /* 1489 * Always program an integral # of max packets for IN 1490 * transfers 1491 */ 1492 chan->xfer_len = num_packets * chan->max_packet; 1493 1494 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1495 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1496 /* 1497 * Make sure that the multi_count field matches the 1498 * actual transfer length 1499 */ 1500 chan->multi_count = num_packets; 1501 1502 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1503 dwc2_set_pid_isoc(chan); 1504 1505 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1506 TSIZ_XFERSIZE_MASK; 1507 1508 /* The ec_mc gets the multi_count for non-split */ 1509 ec_mc = chan->multi_count; 1510 } 1511 1512 chan->start_pkt_count = num_packets; 1513 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1514 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1515 TSIZ_SC_MC_PID_MASK; 1516 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1517 if (dbg_hc(chan)) { 1518 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1519 hctsiz, chan->hc_num); 1520 1521 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1522 chan->hc_num); 1523 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1524 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1525 TSIZ_XFERSIZE_SHIFT); 1526 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1527 (hctsiz & TSIZ_PKTCNT_MASK) >> 1528 TSIZ_PKTCNT_SHIFT); 1529 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1530 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1531 TSIZ_SC_MC_PID_SHIFT); 1532 } 1533 1534 if (hsotg->params.host_dma) { 1535 dwc2_writel((u32)chan->xfer_dma, 1536 hsotg->regs + HCDMA(chan->hc_num)); 1537 if (dbg_hc(chan)) 1538 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1539 (unsigned long)chan->xfer_dma, chan->hc_num); 1540 } 1541 1542 /* Start the split */ 1543 if (chan->do_split) { 1544 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1545 1546 hcsplt |= HCSPLT_SPLTENA; 1547 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1548 } 1549 1550 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1551 hcchar &= ~HCCHAR_MULTICNT_MASK; 1552 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1553 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1554 1555 if (hcchar & HCCHAR_CHDIS) 1556 dev_warn(hsotg->dev, 1557 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1558 __func__, chan->hc_num, hcchar); 1559 1560 /* Set host channel enable after all other setup is complete */ 1561 hcchar |= HCCHAR_CHENA; 1562 hcchar &= ~HCCHAR_CHDIS; 1563 1564 if (dbg_hc(chan)) 1565 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1566 (hcchar & HCCHAR_MULTICNT_MASK) >> 1567 HCCHAR_MULTICNT_SHIFT); 1568 1569 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1570 if (dbg_hc(chan)) 1571 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1572 chan->hc_num); 1573 1574 chan->xfer_started = 1; 1575 chan->requests++; 1576 1577 if (!hsotg->params.host_dma && 1578 !chan->ep_is_in && chan->xfer_len > 0) 1579 /* Load OUT packet into the appropriate Tx FIFO */ 1580 dwc2_hc_write_packet(hsotg, chan); 1581 } 1582 1583 /** 1584 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1585 * host channel and starts the transfer in Descriptor DMA mode 1586 * 1587 * @hsotg: Programming view of DWC_otg controller 1588 * @chan: Information needed to initialize the host channel 1589 * 1590 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1591 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1592 * with micro-frame bitmap. 1593 * 1594 * Initializes HCDMA register with descriptor list address and CTD value then 1595 * starts the transfer via enabling the channel. 1596 */ 1597 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1598 struct dwc2_host_chan *chan) 1599 { 1600 u32 hcchar; 1601 u32 hctsiz = 0; 1602 1603 if (chan->do_ping) 1604 hctsiz |= TSIZ_DOPNG; 1605 1606 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1607 dwc2_set_pid_isoc(chan); 1608 1609 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1610 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1611 TSIZ_SC_MC_PID_MASK; 1612 1613 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1614 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1615 1616 /* Non-zero only for high-speed interrupt endpoints */ 1617 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1618 1619 if (dbg_hc(chan)) { 1620 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1621 chan->hc_num); 1622 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1623 chan->data_pid_start); 1624 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1625 } 1626 1627 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1628 1629 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1630 chan->desc_list_sz, DMA_TO_DEVICE); 1631 1632 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1633 1634 if (dbg_hc(chan)) 1635 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1636 &chan->desc_list_addr, chan->hc_num); 1637 1638 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1639 hcchar &= ~HCCHAR_MULTICNT_MASK; 1640 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1641 HCCHAR_MULTICNT_MASK; 1642 1643 if (hcchar & HCCHAR_CHDIS) 1644 dev_warn(hsotg->dev, 1645 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1646 __func__, chan->hc_num, hcchar); 1647 1648 /* Set host channel enable after all other setup is complete */ 1649 hcchar |= HCCHAR_CHENA; 1650 hcchar &= ~HCCHAR_CHDIS; 1651 1652 if (dbg_hc(chan)) 1653 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1654 (hcchar & HCCHAR_MULTICNT_MASK) >> 1655 HCCHAR_MULTICNT_SHIFT); 1656 1657 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1658 if (dbg_hc(chan)) 1659 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1660 chan->hc_num); 1661 1662 chan->xfer_started = 1; 1663 chan->requests++; 1664 } 1665 1666 /** 1667 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1668 * a previous call to dwc2_hc_start_transfer() 1669 * 1670 * @hsotg: Programming view of DWC_otg controller 1671 * @chan: Information needed to initialize the host channel 1672 * 1673 * The caller must ensure there is sufficient space in the request queue and Tx 1674 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1675 * the controller acts autonomously to complete transfers programmed to a host 1676 * channel. 1677 * 1678 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1679 * if there is any data remaining to be queued. For an IN transfer, another 1680 * data packet is always requested. For the SETUP phase of a control transfer, 1681 * this function does nothing. 1682 * 1683 * Return: 1 if a new request is queued, 0 if no more requests are required 1684 * for this transfer 1685 */ 1686 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1687 struct dwc2_host_chan *chan) 1688 { 1689 if (dbg_hc(chan)) 1690 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1691 chan->hc_num); 1692 1693 if (chan->do_split) 1694 /* SPLITs always queue just once per channel */ 1695 return 0; 1696 1697 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1698 /* SETUPs are queued only once since they can't be NAK'd */ 1699 return 0; 1700 1701 if (chan->ep_is_in) { 1702 /* 1703 * Always queue another request for other IN transfers. If 1704 * back-to-back INs are issued and NAKs are received for both, 1705 * the driver may still be processing the first NAK when the 1706 * second NAK is received. When the interrupt handler clears 1707 * the NAK interrupt for the first NAK, the second NAK will 1708 * not be seen. So we can't depend on the NAK interrupt 1709 * handler to requeue a NAK'd request. Instead, IN requests 1710 * are issued each time this function is called. When the 1711 * transfer completes, the extra requests for the channel will 1712 * be flushed. 1713 */ 1714 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1715 1716 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1717 hcchar |= HCCHAR_CHENA; 1718 hcchar &= ~HCCHAR_CHDIS; 1719 if (dbg_hc(chan)) 1720 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1721 hcchar); 1722 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1723 chan->requests++; 1724 return 1; 1725 } 1726 1727 /* OUT transfers */ 1728 1729 if (chan->xfer_count < chan->xfer_len) { 1730 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1731 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1732 u32 hcchar = dwc2_readl(hsotg->regs + 1733 HCCHAR(chan->hc_num)); 1734 1735 dwc2_hc_set_even_odd_frame(hsotg, chan, 1736 &hcchar); 1737 } 1738 1739 /* Load OUT packet into the appropriate Tx FIFO */ 1740 dwc2_hc_write_packet(hsotg, chan); 1741 chan->requests++; 1742 return 1; 1743 } 1744 1745 return 0; 1746 } 1747 1748 /* 1749 * ========================================================================= 1750 * HCD 1751 * ========================================================================= 1752 */ 1753 1754 /* 1755 * Processes all the URBs in a single list of QHs. Completes them with 1756 * -ETIMEDOUT and frees the QTD. 1757 * 1758 * Must be called with interrupt disabled and spinlock held 1759 */ 1760 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1761 struct list_head *qh_list) 1762 { 1763 struct dwc2_qh *qh, *qh_tmp; 1764 struct dwc2_qtd *qtd, *qtd_tmp; 1765 1766 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1767 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1768 qtd_list_entry) { 1769 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1770 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1771 } 1772 } 1773 } 1774 1775 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1776 struct list_head *qh_list) 1777 { 1778 struct dwc2_qtd *qtd, *qtd_tmp; 1779 struct dwc2_qh *qh, *qh_tmp; 1780 unsigned long flags; 1781 1782 if (!qh_list->next) 1783 /* The list hasn't been initialized yet */ 1784 return; 1785 1786 spin_lock_irqsave(&hsotg->lock, flags); 1787 1788 /* Ensure there are no QTDs or URBs left */ 1789 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1790 1791 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1792 dwc2_hcd_qh_unlink(hsotg, qh); 1793 1794 /* Free each QTD in the QH's QTD list */ 1795 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1796 qtd_list_entry) 1797 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1798 1799 if (qh->channel && qh->channel->qh == qh) 1800 qh->channel->qh = NULL; 1801 1802 spin_unlock_irqrestore(&hsotg->lock, flags); 1803 dwc2_hcd_qh_free(hsotg, qh); 1804 spin_lock_irqsave(&hsotg->lock, flags); 1805 } 1806 1807 spin_unlock_irqrestore(&hsotg->lock, flags); 1808 } 1809 1810 /* 1811 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1812 * and periodic schedules. The QTD associated with each URB is removed from 1813 * the schedule and freed. This function may be called when a disconnect is 1814 * detected or when the HCD is being stopped. 1815 * 1816 * Must be called with interrupt disabled and spinlock held 1817 */ 1818 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1819 { 1820 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1821 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1822 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1823 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1824 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1825 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1826 } 1827 1828 /** 1829 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1830 * 1831 * @hsotg: Pointer to struct dwc2_hsotg 1832 */ 1833 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1834 { 1835 u32 hprt0; 1836 1837 if (hsotg->op_state == OTG_STATE_B_HOST) { 1838 /* 1839 * Reset the port. During a HNP mode switch the reset 1840 * needs to occur within 1ms and have a duration of at 1841 * least 50ms. 1842 */ 1843 hprt0 = dwc2_read_hprt0(hsotg); 1844 hprt0 |= HPRT0_RST; 1845 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1846 } 1847 1848 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1849 msecs_to_jiffies(50)); 1850 } 1851 1852 /* Must be called with interrupt disabled and spinlock held */ 1853 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1854 { 1855 int num_channels = hsotg->params.host_channels; 1856 struct dwc2_host_chan *channel; 1857 u32 hcchar; 1858 int i; 1859 1860 if (!hsotg->params.host_dma) { 1861 /* Flush out any channel requests in slave mode */ 1862 for (i = 0; i < num_channels; i++) { 1863 channel = hsotg->hc_ptr_array[i]; 1864 if (!list_empty(&channel->hc_list_entry)) 1865 continue; 1866 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1867 if (hcchar & HCCHAR_CHENA) { 1868 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1869 hcchar |= HCCHAR_CHDIS; 1870 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1871 } 1872 } 1873 } 1874 1875 for (i = 0; i < num_channels; i++) { 1876 channel = hsotg->hc_ptr_array[i]; 1877 if (!list_empty(&channel->hc_list_entry)) 1878 continue; 1879 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1880 if (hcchar & HCCHAR_CHENA) { 1881 /* Halt the channel */ 1882 hcchar |= HCCHAR_CHDIS; 1883 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1884 } 1885 1886 dwc2_hc_cleanup(hsotg, channel); 1887 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1888 /* 1889 * Added for Descriptor DMA to prevent channel double cleanup in 1890 * release_channel_ddma(), which is called from ep_disable when 1891 * device disconnects 1892 */ 1893 channel->qh = NULL; 1894 } 1895 /* All channels have been freed, mark them available */ 1896 if (hsotg->params.uframe_sched) { 1897 hsotg->available_host_channels = 1898 hsotg->params.host_channels; 1899 } else { 1900 hsotg->non_periodic_channels = 0; 1901 hsotg->periodic_channels = 0; 1902 } 1903 } 1904 1905 /** 1906 * dwc2_hcd_connect() - Handles connect of the HCD 1907 * 1908 * @hsotg: Pointer to struct dwc2_hsotg 1909 * 1910 * Must be called with interrupt disabled and spinlock held 1911 */ 1912 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1913 { 1914 if (hsotg->lx_state != DWC2_L0) 1915 usb_hcd_resume_root_hub(hsotg->priv); 1916 1917 hsotg->flags.b.port_connect_status_change = 1; 1918 hsotg->flags.b.port_connect_status = 1; 1919 } 1920 1921 /** 1922 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1923 * 1924 * @hsotg: Pointer to struct dwc2_hsotg 1925 * @force: If true, we won't try to reconnect even if we see device connected. 1926 * 1927 * Must be called with interrupt disabled and spinlock held 1928 */ 1929 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1930 { 1931 u32 intr; 1932 u32 hprt0; 1933 1934 /* Set status flags for the hub driver */ 1935 hsotg->flags.b.port_connect_status_change = 1; 1936 hsotg->flags.b.port_connect_status = 0; 1937 1938 /* 1939 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1940 * interrupt mask and status bits and disabling subsequent host 1941 * channel interrupts. 1942 */ 1943 intr = dwc2_readl(hsotg->regs + GINTMSK); 1944 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1945 dwc2_writel(intr, hsotg->regs + GINTMSK); 1946 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1947 dwc2_writel(intr, hsotg->regs + GINTSTS); 1948 1949 /* 1950 * Turn off the vbus power only if the core has transitioned to device 1951 * mode. If still in host mode, need to keep power on to detect a 1952 * reconnection. 1953 */ 1954 if (dwc2_is_device_mode(hsotg)) { 1955 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1956 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1957 dwc2_writel(0, hsotg->regs + HPRT0); 1958 } 1959 1960 dwc2_disable_host_interrupts(hsotg); 1961 } 1962 1963 /* Respond with an error status to all URBs in the schedule */ 1964 dwc2_kill_all_urbs(hsotg); 1965 1966 if (dwc2_is_host_mode(hsotg)) 1967 /* Clean up any host channels that were in use */ 1968 dwc2_hcd_cleanup_channels(hsotg); 1969 1970 dwc2_host_disconnect(hsotg); 1971 1972 /* 1973 * Add an extra check here to see if we're actually connected but 1974 * we don't have a detection interrupt pending. This can happen if: 1975 * 1. hardware sees connect 1976 * 2. hardware sees disconnect 1977 * 3. hardware sees connect 1978 * 4. dwc2_port_intr() - clears connect interrupt 1979 * 5. dwc2_handle_common_intr() - calls here 1980 * 1981 * Without the extra check here we will end calling disconnect 1982 * and won't get any future interrupts to handle the connect. 1983 */ 1984 if (!force) { 1985 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1986 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 1987 dwc2_hcd_connect(hsotg); 1988 } 1989 } 1990 1991 /** 1992 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 1993 * 1994 * @hsotg: Pointer to struct dwc2_hsotg 1995 */ 1996 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 1997 { 1998 if (hsotg->bus_suspended) { 1999 hsotg->flags.b.port_suspend_change = 1; 2000 usb_hcd_resume_root_hub(hsotg->priv); 2001 } 2002 2003 if (hsotg->lx_state == DWC2_L1) 2004 hsotg->flags.b.port_l1_change = 1; 2005 } 2006 2007 /** 2008 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 2009 * 2010 * @hsotg: Pointer to struct dwc2_hsotg 2011 * 2012 * Must be called with interrupt disabled and spinlock held 2013 */ 2014 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 2015 { 2016 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 2017 2018 /* 2019 * The root hub should be disconnected before this function is called. 2020 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2021 * and the QH lists (via ..._hcd_endpoint_disable). 2022 */ 2023 2024 /* Turn off all host-specific interrupts */ 2025 dwc2_disable_host_interrupts(hsotg); 2026 2027 /* Turn off the vbus power */ 2028 dev_dbg(hsotg->dev, "PortPower off\n"); 2029 dwc2_writel(0, hsotg->regs + HPRT0); 2030 } 2031 2032 /* Caller must hold driver lock */ 2033 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2034 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2035 struct dwc2_qtd *qtd) 2036 { 2037 u32 intr_mask; 2038 int retval; 2039 int dev_speed; 2040 2041 if (!hsotg->flags.b.port_connect_status) { 2042 /* No longer connected */ 2043 dev_err(hsotg->dev, "Not connected\n"); 2044 return -ENODEV; 2045 } 2046 2047 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2048 2049 /* Some configurations cannot support LS traffic on a FS root port */ 2050 if ((dev_speed == USB_SPEED_LOW) && 2051 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2052 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2053 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2054 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2055 2056 if (prtspd == HPRT0_SPD_FULL_SPEED) 2057 return -ENODEV; 2058 } 2059 2060 if (!qtd) 2061 return -EINVAL; 2062 2063 dwc2_hcd_qtd_init(qtd, urb); 2064 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2065 if (retval) { 2066 dev_err(hsotg->dev, 2067 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2068 retval); 2069 return retval; 2070 } 2071 2072 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2073 if (!(intr_mask & GINTSTS_SOF)) { 2074 enum dwc2_transaction_type tr_type; 2075 2076 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2077 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2078 /* 2079 * Do not schedule SG transactions until qtd has 2080 * URB_GIVEBACK_ASAP set 2081 */ 2082 return 0; 2083 2084 tr_type = dwc2_hcd_select_transactions(hsotg); 2085 if (tr_type != DWC2_TRANSACTION_NONE) 2086 dwc2_hcd_queue_transactions(hsotg, tr_type); 2087 } 2088 2089 return 0; 2090 } 2091 2092 /* Must be called with interrupt disabled and spinlock held */ 2093 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2094 struct dwc2_hcd_urb *urb) 2095 { 2096 struct dwc2_qh *qh; 2097 struct dwc2_qtd *urb_qtd; 2098 2099 urb_qtd = urb->qtd; 2100 if (!urb_qtd) { 2101 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2102 return -EINVAL; 2103 } 2104 2105 qh = urb_qtd->qh; 2106 if (!qh) { 2107 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2108 return -EINVAL; 2109 } 2110 2111 urb->priv = NULL; 2112 2113 if (urb_qtd->in_process && qh->channel) { 2114 dwc2_dump_channel_info(hsotg, qh->channel); 2115 2116 /* The QTD is in process (it has been assigned to a channel) */ 2117 if (hsotg->flags.b.port_connect_status) 2118 /* 2119 * If still connected (i.e. in host mode), halt the 2120 * channel so it can be used for other transfers. If 2121 * no longer connected, the host registers can't be 2122 * written to halt the channel since the core is in 2123 * device mode. 2124 */ 2125 dwc2_hc_halt(hsotg, qh->channel, 2126 DWC2_HC_XFER_URB_DEQUEUE); 2127 } 2128 2129 /* 2130 * Free the QTD and clean up the associated QH. Leave the QH in the 2131 * schedule if it has any remaining QTDs. 2132 */ 2133 if (!hsotg->params.dma_desc_enable) { 2134 u8 in_process = urb_qtd->in_process; 2135 2136 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2137 if (in_process) { 2138 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2139 qh->channel = NULL; 2140 } else if (list_empty(&qh->qtd_list)) { 2141 dwc2_hcd_qh_unlink(hsotg, qh); 2142 } 2143 } else { 2144 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2145 } 2146 2147 return 0; 2148 } 2149 2150 /* Must NOT be called with interrupt disabled or spinlock held */ 2151 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2152 struct usb_host_endpoint *ep, int retry) 2153 { 2154 struct dwc2_qtd *qtd, *qtd_tmp; 2155 struct dwc2_qh *qh; 2156 unsigned long flags; 2157 int rc; 2158 2159 spin_lock_irqsave(&hsotg->lock, flags); 2160 2161 qh = ep->hcpriv; 2162 if (!qh) { 2163 rc = -EINVAL; 2164 goto err; 2165 } 2166 2167 while (!list_empty(&qh->qtd_list) && retry--) { 2168 if (retry == 0) { 2169 dev_err(hsotg->dev, 2170 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2171 rc = -EBUSY; 2172 goto err; 2173 } 2174 2175 spin_unlock_irqrestore(&hsotg->lock, flags); 2176 msleep(20); 2177 spin_lock_irqsave(&hsotg->lock, flags); 2178 qh = ep->hcpriv; 2179 if (!qh) { 2180 rc = -EINVAL; 2181 goto err; 2182 } 2183 } 2184 2185 dwc2_hcd_qh_unlink(hsotg, qh); 2186 2187 /* Free each QTD in the QH's QTD list */ 2188 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2189 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2190 2191 ep->hcpriv = NULL; 2192 2193 if (qh->channel && qh->channel->qh == qh) 2194 qh->channel->qh = NULL; 2195 2196 spin_unlock_irqrestore(&hsotg->lock, flags); 2197 2198 dwc2_hcd_qh_free(hsotg, qh); 2199 2200 return 0; 2201 2202 err: 2203 ep->hcpriv = NULL; 2204 spin_unlock_irqrestore(&hsotg->lock, flags); 2205 2206 return rc; 2207 } 2208 2209 /* Must be called with interrupt disabled and spinlock held */ 2210 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2211 struct usb_host_endpoint *ep) 2212 { 2213 struct dwc2_qh *qh = ep->hcpriv; 2214 2215 if (!qh) 2216 return -EINVAL; 2217 2218 qh->data_toggle = DWC2_HC_PID_DATA0; 2219 2220 return 0; 2221 } 2222 2223 /** 2224 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2225 * prepares the core for device mode or host mode operation 2226 * 2227 * @hsotg: Programming view of the DWC_otg controller 2228 * @initial_setup: If true then this is the first init for this instance. 2229 */ 2230 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2231 { 2232 u32 usbcfg, otgctl; 2233 int retval; 2234 2235 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2236 2237 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2238 2239 /* Set ULPI External VBUS bit if needed */ 2240 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2241 if (hsotg->params.phy_ulpi_ext_vbus) 2242 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2243 2244 /* Set external TS Dline pulsing bit if needed */ 2245 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2246 if (hsotg->params.ts_dline) 2247 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2248 2249 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2250 2251 /* 2252 * Reset the Controller 2253 * 2254 * We only need to reset the controller if this is a re-init. 2255 * For the first init we know for sure that earlier code reset us (it 2256 * needed to in order to properly detect various parameters). 2257 */ 2258 if (!initial_setup) { 2259 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2260 if (retval) { 2261 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2262 __func__); 2263 return retval; 2264 } 2265 } 2266 2267 /* 2268 * This needs to happen in FS mode before any other programming occurs 2269 */ 2270 retval = dwc2_phy_init(hsotg, initial_setup); 2271 if (retval) 2272 return retval; 2273 2274 /* Program the GAHBCFG Register */ 2275 retval = dwc2_gahbcfg_init(hsotg); 2276 if (retval) 2277 return retval; 2278 2279 /* Program the GUSBCFG register */ 2280 dwc2_gusbcfg_init(hsotg); 2281 2282 /* Program the GOTGCTL register */ 2283 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2284 otgctl &= ~GOTGCTL_OTGVER; 2285 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2286 2287 /* Clear the SRP success bit for FS-I2c */ 2288 hsotg->srp_success = 0; 2289 2290 /* Enable common interrupts */ 2291 dwc2_enable_common_interrupts(hsotg); 2292 2293 /* 2294 * Do device or host initialization based on mode during PCD and 2295 * HCD initialization 2296 */ 2297 if (dwc2_is_host_mode(hsotg)) { 2298 dev_dbg(hsotg->dev, "Host Mode\n"); 2299 hsotg->op_state = OTG_STATE_A_HOST; 2300 } else { 2301 dev_dbg(hsotg->dev, "Device Mode\n"); 2302 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2303 } 2304 2305 return 0; 2306 } 2307 2308 /** 2309 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2310 * Host mode 2311 * 2312 * @hsotg: Programming view of DWC_otg controller 2313 * 2314 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2315 * request queues. Host channels are reset to ensure that they are ready for 2316 * performing transfers. 2317 */ 2318 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2319 { 2320 u32 hcfg, hfir, otgctl; 2321 2322 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2323 2324 /* Restart the Phy Clock */ 2325 dwc2_writel(0, hsotg->regs + PCGCTL); 2326 2327 /* Initialize Host Configuration Register */ 2328 dwc2_init_fs_ls_pclk_sel(hsotg); 2329 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2330 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2331 hcfg = dwc2_readl(hsotg->regs + HCFG); 2332 hcfg |= HCFG_FSLSSUPP; 2333 dwc2_writel(hcfg, hsotg->regs + HCFG); 2334 } 2335 2336 /* 2337 * This bit allows dynamic reloading of the HFIR register during 2338 * runtime. This bit needs to be programmed during initial configuration 2339 * and its value must not be changed during runtime. 2340 */ 2341 if (hsotg->params.reload_ctl) { 2342 hfir = dwc2_readl(hsotg->regs + HFIR); 2343 hfir |= HFIR_RLDCTRL; 2344 dwc2_writel(hfir, hsotg->regs + HFIR); 2345 } 2346 2347 if (hsotg->params.dma_desc_enable) { 2348 u32 op_mode = hsotg->hw_params.op_mode; 2349 2350 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2351 !hsotg->hw_params.dma_desc_enable || 2352 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2353 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2354 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2355 dev_err(hsotg->dev, 2356 "Hardware does not support descriptor DMA mode -\n"); 2357 dev_err(hsotg->dev, 2358 "falling back to buffer DMA mode.\n"); 2359 hsotg->params.dma_desc_enable = false; 2360 } else { 2361 hcfg = dwc2_readl(hsotg->regs + HCFG); 2362 hcfg |= HCFG_DESCDMA; 2363 dwc2_writel(hcfg, hsotg->regs + HCFG); 2364 } 2365 } 2366 2367 /* Configure data FIFO sizes */ 2368 dwc2_config_fifos(hsotg); 2369 2370 /* TODO - check this */ 2371 /* Clear Host Set HNP Enable in the OTG Control Register */ 2372 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2373 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2374 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2375 2376 /* Make sure the FIFOs are flushed */ 2377 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2378 dwc2_flush_rx_fifo(hsotg); 2379 2380 /* Clear Host Set HNP Enable in the OTG Control Register */ 2381 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2382 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2383 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2384 2385 if (!hsotg->params.dma_desc_enable) { 2386 int num_channels, i; 2387 u32 hcchar; 2388 2389 /* Flush out any leftover queued requests */ 2390 num_channels = hsotg->params.host_channels; 2391 for (i = 0; i < num_channels; i++) { 2392 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2393 hcchar &= ~HCCHAR_CHENA; 2394 hcchar |= HCCHAR_CHDIS; 2395 hcchar &= ~HCCHAR_EPDIR; 2396 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2397 } 2398 2399 /* Halt all channels to put them into a known state */ 2400 for (i = 0; i < num_channels; i++) { 2401 int count = 0; 2402 2403 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2404 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2405 hcchar &= ~HCCHAR_EPDIR; 2406 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2407 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2408 __func__, i); 2409 do { 2410 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2411 if (++count > 1000) { 2412 dev_err(hsotg->dev, 2413 "Unable to clear enable on channel %d\n", 2414 i); 2415 break; 2416 } 2417 udelay(1); 2418 } while (hcchar & HCCHAR_CHENA); 2419 } 2420 } 2421 2422 /* Turn on the vbus power */ 2423 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2424 if (hsotg->op_state == OTG_STATE_A_HOST) { 2425 u32 hprt0 = dwc2_read_hprt0(hsotg); 2426 2427 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2428 !!(hprt0 & HPRT0_PWR)); 2429 if (!(hprt0 & HPRT0_PWR)) { 2430 hprt0 |= HPRT0_PWR; 2431 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2432 } 2433 } 2434 2435 dwc2_enable_host_interrupts(hsotg); 2436 } 2437 2438 /* 2439 * Initializes dynamic portions of the DWC_otg HCD state 2440 * 2441 * Must be called with interrupt disabled and spinlock held 2442 */ 2443 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2444 { 2445 struct dwc2_host_chan *chan, *chan_tmp; 2446 int num_channels; 2447 int i; 2448 2449 hsotg->flags.d32 = 0; 2450 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2451 2452 if (hsotg->params.uframe_sched) { 2453 hsotg->available_host_channels = 2454 hsotg->params.host_channels; 2455 } else { 2456 hsotg->non_periodic_channels = 0; 2457 hsotg->periodic_channels = 0; 2458 } 2459 2460 /* 2461 * Put all channels in the free channel list and clean up channel 2462 * states 2463 */ 2464 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2465 hc_list_entry) 2466 list_del_init(&chan->hc_list_entry); 2467 2468 num_channels = hsotg->params.host_channels; 2469 for (i = 0; i < num_channels; i++) { 2470 chan = hsotg->hc_ptr_array[i]; 2471 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2472 dwc2_hc_cleanup(hsotg, chan); 2473 } 2474 2475 /* Initialize the DWC core for host mode operation */ 2476 dwc2_core_host_init(hsotg); 2477 } 2478 2479 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2480 struct dwc2_host_chan *chan, 2481 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2482 { 2483 int hub_addr, hub_port; 2484 2485 chan->do_split = 1; 2486 chan->xact_pos = qtd->isoc_split_pos; 2487 chan->complete_split = qtd->complete_split; 2488 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2489 chan->hub_addr = (u8)hub_addr; 2490 chan->hub_port = (u8)hub_port; 2491 } 2492 2493 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2494 struct dwc2_host_chan *chan, 2495 struct dwc2_qtd *qtd) 2496 { 2497 struct dwc2_hcd_urb *urb = qtd->urb; 2498 struct dwc2_hcd_iso_packet_desc *frame_desc; 2499 2500 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2501 case USB_ENDPOINT_XFER_CONTROL: 2502 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2503 2504 switch (qtd->control_phase) { 2505 case DWC2_CONTROL_SETUP: 2506 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2507 chan->do_ping = 0; 2508 chan->ep_is_in = 0; 2509 chan->data_pid_start = DWC2_HC_PID_SETUP; 2510 if (hsotg->params.host_dma) 2511 chan->xfer_dma = urb->setup_dma; 2512 else 2513 chan->xfer_buf = urb->setup_packet; 2514 chan->xfer_len = 8; 2515 break; 2516 2517 case DWC2_CONTROL_DATA: 2518 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2519 chan->data_pid_start = qtd->data_toggle; 2520 break; 2521 2522 case DWC2_CONTROL_STATUS: 2523 /* 2524 * Direction is opposite of data direction or IN if no 2525 * data 2526 */ 2527 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2528 if (urb->length == 0) 2529 chan->ep_is_in = 1; 2530 else 2531 chan->ep_is_in = 2532 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2533 if (chan->ep_is_in) 2534 chan->do_ping = 0; 2535 chan->data_pid_start = DWC2_HC_PID_DATA1; 2536 chan->xfer_len = 0; 2537 if (hsotg->params.host_dma) 2538 chan->xfer_dma = hsotg->status_buf_dma; 2539 else 2540 chan->xfer_buf = hsotg->status_buf; 2541 break; 2542 } 2543 break; 2544 2545 case USB_ENDPOINT_XFER_BULK: 2546 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2547 break; 2548 2549 case USB_ENDPOINT_XFER_INT: 2550 chan->ep_type = USB_ENDPOINT_XFER_INT; 2551 break; 2552 2553 case USB_ENDPOINT_XFER_ISOC: 2554 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2555 if (hsotg->params.dma_desc_enable) 2556 break; 2557 2558 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2559 frame_desc->status = 0; 2560 2561 if (hsotg->params.host_dma) { 2562 chan->xfer_dma = urb->dma; 2563 chan->xfer_dma += frame_desc->offset + 2564 qtd->isoc_split_offset; 2565 } else { 2566 chan->xfer_buf = urb->buf; 2567 chan->xfer_buf += frame_desc->offset + 2568 qtd->isoc_split_offset; 2569 } 2570 2571 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2572 2573 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2574 if (chan->xfer_len <= 188) 2575 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2576 else 2577 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2578 } 2579 break; 2580 } 2581 } 2582 2583 #define DWC2_USB_DMA_ALIGN 4 2584 2585 struct dma_aligned_buffer { 2586 void *kmalloc_ptr; 2587 void *old_xfer_buffer; 2588 u8 data[0]; 2589 }; 2590 2591 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2592 { 2593 struct dma_aligned_buffer *temp; 2594 2595 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2596 return; 2597 2598 temp = container_of(urb->transfer_buffer, 2599 struct dma_aligned_buffer, data); 2600 2601 if (usb_urb_dir_in(urb)) 2602 memcpy(temp->old_xfer_buffer, temp->data, 2603 urb->transfer_buffer_length); 2604 urb->transfer_buffer = temp->old_xfer_buffer; 2605 kfree(temp->kmalloc_ptr); 2606 2607 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2608 } 2609 2610 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2611 { 2612 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2613 size_t kmalloc_size; 2614 2615 if (urb->num_sgs || urb->sg || 2616 urb->transfer_buffer_length == 0 || 2617 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2618 return 0; 2619 2620 /* Allocate a buffer with enough padding for alignment */ 2621 kmalloc_size = urb->transfer_buffer_length + 2622 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2623 2624 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2625 if (!kmalloc_ptr) 2626 return -ENOMEM; 2627 2628 /* Position our struct dma_aligned_buffer such that data is aligned */ 2629 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2630 temp->kmalloc_ptr = kmalloc_ptr; 2631 temp->old_xfer_buffer = urb->transfer_buffer; 2632 if (usb_urb_dir_out(urb)) 2633 memcpy(temp->data, urb->transfer_buffer, 2634 urb->transfer_buffer_length); 2635 urb->transfer_buffer = temp->data; 2636 2637 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2638 2639 return 0; 2640 } 2641 2642 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2643 gfp_t mem_flags) 2644 { 2645 int ret; 2646 2647 /* We assume setup_dma is always aligned; warn if not */ 2648 WARN_ON_ONCE(urb->setup_dma && 2649 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2650 2651 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2652 if (ret) 2653 return ret; 2654 2655 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2656 if (ret) 2657 dwc2_free_dma_aligned_buffer(urb); 2658 2659 return ret; 2660 } 2661 2662 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2663 { 2664 usb_hcd_unmap_urb_for_dma(hcd, urb); 2665 dwc2_free_dma_aligned_buffer(urb); 2666 } 2667 2668 /** 2669 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2670 * channel and initializes the host channel to perform the transactions. The 2671 * host channel is removed from the free list. 2672 * 2673 * @hsotg: The HCD state structure 2674 * @qh: Transactions from the first QTD for this QH are selected and assigned 2675 * to a free host channel 2676 */ 2677 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2678 { 2679 struct dwc2_host_chan *chan; 2680 struct dwc2_hcd_urb *urb; 2681 struct dwc2_qtd *qtd; 2682 2683 if (dbg_qh(qh)) 2684 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2685 2686 if (list_empty(&qh->qtd_list)) { 2687 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2688 return -ENOMEM; 2689 } 2690 2691 if (list_empty(&hsotg->free_hc_list)) { 2692 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2693 return -ENOMEM; 2694 } 2695 2696 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2697 hc_list_entry); 2698 2699 /* Remove host channel from free list */ 2700 list_del_init(&chan->hc_list_entry); 2701 2702 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2703 urb = qtd->urb; 2704 qh->channel = chan; 2705 qtd->in_process = 1; 2706 2707 /* 2708 * Use usb_pipedevice to determine device address. This address is 2709 * 0 before the SET_ADDRESS command and the correct address afterward. 2710 */ 2711 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2712 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2713 chan->speed = qh->dev_speed; 2714 chan->max_packet = dwc2_max_packet(qh->maxp); 2715 2716 chan->xfer_started = 0; 2717 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2718 chan->error_state = (qtd->error_count > 0); 2719 chan->halt_on_queue = 0; 2720 chan->halt_pending = 0; 2721 chan->requests = 0; 2722 2723 /* 2724 * The following values may be modified in the transfer type section 2725 * below. The xfer_len value may be reduced when the transfer is 2726 * started to accommodate the max widths of the XferSize and PktCnt 2727 * fields in the HCTSIZn register. 2728 */ 2729 2730 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2731 if (chan->ep_is_in) 2732 chan->do_ping = 0; 2733 else 2734 chan->do_ping = qh->ping_state; 2735 2736 chan->data_pid_start = qh->data_toggle; 2737 chan->multi_count = 1; 2738 2739 if (urb->actual_length > urb->length && 2740 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2741 urb->actual_length = urb->length; 2742 2743 if (hsotg->params.host_dma) 2744 chan->xfer_dma = urb->dma + urb->actual_length; 2745 else 2746 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2747 2748 chan->xfer_len = urb->length - urb->actual_length; 2749 chan->xfer_count = 0; 2750 2751 /* Set the split attributes if required */ 2752 if (qh->do_split) 2753 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2754 else 2755 chan->do_split = 0; 2756 2757 /* Set the transfer attributes */ 2758 dwc2_hc_init_xfer(hsotg, chan, qtd); 2759 2760 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2761 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2762 /* 2763 * This value may be modified when the transfer is started 2764 * to reflect the actual transfer length 2765 */ 2766 chan->multi_count = dwc2_hb_mult(qh->maxp); 2767 2768 if (hsotg->params.dma_desc_enable) { 2769 chan->desc_list_addr = qh->desc_list_dma; 2770 chan->desc_list_sz = qh->desc_list_sz; 2771 } 2772 2773 dwc2_hc_init(hsotg, chan); 2774 chan->qh = qh; 2775 2776 return 0; 2777 } 2778 2779 /** 2780 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2781 * schedule and assigns them to available host channels. Called from the HCD 2782 * interrupt handler functions. 2783 * 2784 * @hsotg: The HCD state structure 2785 * 2786 * Return: The types of new transactions that were assigned to host channels 2787 */ 2788 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2789 struct dwc2_hsotg *hsotg) 2790 { 2791 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2792 struct list_head *qh_ptr; 2793 struct dwc2_qh *qh; 2794 int num_channels; 2795 2796 #ifdef DWC2_DEBUG_SOF 2797 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2798 #endif 2799 2800 /* Process entries in the periodic ready list */ 2801 qh_ptr = hsotg->periodic_sched_ready.next; 2802 while (qh_ptr != &hsotg->periodic_sched_ready) { 2803 if (list_empty(&hsotg->free_hc_list)) 2804 break; 2805 if (hsotg->params.uframe_sched) { 2806 if (hsotg->available_host_channels <= 1) 2807 break; 2808 hsotg->available_host_channels--; 2809 } 2810 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2811 if (dwc2_assign_and_init_hc(hsotg, qh)) 2812 break; 2813 2814 /* 2815 * Move the QH from the periodic ready schedule to the 2816 * periodic assigned schedule 2817 */ 2818 qh_ptr = qh_ptr->next; 2819 list_move_tail(&qh->qh_list_entry, 2820 &hsotg->periodic_sched_assigned); 2821 ret_val = DWC2_TRANSACTION_PERIODIC; 2822 } 2823 2824 /* 2825 * Process entries in the inactive portion of the non-periodic 2826 * schedule. Some free host channels may not be used if they are 2827 * reserved for periodic transfers. 2828 */ 2829 num_channels = hsotg->params.host_channels; 2830 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2831 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2832 if (!hsotg->params.uframe_sched && 2833 hsotg->non_periodic_channels >= num_channels - 2834 hsotg->periodic_channels) 2835 break; 2836 if (list_empty(&hsotg->free_hc_list)) 2837 break; 2838 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2839 if (hsotg->params.uframe_sched) { 2840 if (hsotg->available_host_channels < 1) 2841 break; 2842 hsotg->available_host_channels--; 2843 } 2844 2845 if (dwc2_assign_and_init_hc(hsotg, qh)) 2846 break; 2847 2848 /* 2849 * Move the QH from the non-periodic inactive schedule to the 2850 * non-periodic active schedule 2851 */ 2852 qh_ptr = qh_ptr->next; 2853 list_move_tail(&qh->qh_list_entry, 2854 &hsotg->non_periodic_sched_active); 2855 2856 if (ret_val == DWC2_TRANSACTION_NONE) 2857 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2858 else 2859 ret_val = DWC2_TRANSACTION_ALL; 2860 2861 if (!hsotg->params.uframe_sched) 2862 hsotg->non_periodic_channels++; 2863 } 2864 2865 return ret_val; 2866 } 2867 2868 /** 2869 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2870 * a host channel associated with either a periodic or non-periodic transfer 2871 * 2872 * @hsotg: The HCD state structure 2873 * @chan: Host channel descriptor associated with either a periodic or 2874 * non-periodic transfer 2875 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2876 * for periodic transfers or the non-periodic Tx FIFO 2877 * for non-periodic transfers 2878 * 2879 * Return: 1 if a request is queued and more requests may be needed to 2880 * complete the transfer, 0 if no more requests are required for this 2881 * transfer, -1 if there is insufficient space in the Tx FIFO 2882 * 2883 * This function assumes that there is space available in the appropriate 2884 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2885 * it checks whether space is available in the appropriate Tx FIFO. 2886 * 2887 * Must be called with interrupt disabled and spinlock held 2888 */ 2889 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2890 struct dwc2_host_chan *chan, 2891 u16 fifo_dwords_avail) 2892 { 2893 int retval = 0; 2894 2895 if (chan->do_split) 2896 /* Put ourselves on the list to keep order straight */ 2897 list_move_tail(&chan->split_order_list_entry, 2898 &hsotg->split_order); 2899 2900 if (hsotg->params.host_dma) { 2901 if (hsotg->params.dma_desc_enable) { 2902 if (!chan->xfer_started || 2903 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2904 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2905 chan->qh->ping_state = 0; 2906 } 2907 } else if (!chan->xfer_started) { 2908 dwc2_hc_start_transfer(hsotg, chan); 2909 chan->qh->ping_state = 0; 2910 } 2911 } else if (chan->halt_pending) { 2912 /* Don't queue a request if the channel has been halted */ 2913 } else if (chan->halt_on_queue) { 2914 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2915 } else if (chan->do_ping) { 2916 if (!chan->xfer_started) 2917 dwc2_hc_start_transfer(hsotg, chan); 2918 } else if (!chan->ep_is_in || 2919 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2920 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2921 if (!chan->xfer_started) { 2922 dwc2_hc_start_transfer(hsotg, chan); 2923 retval = 1; 2924 } else { 2925 retval = dwc2_hc_continue_transfer(hsotg, chan); 2926 } 2927 } else { 2928 retval = -1; 2929 } 2930 } else { 2931 if (!chan->xfer_started) { 2932 dwc2_hc_start_transfer(hsotg, chan); 2933 retval = 1; 2934 } else { 2935 retval = dwc2_hc_continue_transfer(hsotg, chan); 2936 } 2937 } 2938 2939 return retval; 2940 } 2941 2942 /* 2943 * Processes periodic channels for the next frame and queues transactions for 2944 * these channels to the DWC_otg controller. After queueing transactions, the 2945 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2946 * to queue as Periodic Tx FIFO or request queue space becomes available. 2947 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2948 * 2949 * Must be called with interrupt disabled and spinlock held 2950 */ 2951 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2952 { 2953 struct list_head *qh_ptr; 2954 struct dwc2_qh *qh; 2955 u32 tx_status; 2956 u32 fspcavail; 2957 u32 gintmsk; 2958 int status; 2959 bool no_queue_space = false; 2960 bool no_fifo_space = false; 2961 u32 qspcavail; 2962 2963 /* If empty list then just adjust interrupt enables */ 2964 if (list_empty(&hsotg->periodic_sched_assigned)) 2965 goto exit; 2966 2967 if (dbg_perio()) 2968 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2969 2970 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2971 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2972 TXSTS_QSPCAVAIL_SHIFT; 2973 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2974 TXSTS_FSPCAVAIL_SHIFT; 2975 2976 if (dbg_perio()) { 2977 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 2978 qspcavail); 2979 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 2980 fspcavail); 2981 } 2982 2983 qh_ptr = hsotg->periodic_sched_assigned.next; 2984 while (qh_ptr != &hsotg->periodic_sched_assigned) { 2985 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2986 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2987 TXSTS_QSPCAVAIL_SHIFT; 2988 if (qspcavail == 0) { 2989 no_queue_space = true; 2990 break; 2991 } 2992 2993 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2994 if (!qh->channel) { 2995 qh_ptr = qh_ptr->next; 2996 continue; 2997 } 2998 2999 /* Make sure EP's TT buffer is clean before queueing qtds */ 3000 if (qh->tt_buffer_dirty) { 3001 qh_ptr = qh_ptr->next; 3002 continue; 3003 } 3004 3005 /* 3006 * Set a flag if we're queuing high-bandwidth in slave mode. 3007 * The flag prevents any halts to get into the request queue in 3008 * the middle of multiple high-bandwidth packets getting queued. 3009 */ 3010 if (!hsotg->params.host_dma && 3011 qh->channel->multi_count > 1) 3012 hsotg->queuing_high_bandwidth = 1; 3013 3014 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3015 TXSTS_FSPCAVAIL_SHIFT; 3016 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3017 if (status < 0) { 3018 no_fifo_space = true; 3019 break; 3020 } 3021 3022 /* 3023 * In Slave mode, stay on the current transfer until there is 3024 * nothing more to do or the high-bandwidth request count is 3025 * reached. In DMA mode, only need to queue one request. The 3026 * controller automatically handles multiple packets for 3027 * high-bandwidth transfers. 3028 */ 3029 if (hsotg->params.host_dma || status == 0 || 3030 qh->channel->requests == qh->channel->multi_count) { 3031 qh_ptr = qh_ptr->next; 3032 /* 3033 * Move the QH from the periodic assigned schedule to 3034 * the periodic queued schedule 3035 */ 3036 list_move_tail(&qh->qh_list_entry, 3037 &hsotg->periodic_sched_queued); 3038 3039 /* done queuing high bandwidth */ 3040 hsotg->queuing_high_bandwidth = 0; 3041 } 3042 } 3043 3044 exit: 3045 if (no_queue_space || no_fifo_space || 3046 (!hsotg->params.host_dma && 3047 !list_empty(&hsotg->periodic_sched_assigned))) { 3048 /* 3049 * May need to queue more transactions as the request 3050 * queue or Tx FIFO empties. Enable the periodic Tx 3051 * FIFO empty interrupt. (Always use the half-empty 3052 * level to ensure that new requests are loaded as 3053 * soon as possible.) 3054 */ 3055 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3056 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3057 gintmsk |= GINTSTS_PTXFEMP; 3058 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3059 } 3060 } else { 3061 /* 3062 * Disable the Tx FIFO empty interrupt since there are 3063 * no more transactions that need to be queued right 3064 * now. This function is called from interrupt 3065 * handlers to queue more transactions as transfer 3066 * states change. 3067 */ 3068 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3069 if (gintmsk & GINTSTS_PTXFEMP) { 3070 gintmsk &= ~GINTSTS_PTXFEMP; 3071 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3072 } 3073 } 3074 } 3075 3076 /* 3077 * Processes active non-periodic channels and queues transactions for these 3078 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3079 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3080 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3081 * FIFO Empty interrupt is disabled. 3082 * 3083 * Must be called with interrupt disabled and spinlock held 3084 */ 3085 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3086 { 3087 struct list_head *orig_qh_ptr; 3088 struct dwc2_qh *qh; 3089 u32 tx_status; 3090 u32 qspcavail; 3091 u32 fspcavail; 3092 u32 gintmsk; 3093 int status; 3094 int no_queue_space = 0; 3095 int no_fifo_space = 0; 3096 int more_to_do = 0; 3097 3098 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3099 3100 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3101 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3102 TXSTS_QSPCAVAIL_SHIFT; 3103 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3104 TXSTS_FSPCAVAIL_SHIFT; 3105 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3106 qspcavail); 3107 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3108 fspcavail); 3109 3110 /* 3111 * Keep track of the starting point. Skip over the start-of-list 3112 * entry. 3113 */ 3114 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3115 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3116 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3117 3118 /* 3119 * Process once through the active list or until no more space is 3120 * available in the request queue or the Tx FIFO 3121 */ 3122 do { 3123 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3124 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3125 TXSTS_QSPCAVAIL_SHIFT; 3126 if (!hsotg->params.host_dma && qspcavail == 0) { 3127 no_queue_space = 1; 3128 break; 3129 } 3130 3131 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3132 qh_list_entry); 3133 if (!qh->channel) 3134 goto next; 3135 3136 /* Make sure EP's TT buffer is clean before queueing qtds */ 3137 if (qh->tt_buffer_dirty) 3138 goto next; 3139 3140 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3141 TXSTS_FSPCAVAIL_SHIFT; 3142 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3143 3144 if (status > 0) { 3145 more_to_do = 1; 3146 } else if (status < 0) { 3147 no_fifo_space = 1; 3148 break; 3149 } 3150 next: 3151 /* Advance to next QH, skipping start-of-list entry */ 3152 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3153 if (hsotg->non_periodic_qh_ptr == 3154 &hsotg->non_periodic_sched_active) 3155 hsotg->non_periodic_qh_ptr = 3156 hsotg->non_periodic_qh_ptr->next; 3157 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3158 3159 if (!hsotg->params.host_dma) { 3160 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3161 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3162 TXSTS_QSPCAVAIL_SHIFT; 3163 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3164 TXSTS_FSPCAVAIL_SHIFT; 3165 dev_vdbg(hsotg->dev, 3166 " NP Tx Req Queue Space Avail (after queue): %d\n", 3167 qspcavail); 3168 dev_vdbg(hsotg->dev, 3169 " NP Tx FIFO Space Avail (after queue): %d\n", 3170 fspcavail); 3171 3172 if (more_to_do || no_queue_space || no_fifo_space) { 3173 /* 3174 * May need to queue more transactions as the request 3175 * queue or Tx FIFO empties. Enable the non-periodic 3176 * Tx FIFO empty interrupt. (Always use the half-empty 3177 * level to ensure that new requests are loaded as 3178 * soon as possible.) 3179 */ 3180 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3181 gintmsk |= GINTSTS_NPTXFEMP; 3182 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3183 } else { 3184 /* 3185 * Disable the Tx FIFO empty interrupt since there are 3186 * no more transactions that need to be queued right 3187 * now. This function is called from interrupt 3188 * handlers to queue more transactions as transfer 3189 * states change. 3190 */ 3191 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3192 gintmsk &= ~GINTSTS_NPTXFEMP; 3193 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3194 } 3195 } 3196 } 3197 3198 /** 3199 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3200 * and queues transactions for these channels to the DWC_otg controller. Called 3201 * from the HCD interrupt handler functions. 3202 * 3203 * @hsotg: The HCD state structure 3204 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3205 * or both) 3206 * 3207 * Must be called with interrupt disabled and spinlock held 3208 */ 3209 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3210 enum dwc2_transaction_type tr_type) 3211 { 3212 #ifdef DWC2_DEBUG_SOF 3213 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3214 #endif 3215 /* Process host channels associated with periodic transfers */ 3216 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3217 tr_type == DWC2_TRANSACTION_ALL) 3218 dwc2_process_periodic_channels(hsotg); 3219 3220 /* Process host channels associated with non-periodic transfers */ 3221 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3222 tr_type == DWC2_TRANSACTION_ALL) { 3223 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3224 dwc2_process_non_periodic_channels(hsotg); 3225 } else { 3226 /* 3227 * Ensure NP Tx FIFO empty interrupt is disabled when 3228 * there are no non-periodic transfers to process 3229 */ 3230 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3231 3232 gintmsk &= ~GINTSTS_NPTXFEMP; 3233 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3234 } 3235 } 3236 } 3237 3238 static void dwc2_conn_id_status_change(struct work_struct *work) 3239 { 3240 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3241 wf_otg); 3242 u32 count = 0; 3243 u32 gotgctl; 3244 unsigned long flags; 3245 3246 dev_dbg(hsotg->dev, "%s()\n", __func__); 3247 3248 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3249 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3250 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3251 !!(gotgctl & GOTGCTL_CONID_B)); 3252 3253 /* B-Device connector (Device Mode) */ 3254 if (gotgctl & GOTGCTL_CONID_B) { 3255 /* Wait for switch to device mode */ 3256 dev_dbg(hsotg->dev, "connId B\n"); 3257 if (hsotg->bus_suspended) { 3258 dev_info(hsotg->dev, 3259 "Do port resume before switching to device mode\n"); 3260 dwc2_port_resume(hsotg); 3261 } 3262 while (!dwc2_is_device_mode(hsotg)) { 3263 dev_info(hsotg->dev, 3264 "Waiting for Peripheral Mode, Mode=%s\n", 3265 dwc2_is_host_mode(hsotg) ? "Host" : 3266 "Peripheral"); 3267 msleep(20); 3268 /* 3269 * Sometimes the initial GOTGCTRL read is wrong, so 3270 * check it again and jump to host mode if that was 3271 * the case. 3272 */ 3273 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3274 if (!(gotgctl & GOTGCTL_CONID_B)) 3275 goto host; 3276 if (++count > 250) 3277 break; 3278 } 3279 if (count > 250) 3280 dev_err(hsotg->dev, 3281 "Connection id status change timed out\n"); 3282 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3283 dwc2_core_init(hsotg, false); 3284 dwc2_enable_global_interrupts(hsotg); 3285 spin_lock_irqsave(&hsotg->lock, flags); 3286 dwc2_hsotg_core_init_disconnected(hsotg, false); 3287 spin_unlock_irqrestore(&hsotg->lock, flags); 3288 dwc2_hsotg_core_connect(hsotg); 3289 } else { 3290 host: 3291 /* A-Device connector (Host Mode) */ 3292 dev_dbg(hsotg->dev, "connId A\n"); 3293 while (!dwc2_is_host_mode(hsotg)) { 3294 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3295 dwc2_is_host_mode(hsotg) ? 3296 "Host" : "Peripheral"); 3297 msleep(20); 3298 if (++count > 250) 3299 break; 3300 } 3301 if (count > 250) 3302 dev_err(hsotg->dev, 3303 "Connection id status change timed out\n"); 3304 3305 spin_lock_irqsave(&hsotg->lock, flags); 3306 dwc2_hsotg_disconnect(hsotg); 3307 spin_unlock_irqrestore(&hsotg->lock, flags); 3308 3309 hsotg->op_state = OTG_STATE_A_HOST; 3310 /* Initialize the Core for Host mode */ 3311 dwc2_core_init(hsotg, false); 3312 dwc2_enable_global_interrupts(hsotg); 3313 dwc2_hcd_start(hsotg); 3314 } 3315 } 3316 3317 static void dwc2_wakeup_detected(struct timer_list *t) 3318 { 3319 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); 3320 u32 hprt0; 3321 3322 dev_dbg(hsotg->dev, "%s()\n", __func__); 3323 3324 /* 3325 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3326 * so that OPT tests pass with all PHYs.) 3327 */ 3328 hprt0 = dwc2_read_hprt0(hsotg); 3329 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3330 hprt0 &= ~HPRT0_RES; 3331 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3332 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3333 dwc2_readl(hsotg->regs + HPRT0)); 3334 3335 dwc2_hcd_rem_wakeup(hsotg); 3336 hsotg->bus_suspended = false; 3337 3338 /* Change to L0 state */ 3339 hsotg->lx_state = DWC2_L0; 3340 } 3341 3342 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3343 { 3344 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3345 3346 return hcd->self.b_hnp_enable; 3347 } 3348 3349 /* Must NOT be called with interrupt disabled or spinlock held */ 3350 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3351 { 3352 unsigned long flags; 3353 u32 hprt0; 3354 u32 pcgctl; 3355 u32 gotgctl; 3356 3357 dev_dbg(hsotg->dev, "%s()\n", __func__); 3358 3359 spin_lock_irqsave(&hsotg->lock, flags); 3360 3361 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3362 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3363 gotgctl |= GOTGCTL_HSTSETHNPEN; 3364 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3365 hsotg->op_state = OTG_STATE_A_SUSPEND; 3366 } 3367 3368 hprt0 = dwc2_read_hprt0(hsotg); 3369 hprt0 |= HPRT0_SUSP; 3370 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3371 3372 hsotg->bus_suspended = true; 3373 3374 /* 3375 * If hibernation is supported, Phy clock will be suspended 3376 * after registers are backuped. 3377 */ 3378 if (!hsotg->params.hibernation) { 3379 /* Suspend the Phy Clock */ 3380 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3381 pcgctl |= PCGCTL_STOPPCLK; 3382 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3383 udelay(10); 3384 } 3385 3386 /* For HNP the bus must be suspended for at least 200ms */ 3387 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3388 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3389 pcgctl &= ~PCGCTL_STOPPCLK; 3390 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3391 3392 spin_unlock_irqrestore(&hsotg->lock, flags); 3393 3394 msleep(200); 3395 } else { 3396 spin_unlock_irqrestore(&hsotg->lock, flags); 3397 } 3398 } 3399 3400 /* Must NOT be called with interrupt disabled or spinlock held */ 3401 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3402 { 3403 unsigned long flags; 3404 u32 hprt0; 3405 u32 pcgctl; 3406 3407 spin_lock_irqsave(&hsotg->lock, flags); 3408 3409 /* 3410 * If hibernation is supported, Phy clock is already resumed 3411 * after registers restore. 3412 */ 3413 if (!hsotg->params.hibernation) { 3414 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3415 pcgctl &= ~PCGCTL_STOPPCLK; 3416 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3417 spin_unlock_irqrestore(&hsotg->lock, flags); 3418 msleep(20); 3419 spin_lock_irqsave(&hsotg->lock, flags); 3420 } 3421 3422 hprt0 = dwc2_read_hprt0(hsotg); 3423 hprt0 |= HPRT0_RES; 3424 hprt0 &= ~HPRT0_SUSP; 3425 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3426 spin_unlock_irqrestore(&hsotg->lock, flags); 3427 3428 msleep(USB_RESUME_TIMEOUT); 3429 3430 spin_lock_irqsave(&hsotg->lock, flags); 3431 hprt0 = dwc2_read_hprt0(hsotg); 3432 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3433 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3434 hsotg->bus_suspended = false; 3435 spin_unlock_irqrestore(&hsotg->lock, flags); 3436 } 3437 3438 /* Handles hub class-specific requests */ 3439 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3440 u16 wvalue, u16 windex, char *buf, u16 wlength) 3441 { 3442 struct usb_hub_descriptor *hub_desc; 3443 int retval = 0; 3444 u32 hprt0; 3445 u32 port_status; 3446 u32 speed; 3447 u32 pcgctl; 3448 3449 switch (typereq) { 3450 case ClearHubFeature: 3451 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3452 3453 switch (wvalue) { 3454 case C_HUB_LOCAL_POWER: 3455 case C_HUB_OVER_CURRENT: 3456 /* Nothing required here */ 3457 break; 3458 3459 default: 3460 retval = -EINVAL; 3461 dev_err(hsotg->dev, 3462 "ClearHubFeature request %1xh unknown\n", 3463 wvalue); 3464 } 3465 break; 3466 3467 case ClearPortFeature: 3468 if (wvalue != USB_PORT_FEAT_L1) 3469 if (!windex || windex > 1) 3470 goto error; 3471 switch (wvalue) { 3472 case USB_PORT_FEAT_ENABLE: 3473 dev_dbg(hsotg->dev, 3474 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3475 hprt0 = dwc2_read_hprt0(hsotg); 3476 hprt0 |= HPRT0_ENA; 3477 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3478 break; 3479 3480 case USB_PORT_FEAT_SUSPEND: 3481 dev_dbg(hsotg->dev, 3482 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3483 3484 if (hsotg->bus_suspended) 3485 dwc2_port_resume(hsotg); 3486 break; 3487 3488 case USB_PORT_FEAT_POWER: 3489 dev_dbg(hsotg->dev, 3490 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3491 hprt0 = dwc2_read_hprt0(hsotg); 3492 hprt0 &= ~HPRT0_PWR; 3493 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3494 break; 3495 3496 case USB_PORT_FEAT_INDICATOR: 3497 dev_dbg(hsotg->dev, 3498 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3499 /* Port indicator not supported */ 3500 break; 3501 3502 case USB_PORT_FEAT_C_CONNECTION: 3503 /* 3504 * Clears driver's internal Connect Status Change flag 3505 */ 3506 dev_dbg(hsotg->dev, 3507 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3508 hsotg->flags.b.port_connect_status_change = 0; 3509 break; 3510 3511 case USB_PORT_FEAT_C_RESET: 3512 /* Clears driver's internal Port Reset Change flag */ 3513 dev_dbg(hsotg->dev, 3514 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3515 hsotg->flags.b.port_reset_change = 0; 3516 break; 3517 3518 case USB_PORT_FEAT_C_ENABLE: 3519 /* 3520 * Clears the driver's internal Port Enable/Disable 3521 * Change flag 3522 */ 3523 dev_dbg(hsotg->dev, 3524 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3525 hsotg->flags.b.port_enable_change = 0; 3526 break; 3527 3528 case USB_PORT_FEAT_C_SUSPEND: 3529 /* 3530 * Clears the driver's internal Port Suspend Change 3531 * flag, which is set when resume signaling on the host 3532 * port is complete 3533 */ 3534 dev_dbg(hsotg->dev, 3535 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3536 hsotg->flags.b.port_suspend_change = 0; 3537 break; 3538 3539 case USB_PORT_FEAT_C_PORT_L1: 3540 dev_dbg(hsotg->dev, 3541 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3542 hsotg->flags.b.port_l1_change = 0; 3543 break; 3544 3545 case USB_PORT_FEAT_C_OVER_CURRENT: 3546 dev_dbg(hsotg->dev, 3547 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3548 hsotg->flags.b.port_over_current_change = 0; 3549 break; 3550 3551 default: 3552 retval = -EINVAL; 3553 dev_err(hsotg->dev, 3554 "ClearPortFeature request %1xh unknown or unsupported\n", 3555 wvalue); 3556 } 3557 break; 3558 3559 case GetHubDescriptor: 3560 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3561 hub_desc = (struct usb_hub_descriptor *)buf; 3562 hub_desc->bDescLength = 9; 3563 hub_desc->bDescriptorType = USB_DT_HUB; 3564 hub_desc->bNbrPorts = 1; 3565 hub_desc->wHubCharacteristics = 3566 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3567 HUB_CHAR_INDV_PORT_OCPM); 3568 hub_desc->bPwrOn2PwrGood = 1; 3569 hub_desc->bHubContrCurrent = 0; 3570 hub_desc->u.hs.DeviceRemovable[0] = 0; 3571 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3572 break; 3573 3574 case GetHubStatus: 3575 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3576 memset(buf, 0, 4); 3577 break; 3578 3579 case GetPortStatus: 3580 dev_vdbg(hsotg->dev, 3581 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3582 hsotg->flags.d32); 3583 if (!windex || windex > 1) 3584 goto error; 3585 3586 port_status = 0; 3587 if (hsotg->flags.b.port_connect_status_change) 3588 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3589 if (hsotg->flags.b.port_enable_change) 3590 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3591 if (hsotg->flags.b.port_suspend_change) 3592 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3593 if (hsotg->flags.b.port_l1_change) 3594 port_status |= USB_PORT_STAT_C_L1 << 16; 3595 if (hsotg->flags.b.port_reset_change) 3596 port_status |= USB_PORT_STAT_C_RESET << 16; 3597 if (hsotg->flags.b.port_over_current_change) { 3598 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3599 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3600 } 3601 3602 if (!hsotg->flags.b.port_connect_status) { 3603 /* 3604 * The port is disconnected, which means the core is 3605 * either in device mode or it soon will be. Just 3606 * return 0's for the remainder of the port status 3607 * since the port register can't be read if the core 3608 * is in device mode. 3609 */ 3610 *(__le32 *)buf = cpu_to_le32(port_status); 3611 break; 3612 } 3613 3614 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3615 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3616 3617 if (hprt0 & HPRT0_CONNSTS) 3618 port_status |= USB_PORT_STAT_CONNECTION; 3619 if (hprt0 & HPRT0_ENA) 3620 port_status |= USB_PORT_STAT_ENABLE; 3621 if (hprt0 & HPRT0_SUSP) 3622 port_status |= USB_PORT_STAT_SUSPEND; 3623 if (hprt0 & HPRT0_OVRCURRACT) 3624 port_status |= USB_PORT_STAT_OVERCURRENT; 3625 if (hprt0 & HPRT0_RST) 3626 port_status |= USB_PORT_STAT_RESET; 3627 if (hprt0 & HPRT0_PWR) 3628 port_status |= USB_PORT_STAT_POWER; 3629 3630 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3631 if (speed == HPRT0_SPD_HIGH_SPEED) 3632 port_status |= USB_PORT_STAT_HIGH_SPEED; 3633 else if (speed == HPRT0_SPD_LOW_SPEED) 3634 port_status |= USB_PORT_STAT_LOW_SPEED; 3635 3636 if (hprt0 & HPRT0_TSTCTL_MASK) 3637 port_status |= USB_PORT_STAT_TEST; 3638 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3639 3640 if (hsotg->params.dma_desc_fs_enable) { 3641 /* 3642 * Enable descriptor DMA only if a full speed 3643 * device is connected. 3644 */ 3645 if (hsotg->new_connection && 3646 ((port_status & 3647 (USB_PORT_STAT_CONNECTION | 3648 USB_PORT_STAT_HIGH_SPEED | 3649 USB_PORT_STAT_LOW_SPEED)) == 3650 USB_PORT_STAT_CONNECTION)) { 3651 u32 hcfg; 3652 3653 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3654 hsotg->params.dma_desc_enable = true; 3655 hcfg = dwc2_readl(hsotg->regs + HCFG); 3656 hcfg |= HCFG_DESCDMA; 3657 dwc2_writel(hcfg, hsotg->regs + HCFG); 3658 hsotg->new_connection = false; 3659 } 3660 } 3661 3662 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3663 *(__le32 *)buf = cpu_to_le32(port_status); 3664 break; 3665 3666 case SetHubFeature: 3667 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3668 /* No HUB features supported */ 3669 break; 3670 3671 case SetPortFeature: 3672 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3673 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3674 goto error; 3675 3676 if (!hsotg->flags.b.port_connect_status) { 3677 /* 3678 * The port is disconnected, which means the core is 3679 * either in device mode or it soon will be. Just 3680 * return without doing anything since the port 3681 * register can't be written if the core is in device 3682 * mode. 3683 */ 3684 break; 3685 } 3686 3687 switch (wvalue) { 3688 case USB_PORT_FEAT_SUSPEND: 3689 dev_dbg(hsotg->dev, 3690 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3691 if (windex != hsotg->otg_port) 3692 goto error; 3693 dwc2_port_suspend(hsotg, windex); 3694 break; 3695 3696 case USB_PORT_FEAT_POWER: 3697 dev_dbg(hsotg->dev, 3698 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3699 hprt0 = dwc2_read_hprt0(hsotg); 3700 hprt0 |= HPRT0_PWR; 3701 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3702 break; 3703 3704 case USB_PORT_FEAT_RESET: 3705 hprt0 = dwc2_read_hprt0(hsotg); 3706 dev_dbg(hsotg->dev, 3707 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3708 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3709 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3710 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3711 /* ??? Original driver does this */ 3712 dwc2_writel(0, hsotg->regs + PCGCTL); 3713 3714 hprt0 = dwc2_read_hprt0(hsotg); 3715 /* Clear suspend bit if resetting from suspend state */ 3716 hprt0 &= ~HPRT0_SUSP; 3717 3718 /* 3719 * When B-Host the Port reset bit is set in the Start 3720 * HCD Callback function, so that the reset is started 3721 * within 1ms of the HNP success interrupt 3722 */ 3723 if (!dwc2_hcd_is_b_host(hsotg)) { 3724 hprt0 |= HPRT0_PWR | HPRT0_RST; 3725 dev_dbg(hsotg->dev, 3726 "In host mode, hprt0=%08x\n", hprt0); 3727 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3728 } 3729 3730 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3731 msleep(50); 3732 hprt0 &= ~HPRT0_RST; 3733 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3734 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3735 break; 3736 3737 case USB_PORT_FEAT_INDICATOR: 3738 dev_dbg(hsotg->dev, 3739 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3740 /* Not supported */ 3741 break; 3742 3743 case USB_PORT_FEAT_TEST: 3744 hprt0 = dwc2_read_hprt0(hsotg); 3745 dev_dbg(hsotg->dev, 3746 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3747 hprt0 &= ~HPRT0_TSTCTL_MASK; 3748 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3749 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3750 break; 3751 3752 default: 3753 retval = -EINVAL; 3754 dev_err(hsotg->dev, 3755 "SetPortFeature %1xh unknown or unsupported\n", 3756 wvalue); 3757 break; 3758 } 3759 break; 3760 3761 default: 3762 error: 3763 retval = -EINVAL; 3764 dev_dbg(hsotg->dev, 3765 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3766 typereq, windex, wvalue); 3767 break; 3768 } 3769 3770 return retval; 3771 } 3772 3773 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3774 { 3775 int retval; 3776 3777 if (port != 1) 3778 return -EINVAL; 3779 3780 retval = (hsotg->flags.b.port_connect_status_change || 3781 hsotg->flags.b.port_reset_change || 3782 hsotg->flags.b.port_enable_change || 3783 hsotg->flags.b.port_suspend_change || 3784 hsotg->flags.b.port_over_current_change); 3785 3786 if (retval) { 3787 dev_dbg(hsotg->dev, 3788 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3789 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3790 hsotg->flags.b.port_connect_status_change); 3791 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3792 hsotg->flags.b.port_reset_change); 3793 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3794 hsotg->flags.b.port_enable_change); 3795 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3796 hsotg->flags.b.port_suspend_change); 3797 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3798 hsotg->flags.b.port_over_current_change); 3799 } 3800 3801 return retval; 3802 } 3803 3804 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3805 { 3806 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3807 3808 #ifdef DWC2_DEBUG_SOF 3809 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3810 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3811 #endif 3812 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3813 } 3814 3815 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3816 { 3817 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3818 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3819 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3820 unsigned int us_per_frame; 3821 unsigned int frame_number; 3822 unsigned int remaining; 3823 unsigned int interval; 3824 unsigned int phy_clks; 3825 3826 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3827 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3828 3829 /* Extract fields */ 3830 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3831 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3832 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3833 3834 /* 3835 * Number of phy clocks since the last tick of the frame number after 3836 * "us" has passed. 3837 */ 3838 phy_clks = (interval - remaining) + 3839 DIV_ROUND_UP(interval * us, us_per_frame); 3840 3841 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3842 } 3843 3844 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3845 { 3846 return hsotg->op_state == OTG_STATE_B_HOST; 3847 } 3848 3849 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3850 int iso_desc_count, 3851 gfp_t mem_flags) 3852 { 3853 struct dwc2_hcd_urb *urb; 3854 u32 size = sizeof(*urb) + iso_desc_count * 3855 sizeof(struct dwc2_hcd_iso_packet_desc); 3856 3857 urb = kzalloc(size, mem_flags); 3858 if (urb) 3859 urb->packet_count = iso_desc_count; 3860 return urb; 3861 } 3862 3863 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3864 struct dwc2_hcd_urb *urb, u8 dev_addr, 3865 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3866 { 3867 if (dbg_perio() || 3868 ep_type == USB_ENDPOINT_XFER_BULK || 3869 ep_type == USB_ENDPOINT_XFER_CONTROL) 3870 dev_vdbg(hsotg->dev, 3871 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3872 dev_addr, ep_num, ep_dir, ep_type, mps); 3873 urb->pipe_info.dev_addr = dev_addr; 3874 urb->pipe_info.ep_num = ep_num; 3875 urb->pipe_info.pipe_type = ep_type; 3876 urb->pipe_info.pipe_dir = ep_dir; 3877 urb->pipe_info.mps = mps; 3878 } 3879 3880 /* 3881 * NOTE: This function will be removed once the peripheral controller code 3882 * is integrated and the driver is stable 3883 */ 3884 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3885 { 3886 #ifdef DEBUG 3887 struct dwc2_host_chan *chan; 3888 struct dwc2_hcd_urb *urb; 3889 struct dwc2_qtd *qtd; 3890 int num_channels; 3891 u32 np_tx_status; 3892 u32 p_tx_status; 3893 int i; 3894 3895 num_channels = hsotg->params.host_channels; 3896 dev_dbg(hsotg->dev, "\n"); 3897 dev_dbg(hsotg->dev, 3898 "************************************************************\n"); 3899 dev_dbg(hsotg->dev, "HCD State:\n"); 3900 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3901 3902 for (i = 0; i < num_channels; i++) { 3903 chan = hsotg->hc_ptr_array[i]; 3904 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3905 dev_dbg(hsotg->dev, 3906 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3907 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3908 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3909 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3910 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3911 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3912 chan->data_pid_start); 3913 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3914 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3915 chan->xfer_started); 3916 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3917 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3918 (unsigned long)chan->xfer_dma); 3919 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3920 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3921 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3922 chan->halt_on_queue); 3923 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3924 chan->halt_pending); 3925 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3926 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3927 dev_dbg(hsotg->dev, " complete_split: %d\n", 3928 chan->complete_split); 3929 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3930 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3931 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3932 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3933 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3934 3935 if (chan->xfer_started) { 3936 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3937 3938 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3939 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3940 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3941 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3942 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3943 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3944 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3945 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3946 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3947 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3948 } 3949 3950 if (!(chan->xfer_started && chan->qh)) 3951 continue; 3952 3953 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3954 if (!qtd->in_process) 3955 break; 3956 urb = qtd->urb; 3957 dev_dbg(hsotg->dev, " URB Info:\n"); 3958 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3959 qtd, urb); 3960 if (urb) { 3961 dev_dbg(hsotg->dev, 3962 " Dev: %d, EP: %d %s\n", 3963 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3964 dwc2_hcd_get_ep_num(&urb->pipe_info), 3965 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3966 "IN" : "OUT"); 3967 dev_dbg(hsotg->dev, 3968 " Max packet size: %d\n", 3969 dwc2_hcd_get_mps(&urb->pipe_info)); 3970 dev_dbg(hsotg->dev, 3971 " transfer_buffer: %p\n", 3972 urb->buf); 3973 dev_dbg(hsotg->dev, 3974 " transfer_dma: %08lx\n", 3975 (unsigned long)urb->dma); 3976 dev_dbg(hsotg->dev, 3977 " transfer_buffer_length: %d\n", 3978 urb->length); 3979 dev_dbg(hsotg->dev, " actual_length: %d\n", 3980 urb->actual_length); 3981 } 3982 } 3983 } 3984 3985 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 3986 hsotg->non_periodic_channels); 3987 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 3988 hsotg->periodic_channels); 3989 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 3990 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3991 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 3992 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3993 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 3994 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 3995 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3996 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 3997 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 3998 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 3999 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4000 dwc2_hcd_dump_frrem(hsotg); 4001 dwc2_dump_global_registers(hsotg); 4002 dwc2_dump_host_registers(hsotg); 4003 dev_dbg(hsotg->dev, 4004 "************************************************************\n"); 4005 dev_dbg(hsotg->dev, "\n"); 4006 #endif 4007 } 4008 4009 /* 4010 * NOTE: This function will be removed once the peripheral controller code 4011 * is integrated and the driver is stable 4012 */ 4013 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 4014 { 4015 #ifdef DWC2_DUMP_FRREM 4016 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 4017 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4018 hsotg->frrem_samples, hsotg->frrem_accum, 4019 hsotg->frrem_samples > 0 ? 4020 hsotg->frrem_accum / hsotg->frrem_samples : 0); 4021 dev_dbg(hsotg->dev, "\n"); 4022 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 4023 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4024 hsotg->hfnum_7_samples, 4025 hsotg->hfnum_7_frrem_accum, 4026 hsotg->hfnum_7_samples > 0 ? 4027 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 4028 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 4029 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4030 hsotg->hfnum_0_samples, 4031 hsotg->hfnum_0_frrem_accum, 4032 hsotg->hfnum_0_samples > 0 ? 4033 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 4034 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 4035 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4036 hsotg->hfnum_other_samples, 4037 hsotg->hfnum_other_frrem_accum, 4038 hsotg->hfnum_other_samples > 0 ? 4039 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 4040 0); 4041 dev_dbg(hsotg->dev, "\n"); 4042 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 4043 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4044 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 4045 hsotg->hfnum_7_samples_a > 0 ? 4046 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 4047 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 4048 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4049 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 4050 hsotg->hfnum_0_samples_a > 0 ? 4051 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 4052 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 4053 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4054 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 4055 hsotg->hfnum_other_samples_a > 0 ? 4056 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 4057 : 0); 4058 dev_dbg(hsotg->dev, "\n"); 4059 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 4060 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4061 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 4062 hsotg->hfnum_7_samples_b > 0 ? 4063 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 4064 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 4065 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4066 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 4067 (hsotg->hfnum_0_samples_b > 0) ? 4068 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 4069 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 4070 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 4071 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 4072 (hsotg->hfnum_other_samples_b > 0) ? 4073 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 4074 : 0); 4075 #endif 4076 } 4077 4078 struct wrapper_priv_data { 4079 struct dwc2_hsotg *hsotg; 4080 }; 4081 4082 /* Gets the dwc2_hsotg from a usb_hcd */ 4083 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4084 { 4085 struct wrapper_priv_data *p; 4086 4087 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4088 return p->hsotg; 4089 } 4090 4091 /** 4092 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4093 * 4094 * This will get the dwc2_tt structure (and ttport) associated with the given 4095 * context (which is really just a struct urb pointer). 4096 * 4097 * The first time this is called for a given TT we allocate memory for our 4098 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4099 * then the refcount for the structure will go to 0 and we'll free it. 4100 * 4101 * @hsotg: The HCD state structure for the DWC OTG controller. 4102 * @qh: The QH structure. 4103 * @context: The priv pointer from a struct dwc2_hcd_urb. 4104 * @mem_flags: Flags for allocating memory. 4105 * @ttport: We'll return this device's port number here. That's used to 4106 * reference into the bitmap if we're on a multi_tt hub. 4107 * 4108 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4109 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4110 */ 4111 4112 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4113 gfp_t mem_flags, int *ttport) 4114 { 4115 struct urb *urb = context; 4116 struct dwc2_tt *dwc_tt = NULL; 4117 4118 if (urb->dev->tt) { 4119 *ttport = urb->dev->ttport; 4120 4121 dwc_tt = urb->dev->tt->hcpriv; 4122 if (!dwc_tt) { 4123 size_t bitmap_size; 4124 4125 /* 4126 * For single_tt we need one schedule. For multi_tt 4127 * we need one per port. 4128 */ 4129 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4130 sizeof(dwc_tt->periodic_bitmaps[0]); 4131 if (urb->dev->tt->multi) 4132 bitmap_size *= urb->dev->tt->hub->maxchild; 4133 4134 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4135 mem_flags); 4136 if (!dwc_tt) 4137 return NULL; 4138 4139 dwc_tt->usb_tt = urb->dev->tt; 4140 dwc_tt->usb_tt->hcpriv = dwc_tt; 4141 } 4142 4143 dwc_tt->refcount++; 4144 } 4145 4146 return dwc_tt; 4147 } 4148 4149 /** 4150 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4151 * 4152 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4153 * of the structure are done. 4154 * 4155 * It's OK to call this with NULL. 4156 * 4157 * @hsotg: The HCD state structure for the DWC OTG controller. 4158 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4159 */ 4160 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4161 { 4162 /* Model kfree and make put of NULL a no-op */ 4163 if (!dwc_tt) 4164 return; 4165 4166 WARN_ON(dwc_tt->refcount < 1); 4167 4168 dwc_tt->refcount--; 4169 if (!dwc_tt->refcount) { 4170 dwc_tt->usb_tt->hcpriv = NULL; 4171 kfree(dwc_tt); 4172 } 4173 } 4174 4175 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4176 { 4177 struct urb *urb = context; 4178 4179 return urb->dev->speed; 4180 } 4181 4182 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4183 struct urb *urb) 4184 { 4185 struct usb_bus *bus = hcd_to_bus(hcd); 4186 4187 if (urb->interval) 4188 bus->bandwidth_allocated += bw / urb->interval; 4189 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4190 bus->bandwidth_isoc_reqs++; 4191 else 4192 bus->bandwidth_int_reqs++; 4193 } 4194 4195 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4196 struct urb *urb) 4197 { 4198 struct usb_bus *bus = hcd_to_bus(hcd); 4199 4200 if (urb->interval) 4201 bus->bandwidth_allocated -= bw / urb->interval; 4202 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4203 bus->bandwidth_isoc_reqs--; 4204 else 4205 bus->bandwidth_int_reqs--; 4206 } 4207 4208 /* 4209 * Sets the final status of an URB and returns it to the upper layer. Any 4210 * required cleanup of the URB is performed. 4211 * 4212 * Must be called with interrupt disabled and spinlock held 4213 */ 4214 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4215 int status) 4216 { 4217 struct urb *urb; 4218 int i; 4219 4220 if (!qtd) { 4221 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4222 return; 4223 } 4224 4225 if (!qtd->urb) { 4226 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4227 return; 4228 } 4229 4230 urb = qtd->urb->priv; 4231 if (!urb) { 4232 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4233 return; 4234 } 4235 4236 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4237 4238 if (dbg_urb(urb)) 4239 dev_vdbg(hsotg->dev, 4240 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4241 __func__, urb, usb_pipedevice(urb->pipe), 4242 usb_pipeendpoint(urb->pipe), 4243 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4244 urb->actual_length); 4245 4246 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4247 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4248 for (i = 0; i < urb->number_of_packets; ++i) { 4249 urb->iso_frame_desc[i].actual_length = 4250 dwc2_hcd_urb_get_iso_desc_actual_length( 4251 qtd->urb, i); 4252 urb->iso_frame_desc[i].status = 4253 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4254 } 4255 } 4256 4257 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4258 for (i = 0; i < urb->number_of_packets; i++) 4259 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4260 i, urb->iso_frame_desc[i].status); 4261 } 4262 4263 urb->status = status; 4264 if (!status) { 4265 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4266 urb->actual_length < urb->transfer_buffer_length) 4267 urb->status = -EREMOTEIO; 4268 } 4269 4270 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4271 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4272 struct usb_host_endpoint *ep = urb->ep; 4273 4274 if (ep) 4275 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4276 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4277 urb); 4278 } 4279 4280 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4281 urb->hcpriv = NULL; 4282 kfree(qtd->urb); 4283 qtd->urb = NULL; 4284 4285 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4286 } 4287 4288 /* 4289 * Work queue function for starting the HCD when A-Cable is connected 4290 */ 4291 static void dwc2_hcd_start_func(struct work_struct *work) 4292 { 4293 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4294 start_work.work); 4295 4296 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4297 dwc2_host_start(hsotg); 4298 } 4299 4300 /* 4301 * Reset work queue function 4302 */ 4303 static void dwc2_hcd_reset_func(struct work_struct *work) 4304 { 4305 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4306 reset_work.work); 4307 unsigned long flags; 4308 u32 hprt0; 4309 4310 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4311 4312 spin_lock_irqsave(&hsotg->lock, flags); 4313 4314 hprt0 = dwc2_read_hprt0(hsotg); 4315 hprt0 &= ~HPRT0_RST; 4316 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4317 hsotg->flags.b.port_reset_change = 1; 4318 4319 spin_unlock_irqrestore(&hsotg->lock, flags); 4320 } 4321 4322 /* 4323 * ========================================================================= 4324 * Linux HC Driver Functions 4325 * ========================================================================= 4326 */ 4327 4328 /* 4329 * Initializes the DWC_otg controller and its root hub and prepares it for host 4330 * mode operation. Activates the root port. Returns 0 on success and a negative 4331 * error code on failure. 4332 */ 4333 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4334 { 4335 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4336 struct usb_bus *bus = hcd_to_bus(hcd); 4337 unsigned long flags; 4338 4339 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4340 4341 spin_lock_irqsave(&hsotg->lock, flags); 4342 hsotg->lx_state = DWC2_L0; 4343 hcd->state = HC_STATE_RUNNING; 4344 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4345 4346 if (dwc2_is_device_mode(hsotg)) { 4347 spin_unlock_irqrestore(&hsotg->lock, flags); 4348 return 0; /* why 0 ?? */ 4349 } 4350 4351 dwc2_hcd_reinit(hsotg); 4352 4353 /* Initialize and connect root hub if one is not already attached */ 4354 if (bus->root_hub) { 4355 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4356 /* Inform the HUB driver to resume */ 4357 usb_hcd_resume_root_hub(hcd); 4358 } 4359 4360 spin_unlock_irqrestore(&hsotg->lock, flags); 4361 return 0; 4362 } 4363 4364 /* 4365 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4366 * stopped. 4367 */ 4368 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4369 { 4370 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4371 unsigned long flags; 4372 4373 /* Turn off all host-specific interrupts */ 4374 dwc2_disable_host_interrupts(hsotg); 4375 4376 /* Wait for interrupt processing to finish */ 4377 synchronize_irq(hcd->irq); 4378 4379 spin_lock_irqsave(&hsotg->lock, flags); 4380 /* Ensure hcd is disconnected */ 4381 dwc2_hcd_disconnect(hsotg, true); 4382 dwc2_hcd_stop(hsotg); 4383 hsotg->lx_state = DWC2_L3; 4384 hcd->state = HC_STATE_HALT; 4385 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4386 spin_unlock_irqrestore(&hsotg->lock, flags); 4387 4388 usleep_range(1000, 3000); 4389 } 4390 4391 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4392 { 4393 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4394 unsigned long flags; 4395 int ret = 0; 4396 u32 hprt0; 4397 4398 spin_lock_irqsave(&hsotg->lock, flags); 4399 4400 if (dwc2_is_device_mode(hsotg)) 4401 goto unlock; 4402 4403 if (hsotg->lx_state != DWC2_L0) 4404 goto unlock; 4405 4406 if (!HCD_HW_ACCESSIBLE(hcd)) 4407 goto unlock; 4408 4409 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4410 goto unlock; 4411 4412 if (!hsotg->params.hibernation) 4413 goto skip_power_saving; 4414 4415 /* 4416 * Drive USB suspend and disable port Power 4417 * if usb bus is not suspended. 4418 */ 4419 if (!hsotg->bus_suspended) { 4420 hprt0 = dwc2_read_hprt0(hsotg); 4421 hprt0 |= HPRT0_SUSP; 4422 hprt0 &= ~HPRT0_PWR; 4423 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4424 } 4425 4426 /* Enter hibernation */ 4427 ret = dwc2_enter_hibernation(hsotg); 4428 if (ret) { 4429 if (ret != -ENOTSUPP) 4430 dev_err(hsotg->dev, 4431 "enter hibernation failed\n"); 4432 goto skip_power_saving; 4433 } 4434 4435 /* Ask phy to be suspended */ 4436 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4437 spin_unlock_irqrestore(&hsotg->lock, flags); 4438 usb_phy_set_suspend(hsotg->uphy, true); 4439 spin_lock_irqsave(&hsotg->lock, flags); 4440 } 4441 4442 /* After entering hibernation, hardware is no more accessible */ 4443 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4444 4445 skip_power_saving: 4446 hsotg->lx_state = DWC2_L2; 4447 unlock: 4448 spin_unlock_irqrestore(&hsotg->lock, flags); 4449 4450 return ret; 4451 } 4452 4453 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4454 { 4455 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4456 unsigned long flags; 4457 int ret = 0; 4458 4459 spin_lock_irqsave(&hsotg->lock, flags); 4460 4461 if (dwc2_is_device_mode(hsotg)) 4462 goto unlock; 4463 4464 if (hsotg->lx_state != DWC2_L2) 4465 goto unlock; 4466 4467 if (!hsotg->params.hibernation) { 4468 hsotg->lx_state = DWC2_L0; 4469 goto unlock; 4470 } 4471 4472 /* 4473 * Set HW accessible bit before powering on the controller 4474 * since an interrupt may rise. 4475 */ 4476 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4477 4478 /* 4479 * Enable power if not already done. 4480 * This must not be spinlocked since duration 4481 * of this call is unknown. 4482 */ 4483 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4484 spin_unlock_irqrestore(&hsotg->lock, flags); 4485 usb_phy_set_suspend(hsotg->uphy, false); 4486 spin_lock_irqsave(&hsotg->lock, flags); 4487 } 4488 4489 /* Exit hibernation */ 4490 ret = dwc2_exit_hibernation(hsotg, true); 4491 if (ret && (ret != -ENOTSUPP)) 4492 dev_err(hsotg->dev, "exit hibernation failed\n"); 4493 4494 hsotg->lx_state = DWC2_L0; 4495 4496 spin_unlock_irqrestore(&hsotg->lock, flags); 4497 4498 if (hsotg->bus_suspended) { 4499 spin_lock_irqsave(&hsotg->lock, flags); 4500 hsotg->flags.b.port_suspend_change = 1; 4501 spin_unlock_irqrestore(&hsotg->lock, flags); 4502 dwc2_port_resume(hsotg); 4503 } else { 4504 /* Wait for controller to correctly update D+/D- level */ 4505 usleep_range(3000, 5000); 4506 4507 /* 4508 * Clear Port Enable and Port Status changes. 4509 * Enable Port Power. 4510 */ 4511 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4512 HPRT0_ENACHG, hsotg->regs + HPRT0); 4513 /* Wait for controller to detect Port Connect */ 4514 usleep_range(5000, 7000); 4515 } 4516 4517 return ret; 4518 unlock: 4519 spin_unlock_irqrestore(&hsotg->lock, flags); 4520 4521 return ret; 4522 } 4523 4524 /* Returns the current frame number */ 4525 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4526 { 4527 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4528 4529 return dwc2_hcd_get_frame_number(hsotg); 4530 } 4531 4532 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4533 char *fn_name) 4534 { 4535 #ifdef VERBOSE_DEBUG 4536 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4537 char *pipetype = NULL; 4538 char *speed = NULL; 4539 4540 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4541 dev_vdbg(hsotg->dev, " Device address: %d\n", 4542 usb_pipedevice(urb->pipe)); 4543 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4544 usb_pipeendpoint(urb->pipe), 4545 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4546 4547 switch (usb_pipetype(urb->pipe)) { 4548 case PIPE_CONTROL: 4549 pipetype = "CONTROL"; 4550 break; 4551 case PIPE_BULK: 4552 pipetype = "BULK"; 4553 break; 4554 case PIPE_INTERRUPT: 4555 pipetype = "INTERRUPT"; 4556 break; 4557 case PIPE_ISOCHRONOUS: 4558 pipetype = "ISOCHRONOUS"; 4559 break; 4560 } 4561 4562 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4563 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4564 "IN" : "OUT"); 4565 4566 switch (urb->dev->speed) { 4567 case USB_SPEED_HIGH: 4568 speed = "HIGH"; 4569 break; 4570 case USB_SPEED_FULL: 4571 speed = "FULL"; 4572 break; 4573 case USB_SPEED_LOW: 4574 speed = "LOW"; 4575 break; 4576 default: 4577 speed = "UNKNOWN"; 4578 break; 4579 } 4580 4581 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4582 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4583 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4584 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4585 urb->transfer_buffer_length); 4586 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4587 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4588 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4589 urb->setup_packet, (unsigned long)urb->setup_dma); 4590 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4591 4592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4593 int i; 4594 4595 for (i = 0; i < urb->number_of_packets; i++) { 4596 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4597 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4598 urb->iso_frame_desc[i].offset, 4599 urb->iso_frame_desc[i].length); 4600 } 4601 } 4602 #endif 4603 } 4604 4605 /* 4606 * Starts processing a USB transfer request specified by a USB Request Block 4607 * (URB). mem_flags indicates the type of memory allocation to use while 4608 * processing this URB. 4609 */ 4610 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4611 gfp_t mem_flags) 4612 { 4613 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4614 struct usb_host_endpoint *ep = urb->ep; 4615 struct dwc2_hcd_urb *dwc2_urb; 4616 int i; 4617 int retval; 4618 int alloc_bandwidth = 0; 4619 u8 ep_type = 0; 4620 u32 tflags = 0; 4621 void *buf; 4622 unsigned long flags; 4623 struct dwc2_qh *qh; 4624 bool qh_allocated = false; 4625 struct dwc2_qtd *qtd; 4626 4627 if (dbg_urb(urb)) { 4628 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4629 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4630 } 4631 4632 if (!ep) 4633 return -EINVAL; 4634 4635 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4636 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4637 spin_lock_irqsave(&hsotg->lock, flags); 4638 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4639 alloc_bandwidth = 1; 4640 spin_unlock_irqrestore(&hsotg->lock, flags); 4641 } 4642 4643 switch (usb_pipetype(urb->pipe)) { 4644 case PIPE_CONTROL: 4645 ep_type = USB_ENDPOINT_XFER_CONTROL; 4646 break; 4647 case PIPE_ISOCHRONOUS: 4648 ep_type = USB_ENDPOINT_XFER_ISOC; 4649 break; 4650 case PIPE_BULK: 4651 ep_type = USB_ENDPOINT_XFER_BULK; 4652 break; 4653 case PIPE_INTERRUPT: 4654 ep_type = USB_ENDPOINT_XFER_INT; 4655 break; 4656 } 4657 4658 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4659 mem_flags); 4660 if (!dwc2_urb) 4661 return -ENOMEM; 4662 4663 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4664 usb_pipeendpoint(urb->pipe), ep_type, 4665 usb_pipein(urb->pipe), 4666 usb_maxpacket(urb->dev, urb->pipe, 4667 !(usb_pipein(urb->pipe)))); 4668 4669 buf = urb->transfer_buffer; 4670 4671 if (hcd->self.uses_dma) { 4672 if (!buf && (urb->transfer_dma & 3)) { 4673 dev_err(hsotg->dev, 4674 "%s: unaligned transfer with no transfer_buffer", 4675 __func__); 4676 retval = -EINVAL; 4677 goto fail0; 4678 } 4679 } 4680 4681 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4682 tflags |= URB_GIVEBACK_ASAP; 4683 if (urb->transfer_flags & URB_ZERO_PACKET) 4684 tflags |= URB_SEND_ZERO_PACKET; 4685 4686 dwc2_urb->priv = urb; 4687 dwc2_urb->buf = buf; 4688 dwc2_urb->dma = urb->transfer_dma; 4689 dwc2_urb->length = urb->transfer_buffer_length; 4690 dwc2_urb->setup_packet = urb->setup_packet; 4691 dwc2_urb->setup_dma = urb->setup_dma; 4692 dwc2_urb->flags = tflags; 4693 dwc2_urb->interval = urb->interval; 4694 dwc2_urb->status = -EINPROGRESS; 4695 4696 for (i = 0; i < urb->number_of_packets; ++i) 4697 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4698 urb->iso_frame_desc[i].offset, 4699 urb->iso_frame_desc[i].length); 4700 4701 urb->hcpriv = dwc2_urb; 4702 qh = (struct dwc2_qh *)ep->hcpriv; 4703 /* Create QH for the endpoint if it doesn't exist */ 4704 if (!qh) { 4705 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4706 if (!qh) { 4707 retval = -ENOMEM; 4708 goto fail0; 4709 } 4710 ep->hcpriv = qh; 4711 qh_allocated = true; 4712 } 4713 4714 qtd = kzalloc(sizeof(*qtd), mem_flags); 4715 if (!qtd) { 4716 retval = -ENOMEM; 4717 goto fail1; 4718 } 4719 4720 spin_lock_irqsave(&hsotg->lock, flags); 4721 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4722 if (retval) 4723 goto fail2; 4724 4725 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4726 if (retval) 4727 goto fail3; 4728 4729 if (alloc_bandwidth) { 4730 dwc2_allocate_bus_bandwidth(hcd, 4731 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4732 urb); 4733 } 4734 4735 spin_unlock_irqrestore(&hsotg->lock, flags); 4736 4737 return 0; 4738 4739 fail3: 4740 dwc2_urb->priv = NULL; 4741 usb_hcd_unlink_urb_from_ep(hcd, urb); 4742 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4743 qh->channel->qh = NULL; 4744 fail2: 4745 spin_unlock_irqrestore(&hsotg->lock, flags); 4746 urb->hcpriv = NULL; 4747 kfree(qtd); 4748 qtd = NULL; 4749 fail1: 4750 if (qh_allocated) { 4751 struct dwc2_qtd *qtd2, *qtd2_tmp; 4752 4753 ep->hcpriv = NULL; 4754 dwc2_hcd_qh_unlink(hsotg, qh); 4755 /* Free each QTD in the QH's QTD list */ 4756 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4757 qtd_list_entry) 4758 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4759 dwc2_hcd_qh_free(hsotg, qh); 4760 } 4761 fail0: 4762 kfree(dwc2_urb); 4763 4764 return retval; 4765 } 4766 4767 /* 4768 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4769 */ 4770 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4771 int status) 4772 { 4773 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4774 int rc; 4775 unsigned long flags; 4776 4777 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4778 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4779 4780 spin_lock_irqsave(&hsotg->lock, flags); 4781 4782 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4783 if (rc) 4784 goto out; 4785 4786 if (!urb->hcpriv) { 4787 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4788 goto out; 4789 } 4790 4791 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4792 4793 usb_hcd_unlink_urb_from_ep(hcd, urb); 4794 4795 kfree(urb->hcpriv); 4796 urb->hcpriv = NULL; 4797 4798 /* Higher layer software sets URB status */ 4799 spin_unlock(&hsotg->lock); 4800 usb_hcd_giveback_urb(hcd, urb, status); 4801 spin_lock(&hsotg->lock); 4802 4803 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4804 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4805 out: 4806 spin_unlock_irqrestore(&hsotg->lock, flags); 4807 4808 return rc; 4809 } 4810 4811 /* 4812 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4813 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4814 * must already be dequeued. 4815 */ 4816 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4817 struct usb_host_endpoint *ep) 4818 { 4819 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4820 4821 dev_dbg(hsotg->dev, 4822 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4823 ep->desc.bEndpointAddress, ep->hcpriv); 4824 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4825 } 4826 4827 /* 4828 * Resets endpoint specific parameter values, in current version used to reset 4829 * the data toggle (as a WA). This function can be called from usb_clear_halt 4830 * routine. 4831 */ 4832 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4833 struct usb_host_endpoint *ep) 4834 { 4835 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4836 unsigned long flags; 4837 4838 dev_dbg(hsotg->dev, 4839 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4840 ep->desc.bEndpointAddress); 4841 4842 spin_lock_irqsave(&hsotg->lock, flags); 4843 dwc2_hcd_endpoint_reset(hsotg, ep); 4844 spin_unlock_irqrestore(&hsotg->lock, flags); 4845 } 4846 4847 /* 4848 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4849 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4850 * interrupt. 4851 * 4852 * This function is called by the USB core when an interrupt occurs 4853 */ 4854 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4855 { 4856 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4857 4858 return dwc2_handle_hcd_intr(hsotg); 4859 } 4860 4861 /* 4862 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4863 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4864 * is the status change indicator for the single root port. Returns 1 if either 4865 * change indicator is 1, otherwise returns 0. 4866 */ 4867 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4868 { 4869 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4870 4871 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4872 return buf[0] != 0; 4873 } 4874 4875 /* Handles hub class-specific requests */ 4876 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4877 u16 windex, char *buf, u16 wlength) 4878 { 4879 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4880 wvalue, windex, buf, wlength); 4881 return retval; 4882 } 4883 4884 /* Handles hub TT buffer clear completions */ 4885 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4886 struct usb_host_endpoint *ep) 4887 { 4888 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4889 struct dwc2_qh *qh; 4890 unsigned long flags; 4891 4892 qh = ep->hcpriv; 4893 if (!qh) 4894 return; 4895 4896 spin_lock_irqsave(&hsotg->lock, flags); 4897 qh->tt_buffer_dirty = 0; 4898 4899 if (hsotg->flags.b.port_connect_status) 4900 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4901 4902 spin_unlock_irqrestore(&hsotg->lock, flags); 4903 } 4904 4905 /* 4906 * HPRT0_SPD_HIGH_SPEED: high speed 4907 * HPRT0_SPD_FULL_SPEED: full speed 4908 */ 4909 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4910 { 4911 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4912 4913 if (hsotg->params.speed == speed) 4914 return; 4915 4916 hsotg->params.speed = speed; 4917 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4918 } 4919 4920 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4921 { 4922 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4923 4924 if (!hsotg->params.change_speed_quirk) 4925 return; 4926 4927 /* 4928 * On removal, set speed to default high-speed. 4929 */ 4930 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4931 udev->parent->speed < USB_SPEED_HIGH) { 4932 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4933 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4934 } 4935 } 4936 4937 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 4938 { 4939 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4940 4941 if (!hsotg->params.change_speed_quirk) 4942 return 0; 4943 4944 if (udev->speed == USB_SPEED_HIGH) { 4945 dev_info(hsotg->dev, "Set speed to high-speed\n"); 4946 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4947 } else if ((udev->speed == USB_SPEED_FULL || 4948 udev->speed == USB_SPEED_LOW)) { 4949 /* 4950 * Change speed setting to full-speed if there's 4951 * a full-speed or low-speed device plugged in. 4952 */ 4953 dev_info(hsotg->dev, "Set speed to full-speed\n"); 4954 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 4955 } 4956 4957 return 0; 4958 } 4959 4960 static struct hc_driver dwc2_hc_driver = { 4961 .description = "dwc2_hsotg", 4962 .product_desc = "DWC OTG Controller", 4963 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4964 4965 .irq = _dwc2_hcd_irq, 4966 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4967 4968 .start = _dwc2_hcd_start, 4969 .stop = _dwc2_hcd_stop, 4970 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4971 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4972 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4973 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4974 .get_frame_number = _dwc2_hcd_get_frame_number, 4975 4976 .hub_status_data = _dwc2_hcd_hub_status_data, 4977 .hub_control = _dwc2_hcd_hub_control, 4978 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4979 4980 .bus_suspend = _dwc2_hcd_suspend, 4981 .bus_resume = _dwc2_hcd_resume, 4982 4983 .map_urb_for_dma = dwc2_map_urb_for_dma, 4984 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4985 }; 4986 4987 /* 4988 * Frees secondary storage associated with the dwc2_hsotg structure contained 4989 * in the struct usb_hcd field 4990 */ 4991 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4992 { 4993 u32 ahbcfg; 4994 u32 dctl; 4995 int i; 4996 4997 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4998 4999 /* Free memory for QH/QTD lists */ 5000 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 5001 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 5002 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 5003 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 5004 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 5005 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 5006 5007 /* Free memory for the host channels */ 5008 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 5009 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 5010 5011 if (chan) { 5012 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 5013 i, chan); 5014 hsotg->hc_ptr_array[i] = NULL; 5015 kfree(chan); 5016 } 5017 } 5018 5019 if (hsotg->params.host_dma) { 5020 if (hsotg->status_buf) { 5021 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 5022 hsotg->status_buf, 5023 hsotg->status_buf_dma); 5024 hsotg->status_buf = NULL; 5025 } 5026 } else { 5027 kfree(hsotg->status_buf); 5028 hsotg->status_buf = NULL; 5029 } 5030 5031 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 5032 5033 /* Disable all interrupts */ 5034 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 5035 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 5036 dwc2_writel(0, hsotg->regs + GINTMSK); 5037 5038 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 5039 dctl = dwc2_readl(hsotg->regs + DCTL); 5040 dctl |= DCTL_SFTDISCON; 5041 dwc2_writel(dctl, hsotg->regs + DCTL); 5042 } 5043 5044 if (hsotg->wq_otg) { 5045 if (!cancel_work_sync(&hsotg->wf_otg)) 5046 flush_workqueue(hsotg->wq_otg); 5047 destroy_workqueue(hsotg->wq_otg); 5048 } 5049 5050 del_timer(&hsotg->wkp_timer); 5051 } 5052 5053 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5054 { 5055 /* Turn off all host-specific interrupts */ 5056 dwc2_disable_host_interrupts(hsotg); 5057 5058 dwc2_hcd_free(hsotg); 5059 } 5060 5061 /* 5062 * Initializes the HCD. This function allocates memory for and initializes the 5063 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5064 * USB bus with the core and calls the hc_driver->start() function. It returns 5065 * a negative error on failure. 5066 */ 5067 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5068 { 5069 struct platform_device *pdev = to_platform_device(hsotg->dev); 5070 struct resource *res; 5071 struct usb_hcd *hcd; 5072 struct dwc2_host_chan *channel; 5073 u32 hcfg; 5074 int i, num_channels; 5075 int retval; 5076 5077 if (usb_disabled()) 5078 return -ENODEV; 5079 5080 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5081 5082 retval = -ENOMEM; 5083 5084 hcfg = dwc2_readl(hsotg->regs + HCFG); 5085 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5086 5087 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5088 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 5089 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5090 if (!hsotg->frame_num_array) 5091 goto error1; 5092 hsotg->last_frame_num_array = kzalloc( 5093 sizeof(*hsotg->last_frame_num_array) * 5094 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5095 if (!hsotg->last_frame_num_array) 5096 goto error1; 5097 #endif 5098 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5099 5100 /* Check if the bus driver or platform code has setup a dma_mask */ 5101 if (hsotg->params.host_dma && 5102 !hsotg->dev->dma_mask) { 5103 dev_warn(hsotg->dev, 5104 "dma_mask not set, disabling DMA\n"); 5105 hsotg->params.host_dma = false; 5106 hsotg->params.dma_desc_enable = false; 5107 } 5108 5109 /* Set device flags indicating whether the HCD supports DMA */ 5110 if (hsotg->params.host_dma) { 5111 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5112 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5113 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5114 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5115 } 5116 5117 if (hsotg->params.change_speed_quirk) { 5118 dwc2_hc_driver.free_dev = dwc2_free_dev; 5119 dwc2_hc_driver.reset_device = dwc2_reset_device; 5120 } 5121 5122 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5123 if (!hcd) 5124 goto error1; 5125 5126 if (!hsotg->params.host_dma) 5127 hcd->self.uses_dma = 0; 5128 5129 hcd->has_tt = 1; 5130 5131 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5132 hcd->rsrc_start = res->start; 5133 hcd->rsrc_len = resource_size(res); 5134 5135 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5136 hsotg->priv = hcd; 5137 5138 /* 5139 * Disable the global interrupt until all the interrupt handlers are 5140 * installed 5141 */ 5142 dwc2_disable_global_interrupts(hsotg); 5143 5144 /* Initialize the DWC_otg core, and select the Phy type */ 5145 retval = dwc2_core_init(hsotg, true); 5146 if (retval) 5147 goto error2; 5148 5149 /* Create new workqueue and init work */ 5150 retval = -ENOMEM; 5151 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5152 if (!hsotg->wq_otg) { 5153 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5154 goto error2; 5155 } 5156 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5157 5158 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); 5159 5160 /* Initialize the non-periodic schedule */ 5161 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5162 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5163 5164 /* Initialize the periodic schedule */ 5165 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5166 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5167 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5168 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5169 5170 INIT_LIST_HEAD(&hsotg->split_order); 5171 5172 /* 5173 * Create a host channel descriptor for each host channel implemented 5174 * in the controller. Initialize the channel descriptor array. 5175 */ 5176 INIT_LIST_HEAD(&hsotg->free_hc_list); 5177 num_channels = hsotg->params.host_channels; 5178 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5179 5180 for (i = 0; i < num_channels; i++) { 5181 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5182 if (!channel) 5183 goto error3; 5184 channel->hc_num = i; 5185 INIT_LIST_HEAD(&channel->split_order_list_entry); 5186 hsotg->hc_ptr_array[i] = channel; 5187 } 5188 5189 /* Initialize hsotg start work */ 5190 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5191 5192 /* Initialize port reset work */ 5193 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5194 5195 /* 5196 * Allocate space for storing data on status transactions. Normally no 5197 * data is sent, but this space acts as a bit bucket. This must be 5198 * done after usb_add_hcd since that function allocates the DMA buffer 5199 * pool. 5200 */ 5201 if (hsotg->params.host_dma) 5202 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5203 DWC2_HCD_STATUS_BUF_SIZE, 5204 &hsotg->status_buf_dma, GFP_KERNEL); 5205 else 5206 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5207 GFP_KERNEL); 5208 5209 if (!hsotg->status_buf) 5210 goto error3; 5211 5212 /* 5213 * Create kmem caches to handle descriptor buffers in descriptor 5214 * DMA mode. 5215 * Alignment must be set to 512 bytes. 5216 */ 5217 if (hsotg->params.dma_desc_enable || 5218 hsotg->params.dma_desc_fs_enable) { 5219 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5220 sizeof(struct dwc2_dma_desc) * 5221 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5222 NULL); 5223 if (!hsotg->desc_gen_cache) { 5224 dev_err(hsotg->dev, 5225 "unable to create dwc2 generic desc cache\n"); 5226 5227 /* 5228 * Disable descriptor dma mode since it will not be 5229 * usable. 5230 */ 5231 hsotg->params.dma_desc_enable = false; 5232 hsotg->params.dma_desc_fs_enable = false; 5233 } 5234 5235 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5236 sizeof(struct dwc2_dma_desc) * 5237 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5238 if (!hsotg->desc_hsisoc_cache) { 5239 dev_err(hsotg->dev, 5240 "unable to create dwc2 hs isoc desc cache\n"); 5241 5242 kmem_cache_destroy(hsotg->desc_gen_cache); 5243 5244 /* 5245 * Disable descriptor dma mode since it will not be 5246 * usable. 5247 */ 5248 hsotg->params.dma_desc_enable = false; 5249 hsotg->params.dma_desc_fs_enable = false; 5250 } 5251 } 5252 5253 hsotg->otg_port = 1; 5254 hsotg->frame_list = NULL; 5255 hsotg->frame_list_dma = 0; 5256 hsotg->periodic_qh_count = 0; 5257 5258 /* Initiate lx_state to L3 disconnected state */ 5259 hsotg->lx_state = DWC2_L3; 5260 5261 hcd->self.otg_port = hsotg->otg_port; 5262 5263 /* Don't support SG list at this point */ 5264 hcd->self.sg_tablesize = 0; 5265 5266 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5267 otg_set_host(hsotg->uphy->otg, &hcd->self); 5268 5269 /* 5270 * Finish generic HCD initialization and start the HCD. This function 5271 * allocates the DMA buffer pool, registers the USB bus, requests the 5272 * IRQ line, and calls hcd_start method. 5273 */ 5274 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5275 if (retval < 0) 5276 goto error4; 5277 5278 device_wakeup_enable(hcd->self.controller); 5279 5280 dwc2_hcd_dump_state(hsotg); 5281 5282 dwc2_enable_global_interrupts(hsotg); 5283 5284 return 0; 5285 5286 error4: 5287 kmem_cache_destroy(hsotg->desc_gen_cache); 5288 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5289 error3: 5290 dwc2_hcd_release(hsotg); 5291 error2: 5292 usb_put_hcd(hcd); 5293 error1: 5294 5295 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5296 kfree(hsotg->last_frame_num_array); 5297 kfree(hsotg->frame_num_array); 5298 #endif 5299 5300 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5301 return retval; 5302 } 5303 5304 /* 5305 * Removes the HCD. 5306 * Frees memory and resources associated with the HCD and deregisters the bus. 5307 */ 5308 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5309 { 5310 struct usb_hcd *hcd; 5311 5312 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5313 5314 hcd = dwc2_hsotg_to_hcd(hsotg); 5315 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5316 5317 if (!hcd) { 5318 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5319 __func__); 5320 return; 5321 } 5322 5323 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5324 otg_set_host(hsotg->uphy->otg, NULL); 5325 5326 usb_remove_hcd(hcd); 5327 hsotg->priv = NULL; 5328 5329 kmem_cache_destroy(hsotg->desc_gen_cache); 5330 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5331 5332 dwc2_hcd_release(hsotg); 5333 usb_put_hcd(hcd); 5334 5335 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5336 kfree(hsotg->last_frame_num_array); 5337 kfree(hsotg->frame_num_array); 5338 #endif 5339 } 5340 5341 /** 5342 * dwc2_backup_host_registers() - Backup controller host registers. 5343 * When suspending usb bus, registers needs to be backuped 5344 * if controller power is disabled once suspended. 5345 * 5346 * @hsotg: Programming view of the DWC_otg controller 5347 */ 5348 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5349 { 5350 struct dwc2_hregs_backup *hr; 5351 int i; 5352 5353 dev_dbg(hsotg->dev, "%s\n", __func__); 5354 5355 /* Backup Host regs */ 5356 hr = &hsotg->hr_backup; 5357 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5358 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5359 for (i = 0; i < hsotg->params.host_channels; ++i) 5360 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5361 5362 hr->hprt0 = dwc2_read_hprt0(hsotg); 5363 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5364 hr->valid = true; 5365 5366 return 0; 5367 } 5368 5369 /** 5370 * dwc2_restore_host_registers() - Restore controller host registers. 5371 * When resuming usb bus, device registers needs to be restored 5372 * if controller power were disabled. 5373 * 5374 * @hsotg: Programming view of the DWC_otg controller 5375 */ 5376 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5377 { 5378 struct dwc2_hregs_backup *hr; 5379 int i; 5380 5381 dev_dbg(hsotg->dev, "%s\n", __func__); 5382 5383 /* Restore host regs */ 5384 hr = &hsotg->hr_backup; 5385 if (!hr->valid) { 5386 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5387 __func__); 5388 return -EINVAL; 5389 } 5390 hr->valid = false; 5391 5392 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5393 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5394 5395 for (i = 0; i < hsotg->params.host_channels; ++i) 5396 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5397 5398 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5399 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5400 hsotg->frame_number = 0; 5401 5402 return 0; 5403 } 5404