1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173 } 174 175 /* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184 { 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191 } 192 193 /** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199 { 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 dwc2_writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215 } 216 217 /* Must be called with interrupt disabled and spinlock held */ 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219 { 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260 /* All channels have been freed, mark them available */ 261 if (hsotg->core_params->uframe_sched > 0) { 262 hsotg->available_host_channels = 263 hsotg->core_params->host_channels; 264 } else { 265 hsotg->non_periodic_channels = 0; 266 hsotg->periodic_channels = 0; 267 } 268 } 269 270 /** 271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 272 * 273 * @hsotg: Pointer to struct dwc2_hsotg 274 * 275 * Must be called with interrupt disabled and spinlock held 276 */ 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 278 { 279 u32 intr; 280 281 /* Set status flags for the hub driver */ 282 hsotg->flags.b.port_connect_status_change = 1; 283 hsotg->flags.b.port_connect_status = 0; 284 285 /* 286 * Shutdown any transfers in process by clearing the Tx FIFO Empty 287 * interrupt mask and status bits and disabling subsequent host 288 * channel interrupts. 289 */ 290 intr = dwc2_readl(hsotg->regs + GINTMSK); 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 292 dwc2_writel(intr, hsotg->regs + GINTMSK); 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 294 dwc2_writel(intr, hsotg->regs + GINTSTS); 295 296 /* 297 * Turn off the vbus power only if the core has transitioned to device 298 * mode. If still in host mode, need to keep power on to detect a 299 * reconnection. 300 */ 301 if (dwc2_is_device_mode(hsotg)) { 302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 304 dwc2_writel(0, hsotg->regs + HPRT0); 305 } 306 307 dwc2_disable_host_interrupts(hsotg); 308 } 309 310 /* Respond with an error status to all URBs in the schedule */ 311 dwc2_kill_all_urbs(hsotg); 312 313 if (dwc2_is_host_mode(hsotg)) 314 /* Clean up any host channels that were in use */ 315 dwc2_hcd_cleanup_channels(hsotg); 316 317 dwc2_host_disconnect(hsotg); 318 } 319 320 /** 321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 322 * 323 * @hsotg: Pointer to struct dwc2_hsotg 324 */ 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 326 { 327 if (hsotg->lx_state == DWC2_L2) { 328 hsotg->flags.b.port_suspend_change = 1; 329 usb_hcd_resume_root_hub(hsotg->priv); 330 } else { 331 hsotg->flags.b.port_l1_change = 1; 332 } 333 } 334 335 /** 336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 337 * 338 * @hsotg: Pointer to struct dwc2_hsotg 339 * 340 * Must be called with interrupt disabled and spinlock held 341 */ 342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 343 { 344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 345 346 /* 347 * The root hub should be disconnected before this function is called. 348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 349 * and the QH lists (via ..._hcd_endpoint_disable). 350 */ 351 352 /* Turn off all host-specific interrupts */ 353 dwc2_disable_host_interrupts(hsotg); 354 355 /* Turn off the vbus power */ 356 dev_dbg(hsotg->dev, "PortPower off\n"); 357 dwc2_writel(0, hsotg->regs + HPRT0); 358 } 359 360 /* Caller must hold driver lock */ 361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 362 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 363 struct dwc2_qtd *qtd) 364 { 365 u32 intr_mask; 366 int retval; 367 int dev_speed; 368 369 if (!hsotg->flags.b.port_connect_status) { 370 /* No longer connected */ 371 dev_err(hsotg->dev, "Not connected\n"); 372 return -ENODEV; 373 } 374 375 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 376 377 /* Some configurations cannot support LS traffic on a FS root port */ 378 if ((dev_speed == USB_SPEED_LOW) && 379 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 380 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 381 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 382 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 383 384 if (prtspd == HPRT0_SPD_FULL_SPEED) 385 return -ENODEV; 386 } 387 388 if (!qtd) 389 return -EINVAL; 390 391 dwc2_hcd_qtd_init(qtd, urb); 392 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 393 if (retval) { 394 dev_err(hsotg->dev, 395 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 396 retval); 397 return retval; 398 } 399 400 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 401 if (!(intr_mask & GINTSTS_SOF)) { 402 enum dwc2_transaction_type tr_type; 403 404 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 405 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 406 /* 407 * Do not schedule SG transactions until qtd has 408 * URB_GIVEBACK_ASAP set 409 */ 410 return 0; 411 412 tr_type = dwc2_hcd_select_transactions(hsotg); 413 if (tr_type != DWC2_TRANSACTION_NONE) 414 dwc2_hcd_queue_transactions(hsotg, tr_type); 415 } 416 417 return 0; 418 } 419 420 /* Must be called with interrupt disabled and spinlock held */ 421 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 422 struct dwc2_hcd_urb *urb) 423 { 424 struct dwc2_qh *qh; 425 struct dwc2_qtd *urb_qtd; 426 427 urb_qtd = urb->qtd; 428 if (!urb_qtd) { 429 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 430 return -EINVAL; 431 } 432 433 qh = urb_qtd->qh; 434 if (!qh) { 435 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 436 return -EINVAL; 437 } 438 439 urb->priv = NULL; 440 441 if (urb_qtd->in_process && qh->channel) { 442 dwc2_dump_channel_info(hsotg, qh->channel); 443 444 /* The QTD is in process (it has been assigned to a channel) */ 445 if (hsotg->flags.b.port_connect_status) 446 /* 447 * If still connected (i.e. in host mode), halt the 448 * channel so it can be used for other transfers. If 449 * no longer connected, the host registers can't be 450 * written to halt the channel since the core is in 451 * device mode. 452 */ 453 dwc2_hc_halt(hsotg, qh->channel, 454 DWC2_HC_XFER_URB_DEQUEUE); 455 } 456 457 /* 458 * Free the QTD and clean up the associated QH. Leave the QH in the 459 * schedule if it has any remaining QTDs. 460 */ 461 if (hsotg->core_params->dma_desc_enable <= 0) { 462 u8 in_process = urb_qtd->in_process; 463 464 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 465 if (in_process) { 466 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 467 qh->channel = NULL; 468 } else if (list_empty(&qh->qtd_list)) { 469 dwc2_hcd_qh_unlink(hsotg, qh); 470 } 471 } else { 472 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 473 } 474 475 return 0; 476 } 477 478 /* Must NOT be called with interrupt disabled or spinlock held */ 479 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 480 struct usb_host_endpoint *ep, int retry) 481 { 482 struct dwc2_qtd *qtd, *qtd_tmp; 483 struct dwc2_qh *qh; 484 unsigned long flags; 485 int rc; 486 487 spin_lock_irqsave(&hsotg->lock, flags); 488 489 qh = ep->hcpriv; 490 if (!qh) { 491 rc = -EINVAL; 492 goto err; 493 } 494 495 while (!list_empty(&qh->qtd_list) && retry--) { 496 if (retry == 0) { 497 dev_err(hsotg->dev, 498 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 499 rc = -EBUSY; 500 goto err; 501 } 502 503 spin_unlock_irqrestore(&hsotg->lock, flags); 504 usleep_range(20000, 40000); 505 spin_lock_irqsave(&hsotg->lock, flags); 506 qh = ep->hcpriv; 507 if (!qh) { 508 rc = -EINVAL; 509 goto err; 510 } 511 } 512 513 dwc2_hcd_qh_unlink(hsotg, qh); 514 515 /* Free each QTD in the QH's QTD list */ 516 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 517 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 518 519 ep->hcpriv = NULL; 520 spin_unlock_irqrestore(&hsotg->lock, flags); 521 dwc2_hcd_qh_free(hsotg, qh); 522 523 return 0; 524 525 err: 526 ep->hcpriv = NULL; 527 spin_unlock_irqrestore(&hsotg->lock, flags); 528 529 return rc; 530 } 531 532 /* Must be called with interrupt disabled and spinlock held */ 533 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 534 struct usb_host_endpoint *ep) 535 { 536 struct dwc2_qh *qh = ep->hcpriv; 537 538 if (!qh) 539 return -EINVAL; 540 541 qh->data_toggle = DWC2_HC_PID_DATA0; 542 543 return 0; 544 } 545 546 /* 547 * Initializes dynamic portions of the DWC_otg HCD state 548 * 549 * Must be called with interrupt disabled and spinlock held 550 */ 551 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 552 { 553 struct dwc2_host_chan *chan, *chan_tmp; 554 int num_channels; 555 int i; 556 557 hsotg->flags.d32 = 0; 558 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 559 560 if (hsotg->core_params->uframe_sched > 0) { 561 hsotg->available_host_channels = 562 hsotg->core_params->host_channels; 563 } else { 564 hsotg->non_periodic_channels = 0; 565 hsotg->periodic_channels = 0; 566 } 567 568 /* 569 * Put all channels in the free channel list and clean up channel 570 * states 571 */ 572 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 573 hc_list_entry) 574 list_del_init(&chan->hc_list_entry); 575 576 num_channels = hsotg->core_params->host_channels; 577 for (i = 0; i < num_channels; i++) { 578 chan = hsotg->hc_ptr_array[i]; 579 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 580 dwc2_hc_cleanup(hsotg, chan); 581 } 582 583 /* Initialize the DWC core for host mode operation */ 584 dwc2_core_host_init(hsotg); 585 } 586 587 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 588 struct dwc2_host_chan *chan, 589 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 590 { 591 int hub_addr, hub_port; 592 593 chan->do_split = 1; 594 chan->xact_pos = qtd->isoc_split_pos; 595 chan->complete_split = qtd->complete_split; 596 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 597 chan->hub_addr = (u8)hub_addr; 598 chan->hub_port = (u8)hub_port; 599 } 600 601 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 602 struct dwc2_host_chan *chan, 603 struct dwc2_qtd *qtd, void *bufptr) 604 { 605 struct dwc2_hcd_urb *urb = qtd->urb; 606 struct dwc2_hcd_iso_packet_desc *frame_desc; 607 608 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 609 case USB_ENDPOINT_XFER_CONTROL: 610 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 611 612 switch (qtd->control_phase) { 613 case DWC2_CONTROL_SETUP: 614 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 615 chan->do_ping = 0; 616 chan->ep_is_in = 0; 617 chan->data_pid_start = DWC2_HC_PID_SETUP; 618 if (hsotg->core_params->dma_enable > 0) 619 chan->xfer_dma = urb->setup_dma; 620 else 621 chan->xfer_buf = urb->setup_packet; 622 chan->xfer_len = 8; 623 bufptr = NULL; 624 break; 625 626 case DWC2_CONTROL_DATA: 627 dev_vdbg(hsotg->dev, " Control data transaction\n"); 628 chan->data_pid_start = qtd->data_toggle; 629 break; 630 631 case DWC2_CONTROL_STATUS: 632 /* 633 * Direction is opposite of data direction or IN if no 634 * data 635 */ 636 dev_vdbg(hsotg->dev, " Control status transaction\n"); 637 if (urb->length == 0) 638 chan->ep_is_in = 1; 639 else 640 chan->ep_is_in = 641 dwc2_hcd_is_pipe_out(&urb->pipe_info); 642 if (chan->ep_is_in) 643 chan->do_ping = 0; 644 chan->data_pid_start = DWC2_HC_PID_DATA1; 645 chan->xfer_len = 0; 646 if (hsotg->core_params->dma_enable > 0) 647 chan->xfer_dma = hsotg->status_buf_dma; 648 else 649 chan->xfer_buf = hsotg->status_buf; 650 bufptr = NULL; 651 break; 652 } 653 break; 654 655 case USB_ENDPOINT_XFER_BULK: 656 chan->ep_type = USB_ENDPOINT_XFER_BULK; 657 break; 658 659 case USB_ENDPOINT_XFER_INT: 660 chan->ep_type = USB_ENDPOINT_XFER_INT; 661 break; 662 663 case USB_ENDPOINT_XFER_ISOC: 664 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 665 if (hsotg->core_params->dma_desc_enable > 0) 666 break; 667 668 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 669 frame_desc->status = 0; 670 671 if (hsotg->core_params->dma_enable > 0) { 672 chan->xfer_dma = urb->dma; 673 chan->xfer_dma += frame_desc->offset + 674 qtd->isoc_split_offset; 675 } else { 676 chan->xfer_buf = urb->buf; 677 chan->xfer_buf += frame_desc->offset + 678 qtd->isoc_split_offset; 679 } 680 681 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 682 683 /* For non-dword aligned buffers */ 684 if (hsotg->core_params->dma_enable > 0 && 685 (chan->xfer_dma & 0x3)) 686 bufptr = (u8 *)urb->buf + frame_desc->offset + 687 qtd->isoc_split_offset; 688 else 689 bufptr = NULL; 690 691 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 692 if (chan->xfer_len <= 188) 693 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 694 else 695 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 696 } 697 break; 698 } 699 700 return bufptr; 701 } 702 703 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 704 struct dwc2_host_chan *chan, 705 struct dwc2_hcd_urb *urb, void *bufptr) 706 { 707 u32 buf_size; 708 struct urb *usb_urb; 709 struct usb_hcd *hcd; 710 711 if (!qh->dw_align_buf) { 712 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 713 buf_size = hsotg->core_params->max_transfer_size; 714 else 715 /* 3072 = 3 max-size Isoc packets */ 716 buf_size = 3072; 717 718 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA); 719 if (!qh->dw_align_buf) 720 return -ENOMEM; 721 qh->dw_align_buf_size = buf_size; 722 } 723 724 if (chan->xfer_len) { 725 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 726 usb_urb = urb->priv; 727 728 if (usb_urb) { 729 if (usb_urb->transfer_flags & 730 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 731 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 732 hcd = dwc2_hsotg_to_hcd(hsotg); 733 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 734 } 735 if (!chan->ep_is_in) 736 memcpy(qh->dw_align_buf, bufptr, 737 chan->xfer_len); 738 } else { 739 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 740 } 741 } 742 743 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, 744 qh->dw_align_buf, qh->dw_align_buf_size, 745 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 746 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 747 dev_err(hsotg->dev, "can't map align_buf\n"); 748 chan->align_buf = 0; 749 return -EINVAL; 750 } 751 752 chan->align_buf = qh->dw_align_buf_dma; 753 return 0; 754 } 755 756 /** 757 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 758 * channel and initializes the host channel to perform the transactions. The 759 * host channel is removed from the free list. 760 * 761 * @hsotg: The HCD state structure 762 * @qh: Transactions from the first QTD for this QH are selected and assigned 763 * to a free host channel 764 */ 765 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 766 { 767 struct dwc2_host_chan *chan; 768 struct dwc2_hcd_urb *urb; 769 struct dwc2_qtd *qtd; 770 void *bufptr = NULL; 771 772 if (dbg_qh(qh)) 773 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 774 775 if (list_empty(&qh->qtd_list)) { 776 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 777 return -ENOMEM; 778 } 779 780 if (list_empty(&hsotg->free_hc_list)) { 781 dev_dbg(hsotg->dev, "No free channel to assign\n"); 782 return -ENOMEM; 783 } 784 785 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 786 hc_list_entry); 787 788 /* Remove host channel from free list */ 789 list_del_init(&chan->hc_list_entry); 790 791 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 792 urb = qtd->urb; 793 qh->channel = chan; 794 qtd->in_process = 1; 795 796 /* 797 * Use usb_pipedevice to determine device address. This address is 798 * 0 before the SET_ADDRESS command and the correct address afterward. 799 */ 800 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 801 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 802 chan->speed = qh->dev_speed; 803 chan->max_packet = dwc2_max_packet(qh->maxp); 804 805 chan->xfer_started = 0; 806 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 807 chan->error_state = (qtd->error_count > 0); 808 chan->halt_on_queue = 0; 809 chan->halt_pending = 0; 810 chan->requests = 0; 811 812 /* 813 * The following values may be modified in the transfer type section 814 * below. The xfer_len value may be reduced when the transfer is 815 * started to accommodate the max widths of the XferSize and PktCnt 816 * fields in the HCTSIZn register. 817 */ 818 819 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 820 if (chan->ep_is_in) 821 chan->do_ping = 0; 822 else 823 chan->do_ping = qh->ping_state; 824 825 chan->data_pid_start = qh->data_toggle; 826 chan->multi_count = 1; 827 828 if (urb->actual_length > urb->length && 829 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 830 urb->actual_length = urb->length; 831 832 if (hsotg->core_params->dma_enable > 0) { 833 chan->xfer_dma = urb->dma + urb->actual_length; 834 835 /* For non-dword aligned case */ 836 if (hsotg->core_params->dma_desc_enable <= 0 && 837 (chan->xfer_dma & 0x3)) 838 bufptr = (u8 *)urb->buf + urb->actual_length; 839 } else { 840 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 841 } 842 843 chan->xfer_len = urb->length - urb->actual_length; 844 chan->xfer_count = 0; 845 846 /* Set the split attributes if required */ 847 if (qh->do_split) 848 dwc2_hc_init_split(hsotg, chan, qtd, urb); 849 else 850 chan->do_split = 0; 851 852 /* Set the transfer attributes */ 853 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 854 855 /* Non DWORD-aligned buffer case */ 856 if (bufptr) { 857 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 858 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 859 dev_err(hsotg->dev, 860 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 861 __func__); 862 /* Add channel back to free list */ 863 chan->align_buf = 0; 864 chan->multi_count = 0; 865 list_add_tail(&chan->hc_list_entry, 866 &hsotg->free_hc_list); 867 qtd->in_process = 0; 868 qh->channel = NULL; 869 return -ENOMEM; 870 } 871 } else { 872 chan->align_buf = 0; 873 } 874 875 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 876 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 877 /* 878 * This value may be modified when the transfer is started 879 * to reflect the actual transfer length 880 */ 881 chan->multi_count = dwc2_hb_mult(qh->maxp); 882 883 if (hsotg->core_params->dma_desc_enable > 0) 884 chan->desc_list_addr = qh->desc_list_dma; 885 886 dwc2_hc_init(hsotg, chan); 887 chan->qh = qh; 888 889 return 0; 890 } 891 892 /** 893 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 894 * schedule and assigns them to available host channels. Called from the HCD 895 * interrupt handler functions. 896 * 897 * @hsotg: The HCD state structure 898 * 899 * Return: The types of new transactions that were assigned to host channels 900 */ 901 enum dwc2_transaction_type dwc2_hcd_select_transactions( 902 struct dwc2_hsotg *hsotg) 903 { 904 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 905 struct list_head *qh_ptr; 906 struct dwc2_qh *qh; 907 int num_channels; 908 909 #ifdef DWC2_DEBUG_SOF 910 dev_vdbg(hsotg->dev, " Select Transactions\n"); 911 #endif 912 913 /* Process entries in the periodic ready list */ 914 qh_ptr = hsotg->periodic_sched_ready.next; 915 while (qh_ptr != &hsotg->periodic_sched_ready) { 916 if (list_empty(&hsotg->free_hc_list)) 917 break; 918 if (hsotg->core_params->uframe_sched > 0) { 919 if (hsotg->available_host_channels <= 1) 920 break; 921 hsotg->available_host_channels--; 922 } 923 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 924 if (dwc2_assign_and_init_hc(hsotg, qh)) 925 break; 926 927 /* 928 * Move the QH from the periodic ready schedule to the 929 * periodic assigned schedule 930 */ 931 qh_ptr = qh_ptr->next; 932 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 933 ret_val = DWC2_TRANSACTION_PERIODIC; 934 } 935 936 /* 937 * Process entries in the inactive portion of the non-periodic 938 * schedule. Some free host channels may not be used if they are 939 * reserved for periodic transfers. 940 */ 941 num_channels = hsotg->core_params->host_channels; 942 qh_ptr = hsotg->non_periodic_sched_inactive.next; 943 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 944 if (hsotg->core_params->uframe_sched <= 0 && 945 hsotg->non_periodic_channels >= num_channels - 946 hsotg->periodic_channels) 947 break; 948 if (list_empty(&hsotg->free_hc_list)) 949 break; 950 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 951 if (hsotg->core_params->uframe_sched > 0) { 952 if (hsotg->available_host_channels < 1) 953 break; 954 hsotg->available_host_channels--; 955 } 956 957 if (dwc2_assign_and_init_hc(hsotg, qh)) 958 break; 959 960 /* 961 * Move the QH from the non-periodic inactive schedule to the 962 * non-periodic active schedule 963 */ 964 qh_ptr = qh_ptr->next; 965 list_move(&qh->qh_list_entry, 966 &hsotg->non_periodic_sched_active); 967 968 if (ret_val == DWC2_TRANSACTION_NONE) 969 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 970 else 971 ret_val = DWC2_TRANSACTION_ALL; 972 973 if (hsotg->core_params->uframe_sched <= 0) 974 hsotg->non_periodic_channels++; 975 } 976 977 return ret_val; 978 } 979 980 /** 981 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 982 * a host channel associated with either a periodic or non-periodic transfer 983 * 984 * @hsotg: The HCD state structure 985 * @chan: Host channel descriptor associated with either a periodic or 986 * non-periodic transfer 987 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 988 * for periodic transfers or the non-periodic Tx FIFO 989 * for non-periodic transfers 990 * 991 * Return: 1 if a request is queued and more requests may be needed to 992 * complete the transfer, 0 if no more requests are required for this 993 * transfer, -1 if there is insufficient space in the Tx FIFO 994 * 995 * This function assumes that there is space available in the appropriate 996 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 997 * it checks whether space is available in the appropriate Tx FIFO. 998 * 999 * Must be called with interrupt disabled and spinlock held 1000 */ 1001 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1002 struct dwc2_host_chan *chan, 1003 u16 fifo_dwords_avail) 1004 { 1005 int retval = 0; 1006 1007 if (hsotg->core_params->dma_enable > 0) { 1008 if (hsotg->core_params->dma_desc_enable > 0) { 1009 if (!chan->xfer_started || 1010 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1011 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1012 chan->qh->ping_state = 0; 1013 } 1014 } else if (!chan->xfer_started) { 1015 dwc2_hc_start_transfer(hsotg, chan); 1016 chan->qh->ping_state = 0; 1017 } 1018 } else if (chan->halt_pending) { 1019 /* Don't queue a request if the channel has been halted */ 1020 } else if (chan->halt_on_queue) { 1021 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1022 } else if (chan->do_ping) { 1023 if (!chan->xfer_started) 1024 dwc2_hc_start_transfer(hsotg, chan); 1025 } else if (!chan->ep_is_in || 1026 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1027 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1028 if (!chan->xfer_started) { 1029 dwc2_hc_start_transfer(hsotg, chan); 1030 retval = 1; 1031 } else { 1032 retval = dwc2_hc_continue_transfer(hsotg, chan); 1033 } 1034 } else { 1035 retval = -1; 1036 } 1037 } else { 1038 if (!chan->xfer_started) { 1039 dwc2_hc_start_transfer(hsotg, chan); 1040 retval = 1; 1041 } else { 1042 retval = dwc2_hc_continue_transfer(hsotg, chan); 1043 } 1044 } 1045 1046 return retval; 1047 } 1048 1049 /* 1050 * Processes periodic channels for the next frame and queues transactions for 1051 * these channels to the DWC_otg controller. After queueing transactions, the 1052 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1053 * to queue as Periodic Tx FIFO or request queue space becomes available. 1054 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1055 * 1056 * Must be called with interrupt disabled and spinlock held 1057 */ 1058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1059 { 1060 struct list_head *qh_ptr; 1061 struct dwc2_qh *qh; 1062 u32 tx_status; 1063 u32 fspcavail; 1064 u32 gintmsk; 1065 int status; 1066 int no_queue_space = 0; 1067 int no_fifo_space = 0; 1068 u32 qspcavail; 1069 1070 if (dbg_perio()) 1071 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1072 1073 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1074 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1075 TXSTS_QSPCAVAIL_SHIFT; 1076 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1077 TXSTS_FSPCAVAIL_SHIFT; 1078 1079 if (dbg_perio()) { 1080 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1081 qspcavail); 1082 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1083 fspcavail); 1084 } 1085 1086 qh_ptr = hsotg->periodic_sched_assigned.next; 1087 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1088 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1089 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1090 TXSTS_QSPCAVAIL_SHIFT; 1091 if (qspcavail == 0) { 1092 no_queue_space = 1; 1093 break; 1094 } 1095 1096 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1097 if (!qh->channel) { 1098 qh_ptr = qh_ptr->next; 1099 continue; 1100 } 1101 1102 /* Make sure EP's TT buffer is clean before queueing qtds */ 1103 if (qh->tt_buffer_dirty) { 1104 qh_ptr = qh_ptr->next; 1105 continue; 1106 } 1107 1108 /* 1109 * Set a flag if we're queuing high-bandwidth in slave mode. 1110 * The flag prevents any halts to get into the request queue in 1111 * the middle of multiple high-bandwidth packets getting queued. 1112 */ 1113 if (hsotg->core_params->dma_enable <= 0 && 1114 qh->channel->multi_count > 1) 1115 hsotg->queuing_high_bandwidth = 1; 1116 1117 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1118 TXSTS_FSPCAVAIL_SHIFT; 1119 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1120 if (status < 0) { 1121 no_fifo_space = 1; 1122 break; 1123 } 1124 1125 /* 1126 * In Slave mode, stay on the current transfer until there is 1127 * nothing more to do or the high-bandwidth request count is 1128 * reached. In DMA mode, only need to queue one request. The 1129 * controller automatically handles multiple packets for 1130 * high-bandwidth transfers. 1131 */ 1132 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1133 qh->channel->requests == qh->channel->multi_count) { 1134 qh_ptr = qh_ptr->next; 1135 /* 1136 * Move the QH from the periodic assigned schedule to 1137 * the periodic queued schedule 1138 */ 1139 list_move(&qh->qh_list_entry, 1140 &hsotg->periodic_sched_queued); 1141 1142 /* done queuing high bandwidth */ 1143 hsotg->queuing_high_bandwidth = 0; 1144 } 1145 } 1146 1147 if (hsotg->core_params->dma_enable <= 0) { 1148 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1149 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1150 TXSTS_QSPCAVAIL_SHIFT; 1151 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1152 TXSTS_FSPCAVAIL_SHIFT; 1153 if (dbg_perio()) { 1154 dev_vdbg(hsotg->dev, 1155 " P Tx Req Queue Space Avail (after queue): %d\n", 1156 qspcavail); 1157 dev_vdbg(hsotg->dev, 1158 " P Tx FIFO Space Avail (after queue): %d\n", 1159 fspcavail); 1160 } 1161 1162 if (!list_empty(&hsotg->periodic_sched_assigned) || 1163 no_queue_space || no_fifo_space) { 1164 /* 1165 * May need to queue more transactions as the request 1166 * queue or Tx FIFO empties. Enable the periodic Tx 1167 * FIFO empty interrupt. (Always use the half-empty 1168 * level to ensure that new requests are loaded as 1169 * soon as possible.) 1170 */ 1171 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1172 gintmsk |= GINTSTS_PTXFEMP; 1173 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1174 } else { 1175 /* 1176 * Disable the Tx FIFO empty interrupt since there are 1177 * no more transactions that need to be queued right 1178 * now. This function is called from interrupt 1179 * handlers to queue more transactions as transfer 1180 * states change. 1181 */ 1182 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1183 gintmsk &= ~GINTSTS_PTXFEMP; 1184 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1185 } 1186 } 1187 } 1188 1189 /* 1190 * Processes active non-periodic channels and queues transactions for these 1191 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1192 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1193 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1194 * FIFO Empty interrupt is disabled. 1195 * 1196 * Must be called with interrupt disabled and spinlock held 1197 */ 1198 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1199 { 1200 struct list_head *orig_qh_ptr; 1201 struct dwc2_qh *qh; 1202 u32 tx_status; 1203 u32 qspcavail; 1204 u32 fspcavail; 1205 u32 gintmsk; 1206 int status; 1207 int no_queue_space = 0; 1208 int no_fifo_space = 0; 1209 int more_to_do = 0; 1210 1211 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1212 1213 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1214 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1215 TXSTS_QSPCAVAIL_SHIFT; 1216 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1217 TXSTS_FSPCAVAIL_SHIFT; 1218 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1219 qspcavail); 1220 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1221 fspcavail); 1222 1223 /* 1224 * Keep track of the starting point. Skip over the start-of-list 1225 * entry. 1226 */ 1227 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1228 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1229 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1230 1231 /* 1232 * Process once through the active list or until no more space is 1233 * available in the request queue or the Tx FIFO 1234 */ 1235 do { 1236 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1237 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1238 TXSTS_QSPCAVAIL_SHIFT; 1239 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1240 no_queue_space = 1; 1241 break; 1242 } 1243 1244 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1245 qh_list_entry); 1246 if (!qh->channel) 1247 goto next; 1248 1249 /* Make sure EP's TT buffer is clean before queueing qtds */ 1250 if (qh->tt_buffer_dirty) 1251 goto next; 1252 1253 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1254 TXSTS_FSPCAVAIL_SHIFT; 1255 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1256 1257 if (status > 0) { 1258 more_to_do = 1; 1259 } else if (status < 0) { 1260 no_fifo_space = 1; 1261 break; 1262 } 1263 next: 1264 /* Advance to next QH, skipping start-of-list entry */ 1265 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1266 if (hsotg->non_periodic_qh_ptr == 1267 &hsotg->non_periodic_sched_active) 1268 hsotg->non_periodic_qh_ptr = 1269 hsotg->non_periodic_qh_ptr->next; 1270 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1271 1272 if (hsotg->core_params->dma_enable <= 0) { 1273 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1274 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1275 TXSTS_QSPCAVAIL_SHIFT; 1276 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1277 TXSTS_FSPCAVAIL_SHIFT; 1278 dev_vdbg(hsotg->dev, 1279 " NP Tx Req Queue Space Avail (after queue): %d\n", 1280 qspcavail); 1281 dev_vdbg(hsotg->dev, 1282 " NP Tx FIFO Space Avail (after queue): %d\n", 1283 fspcavail); 1284 1285 if (more_to_do || no_queue_space || no_fifo_space) { 1286 /* 1287 * May need to queue more transactions as the request 1288 * queue or Tx FIFO empties. Enable the non-periodic 1289 * Tx FIFO empty interrupt. (Always use the half-empty 1290 * level to ensure that new requests are loaded as 1291 * soon as possible.) 1292 */ 1293 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1294 gintmsk |= GINTSTS_NPTXFEMP; 1295 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1296 } else { 1297 /* 1298 * Disable the Tx FIFO empty interrupt since there are 1299 * no more transactions that need to be queued right 1300 * now. This function is called from interrupt 1301 * handlers to queue more transactions as transfer 1302 * states change. 1303 */ 1304 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1305 gintmsk &= ~GINTSTS_NPTXFEMP; 1306 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1307 } 1308 } 1309 } 1310 1311 /** 1312 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1313 * and queues transactions for these channels to the DWC_otg controller. Called 1314 * from the HCD interrupt handler functions. 1315 * 1316 * @hsotg: The HCD state structure 1317 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1318 * or both) 1319 * 1320 * Must be called with interrupt disabled and spinlock held 1321 */ 1322 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1323 enum dwc2_transaction_type tr_type) 1324 { 1325 #ifdef DWC2_DEBUG_SOF 1326 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1327 #endif 1328 /* Process host channels associated with periodic transfers */ 1329 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1330 tr_type == DWC2_TRANSACTION_ALL) && 1331 !list_empty(&hsotg->periodic_sched_assigned)) 1332 dwc2_process_periodic_channels(hsotg); 1333 1334 /* Process host channels associated with non-periodic transfers */ 1335 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1336 tr_type == DWC2_TRANSACTION_ALL) { 1337 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1338 dwc2_process_non_periodic_channels(hsotg); 1339 } else { 1340 /* 1341 * Ensure NP Tx FIFO empty interrupt is disabled when 1342 * there are no non-periodic transfers to process 1343 */ 1344 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1345 1346 gintmsk &= ~GINTSTS_NPTXFEMP; 1347 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1348 } 1349 } 1350 } 1351 1352 static void dwc2_conn_id_status_change(struct work_struct *work) 1353 { 1354 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1355 wf_otg); 1356 u32 count = 0; 1357 u32 gotgctl; 1358 1359 dev_dbg(hsotg->dev, "%s()\n", __func__); 1360 1361 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1362 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1363 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1364 !!(gotgctl & GOTGCTL_CONID_B)); 1365 1366 /* B-Device connector (Device Mode) */ 1367 if (gotgctl & GOTGCTL_CONID_B) { 1368 /* Wait for switch to device mode */ 1369 dev_dbg(hsotg->dev, "connId B\n"); 1370 while (!dwc2_is_device_mode(hsotg)) { 1371 dev_info(hsotg->dev, 1372 "Waiting for Peripheral Mode, Mode=%s\n", 1373 dwc2_is_host_mode(hsotg) ? "Host" : 1374 "Peripheral"); 1375 usleep_range(20000, 40000); 1376 if (++count > 250) 1377 break; 1378 } 1379 if (count > 250) 1380 dev_err(hsotg->dev, 1381 "Connection id status change timed out\n"); 1382 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1383 dwc2_core_init(hsotg, false, -1); 1384 dwc2_enable_global_interrupts(hsotg); 1385 dwc2_hsotg_core_init_disconnected(hsotg, false); 1386 dwc2_hsotg_core_connect(hsotg); 1387 } else { 1388 /* A-Device connector (Host Mode) */ 1389 dev_dbg(hsotg->dev, "connId A\n"); 1390 while (!dwc2_is_host_mode(hsotg)) { 1391 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1392 dwc2_is_host_mode(hsotg) ? 1393 "Host" : "Peripheral"); 1394 usleep_range(20000, 40000); 1395 if (++count > 250) 1396 break; 1397 } 1398 if (count > 250) 1399 dev_err(hsotg->dev, 1400 "Connection id status change timed out\n"); 1401 hsotg->op_state = OTG_STATE_A_HOST; 1402 1403 /* Initialize the Core for Host mode */ 1404 dwc2_core_init(hsotg, false, -1); 1405 dwc2_enable_global_interrupts(hsotg); 1406 dwc2_hcd_start(hsotg); 1407 } 1408 } 1409 1410 static void dwc2_wakeup_detected(unsigned long data) 1411 { 1412 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1413 u32 hprt0; 1414 1415 dev_dbg(hsotg->dev, "%s()\n", __func__); 1416 1417 /* 1418 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1419 * so that OPT tests pass with all PHYs.) 1420 */ 1421 hprt0 = dwc2_read_hprt0(hsotg); 1422 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1423 hprt0 &= ~HPRT0_RES; 1424 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1425 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1426 dwc2_readl(hsotg->regs + HPRT0)); 1427 1428 hsotg->bus_suspended = 0; 1429 dwc2_hcd_rem_wakeup(hsotg); 1430 1431 /* Change to L0 state */ 1432 hsotg->lx_state = DWC2_L0; 1433 } 1434 1435 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1436 { 1437 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1438 1439 return hcd->self.b_hnp_enable; 1440 } 1441 1442 /* Must NOT be called with interrupt disabled or spinlock held */ 1443 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1444 { 1445 unsigned long flags; 1446 u32 hprt0; 1447 u32 pcgctl; 1448 u32 gotgctl; 1449 1450 dev_dbg(hsotg->dev, "%s()\n", __func__); 1451 1452 spin_lock_irqsave(&hsotg->lock, flags); 1453 1454 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1455 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1456 gotgctl |= GOTGCTL_HSTSETHNPEN; 1457 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 1458 hsotg->op_state = OTG_STATE_A_SUSPEND; 1459 } 1460 1461 hprt0 = dwc2_read_hprt0(hsotg); 1462 hprt0 |= HPRT0_SUSP; 1463 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1464 1465 hsotg->bus_suspended = 1; 1466 1467 /* 1468 * If hibernation is supported, Phy clock will be suspended 1469 * after registers are backuped. 1470 */ 1471 if (!hsotg->core_params->hibernation) { 1472 /* Suspend the Phy Clock */ 1473 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1474 pcgctl |= PCGCTL_STOPPCLK; 1475 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1476 udelay(10); 1477 } 1478 1479 /* For HNP the bus must be suspended for at least 200ms */ 1480 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1481 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1482 pcgctl &= ~PCGCTL_STOPPCLK; 1483 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1484 1485 spin_unlock_irqrestore(&hsotg->lock, flags); 1486 1487 usleep_range(200000, 250000); 1488 } else { 1489 spin_unlock_irqrestore(&hsotg->lock, flags); 1490 } 1491 } 1492 1493 /* Must NOT be called with interrupt disabled or spinlock held */ 1494 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1495 { 1496 unsigned long flags; 1497 u32 hprt0; 1498 u32 pcgctl; 1499 1500 /* 1501 * If hibernation is supported, Phy clock is already resumed 1502 * after registers restore. 1503 */ 1504 if (!hsotg->core_params->hibernation) { 1505 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1506 pcgctl &= ~PCGCTL_STOPPCLK; 1507 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1508 usleep_range(20000, 40000); 1509 } 1510 1511 spin_lock_irqsave(&hsotg->lock, flags); 1512 hprt0 = dwc2_read_hprt0(hsotg); 1513 hprt0 |= HPRT0_RES; 1514 hprt0 &= ~HPRT0_SUSP; 1515 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1516 spin_unlock_irqrestore(&hsotg->lock, flags); 1517 1518 msleep(USB_RESUME_TIMEOUT); 1519 1520 spin_lock_irqsave(&hsotg->lock, flags); 1521 hprt0 = dwc2_read_hprt0(hsotg); 1522 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1523 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1524 hsotg->bus_suspended = 0; 1525 spin_unlock_irqrestore(&hsotg->lock, flags); 1526 } 1527 1528 /* Handles hub class-specific requests */ 1529 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1530 u16 wvalue, u16 windex, char *buf, u16 wlength) 1531 { 1532 struct usb_hub_descriptor *hub_desc; 1533 int retval = 0; 1534 u32 hprt0; 1535 u32 port_status; 1536 u32 speed; 1537 u32 pcgctl; 1538 1539 switch (typereq) { 1540 case ClearHubFeature: 1541 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1542 1543 switch (wvalue) { 1544 case C_HUB_LOCAL_POWER: 1545 case C_HUB_OVER_CURRENT: 1546 /* Nothing required here */ 1547 break; 1548 1549 default: 1550 retval = -EINVAL; 1551 dev_err(hsotg->dev, 1552 "ClearHubFeature request %1xh unknown\n", 1553 wvalue); 1554 } 1555 break; 1556 1557 case ClearPortFeature: 1558 if (wvalue != USB_PORT_FEAT_L1) 1559 if (!windex || windex > 1) 1560 goto error; 1561 switch (wvalue) { 1562 case USB_PORT_FEAT_ENABLE: 1563 dev_dbg(hsotg->dev, 1564 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1565 hprt0 = dwc2_read_hprt0(hsotg); 1566 hprt0 |= HPRT0_ENA; 1567 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1568 break; 1569 1570 case USB_PORT_FEAT_SUSPEND: 1571 dev_dbg(hsotg->dev, 1572 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1573 1574 if (hsotg->bus_suspended) 1575 dwc2_port_resume(hsotg); 1576 break; 1577 1578 case USB_PORT_FEAT_POWER: 1579 dev_dbg(hsotg->dev, 1580 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1581 hprt0 = dwc2_read_hprt0(hsotg); 1582 hprt0 &= ~HPRT0_PWR; 1583 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1584 break; 1585 1586 case USB_PORT_FEAT_INDICATOR: 1587 dev_dbg(hsotg->dev, 1588 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1589 /* Port indicator not supported */ 1590 break; 1591 1592 case USB_PORT_FEAT_C_CONNECTION: 1593 /* 1594 * Clears driver's internal Connect Status Change flag 1595 */ 1596 dev_dbg(hsotg->dev, 1597 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1598 hsotg->flags.b.port_connect_status_change = 0; 1599 break; 1600 1601 case USB_PORT_FEAT_C_RESET: 1602 /* Clears driver's internal Port Reset Change flag */ 1603 dev_dbg(hsotg->dev, 1604 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1605 hsotg->flags.b.port_reset_change = 0; 1606 break; 1607 1608 case USB_PORT_FEAT_C_ENABLE: 1609 /* 1610 * Clears the driver's internal Port Enable/Disable 1611 * Change flag 1612 */ 1613 dev_dbg(hsotg->dev, 1614 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1615 hsotg->flags.b.port_enable_change = 0; 1616 break; 1617 1618 case USB_PORT_FEAT_C_SUSPEND: 1619 /* 1620 * Clears the driver's internal Port Suspend Change 1621 * flag, which is set when resume signaling on the host 1622 * port is complete 1623 */ 1624 dev_dbg(hsotg->dev, 1625 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1626 hsotg->flags.b.port_suspend_change = 0; 1627 break; 1628 1629 case USB_PORT_FEAT_C_PORT_L1: 1630 dev_dbg(hsotg->dev, 1631 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1632 hsotg->flags.b.port_l1_change = 0; 1633 break; 1634 1635 case USB_PORT_FEAT_C_OVER_CURRENT: 1636 dev_dbg(hsotg->dev, 1637 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1638 hsotg->flags.b.port_over_current_change = 0; 1639 break; 1640 1641 default: 1642 retval = -EINVAL; 1643 dev_err(hsotg->dev, 1644 "ClearPortFeature request %1xh unknown or unsupported\n", 1645 wvalue); 1646 } 1647 break; 1648 1649 case GetHubDescriptor: 1650 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1651 hub_desc = (struct usb_hub_descriptor *)buf; 1652 hub_desc->bDescLength = 9; 1653 hub_desc->bDescriptorType = USB_DT_HUB; 1654 hub_desc->bNbrPorts = 1; 1655 hub_desc->wHubCharacteristics = 1656 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1657 HUB_CHAR_INDV_PORT_OCPM); 1658 hub_desc->bPwrOn2PwrGood = 1; 1659 hub_desc->bHubContrCurrent = 0; 1660 hub_desc->u.hs.DeviceRemovable[0] = 0; 1661 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1662 break; 1663 1664 case GetHubStatus: 1665 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1666 memset(buf, 0, 4); 1667 break; 1668 1669 case GetPortStatus: 1670 dev_vdbg(hsotg->dev, 1671 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1672 hsotg->flags.d32); 1673 if (!windex || windex > 1) 1674 goto error; 1675 1676 port_status = 0; 1677 if (hsotg->flags.b.port_connect_status_change) 1678 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1679 if (hsotg->flags.b.port_enable_change) 1680 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1681 if (hsotg->flags.b.port_suspend_change) 1682 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1683 if (hsotg->flags.b.port_l1_change) 1684 port_status |= USB_PORT_STAT_C_L1 << 16; 1685 if (hsotg->flags.b.port_reset_change) 1686 port_status |= USB_PORT_STAT_C_RESET << 16; 1687 if (hsotg->flags.b.port_over_current_change) { 1688 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1689 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1690 } 1691 1692 if (!hsotg->flags.b.port_connect_status) { 1693 /* 1694 * The port is disconnected, which means the core is 1695 * either in device mode or it soon will be. Just 1696 * return 0's for the remainder of the port status 1697 * since the port register can't be read if the core 1698 * is in device mode. 1699 */ 1700 *(__le32 *)buf = cpu_to_le32(port_status); 1701 break; 1702 } 1703 1704 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1705 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1706 1707 if (hprt0 & HPRT0_CONNSTS) 1708 port_status |= USB_PORT_STAT_CONNECTION; 1709 if (hprt0 & HPRT0_ENA) 1710 port_status |= USB_PORT_STAT_ENABLE; 1711 if (hprt0 & HPRT0_SUSP) 1712 port_status |= USB_PORT_STAT_SUSPEND; 1713 if (hprt0 & HPRT0_OVRCURRACT) 1714 port_status |= USB_PORT_STAT_OVERCURRENT; 1715 if (hprt0 & HPRT0_RST) 1716 port_status |= USB_PORT_STAT_RESET; 1717 if (hprt0 & HPRT0_PWR) 1718 port_status |= USB_PORT_STAT_POWER; 1719 1720 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1721 if (speed == HPRT0_SPD_HIGH_SPEED) 1722 port_status |= USB_PORT_STAT_HIGH_SPEED; 1723 else if (speed == HPRT0_SPD_LOW_SPEED) 1724 port_status |= USB_PORT_STAT_LOW_SPEED; 1725 1726 if (hprt0 & HPRT0_TSTCTL_MASK) 1727 port_status |= USB_PORT_STAT_TEST; 1728 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1729 1730 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1731 *(__le32 *)buf = cpu_to_le32(port_status); 1732 break; 1733 1734 case SetHubFeature: 1735 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1736 /* No HUB features supported */ 1737 break; 1738 1739 case SetPortFeature: 1740 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1741 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1742 goto error; 1743 1744 if (!hsotg->flags.b.port_connect_status) { 1745 /* 1746 * The port is disconnected, which means the core is 1747 * either in device mode or it soon will be. Just 1748 * return without doing anything since the port 1749 * register can't be written if the core is in device 1750 * mode. 1751 */ 1752 break; 1753 } 1754 1755 switch (wvalue) { 1756 case USB_PORT_FEAT_SUSPEND: 1757 dev_dbg(hsotg->dev, 1758 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1759 if (windex != hsotg->otg_port) 1760 goto error; 1761 dwc2_port_suspend(hsotg, windex); 1762 break; 1763 1764 case USB_PORT_FEAT_POWER: 1765 dev_dbg(hsotg->dev, 1766 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1767 hprt0 = dwc2_read_hprt0(hsotg); 1768 hprt0 |= HPRT0_PWR; 1769 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1770 break; 1771 1772 case USB_PORT_FEAT_RESET: 1773 hprt0 = dwc2_read_hprt0(hsotg); 1774 dev_dbg(hsotg->dev, 1775 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1776 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1777 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1778 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1779 /* ??? Original driver does this */ 1780 dwc2_writel(0, hsotg->regs + PCGCTL); 1781 1782 hprt0 = dwc2_read_hprt0(hsotg); 1783 /* Clear suspend bit if resetting from suspend state */ 1784 hprt0 &= ~HPRT0_SUSP; 1785 1786 /* 1787 * When B-Host the Port reset bit is set in the Start 1788 * HCD Callback function, so that the reset is started 1789 * within 1ms of the HNP success interrupt 1790 */ 1791 if (!dwc2_hcd_is_b_host(hsotg)) { 1792 hprt0 |= HPRT0_PWR | HPRT0_RST; 1793 dev_dbg(hsotg->dev, 1794 "In host mode, hprt0=%08x\n", hprt0); 1795 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1796 } 1797 1798 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1799 usleep_range(50000, 70000); 1800 hprt0 &= ~HPRT0_RST; 1801 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1802 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1803 break; 1804 1805 case USB_PORT_FEAT_INDICATOR: 1806 dev_dbg(hsotg->dev, 1807 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1808 /* Not supported */ 1809 break; 1810 1811 case USB_PORT_FEAT_TEST: 1812 hprt0 = dwc2_read_hprt0(hsotg); 1813 dev_dbg(hsotg->dev, 1814 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1815 hprt0 &= ~HPRT0_TSTCTL_MASK; 1816 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1817 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1818 break; 1819 1820 default: 1821 retval = -EINVAL; 1822 dev_err(hsotg->dev, 1823 "SetPortFeature %1xh unknown or unsupported\n", 1824 wvalue); 1825 break; 1826 } 1827 break; 1828 1829 default: 1830 error: 1831 retval = -EINVAL; 1832 dev_dbg(hsotg->dev, 1833 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1834 typereq, windex, wvalue); 1835 break; 1836 } 1837 1838 return retval; 1839 } 1840 1841 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1842 { 1843 int retval; 1844 1845 if (port != 1) 1846 return -EINVAL; 1847 1848 retval = (hsotg->flags.b.port_connect_status_change || 1849 hsotg->flags.b.port_reset_change || 1850 hsotg->flags.b.port_enable_change || 1851 hsotg->flags.b.port_suspend_change || 1852 hsotg->flags.b.port_over_current_change); 1853 1854 if (retval) { 1855 dev_dbg(hsotg->dev, 1856 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1857 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1858 hsotg->flags.b.port_connect_status_change); 1859 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1860 hsotg->flags.b.port_reset_change); 1861 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1862 hsotg->flags.b.port_enable_change); 1863 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1864 hsotg->flags.b.port_suspend_change); 1865 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1866 hsotg->flags.b.port_over_current_change); 1867 } 1868 1869 return retval; 1870 } 1871 1872 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1873 { 1874 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1875 1876 #ifdef DWC2_DEBUG_SOF 1877 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1878 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1879 #endif 1880 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1881 } 1882 1883 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1884 { 1885 return hsotg->op_state == OTG_STATE_B_HOST; 1886 } 1887 1888 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1889 int iso_desc_count, 1890 gfp_t mem_flags) 1891 { 1892 struct dwc2_hcd_urb *urb; 1893 u32 size = sizeof(*urb) + iso_desc_count * 1894 sizeof(struct dwc2_hcd_iso_packet_desc); 1895 1896 urb = kzalloc(size, mem_flags); 1897 if (urb) 1898 urb->packet_count = iso_desc_count; 1899 return urb; 1900 } 1901 1902 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1903 struct dwc2_hcd_urb *urb, u8 dev_addr, 1904 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1905 { 1906 if (dbg_perio() || 1907 ep_type == USB_ENDPOINT_XFER_BULK || 1908 ep_type == USB_ENDPOINT_XFER_CONTROL) 1909 dev_vdbg(hsotg->dev, 1910 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1911 dev_addr, ep_num, ep_dir, ep_type, mps); 1912 urb->pipe_info.dev_addr = dev_addr; 1913 urb->pipe_info.ep_num = ep_num; 1914 urb->pipe_info.pipe_type = ep_type; 1915 urb->pipe_info.pipe_dir = ep_dir; 1916 urb->pipe_info.mps = mps; 1917 } 1918 1919 /* 1920 * NOTE: This function will be removed once the peripheral controller code 1921 * is integrated and the driver is stable 1922 */ 1923 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1924 { 1925 #ifdef DEBUG 1926 struct dwc2_host_chan *chan; 1927 struct dwc2_hcd_urb *urb; 1928 struct dwc2_qtd *qtd; 1929 int num_channels; 1930 u32 np_tx_status; 1931 u32 p_tx_status; 1932 int i; 1933 1934 num_channels = hsotg->core_params->host_channels; 1935 dev_dbg(hsotg->dev, "\n"); 1936 dev_dbg(hsotg->dev, 1937 "************************************************************\n"); 1938 dev_dbg(hsotg->dev, "HCD State:\n"); 1939 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1940 1941 for (i = 0; i < num_channels; i++) { 1942 chan = hsotg->hc_ptr_array[i]; 1943 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1944 dev_dbg(hsotg->dev, 1945 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1946 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1947 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1948 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1949 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1950 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1951 chan->data_pid_start); 1952 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1953 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1954 chan->xfer_started); 1955 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1956 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1957 (unsigned long)chan->xfer_dma); 1958 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1959 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1960 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1961 chan->halt_on_queue); 1962 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1963 chan->halt_pending); 1964 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1965 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1966 dev_dbg(hsotg->dev, " complete_split: %d\n", 1967 chan->complete_split); 1968 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1969 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1970 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1971 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1972 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1973 1974 if (chan->xfer_started) { 1975 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1976 1977 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1978 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1979 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 1980 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 1981 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 1982 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1983 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1984 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1985 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1986 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1987 } 1988 1989 if (!(chan->xfer_started && chan->qh)) 1990 continue; 1991 1992 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1993 if (!qtd->in_process) 1994 break; 1995 urb = qtd->urb; 1996 dev_dbg(hsotg->dev, " URB Info:\n"); 1997 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1998 qtd, urb); 1999 if (urb) { 2000 dev_dbg(hsotg->dev, 2001 " Dev: %d, EP: %d %s\n", 2002 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2003 dwc2_hcd_get_ep_num(&urb->pipe_info), 2004 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2005 "IN" : "OUT"); 2006 dev_dbg(hsotg->dev, 2007 " Max packet size: %d\n", 2008 dwc2_hcd_get_mps(&urb->pipe_info)); 2009 dev_dbg(hsotg->dev, 2010 " transfer_buffer: %p\n", 2011 urb->buf); 2012 dev_dbg(hsotg->dev, 2013 " transfer_dma: %08lx\n", 2014 (unsigned long)urb->dma); 2015 dev_dbg(hsotg->dev, 2016 " transfer_buffer_length: %d\n", 2017 urb->length); 2018 dev_dbg(hsotg->dev, " actual_length: %d\n", 2019 urb->actual_length); 2020 } 2021 } 2022 } 2023 2024 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2025 hsotg->non_periodic_channels); 2026 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2027 hsotg->periodic_channels); 2028 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2029 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 2030 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2031 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2032 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2033 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2034 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2035 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2036 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2037 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2038 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2039 dwc2_hcd_dump_frrem(hsotg); 2040 dwc2_dump_global_registers(hsotg); 2041 dwc2_dump_host_registers(hsotg); 2042 dev_dbg(hsotg->dev, 2043 "************************************************************\n"); 2044 dev_dbg(hsotg->dev, "\n"); 2045 #endif 2046 } 2047 2048 /* 2049 * NOTE: This function will be removed once the peripheral controller code 2050 * is integrated and the driver is stable 2051 */ 2052 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2053 { 2054 #ifdef DWC2_DUMP_FRREM 2055 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2056 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2057 hsotg->frrem_samples, hsotg->frrem_accum, 2058 hsotg->frrem_samples > 0 ? 2059 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2060 dev_dbg(hsotg->dev, "\n"); 2061 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2062 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2063 hsotg->hfnum_7_samples, 2064 hsotg->hfnum_7_frrem_accum, 2065 hsotg->hfnum_7_samples > 0 ? 2066 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2067 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2068 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2069 hsotg->hfnum_0_samples, 2070 hsotg->hfnum_0_frrem_accum, 2071 hsotg->hfnum_0_samples > 0 ? 2072 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2073 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2074 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2075 hsotg->hfnum_other_samples, 2076 hsotg->hfnum_other_frrem_accum, 2077 hsotg->hfnum_other_samples > 0 ? 2078 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2079 0); 2080 dev_dbg(hsotg->dev, "\n"); 2081 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2082 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2083 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2084 hsotg->hfnum_7_samples_a > 0 ? 2085 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2086 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2087 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2088 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2089 hsotg->hfnum_0_samples_a > 0 ? 2090 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2091 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2092 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2093 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2094 hsotg->hfnum_other_samples_a > 0 ? 2095 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2096 : 0); 2097 dev_dbg(hsotg->dev, "\n"); 2098 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2099 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2100 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2101 hsotg->hfnum_7_samples_b > 0 ? 2102 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2103 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2104 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2105 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2106 (hsotg->hfnum_0_samples_b > 0) ? 2107 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2108 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2109 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2110 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2111 (hsotg->hfnum_other_samples_b > 0) ? 2112 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2113 : 0); 2114 #endif 2115 } 2116 2117 struct wrapper_priv_data { 2118 struct dwc2_hsotg *hsotg; 2119 }; 2120 2121 /* Gets the dwc2_hsotg from a usb_hcd */ 2122 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2123 { 2124 struct wrapper_priv_data *p; 2125 2126 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2127 return p->hsotg; 2128 } 2129 2130 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2131 2132 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2133 { 2134 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2135 2136 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2137 _dwc2_hcd_start(hcd); 2138 } 2139 2140 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2141 { 2142 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2143 2144 hcd->self.is_b_host = 0; 2145 } 2146 2147 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2148 int *hub_port) 2149 { 2150 struct urb *urb = context; 2151 2152 if (urb->dev->tt) 2153 *hub_addr = urb->dev->tt->hub->devnum; 2154 else 2155 *hub_addr = 0; 2156 *hub_port = urb->dev->ttport; 2157 } 2158 2159 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2160 { 2161 struct urb *urb = context; 2162 2163 return urb->dev->speed; 2164 } 2165 2166 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2167 struct urb *urb) 2168 { 2169 struct usb_bus *bus = hcd_to_bus(hcd); 2170 2171 if (urb->interval) 2172 bus->bandwidth_allocated += bw / urb->interval; 2173 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2174 bus->bandwidth_isoc_reqs++; 2175 else 2176 bus->bandwidth_int_reqs++; 2177 } 2178 2179 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2180 struct urb *urb) 2181 { 2182 struct usb_bus *bus = hcd_to_bus(hcd); 2183 2184 if (urb->interval) 2185 bus->bandwidth_allocated -= bw / urb->interval; 2186 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2187 bus->bandwidth_isoc_reqs--; 2188 else 2189 bus->bandwidth_int_reqs--; 2190 } 2191 2192 /* 2193 * Sets the final status of an URB and returns it to the upper layer. Any 2194 * required cleanup of the URB is performed. 2195 * 2196 * Must be called with interrupt disabled and spinlock held 2197 */ 2198 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2199 int status) 2200 { 2201 struct urb *urb; 2202 int i; 2203 2204 if (!qtd) { 2205 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2206 return; 2207 } 2208 2209 if (!qtd->urb) { 2210 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2211 return; 2212 } 2213 2214 urb = qtd->urb->priv; 2215 if (!urb) { 2216 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2217 return; 2218 } 2219 2220 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2221 2222 if (dbg_urb(urb)) 2223 dev_vdbg(hsotg->dev, 2224 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2225 __func__, urb, usb_pipedevice(urb->pipe), 2226 usb_pipeendpoint(urb->pipe), 2227 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2228 urb->actual_length); 2229 2230 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2231 for (i = 0; i < urb->number_of_packets; i++) 2232 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2233 i, urb->iso_frame_desc[i].status); 2234 } 2235 2236 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2237 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2238 for (i = 0; i < urb->number_of_packets; ++i) { 2239 urb->iso_frame_desc[i].actual_length = 2240 dwc2_hcd_urb_get_iso_desc_actual_length( 2241 qtd->urb, i); 2242 urb->iso_frame_desc[i].status = 2243 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2244 } 2245 } 2246 2247 urb->status = status; 2248 if (!status) { 2249 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2250 urb->actual_length < urb->transfer_buffer_length) 2251 urb->status = -EREMOTEIO; 2252 } 2253 2254 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2255 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2256 struct usb_host_endpoint *ep = urb->ep; 2257 2258 if (ep) 2259 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2260 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2261 urb); 2262 } 2263 2264 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2265 urb->hcpriv = NULL; 2266 kfree(qtd->urb); 2267 qtd->urb = NULL; 2268 2269 spin_unlock(&hsotg->lock); 2270 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2271 spin_lock(&hsotg->lock); 2272 } 2273 2274 /* 2275 * Work queue function for starting the HCD when A-Cable is connected 2276 */ 2277 static void dwc2_hcd_start_func(struct work_struct *work) 2278 { 2279 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2280 start_work.work); 2281 2282 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2283 dwc2_host_start(hsotg); 2284 } 2285 2286 /* 2287 * Reset work queue function 2288 */ 2289 static void dwc2_hcd_reset_func(struct work_struct *work) 2290 { 2291 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2292 reset_work.work); 2293 u32 hprt0; 2294 2295 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2296 hprt0 = dwc2_read_hprt0(hsotg); 2297 hprt0 &= ~HPRT0_RST; 2298 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2299 hsotg->flags.b.port_reset_change = 1; 2300 } 2301 2302 /* 2303 * ========================================================================= 2304 * Linux HC Driver Functions 2305 * ========================================================================= 2306 */ 2307 2308 /* 2309 * Initializes the DWC_otg controller and its root hub and prepares it for host 2310 * mode operation. Activates the root port. Returns 0 on success and a negative 2311 * error code on failure. 2312 */ 2313 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2314 { 2315 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2316 struct usb_bus *bus = hcd_to_bus(hcd); 2317 unsigned long flags; 2318 2319 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2320 2321 spin_lock_irqsave(&hsotg->lock, flags); 2322 hsotg->lx_state = DWC2_L0; 2323 hcd->state = HC_STATE_RUNNING; 2324 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2325 2326 if (dwc2_is_device_mode(hsotg)) { 2327 spin_unlock_irqrestore(&hsotg->lock, flags); 2328 return 0; /* why 0 ?? */ 2329 } 2330 2331 dwc2_hcd_reinit(hsotg); 2332 2333 /* Initialize and connect root hub if one is not already attached */ 2334 if (bus->root_hub) { 2335 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2336 /* Inform the HUB driver to resume */ 2337 usb_hcd_resume_root_hub(hcd); 2338 } 2339 2340 spin_unlock_irqrestore(&hsotg->lock, flags); 2341 return 0; 2342 } 2343 2344 /* 2345 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2346 * stopped. 2347 */ 2348 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2349 { 2350 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2351 unsigned long flags; 2352 2353 /* Turn off all host-specific interrupts */ 2354 dwc2_disable_host_interrupts(hsotg); 2355 2356 /* Wait for interrupt processing to finish */ 2357 synchronize_irq(hcd->irq); 2358 2359 spin_lock_irqsave(&hsotg->lock, flags); 2360 /* Ensure hcd is disconnected */ 2361 dwc2_hcd_disconnect(hsotg); 2362 dwc2_hcd_stop(hsotg); 2363 hsotg->lx_state = DWC2_L3; 2364 hcd->state = HC_STATE_HALT; 2365 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2366 spin_unlock_irqrestore(&hsotg->lock, flags); 2367 2368 usleep_range(1000, 3000); 2369 } 2370 2371 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2372 { 2373 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2374 unsigned long flags; 2375 int ret = 0; 2376 u32 hprt0; 2377 2378 spin_lock_irqsave(&hsotg->lock, flags); 2379 2380 if (hsotg->lx_state != DWC2_L0) 2381 goto unlock; 2382 2383 if (!HCD_HW_ACCESSIBLE(hcd)) 2384 goto unlock; 2385 2386 if (!hsotg->core_params->hibernation) 2387 goto skip_power_saving; 2388 2389 /* 2390 * Drive USB suspend and disable port Power 2391 * if usb bus is not suspended. 2392 */ 2393 if (!hsotg->bus_suspended) { 2394 hprt0 = dwc2_read_hprt0(hsotg); 2395 hprt0 |= HPRT0_SUSP; 2396 hprt0 &= ~HPRT0_PWR; 2397 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2398 } 2399 2400 /* Enter hibernation */ 2401 ret = dwc2_enter_hibernation(hsotg); 2402 if (ret) { 2403 if (ret != -ENOTSUPP) 2404 dev_err(hsotg->dev, 2405 "enter hibernation failed\n"); 2406 goto skip_power_saving; 2407 } 2408 2409 /* Ask phy to be suspended */ 2410 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2411 spin_unlock_irqrestore(&hsotg->lock, flags); 2412 usb_phy_set_suspend(hsotg->uphy, true); 2413 spin_lock_irqsave(&hsotg->lock, flags); 2414 } 2415 2416 /* After entering hibernation, hardware is no more accessible */ 2417 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2418 2419 skip_power_saving: 2420 hsotg->lx_state = DWC2_L2; 2421 unlock: 2422 spin_unlock_irqrestore(&hsotg->lock, flags); 2423 2424 return ret; 2425 } 2426 2427 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2428 { 2429 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2430 unsigned long flags; 2431 int ret = 0; 2432 2433 spin_lock_irqsave(&hsotg->lock, flags); 2434 2435 if (hsotg->lx_state != DWC2_L2) 2436 goto unlock; 2437 2438 if (!hsotg->core_params->hibernation) { 2439 hsotg->lx_state = DWC2_L0; 2440 goto unlock; 2441 } 2442 2443 /* 2444 * Set HW accessible bit before powering on the controller 2445 * since an interrupt may rise. 2446 */ 2447 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2448 2449 /* 2450 * Enable power if not already done. 2451 * This must not be spinlocked since duration 2452 * of this call is unknown. 2453 */ 2454 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2455 spin_unlock_irqrestore(&hsotg->lock, flags); 2456 usb_phy_set_suspend(hsotg->uphy, false); 2457 spin_lock_irqsave(&hsotg->lock, flags); 2458 } 2459 2460 /* Exit hibernation */ 2461 ret = dwc2_exit_hibernation(hsotg, true); 2462 if (ret && (ret != -ENOTSUPP)) 2463 dev_err(hsotg->dev, "exit hibernation failed\n"); 2464 2465 hsotg->lx_state = DWC2_L0; 2466 2467 spin_unlock_irqrestore(&hsotg->lock, flags); 2468 2469 if (hsotg->bus_suspended) { 2470 spin_lock_irqsave(&hsotg->lock, flags); 2471 hsotg->flags.b.port_suspend_change = 1; 2472 spin_unlock_irqrestore(&hsotg->lock, flags); 2473 dwc2_port_resume(hsotg); 2474 } else { 2475 /* Wait for controller to correctly update D+/D- level */ 2476 usleep_range(3000, 5000); 2477 2478 /* 2479 * Clear Port Enable and Port Status changes. 2480 * Enable Port Power. 2481 */ 2482 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 2483 HPRT0_ENACHG, hsotg->regs + HPRT0); 2484 /* Wait for controller to detect Port Connect */ 2485 usleep_range(5000, 7000); 2486 } 2487 2488 return ret; 2489 unlock: 2490 spin_unlock_irqrestore(&hsotg->lock, flags); 2491 2492 return ret; 2493 } 2494 2495 /* Returns the current frame number */ 2496 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2497 { 2498 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2499 2500 return dwc2_hcd_get_frame_number(hsotg); 2501 } 2502 2503 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2504 char *fn_name) 2505 { 2506 #ifdef VERBOSE_DEBUG 2507 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2508 char *pipetype; 2509 char *speed; 2510 2511 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2512 dev_vdbg(hsotg->dev, " Device address: %d\n", 2513 usb_pipedevice(urb->pipe)); 2514 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2515 usb_pipeendpoint(urb->pipe), 2516 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2517 2518 switch (usb_pipetype(urb->pipe)) { 2519 case PIPE_CONTROL: 2520 pipetype = "CONTROL"; 2521 break; 2522 case PIPE_BULK: 2523 pipetype = "BULK"; 2524 break; 2525 case PIPE_INTERRUPT: 2526 pipetype = "INTERRUPT"; 2527 break; 2528 case PIPE_ISOCHRONOUS: 2529 pipetype = "ISOCHRONOUS"; 2530 break; 2531 default: 2532 pipetype = "UNKNOWN"; 2533 break; 2534 } 2535 2536 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2537 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2538 "IN" : "OUT"); 2539 2540 switch (urb->dev->speed) { 2541 case USB_SPEED_HIGH: 2542 speed = "HIGH"; 2543 break; 2544 case USB_SPEED_FULL: 2545 speed = "FULL"; 2546 break; 2547 case USB_SPEED_LOW: 2548 speed = "LOW"; 2549 break; 2550 default: 2551 speed = "UNKNOWN"; 2552 break; 2553 } 2554 2555 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2556 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2557 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2558 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2559 urb->transfer_buffer_length); 2560 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2561 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2562 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2563 urb->setup_packet, (unsigned long)urb->setup_dma); 2564 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2565 2566 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2567 int i; 2568 2569 for (i = 0; i < urb->number_of_packets; i++) { 2570 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2571 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2572 urb->iso_frame_desc[i].offset, 2573 urb->iso_frame_desc[i].length); 2574 } 2575 } 2576 #endif 2577 } 2578 2579 /* 2580 * Starts processing a USB transfer request specified by a USB Request Block 2581 * (URB). mem_flags indicates the type of memory allocation to use while 2582 * processing this URB. 2583 */ 2584 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2585 gfp_t mem_flags) 2586 { 2587 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2588 struct usb_host_endpoint *ep = urb->ep; 2589 struct dwc2_hcd_urb *dwc2_urb; 2590 int i; 2591 int retval; 2592 int alloc_bandwidth = 0; 2593 u8 ep_type = 0; 2594 u32 tflags = 0; 2595 void *buf; 2596 unsigned long flags; 2597 struct dwc2_qh *qh; 2598 bool qh_allocated = false; 2599 struct dwc2_qtd *qtd; 2600 2601 if (dbg_urb(urb)) { 2602 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2603 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2604 } 2605 2606 if (ep == NULL) 2607 return -EINVAL; 2608 2609 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2610 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2611 spin_lock_irqsave(&hsotg->lock, flags); 2612 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2613 alloc_bandwidth = 1; 2614 spin_unlock_irqrestore(&hsotg->lock, flags); 2615 } 2616 2617 switch (usb_pipetype(urb->pipe)) { 2618 case PIPE_CONTROL: 2619 ep_type = USB_ENDPOINT_XFER_CONTROL; 2620 break; 2621 case PIPE_ISOCHRONOUS: 2622 ep_type = USB_ENDPOINT_XFER_ISOC; 2623 break; 2624 case PIPE_BULK: 2625 ep_type = USB_ENDPOINT_XFER_BULK; 2626 break; 2627 case PIPE_INTERRUPT: 2628 ep_type = USB_ENDPOINT_XFER_INT; 2629 break; 2630 default: 2631 dev_warn(hsotg->dev, "Wrong ep type\n"); 2632 } 2633 2634 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2635 mem_flags); 2636 if (!dwc2_urb) 2637 return -ENOMEM; 2638 2639 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2640 usb_pipeendpoint(urb->pipe), ep_type, 2641 usb_pipein(urb->pipe), 2642 usb_maxpacket(urb->dev, urb->pipe, 2643 !(usb_pipein(urb->pipe)))); 2644 2645 buf = urb->transfer_buffer; 2646 2647 if (hcd->self.uses_dma) { 2648 if (!buf && (urb->transfer_dma & 3)) { 2649 dev_err(hsotg->dev, 2650 "%s: unaligned transfer with no transfer_buffer", 2651 __func__); 2652 retval = -EINVAL; 2653 goto fail0; 2654 } 2655 } 2656 2657 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2658 tflags |= URB_GIVEBACK_ASAP; 2659 if (urb->transfer_flags & URB_ZERO_PACKET) 2660 tflags |= URB_SEND_ZERO_PACKET; 2661 2662 dwc2_urb->priv = urb; 2663 dwc2_urb->buf = buf; 2664 dwc2_urb->dma = urb->transfer_dma; 2665 dwc2_urb->length = urb->transfer_buffer_length; 2666 dwc2_urb->setup_packet = urb->setup_packet; 2667 dwc2_urb->setup_dma = urb->setup_dma; 2668 dwc2_urb->flags = tflags; 2669 dwc2_urb->interval = urb->interval; 2670 dwc2_urb->status = -EINPROGRESS; 2671 2672 for (i = 0; i < urb->number_of_packets; ++i) 2673 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2674 urb->iso_frame_desc[i].offset, 2675 urb->iso_frame_desc[i].length); 2676 2677 urb->hcpriv = dwc2_urb; 2678 qh = (struct dwc2_qh *) ep->hcpriv; 2679 /* Create QH for the endpoint if it doesn't exist */ 2680 if (!qh) { 2681 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2682 if (!qh) { 2683 retval = -ENOMEM; 2684 goto fail0; 2685 } 2686 ep->hcpriv = qh; 2687 qh_allocated = true; 2688 } 2689 2690 qtd = kzalloc(sizeof(*qtd), mem_flags); 2691 if (!qtd) { 2692 retval = -ENOMEM; 2693 goto fail1; 2694 } 2695 2696 spin_lock_irqsave(&hsotg->lock, flags); 2697 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2698 if (retval) 2699 goto fail2; 2700 2701 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2702 if (retval) 2703 goto fail3; 2704 2705 if (alloc_bandwidth) { 2706 dwc2_allocate_bus_bandwidth(hcd, 2707 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2708 urb); 2709 } 2710 2711 spin_unlock_irqrestore(&hsotg->lock, flags); 2712 2713 return 0; 2714 2715 fail3: 2716 dwc2_urb->priv = NULL; 2717 usb_hcd_unlink_urb_from_ep(hcd, urb); 2718 fail2: 2719 spin_unlock_irqrestore(&hsotg->lock, flags); 2720 urb->hcpriv = NULL; 2721 kfree(qtd); 2722 fail1: 2723 if (qh_allocated) { 2724 struct dwc2_qtd *qtd2, *qtd2_tmp; 2725 2726 ep->hcpriv = NULL; 2727 dwc2_hcd_qh_unlink(hsotg, qh); 2728 /* Free each QTD in the QH's QTD list */ 2729 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2730 qtd_list_entry) 2731 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2732 dwc2_hcd_qh_free(hsotg, qh); 2733 } 2734 fail0: 2735 kfree(dwc2_urb); 2736 2737 return retval; 2738 } 2739 2740 /* 2741 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2742 */ 2743 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2744 int status) 2745 { 2746 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2747 int rc; 2748 unsigned long flags; 2749 2750 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2751 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2752 2753 spin_lock_irqsave(&hsotg->lock, flags); 2754 2755 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2756 if (rc) 2757 goto out; 2758 2759 if (!urb->hcpriv) { 2760 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2761 goto out; 2762 } 2763 2764 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2765 2766 usb_hcd_unlink_urb_from_ep(hcd, urb); 2767 2768 kfree(urb->hcpriv); 2769 urb->hcpriv = NULL; 2770 2771 /* Higher layer software sets URB status */ 2772 spin_unlock(&hsotg->lock); 2773 usb_hcd_giveback_urb(hcd, urb, status); 2774 spin_lock(&hsotg->lock); 2775 2776 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2777 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2778 out: 2779 spin_unlock_irqrestore(&hsotg->lock, flags); 2780 2781 return rc; 2782 } 2783 2784 /* 2785 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2786 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2787 * must already be dequeued. 2788 */ 2789 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2790 struct usb_host_endpoint *ep) 2791 { 2792 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2793 2794 dev_dbg(hsotg->dev, 2795 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2796 ep->desc.bEndpointAddress, ep->hcpriv); 2797 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2798 } 2799 2800 /* 2801 * Resets endpoint specific parameter values, in current version used to reset 2802 * the data toggle (as a WA). This function can be called from usb_clear_halt 2803 * routine. 2804 */ 2805 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2806 struct usb_host_endpoint *ep) 2807 { 2808 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2809 unsigned long flags; 2810 2811 dev_dbg(hsotg->dev, 2812 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2813 ep->desc.bEndpointAddress); 2814 2815 spin_lock_irqsave(&hsotg->lock, flags); 2816 dwc2_hcd_endpoint_reset(hsotg, ep); 2817 spin_unlock_irqrestore(&hsotg->lock, flags); 2818 } 2819 2820 /* 2821 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2822 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2823 * interrupt. 2824 * 2825 * This function is called by the USB core when an interrupt occurs 2826 */ 2827 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2828 { 2829 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2830 2831 return dwc2_handle_hcd_intr(hsotg); 2832 } 2833 2834 /* 2835 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2836 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2837 * is the status change indicator for the single root port. Returns 1 if either 2838 * change indicator is 1, otherwise returns 0. 2839 */ 2840 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2841 { 2842 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2843 2844 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2845 return buf[0] != 0; 2846 } 2847 2848 /* Handles hub class-specific requests */ 2849 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2850 u16 windex, char *buf, u16 wlength) 2851 { 2852 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2853 wvalue, windex, buf, wlength); 2854 return retval; 2855 } 2856 2857 /* Handles hub TT buffer clear completions */ 2858 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2859 struct usb_host_endpoint *ep) 2860 { 2861 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2862 struct dwc2_qh *qh; 2863 unsigned long flags; 2864 2865 qh = ep->hcpriv; 2866 if (!qh) 2867 return; 2868 2869 spin_lock_irqsave(&hsotg->lock, flags); 2870 qh->tt_buffer_dirty = 0; 2871 2872 if (hsotg->flags.b.port_connect_status) 2873 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2874 2875 spin_unlock_irqrestore(&hsotg->lock, flags); 2876 } 2877 2878 static struct hc_driver dwc2_hc_driver = { 2879 .description = "dwc2_hsotg", 2880 .product_desc = "DWC OTG Controller", 2881 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2882 2883 .irq = _dwc2_hcd_irq, 2884 .flags = HCD_MEMORY | HCD_USB2, 2885 2886 .start = _dwc2_hcd_start, 2887 .stop = _dwc2_hcd_stop, 2888 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2889 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2890 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2891 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2892 .get_frame_number = _dwc2_hcd_get_frame_number, 2893 2894 .hub_status_data = _dwc2_hcd_hub_status_data, 2895 .hub_control = _dwc2_hcd_hub_control, 2896 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2897 2898 .bus_suspend = _dwc2_hcd_suspend, 2899 .bus_resume = _dwc2_hcd_resume, 2900 }; 2901 2902 /* 2903 * Frees secondary storage associated with the dwc2_hsotg structure contained 2904 * in the struct usb_hcd field 2905 */ 2906 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2907 { 2908 u32 ahbcfg; 2909 u32 dctl; 2910 int i; 2911 2912 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2913 2914 /* Free memory for QH/QTD lists */ 2915 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2916 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2917 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2918 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2919 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2920 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2921 2922 /* Free memory for the host channels */ 2923 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2924 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2925 2926 if (chan != NULL) { 2927 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2928 i, chan); 2929 hsotg->hc_ptr_array[i] = NULL; 2930 kfree(chan); 2931 } 2932 } 2933 2934 if (hsotg->core_params->dma_enable > 0) { 2935 if (hsotg->status_buf) { 2936 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2937 hsotg->status_buf, 2938 hsotg->status_buf_dma); 2939 hsotg->status_buf = NULL; 2940 } 2941 } else { 2942 kfree(hsotg->status_buf); 2943 hsotg->status_buf = NULL; 2944 } 2945 2946 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 2947 2948 /* Disable all interrupts */ 2949 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2950 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 2951 dwc2_writel(0, hsotg->regs + GINTMSK); 2952 2953 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2954 dctl = dwc2_readl(hsotg->regs + DCTL); 2955 dctl |= DCTL_SFTDISCON; 2956 dwc2_writel(dctl, hsotg->regs + DCTL); 2957 } 2958 2959 if (hsotg->wq_otg) { 2960 if (!cancel_work_sync(&hsotg->wf_otg)) 2961 flush_workqueue(hsotg->wq_otg); 2962 destroy_workqueue(hsotg->wq_otg); 2963 } 2964 2965 del_timer(&hsotg->wkp_timer); 2966 } 2967 2968 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2969 { 2970 /* Turn off all host-specific interrupts */ 2971 dwc2_disable_host_interrupts(hsotg); 2972 2973 dwc2_hcd_free(hsotg); 2974 } 2975 2976 /* 2977 * Initializes the HCD. This function allocates memory for and initializes the 2978 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2979 * USB bus with the core and calls the hc_driver->start() function. It returns 2980 * a negative error on failure. 2981 */ 2982 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 2983 { 2984 struct usb_hcd *hcd; 2985 struct dwc2_host_chan *channel; 2986 u32 hcfg; 2987 int i, num_channels; 2988 int retval; 2989 2990 if (usb_disabled()) 2991 return -ENODEV; 2992 2993 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2994 2995 retval = -ENOMEM; 2996 2997 hcfg = dwc2_readl(hsotg->regs + HCFG); 2998 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2999 3000 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3001 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 3002 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3003 if (!hsotg->frame_num_array) 3004 goto error1; 3005 hsotg->last_frame_num_array = kzalloc( 3006 sizeof(*hsotg->last_frame_num_array) * 3007 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3008 if (!hsotg->last_frame_num_array) 3009 goto error1; 3010 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 3011 #endif 3012 3013 /* Check if the bus driver or platform code has setup a dma_mask */ 3014 if (hsotg->core_params->dma_enable > 0 && 3015 hsotg->dev->dma_mask == NULL) { 3016 dev_warn(hsotg->dev, 3017 "dma_mask not set, disabling DMA\n"); 3018 hsotg->core_params->dma_enable = 0; 3019 hsotg->core_params->dma_desc_enable = 0; 3020 } 3021 3022 /* Set device flags indicating whether the HCD supports DMA */ 3023 if (hsotg->core_params->dma_enable > 0) { 3024 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3025 dev_warn(hsotg->dev, "can't set DMA mask\n"); 3026 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3027 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 3028 } 3029 3030 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 3031 if (!hcd) 3032 goto error1; 3033 3034 if (hsotg->core_params->dma_enable <= 0) 3035 hcd->self.uses_dma = 0; 3036 3037 hcd->has_tt = 1; 3038 3039 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 3040 hsotg->priv = hcd; 3041 3042 /* 3043 * Disable the global interrupt until all the interrupt handlers are 3044 * installed 3045 */ 3046 dwc2_disable_global_interrupts(hsotg); 3047 3048 /* Initialize the DWC_otg core, and select the Phy type */ 3049 retval = dwc2_core_init(hsotg, true, irq); 3050 if (retval) 3051 goto error2; 3052 3053 /* Create new workqueue and init work */ 3054 retval = -ENOMEM; 3055 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 3056 if (!hsotg->wq_otg) { 3057 dev_err(hsotg->dev, "Failed to create workqueue\n"); 3058 goto error2; 3059 } 3060 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 3061 3062 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 3063 (unsigned long)hsotg); 3064 3065 /* Initialize the non-periodic schedule */ 3066 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 3067 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 3068 3069 /* Initialize the periodic schedule */ 3070 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 3071 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 3072 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 3073 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 3074 3075 /* 3076 * Create a host channel descriptor for each host channel implemented 3077 * in the controller. Initialize the channel descriptor array. 3078 */ 3079 INIT_LIST_HEAD(&hsotg->free_hc_list); 3080 num_channels = hsotg->core_params->host_channels; 3081 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 3082 3083 for (i = 0; i < num_channels; i++) { 3084 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 3085 if (channel == NULL) 3086 goto error3; 3087 channel->hc_num = i; 3088 hsotg->hc_ptr_array[i] = channel; 3089 } 3090 3091 if (hsotg->core_params->uframe_sched > 0) 3092 dwc2_hcd_init_usecs(hsotg); 3093 3094 /* Initialize hsotg start work */ 3095 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 3096 3097 /* Initialize port reset work */ 3098 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 3099 3100 /* 3101 * Allocate space for storing data on status transactions. Normally no 3102 * data is sent, but this space acts as a bit bucket. This must be 3103 * done after usb_add_hcd since that function allocates the DMA buffer 3104 * pool. 3105 */ 3106 if (hsotg->core_params->dma_enable > 0) 3107 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 3108 DWC2_HCD_STATUS_BUF_SIZE, 3109 &hsotg->status_buf_dma, GFP_KERNEL); 3110 else 3111 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 3112 GFP_KERNEL); 3113 3114 if (!hsotg->status_buf) 3115 goto error3; 3116 3117 hsotg->otg_port = 1; 3118 hsotg->frame_list = NULL; 3119 hsotg->frame_list_dma = 0; 3120 hsotg->periodic_qh_count = 0; 3121 3122 /* Initiate lx_state to L3 disconnected state */ 3123 hsotg->lx_state = DWC2_L3; 3124 3125 hcd->self.otg_port = hsotg->otg_port; 3126 3127 /* Don't support SG list at this point */ 3128 hcd->self.sg_tablesize = 0; 3129 3130 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3131 otg_set_host(hsotg->uphy->otg, &hcd->self); 3132 3133 /* 3134 * Finish generic HCD initialization and start the HCD. This function 3135 * allocates the DMA buffer pool, registers the USB bus, requests the 3136 * IRQ line, and calls hcd_start method. 3137 */ 3138 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3139 if (retval < 0) 3140 goto error3; 3141 3142 device_wakeup_enable(hcd->self.controller); 3143 3144 dwc2_hcd_dump_state(hsotg); 3145 3146 dwc2_enable_global_interrupts(hsotg); 3147 3148 return 0; 3149 3150 error3: 3151 dwc2_hcd_release(hsotg); 3152 error2: 3153 usb_put_hcd(hcd); 3154 error1: 3155 kfree(hsotg->core_params); 3156 3157 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3158 kfree(hsotg->last_frame_num_array); 3159 kfree(hsotg->frame_num_array); 3160 #endif 3161 3162 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3163 return retval; 3164 } 3165 3166 /* 3167 * Removes the HCD. 3168 * Frees memory and resources associated with the HCD and deregisters the bus. 3169 */ 3170 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3171 { 3172 struct usb_hcd *hcd; 3173 3174 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3175 3176 hcd = dwc2_hsotg_to_hcd(hsotg); 3177 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3178 3179 if (!hcd) { 3180 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3181 __func__); 3182 return; 3183 } 3184 3185 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3186 otg_set_host(hsotg->uphy->otg, NULL); 3187 3188 usb_remove_hcd(hcd); 3189 hsotg->priv = NULL; 3190 dwc2_hcd_release(hsotg); 3191 usb_put_hcd(hcd); 3192 3193 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3194 kfree(hsotg->last_frame_num_array); 3195 kfree(hsotg->frame_num_array); 3196 #endif 3197 } 3198