xref: /openbmc/linux/drivers/usb/dwc2/hcd.c (revision 52fb57e7)
1 /*
2  * hcd.c - DesignWare HS OTG Controller host-mode routines
3  *
4  * Copyright (C) 2004-2013 Synopsys, Inc.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer,
11  *    without modification.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. The names of the above-listed copyright holders may not be used
16  *    to endorse or promote products derived from this software without
17  *    specific prior written permission.
18  *
19  * ALTERNATIVELY, this software may be distributed under the terms of the
20  * GNU General Public License ("GPL") as published by the Free Software
21  * Foundation; either version 2 of the License, or (at your option) any
22  * later version.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  */
36 
37 /*
38  * This file contains the core HCD code, and implements the Linux hc_driver
39  * API
40  */
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/spinlock.h>
44 #include <linux/interrupt.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/delay.h>
47 #include <linux/io.h>
48 #include <linux/slab.h>
49 #include <linux/usb.h>
50 
51 #include <linux/usb/hcd.h>
52 #include <linux/usb/ch11.h>
53 
54 #include "core.h"
55 #include "hcd.h"
56 
57 /**
58  * dwc2_dump_channel_info() - Prints the state of a host channel
59  *
60  * @hsotg: Programming view of DWC_otg controller
61  * @chan:  Pointer to the channel to dump
62  *
63  * Must be called with interrupt disabled and spinlock held
64  *
65  * NOTE: This function will be removed once the peripheral controller code
66  * is integrated and the driver is stable
67  */
68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 				   struct dwc2_host_chan *chan)
70 {
71 #ifdef VERBOSE_DEBUG
72 	int num_channels = hsotg->core_params->host_channels;
73 	struct dwc2_qh *qh;
74 	u32 hcchar;
75 	u32 hcsplt;
76 	u32 hctsiz;
77 	u32 hc_dma;
78 	int i;
79 
80 	if (chan == NULL)
81 		return;
82 
83 	hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 	hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 	hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 	hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
87 
88 	dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
89 	dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
90 		hcchar, hcsplt);
91 	dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
92 		hctsiz, hc_dma);
93 	dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 		chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 	dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
96 	dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
97 	dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
98 	dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
99 	dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
100 	dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
101 	dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
102 		(unsigned long)chan->xfer_dma);
103 	dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
104 	dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
105 	dev_dbg(hsotg->dev, "  NP inactive sched:\n");
106 	list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 			    qh_list_entry)
108 		dev_dbg(hsotg->dev, "    %p\n", qh);
109 	dev_dbg(hsotg->dev, "  NP active sched:\n");
110 	list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 			    qh_list_entry)
112 		dev_dbg(hsotg->dev, "    %p\n", qh);
113 	dev_dbg(hsotg->dev, "  Channels:\n");
114 	for (i = 0; i < num_channels; i++) {
115 		struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116 
117 		dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
118 	}
119 #endif /* VERBOSE_DEBUG */
120 }
121 
122 /*
123  * Processes all the URBs in a single list of QHs. Completes them with
124  * -ETIMEDOUT and frees the QTD.
125  *
126  * Must be called with interrupt disabled and spinlock held
127  */
128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 				      struct list_head *qh_list)
130 {
131 	struct dwc2_qh *qh, *qh_tmp;
132 	struct dwc2_qtd *qtd, *qtd_tmp;
133 
134 	list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 		list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 					 qtd_list_entry) {
137 			dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 			dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
139 		}
140 	}
141 }
142 
143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 			      struct list_head *qh_list)
145 {
146 	struct dwc2_qtd *qtd, *qtd_tmp;
147 	struct dwc2_qh *qh, *qh_tmp;
148 	unsigned long flags;
149 
150 	if (!qh_list->next)
151 		/* The list hasn't been initialized yet */
152 		return;
153 
154 	spin_lock_irqsave(&hsotg->lock, flags);
155 
156 	/* Ensure there are no QTDs or URBs left */
157 	dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158 
159 	list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 		dwc2_hcd_qh_unlink(hsotg, qh);
161 
162 		/* Free each QTD in the QH's QTD list */
163 		list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 					 qtd_list_entry)
165 			dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166 
167 		spin_unlock_irqrestore(&hsotg->lock, flags);
168 		dwc2_hcd_qh_free(hsotg, qh);
169 		spin_lock_irqsave(&hsotg->lock, flags);
170 	}
171 
172 	spin_unlock_irqrestore(&hsotg->lock, flags);
173 }
174 
175 /*
176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177  * and periodic schedules. The QTD associated with each URB is removed from
178  * the schedule and freed. This function may be called when a disconnect is
179  * detected or when the HCD is being stopped.
180  *
181  * Must be called with interrupt disabled and spinlock held
182  */
183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
184 {
185 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
191 }
192 
193 /**
194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
195  *
196  * @hsotg: Pointer to struct dwc2_hsotg
197  */
198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
199 {
200 	u32 hprt0;
201 
202 	if (hsotg->op_state == OTG_STATE_B_HOST) {
203 		/*
204 		 * Reset the port. During a HNP mode switch the reset
205 		 * needs to occur within 1ms and have a duration of at
206 		 * least 50ms.
207 		 */
208 		hprt0 = dwc2_read_hprt0(hsotg);
209 		hprt0 |= HPRT0_RST;
210 		writel(hprt0, hsotg->regs + HPRT0);
211 	}
212 
213 	queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 			   msecs_to_jiffies(50));
215 }
216 
217 /* Must be called with interrupt disabled and spinlock held */
218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
219 {
220 	int num_channels = hsotg->core_params->host_channels;
221 	struct dwc2_host_chan *channel;
222 	u32 hcchar;
223 	int i;
224 
225 	if (hsotg->core_params->dma_enable <= 0) {
226 		/* Flush out any channel requests in slave mode */
227 		for (i = 0; i < num_channels; i++) {
228 			channel = hsotg->hc_ptr_array[i];
229 			if (!list_empty(&channel->hc_list_entry))
230 				continue;
231 			hcchar = readl(hsotg->regs + HCCHAR(i));
232 			if (hcchar & HCCHAR_CHENA) {
233 				hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 				hcchar |= HCCHAR_CHDIS;
235 				writel(hcchar, hsotg->regs + HCCHAR(i));
236 			}
237 		}
238 	}
239 
240 	for (i = 0; i < num_channels; i++) {
241 		channel = hsotg->hc_ptr_array[i];
242 		if (!list_empty(&channel->hc_list_entry))
243 			continue;
244 		hcchar = readl(hsotg->regs + HCCHAR(i));
245 		if (hcchar & HCCHAR_CHENA) {
246 			/* Halt the channel */
247 			hcchar |= HCCHAR_CHDIS;
248 			writel(hcchar, hsotg->regs + HCCHAR(i));
249 		}
250 
251 		dwc2_hc_cleanup(hsotg, channel);
252 		list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
253 		/*
254 		 * Added for Descriptor DMA to prevent channel double cleanup in
255 		 * release_channel_ddma(), which is called from ep_disable when
256 		 * device disconnects
257 		 */
258 		channel->qh = NULL;
259 	}
260 	/* All channels have been freed, mark them available */
261 	if (hsotg->core_params->uframe_sched > 0) {
262 		hsotg->available_host_channels =
263 			hsotg->core_params->host_channels;
264 	} else {
265 		hsotg->non_periodic_channels = 0;
266 		hsotg->periodic_channels = 0;
267 	}
268 }
269 
270 /**
271  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
272  *
273  * @hsotg: Pointer to struct dwc2_hsotg
274  *
275  * Must be called with interrupt disabled and spinlock held
276  */
277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
278 {
279 	u32 intr;
280 
281 	/* Set status flags for the hub driver */
282 	hsotg->flags.b.port_connect_status_change = 1;
283 	hsotg->flags.b.port_connect_status = 0;
284 
285 	/*
286 	 * Shutdown any transfers in process by clearing the Tx FIFO Empty
287 	 * interrupt mask and status bits and disabling subsequent host
288 	 * channel interrupts.
289 	 */
290 	intr = readl(hsotg->regs + GINTMSK);
291 	intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
292 	writel(intr, hsotg->regs + GINTMSK);
293 	intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
294 	writel(intr, hsotg->regs + GINTSTS);
295 
296 	/*
297 	 * Turn off the vbus power only if the core has transitioned to device
298 	 * mode. If still in host mode, need to keep power on to detect a
299 	 * reconnection.
300 	 */
301 	if (dwc2_is_device_mode(hsotg)) {
302 		if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
303 			dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
304 			writel(0, hsotg->regs + HPRT0);
305 		}
306 
307 		dwc2_disable_host_interrupts(hsotg);
308 	}
309 
310 	/* Respond with an error status to all URBs in the schedule */
311 	dwc2_kill_all_urbs(hsotg);
312 
313 	if (dwc2_is_host_mode(hsotg))
314 		/* Clean up any host channels that were in use */
315 		dwc2_hcd_cleanup_channels(hsotg);
316 
317 	dwc2_host_disconnect(hsotg);
318 }
319 
320 /**
321  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
322  *
323  * @hsotg: Pointer to struct dwc2_hsotg
324  */
325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
326 {
327 	if (hsotg->lx_state == DWC2_L2) {
328 		hsotg->flags.b.port_suspend_change = 1;
329 		usb_hcd_resume_root_hub(hsotg->priv);
330 	} else {
331 		hsotg->flags.b.port_l1_change = 1;
332 	}
333 }
334 
335 /**
336  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
337  *
338  * @hsotg: Pointer to struct dwc2_hsotg
339  *
340  * Must be called with interrupt disabled and spinlock held
341  */
342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
343 {
344 	dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
345 
346 	/*
347 	 * The root hub should be disconnected before this function is called.
348 	 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
349 	 * and the QH lists (via ..._hcd_endpoint_disable).
350 	 */
351 
352 	/* Turn off all host-specific interrupts */
353 	dwc2_disable_host_interrupts(hsotg);
354 
355 	/* Turn off the vbus power */
356 	dev_dbg(hsotg->dev, "PortPower off\n");
357 	writel(0, hsotg->regs + HPRT0);
358 }
359 
360 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
361 				struct dwc2_hcd_urb *urb, void **ep_handle,
362 				gfp_t mem_flags)
363 {
364 	struct dwc2_qtd *qtd;
365 	unsigned long flags;
366 	u32 intr_mask;
367 	int retval;
368 	int dev_speed;
369 
370 	if (!hsotg->flags.b.port_connect_status) {
371 		/* No longer connected */
372 		dev_err(hsotg->dev, "Not connected\n");
373 		return -ENODEV;
374 	}
375 
376 	dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
377 
378 	/* Some configurations cannot support LS traffic on a FS root port */
379 	if ((dev_speed == USB_SPEED_LOW) &&
380 	    (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
381 	    (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
382 		u32 hprt0 = readl(hsotg->regs + HPRT0);
383 		u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
384 
385 		if (prtspd == HPRT0_SPD_FULL_SPEED)
386 			return -ENODEV;
387 	}
388 
389 	qtd = kzalloc(sizeof(*qtd), mem_flags);
390 	if (!qtd)
391 		return -ENOMEM;
392 
393 	dwc2_hcd_qtd_init(qtd, urb);
394 	retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
395 				  mem_flags);
396 	if (retval) {
397 		dev_err(hsotg->dev,
398 			"DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
399 			retval);
400 		kfree(qtd);
401 		return retval;
402 	}
403 
404 	intr_mask = readl(hsotg->regs + GINTMSK);
405 	if (!(intr_mask & GINTSTS_SOF)) {
406 		enum dwc2_transaction_type tr_type;
407 
408 		if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
409 		    !(qtd->urb->flags & URB_GIVEBACK_ASAP))
410 			/*
411 			 * Do not schedule SG transactions until qtd has
412 			 * URB_GIVEBACK_ASAP set
413 			 */
414 			return 0;
415 
416 		spin_lock_irqsave(&hsotg->lock, flags);
417 		tr_type = dwc2_hcd_select_transactions(hsotg);
418 		if (tr_type != DWC2_TRANSACTION_NONE)
419 			dwc2_hcd_queue_transactions(hsotg, tr_type);
420 		spin_unlock_irqrestore(&hsotg->lock, flags);
421 	}
422 
423 	return 0;
424 }
425 
426 /* Must be called with interrupt disabled and spinlock held */
427 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
428 				struct dwc2_hcd_urb *urb)
429 {
430 	struct dwc2_qh *qh;
431 	struct dwc2_qtd *urb_qtd;
432 
433 	urb_qtd = urb->qtd;
434 	if (!urb_qtd) {
435 		dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
436 		return -EINVAL;
437 	}
438 
439 	qh = urb_qtd->qh;
440 	if (!qh) {
441 		dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
442 		return -EINVAL;
443 	}
444 
445 	urb->priv = NULL;
446 
447 	if (urb_qtd->in_process && qh->channel) {
448 		dwc2_dump_channel_info(hsotg, qh->channel);
449 
450 		/* The QTD is in process (it has been assigned to a channel) */
451 		if (hsotg->flags.b.port_connect_status)
452 			/*
453 			 * If still connected (i.e. in host mode), halt the
454 			 * channel so it can be used for other transfers. If
455 			 * no longer connected, the host registers can't be
456 			 * written to halt the channel since the core is in
457 			 * device mode.
458 			 */
459 			dwc2_hc_halt(hsotg, qh->channel,
460 				     DWC2_HC_XFER_URB_DEQUEUE);
461 	}
462 
463 	/*
464 	 * Free the QTD and clean up the associated QH. Leave the QH in the
465 	 * schedule if it has any remaining QTDs.
466 	 */
467 	if (hsotg->core_params->dma_desc_enable <= 0) {
468 		u8 in_process = urb_qtd->in_process;
469 
470 		dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
471 		if (in_process) {
472 			dwc2_hcd_qh_deactivate(hsotg, qh, 0);
473 			qh->channel = NULL;
474 		} else if (list_empty(&qh->qtd_list)) {
475 			dwc2_hcd_qh_unlink(hsotg, qh);
476 		}
477 	} else {
478 		dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
479 	}
480 
481 	return 0;
482 }
483 
484 /* Must NOT be called with interrupt disabled or spinlock held */
485 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
486 				     struct usb_host_endpoint *ep, int retry)
487 {
488 	struct dwc2_qtd *qtd, *qtd_tmp;
489 	struct dwc2_qh *qh;
490 	unsigned long flags;
491 	int rc;
492 
493 	spin_lock_irqsave(&hsotg->lock, flags);
494 
495 	qh = ep->hcpriv;
496 	if (!qh) {
497 		rc = -EINVAL;
498 		goto err;
499 	}
500 
501 	while (!list_empty(&qh->qtd_list) && retry--) {
502 		if (retry == 0) {
503 			dev_err(hsotg->dev,
504 				"## timeout in dwc2_hcd_endpoint_disable() ##\n");
505 			rc = -EBUSY;
506 			goto err;
507 		}
508 
509 		spin_unlock_irqrestore(&hsotg->lock, flags);
510 		usleep_range(20000, 40000);
511 		spin_lock_irqsave(&hsotg->lock, flags);
512 		qh = ep->hcpriv;
513 		if (!qh) {
514 			rc = -EINVAL;
515 			goto err;
516 		}
517 	}
518 
519 	dwc2_hcd_qh_unlink(hsotg, qh);
520 
521 	/* Free each QTD in the QH's QTD list */
522 	list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
523 		dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
524 
525 	ep->hcpriv = NULL;
526 	spin_unlock_irqrestore(&hsotg->lock, flags);
527 	dwc2_hcd_qh_free(hsotg, qh);
528 
529 	return 0;
530 
531 err:
532 	ep->hcpriv = NULL;
533 	spin_unlock_irqrestore(&hsotg->lock, flags);
534 
535 	return rc;
536 }
537 
538 /* Must be called with interrupt disabled and spinlock held */
539 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
540 				   struct usb_host_endpoint *ep)
541 {
542 	struct dwc2_qh *qh = ep->hcpriv;
543 
544 	if (!qh)
545 		return -EINVAL;
546 
547 	qh->data_toggle = DWC2_HC_PID_DATA0;
548 
549 	return 0;
550 }
551 
552 /*
553  * Initializes dynamic portions of the DWC_otg HCD state
554  *
555  * Must be called with interrupt disabled and spinlock held
556  */
557 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
558 {
559 	struct dwc2_host_chan *chan, *chan_tmp;
560 	int num_channels;
561 	int i;
562 
563 	hsotg->flags.d32 = 0;
564 	hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
565 
566 	if (hsotg->core_params->uframe_sched > 0) {
567 		hsotg->available_host_channels =
568 			hsotg->core_params->host_channels;
569 	} else {
570 		hsotg->non_periodic_channels = 0;
571 		hsotg->periodic_channels = 0;
572 	}
573 
574 	/*
575 	 * Put all channels in the free channel list and clean up channel
576 	 * states
577 	 */
578 	list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
579 				 hc_list_entry)
580 		list_del_init(&chan->hc_list_entry);
581 
582 	num_channels = hsotg->core_params->host_channels;
583 	for (i = 0; i < num_channels; i++) {
584 		chan = hsotg->hc_ptr_array[i];
585 		list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
586 		dwc2_hc_cleanup(hsotg, chan);
587 	}
588 
589 	/* Initialize the DWC core for host mode operation */
590 	dwc2_core_host_init(hsotg);
591 }
592 
593 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
594 			       struct dwc2_host_chan *chan,
595 			       struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
596 {
597 	int hub_addr, hub_port;
598 
599 	chan->do_split = 1;
600 	chan->xact_pos = qtd->isoc_split_pos;
601 	chan->complete_split = qtd->complete_split;
602 	dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
603 	chan->hub_addr = (u8)hub_addr;
604 	chan->hub_port = (u8)hub_port;
605 }
606 
607 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
608 			       struct dwc2_host_chan *chan,
609 			       struct dwc2_qtd *qtd, void *bufptr)
610 {
611 	struct dwc2_hcd_urb *urb = qtd->urb;
612 	struct dwc2_hcd_iso_packet_desc *frame_desc;
613 
614 	switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
615 	case USB_ENDPOINT_XFER_CONTROL:
616 		chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
617 
618 		switch (qtd->control_phase) {
619 		case DWC2_CONTROL_SETUP:
620 			dev_vdbg(hsotg->dev, "  Control setup transaction\n");
621 			chan->do_ping = 0;
622 			chan->ep_is_in = 0;
623 			chan->data_pid_start = DWC2_HC_PID_SETUP;
624 			if (hsotg->core_params->dma_enable > 0)
625 				chan->xfer_dma = urb->setup_dma;
626 			else
627 				chan->xfer_buf = urb->setup_packet;
628 			chan->xfer_len = 8;
629 			bufptr = NULL;
630 			break;
631 
632 		case DWC2_CONTROL_DATA:
633 			dev_vdbg(hsotg->dev, "  Control data transaction\n");
634 			chan->data_pid_start = qtd->data_toggle;
635 			break;
636 
637 		case DWC2_CONTROL_STATUS:
638 			/*
639 			 * Direction is opposite of data direction or IN if no
640 			 * data
641 			 */
642 			dev_vdbg(hsotg->dev, "  Control status transaction\n");
643 			if (urb->length == 0)
644 				chan->ep_is_in = 1;
645 			else
646 				chan->ep_is_in =
647 					dwc2_hcd_is_pipe_out(&urb->pipe_info);
648 			if (chan->ep_is_in)
649 				chan->do_ping = 0;
650 			chan->data_pid_start = DWC2_HC_PID_DATA1;
651 			chan->xfer_len = 0;
652 			if (hsotg->core_params->dma_enable > 0)
653 				chan->xfer_dma = hsotg->status_buf_dma;
654 			else
655 				chan->xfer_buf = hsotg->status_buf;
656 			bufptr = NULL;
657 			break;
658 		}
659 		break;
660 
661 	case USB_ENDPOINT_XFER_BULK:
662 		chan->ep_type = USB_ENDPOINT_XFER_BULK;
663 		break;
664 
665 	case USB_ENDPOINT_XFER_INT:
666 		chan->ep_type = USB_ENDPOINT_XFER_INT;
667 		break;
668 
669 	case USB_ENDPOINT_XFER_ISOC:
670 		chan->ep_type = USB_ENDPOINT_XFER_ISOC;
671 		if (hsotg->core_params->dma_desc_enable > 0)
672 			break;
673 
674 		frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
675 		frame_desc->status = 0;
676 
677 		if (hsotg->core_params->dma_enable > 0) {
678 			chan->xfer_dma = urb->dma;
679 			chan->xfer_dma += frame_desc->offset +
680 					qtd->isoc_split_offset;
681 		} else {
682 			chan->xfer_buf = urb->buf;
683 			chan->xfer_buf += frame_desc->offset +
684 					qtd->isoc_split_offset;
685 		}
686 
687 		chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
688 
689 		/* For non-dword aligned buffers */
690 		if (hsotg->core_params->dma_enable > 0 &&
691 		    (chan->xfer_dma & 0x3))
692 			bufptr = (u8 *)urb->buf + frame_desc->offset +
693 					qtd->isoc_split_offset;
694 		else
695 			bufptr = NULL;
696 
697 		if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
698 			if (chan->xfer_len <= 188)
699 				chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
700 			else
701 				chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
702 		}
703 		break;
704 	}
705 
706 	return bufptr;
707 }
708 
709 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
710 				   struct dwc2_host_chan *chan,
711 				   struct dwc2_hcd_urb *urb, void *bufptr)
712 {
713 	u32 buf_size;
714 	struct urb *usb_urb;
715 	struct usb_hcd *hcd;
716 
717 	if (!qh->dw_align_buf) {
718 		if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
719 			buf_size = hsotg->core_params->max_transfer_size;
720 		else
721 			/* 3072 = 3 max-size Isoc packets */
722 			buf_size = 3072;
723 
724 		qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
725 						      &qh->dw_align_buf_dma,
726 						      GFP_ATOMIC);
727 		if (!qh->dw_align_buf)
728 			return -ENOMEM;
729 		qh->dw_align_buf_size = buf_size;
730 	}
731 
732 	if (chan->xfer_len) {
733 		dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
734 		usb_urb = urb->priv;
735 
736 		if (usb_urb) {
737 			if (usb_urb->transfer_flags &
738 			    (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
739 			     URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
740 				hcd = dwc2_hsotg_to_hcd(hsotg);
741 				usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
742 			}
743 			if (!chan->ep_is_in)
744 				memcpy(qh->dw_align_buf, bufptr,
745 				       chan->xfer_len);
746 		} else {
747 			dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
748 		}
749 	}
750 
751 	chan->align_buf = qh->dw_align_buf_dma;
752 	return 0;
753 }
754 
755 /**
756  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
757  * channel and initializes the host channel to perform the transactions. The
758  * host channel is removed from the free list.
759  *
760  * @hsotg: The HCD state structure
761  * @qh:    Transactions from the first QTD for this QH are selected and assigned
762  *         to a free host channel
763  */
764 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
765 {
766 	struct dwc2_host_chan *chan;
767 	struct dwc2_hcd_urb *urb;
768 	struct dwc2_qtd *qtd;
769 	void *bufptr = NULL;
770 
771 	if (dbg_qh(qh))
772 		dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
773 
774 	if (list_empty(&qh->qtd_list)) {
775 		dev_dbg(hsotg->dev, "No QTDs in QH list\n");
776 		return -ENOMEM;
777 	}
778 
779 	if (list_empty(&hsotg->free_hc_list)) {
780 		dev_dbg(hsotg->dev, "No free channel to assign\n");
781 		return -ENOMEM;
782 	}
783 
784 	chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
785 				hc_list_entry);
786 
787 	/* Remove host channel from free list */
788 	list_del_init(&chan->hc_list_entry);
789 
790 	qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
791 	urb = qtd->urb;
792 	qh->channel = chan;
793 	qtd->in_process = 1;
794 
795 	/*
796 	 * Use usb_pipedevice to determine device address. This address is
797 	 * 0 before the SET_ADDRESS command and the correct address afterward.
798 	 */
799 	chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
800 	chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
801 	chan->speed = qh->dev_speed;
802 	chan->max_packet = dwc2_max_packet(qh->maxp);
803 
804 	chan->xfer_started = 0;
805 	chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
806 	chan->error_state = (qtd->error_count > 0);
807 	chan->halt_on_queue = 0;
808 	chan->halt_pending = 0;
809 	chan->requests = 0;
810 
811 	/*
812 	 * The following values may be modified in the transfer type section
813 	 * below. The xfer_len value may be reduced when the transfer is
814 	 * started to accommodate the max widths of the XferSize and PktCnt
815 	 * fields in the HCTSIZn register.
816 	 */
817 
818 	chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
819 	if (chan->ep_is_in)
820 		chan->do_ping = 0;
821 	else
822 		chan->do_ping = qh->ping_state;
823 
824 	chan->data_pid_start = qh->data_toggle;
825 	chan->multi_count = 1;
826 
827 	if (urb->actual_length > urb->length &&
828 		!dwc2_hcd_is_pipe_in(&urb->pipe_info))
829 		urb->actual_length = urb->length;
830 
831 	if (hsotg->core_params->dma_enable > 0) {
832 		chan->xfer_dma = urb->dma + urb->actual_length;
833 
834 		/* For non-dword aligned case */
835 		if (hsotg->core_params->dma_desc_enable <= 0 &&
836 		    (chan->xfer_dma & 0x3))
837 			bufptr = (u8 *)urb->buf + urb->actual_length;
838 	} else {
839 		chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
840 	}
841 
842 	chan->xfer_len = urb->length - urb->actual_length;
843 	chan->xfer_count = 0;
844 
845 	/* Set the split attributes if required */
846 	if (qh->do_split)
847 		dwc2_hc_init_split(hsotg, chan, qtd, urb);
848 	else
849 		chan->do_split = 0;
850 
851 	/* Set the transfer attributes */
852 	bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
853 
854 	/* Non DWORD-aligned buffer case */
855 	if (bufptr) {
856 		dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
857 		if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
858 			dev_err(hsotg->dev,
859 				"%s: Failed to allocate memory to handle non-dword aligned buffer\n",
860 				__func__);
861 			/* Add channel back to free list */
862 			chan->align_buf = 0;
863 			chan->multi_count = 0;
864 			list_add_tail(&chan->hc_list_entry,
865 				      &hsotg->free_hc_list);
866 			qtd->in_process = 0;
867 			qh->channel = NULL;
868 			return -ENOMEM;
869 		}
870 	} else {
871 		chan->align_buf = 0;
872 	}
873 
874 	if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
875 	    chan->ep_type == USB_ENDPOINT_XFER_ISOC)
876 		/*
877 		 * This value may be modified when the transfer is started
878 		 * to reflect the actual transfer length
879 		 */
880 		chan->multi_count = dwc2_hb_mult(qh->maxp);
881 
882 	if (hsotg->core_params->dma_desc_enable > 0)
883 		chan->desc_list_addr = qh->desc_list_dma;
884 
885 	dwc2_hc_init(hsotg, chan);
886 	chan->qh = qh;
887 
888 	return 0;
889 }
890 
891 /**
892  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
893  * schedule and assigns them to available host channels. Called from the HCD
894  * interrupt handler functions.
895  *
896  * @hsotg: The HCD state structure
897  *
898  * Return: The types of new transactions that were assigned to host channels
899  */
900 enum dwc2_transaction_type dwc2_hcd_select_transactions(
901 		struct dwc2_hsotg *hsotg)
902 {
903 	enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
904 	struct list_head *qh_ptr;
905 	struct dwc2_qh *qh;
906 	int num_channels;
907 
908 #ifdef DWC2_DEBUG_SOF
909 	dev_vdbg(hsotg->dev, "  Select Transactions\n");
910 #endif
911 
912 	/* Process entries in the periodic ready list */
913 	qh_ptr = hsotg->periodic_sched_ready.next;
914 	while (qh_ptr != &hsotg->periodic_sched_ready) {
915 		if (list_empty(&hsotg->free_hc_list))
916 			break;
917 		if (hsotg->core_params->uframe_sched > 0) {
918 			if (hsotg->available_host_channels <= 1)
919 				break;
920 			hsotg->available_host_channels--;
921 		}
922 		qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
923 		if (dwc2_assign_and_init_hc(hsotg, qh))
924 			break;
925 
926 		/*
927 		 * Move the QH from the periodic ready schedule to the
928 		 * periodic assigned schedule
929 		 */
930 		qh_ptr = qh_ptr->next;
931 		list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
932 		ret_val = DWC2_TRANSACTION_PERIODIC;
933 	}
934 
935 	/*
936 	 * Process entries in the inactive portion of the non-periodic
937 	 * schedule. Some free host channels may not be used if they are
938 	 * reserved for periodic transfers.
939 	 */
940 	num_channels = hsotg->core_params->host_channels;
941 	qh_ptr = hsotg->non_periodic_sched_inactive.next;
942 	while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
943 		if (hsotg->core_params->uframe_sched <= 0 &&
944 		    hsotg->non_periodic_channels >= num_channels -
945 						hsotg->periodic_channels)
946 			break;
947 		if (list_empty(&hsotg->free_hc_list))
948 			break;
949 		qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
950 		if (hsotg->core_params->uframe_sched > 0) {
951 			if (hsotg->available_host_channels < 1)
952 				break;
953 			hsotg->available_host_channels--;
954 		}
955 
956 		if (dwc2_assign_and_init_hc(hsotg, qh))
957 			break;
958 
959 		/*
960 		 * Move the QH from the non-periodic inactive schedule to the
961 		 * non-periodic active schedule
962 		 */
963 		qh_ptr = qh_ptr->next;
964 		list_move(&qh->qh_list_entry,
965 			  &hsotg->non_periodic_sched_active);
966 
967 		if (ret_val == DWC2_TRANSACTION_NONE)
968 			ret_val = DWC2_TRANSACTION_NON_PERIODIC;
969 		else
970 			ret_val = DWC2_TRANSACTION_ALL;
971 
972 		if (hsotg->core_params->uframe_sched <= 0)
973 			hsotg->non_periodic_channels++;
974 	}
975 
976 	return ret_val;
977 }
978 
979 /**
980  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
981  * a host channel associated with either a periodic or non-periodic transfer
982  *
983  * @hsotg: The HCD state structure
984  * @chan:  Host channel descriptor associated with either a periodic or
985  *         non-periodic transfer
986  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
987  *                     for periodic transfers or the non-periodic Tx FIFO
988  *                     for non-periodic transfers
989  *
990  * Return: 1 if a request is queued and more requests may be needed to
991  * complete the transfer, 0 if no more requests are required for this
992  * transfer, -1 if there is insufficient space in the Tx FIFO
993  *
994  * This function assumes that there is space available in the appropriate
995  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
996  * it checks whether space is available in the appropriate Tx FIFO.
997  *
998  * Must be called with interrupt disabled and spinlock held
999  */
1000 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1001 				  struct dwc2_host_chan *chan,
1002 				  u16 fifo_dwords_avail)
1003 {
1004 	int retval = 0;
1005 
1006 	if (hsotg->core_params->dma_enable > 0) {
1007 		if (hsotg->core_params->dma_desc_enable > 0) {
1008 			if (!chan->xfer_started ||
1009 			    chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1010 				dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1011 				chan->qh->ping_state = 0;
1012 			}
1013 		} else if (!chan->xfer_started) {
1014 			dwc2_hc_start_transfer(hsotg, chan);
1015 			chan->qh->ping_state = 0;
1016 		}
1017 	} else if (chan->halt_pending) {
1018 		/* Don't queue a request if the channel has been halted */
1019 	} else if (chan->halt_on_queue) {
1020 		dwc2_hc_halt(hsotg, chan, chan->halt_status);
1021 	} else if (chan->do_ping) {
1022 		if (!chan->xfer_started)
1023 			dwc2_hc_start_transfer(hsotg, chan);
1024 	} else if (!chan->ep_is_in ||
1025 		   chan->data_pid_start == DWC2_HC_PID_SETUP) {
1026 		if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1027 			if (!chan->xfer_started) {
1028 				dwc2_hc_start_transfer(hsotg, chan);
1029 				retval = 1;
1030 			} else {
1031 				retval = dwc2_hc_continue_transfer(hsotg, chan);
1032 			}
1033 		} else {
1034 			retval = -1;
1035 		}
1036 	} else {
1037 		if (!chan->xfer_started) {
1038 			dwc2_hc_start_transfer(hsotg, chan);
1039 			retval = 1;
1040 		} else {
1041 			retval = dwc2_hc_continue_transfer(hsotg, chan);
1042 		}
1043 	}
1044 
1045 	return retval;
1046 }
1047 
1048 /*
1049  * Processes periodic channels for the next frame and queues transactions for
1050  * these channels to the DWC_otg controller. After queueing transactions, the
1051  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1052  * to queue as Periodic Tx FIFO or request queue space becomes available.
1053  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1054  *
1055  * Must be called with interrupt disabled and spinlock held
1056  */
1057 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1058 {
1059 	struct list_head *qh_ptr;
1060 	struct dwc2_qh *qh;
1061 	u32 tx_status;
1062 	u32 fspcavail;
1063 	u32 gintmsk;
1064 	int status;
1065 	int no_queue_space = 0;
1066 	int no_fifo_space = 0;
1067 	u32 qspcavail;
1068 
1069 	if (dbg_perio())
1070 		dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1071 
1072 	tx_status = readl(hsotg->regs + HPTXSTS);
1073 	qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1074 		    TXSTS_QSPCAVAIL_SHIFT;
1075 	fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1076 		    TXSTS_FSPCAVAIL_SHIFT;
1077 
1078 	if (dbg_perio()) {
1079 		dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1080 			 qspcavail);
1081 		dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1082 			 fspcavail);
1083 	}
1084 
1085 	qh_ptr = hsotg->periodic_sched_assigned.next;
1086 	while (qh_ptr != &hsotg->periodic_sched_assigned) {
1087 		tx_status = readl(hsotg->regs + HPTXSTS);
1088 		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1089 			    TXSTS_QSPCAVAIL_SHIFT;
1090 		if (qspcavail == 0) {
1091 			no_queue_space = 1;
1092 			break;
1093 		}
1094 
1095 		qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1096 		if (!qh->channel) {
1097 			qh_ptr = qh_ptr->next;
1098 			continue;
1099 		}
1100 
1101 		/* Make sure EP's TT buffer is clean before queueing qtds */
1102 		if (qh->tt_buffer_dirty) {
1103 			qh_ptr = qh_ptr->next;
1104 			continue;
1105 		}
1106 
1107 		/*
1108 		 * Set a flag if we're queuing high-bandwidth in slave mode.
1109 		 * The flag prevents any halts to get into the request queue in
1110 		 * the middle of multiple high-bandwidth packets getting queued.
1111 		 */
1112 		if (hsotg->core_params->dma_enable <= 0 &&
1113 				qh->channel->multi_count > 1)
1114 			hsotg->queuing_high_bandwidth = 1;
1115 
1116 		fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1117 			    TXSTS_FSPCAVAIL_SHIFT;
1118 		status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1119 		if (status < 0) {
1120 			no_fifo_space = 1;
1121 			break;
1122 		}
1123 
1124 		/*
1125 		 * In Slave mode, stay on the current transfer until there is
1126 		 * nothing more to do or the high-bandwidth request count is
1127 		 * reached. In DMA mode, only need to queue one request. The
1128 		 * controller automatically handles multiple packets for
1129 		 * high-bandwidth transfers.
1130 		 */
1131 		if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1132 		    qh->channel->requests == qh->channel->multi_count) {
1133 			qh_ptr = qh_ptr->next;
1134 			/*
1135 			 * Move the QH from the periodic assigned schedule to
1136 			 * the periodic queued schedule
1137 			 */
1138 			list_move(&qh->qh_list_entry,
1139 				  &hsotg->periodic_sched_queued);
1140 
1141 			/* done queuing high bandwidth */
1142 			hsotg->queuing_high_bandwidth = 0;
1143 		}
1144 	}
1145 
1146 	if (hsotg->core_params->dma_enable <= 0) {
1147 		tx_status = readl(hsotg->regs + HPTXSTS);
1148 		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1149 			    TXSTS_QSPCAVAIL_SHIFT;
1150 		fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1151 			    TXSTS_FSPCAVAIL_SHIFT;
1152 		if (dbg_perio()) {
1153 			dev_vdbg(hsotg->dev,
1154 				 "  P Tx Req Queue Space Avail (after queue): %d\n",
1155 				 qspcavail);
1156 			dev_vdbg(hsotg->dev,
1157 				 "  P Tx FIFO Space Avail (after queue): %d\n",
1158 				 fspcavail);
1159 		}
1160 
1161 		if (!list_empty(&hsotg->periodic_sched_assigned) ||
1162 		    no_queue_space || no_fifo_space) {
1163 			/*
1164 			 * May need to queue more transactions as the request
1165 			 * queue or Tx FIFO empties. Enable the periodic Tx
1166 			 * FIFO empty interrupt. (Always use the half-empty
1167 			 * level to ensure that new requests are loaded as
1168 			 * soon as possible.)
1169 			 */
1170 			gintmsk = readl(hsotg->regs + GINTMSK);
1171 			gintmsk |= GINTSTS_PTXFEMP;
1172 			writel(gintmsk, hsotg->regs + GINTMSK);
1173 		} else {
1174 			/*
1175 			 * Disable the Tx FIFO empty interrupt since there are
1176 			 * no more transactions that need to be queued right
1177 			 * now. This function is called from interrupt
1178 			 * handlers to queue more transactions as transfer
1179 			 * states change.
1180 			 */
1181 			gintmsk = readl(hsotg->regs + GINTMSK);
1182 			gintmsk &= ~GINTSTS_PTXFEMP;
1183 			writel(gintmsk, hsotg->regs + GINTMSK);
1184 		}
1185 	}
1186 }
1187 
1188 /*
1189  * Processes active non-periodic channels and queues transactions for these
1190  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1191  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1192  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1193  * FIFO Empty interrupt is disabled.
1194  *
1195  * Must be called with interrupt disabled and spinlock held
1196  */
1197 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1198 {
1199 	struct list_head *orig_qh_ptr;
1200 	struct dwc2_qh *qh;
1201 	u32 tx_status;
1202 	u32 qspcavail;
1203 	u32 fspcavail;
1204 	u32 gintmsk;
1205 	int status;
1206 	int no_queue_space = 0;
1207 	int no_fifo_space = 0;
1208 	int more_to_do = 0;
1209 
1210 	dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1211 
1212 	tx_status = readl(hsotg->regs + GNPTXSTS);
1213 	qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1214 		    TXSTS_QSPCAVAIL_SHIFT;
1215 	fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1216 		    TXSTS_FSPCAVAIL_SHIFT;
1217 	dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1218 		 qspcavail);
1219 	dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1220 		 fspcavail);
1221 
1222 	/*
1223 	 * Keep track of the starting point. Skip over the start-of-list
1224 	 * entry.
1225 	 */
1226 	if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1227 		hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1228 	orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1229 
1230 	/*
1231 	 * Process once through the active list or until no more space is
1232 	 * available in the request queue or the Tx FIFO
1233 	 */
1234 	do {
1235 		tx_status = readl(hsotg->regs + GNPTXSTS);
1236 		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1237 			    TXSTS_QSPCAVAIL_SHIFT;
1238 		if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1239 			no_queue_space = 1;
1240 			break;
1241 		}
1242 
1243 		qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1244 				qh_list_entry);
1245 		if (!qh->channel)
1246 			goto next;
1247 
1248 		/* Make sure EP's TT buffer is clean before queueing qtds */
1249 		if (qh->tt_buffer_dirty)
1250 			goto next;
1251 
1252 		fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1253 			    TXSTS_FSPCAVAIL_SHIFT;
1254 		status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1255 
1256 		if (status > 0) {
1257 			more_to_do = 1;
1258 		} else if (status < 0) {
1259 			no_fifo_space = 1;
1260 			break;
1261 		}
1262 next:
1263 		/* Advance to next QH, skipping start-of-list entry */
1264 		hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1265 		if (hsotg->non_periodic_qh_ptr ==
1266 				&hsotg->non_periodic_sched_active)
1267 			hsotg->non_periodic_qh_ptr =
1268 					hsotg->non_periodic_qh_ptr->next;
1269 	} while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1270 
1271 	if (hsotg->core_params->dma_enable <= 0) {
1272 		tx_status = readl(hsotg->regs + GNPTXSTS);
1273 		qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1274 			    TXSTS_QSPCAVAIL_SHIFT;
1275 		fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1276 			    TXSTS_FSPCAVAIL_SHIFT;
1277 		dev_vdbg(hsotg->dev,
1278 			 "  NP Tx Req Queue Space Avail (after queue): %d\n",
1279 			 qspcavail);
1280 		dev_vdbg(hsotg->dev,
1281 			 "  NP Tx FIFO Space Avail (after queue): %d\n",
1282 			 fspcavail);
1283 
1284 		if (more_to_do || no_queue_space || no_fifo_space) {
1285 			/*
1286 			 * May need to queue more transactions as the request
1287 			 * queue or Tx FIFO empties. Enable the non-periodic
1288 			 * Tx FIFO empty interrupt. (Always use the half-empty
1289 			 * level to ensure that new requests are loaded as
1290 			 * soon as possible.)
1291 			 */
1292 			gintmsk = readl(hsotg->regs + GINTMSK);
1293 			gintmsk |= GINTSTS_NPTXFEMP;
1294 			writel(gintmsk, hsotg->regs + GINTMSK);
1295 		} else {
1296 			/*
1297 			 * Disable the Tx FIFO empty interrupt since there are
1298 			 * no more transactions that need to be queued right
1299 			 * now. This function is called from interrupt
1300 			 * handlers to queue more transactions as transfer
1301 			 * states change.
1302 			 */
1303 			gintmsk = readl(hsotg->regs + GINTMSK);
1304 			gintmsk &= ~GINTSTS_NPTXFEMP;
1305 			writel(gintmsk, hsotg->regs + GINTMSK);
1306 		}
1307 	}
1308 }
1309 
1310 /**
1311  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1312  * and queues transactions for these channels to the DWC_otg controller. Called
1313  * from the HCD interrupt handler functions.
1314  *
1315  * @hsotg:   The HCD state structure
1316  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1317  *           or both)
1318  *
1319  * Must be called with interrupt disabled and spinlock held
1320  */
1321 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1322 				 enum dwc2_transaction_type tr_type)
1323 {
1324 #ifdef DWC2_DEBUG_SOF
1325 	dev_vdbg(hsotg->dev, "Queue Transactions\n");
1326 #endif
1327 	/* Process host channels associated with periodic transfers */
1328 	if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1329 	     tr_type == DWC2_TRANSACTION_ALL) &&
1330 	    !list_empty(&hsotg->periodic_sched_assigned))
1331 		dwc2_process_periodic_channels(hsotg);
1332 
1333 	/* Process host channels associated with non-periodic transfers */
1334 	if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1335 	    tr_type == DWC2_TRANSACTION_ALL) {
1336 		if (!list_empty(&hsotg->non_periodic_sched_active)) {
1337 			dwc2_process_non_periodic_channels(hsotg);
1338 		} else {
1339 			/*
1340 			 * Ensure NP Tx FIFO empty interrupt is disabled when
1341 			 * there are no non-periodic transfers to process
1342 			 */
1343 			u32 gintmsk = readl(hsotg->regs + GINTMSK);
1344 
1345 			gintmsk &= ~GINTSTS_NPTXFEMP;
1346 			writel(gintmsk, hsotg->regs + GINTMSK);
1347 		}
1348 	}
1349 }
1350 
1351 static void dwc2_conn_id_status_change(struct work_struct *work)
1352 {
1353 	struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1354 						wf_otg);
1355 	u32 count = 0;
1356 	u32 gotgctl;
1357 
1358 	dev_dbg(hsotg->dev, "%s()\n", __func__);
1359 
1360 	gotgctl = readl(hsotg->regs + GOTGCTL);
1361 	dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1362 	dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1363 		!!(gotgctl & GOTGCTL_CONID_B));
1364 
1365 	/* B-Device connector (Device Mode) */
1366 	if (gotgctl & GOTGCTL_CONID_B) {
1367 		/* Wait for switch to device mode */
1368 		dev_dbg(hsotg->dev, "connId B\n");
1369 		while (!dwc2_is_device_mode(hsotg)) {
1370 			dev_info(hsotg->dev,
1371 				 "Waiting for Peripheral Mode, Mode=%s\n",
1372 				 dwc2_is_host_mode(hsotg) ? "Host" :
1373 				 "Peripheral");
1374 			usleep_range(20000, 40000);
1375 			if (++count > 250)
1376 				break;
1377 		}
1378 		if (count > 250)
1379 			dev_err(hsotg->dev,
1380 				"Connection id status change timed out\n");
1381 		hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1382 		dwc2_core_init(hsotg, false, -1);
1383 		dwc2_enable_global_interrupts(hsotg);
1384 		s3c_hsotg_core_init_disconnected(hsotg, false);
1385 		s3c_hsotg_core_connect(hsotg);
1386 	} else {
1387 		/* A-Device connector (Host Mode) */
1388 		dev_dbg(hsotg->dev, "connId A\n");
1389 		while (!dwc2_is_host_mode(hsotg)) {
1390 			dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1391 				 dwc2_is_host_mode(hsotg) ?
1392 				 "Host" : "Peripheral");
1393 			usleep_range(20000, 40000);
1394 			if (++count > 250)
1395 				break;
1396 		}
1397 		if (count > 250)
1398 			dev_err(hsotg->dev,
1399 				"Connection id status change timed out\n");
1400 		hsotg->op_state = OTG_STATE_A_HOST;
1401 
1402 		/* Initialize the Core for Host mode */
1403 		dwc2_core_init(hsotg, false, -1);
1404 		dwc2_enable_global_interrupts(hsotg);
1405 		dwc2_hcd_start(hsotg);
1406 	}
1407 }
1408 
1409 static void dwc2_wakeup_detected(unsigned long data)
1410 {
1411 	struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1412 	u32 hprt0;
1413 
1414 	dev_dbg(hsotg->dev, "%s()\n", __func__);
1415 
1416 	/*
1417 	 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1418 	 * so that OPT tests pass with all PHYs.)
1419 	 */
1420 	hprt0 = dwc2_read_hprt0(hsotg);
1421 	dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1422 	hprt0 &= ~HPRT0_RES;
1423 	writel(hprt0, hsotg->regs + HPRT0);
1424 	dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1425 		readl(hsotg->regs + HPRT0));
1426 
1427 	dwc2_hcd_rem_wakeup(hsotg);
1428 
1429 	/* Change to L0 state */
1430 	hsotg->lx_state = DWC2_L0;
1431 }
1432 
1433 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1434 {
1435 	struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1436 
1437 	return hcd->self.b_hnp_enable;
1438 }
1439 
1440 /* Must NOT be called with interrupt disabled or spinlock held */
1441 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1442 {
1443 	unsigned long flags;
1444 	u32 hprt0;
1445 	u32 pcgctl;
1446 	u32 gotgctl;
1447 
1448 	dev_dbg(hsotg->dev, "%s()\n", __func__);
1449 
1450 	spin_lock_irqsave(&hsotg->lock, flags);
1451 
1452 	if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1453 		gotgctl = readl(hsotg->regs + GOTGCTL);
1454 		gotgctl |= GOTGCTL_HSTSETHNPEN;
1455 		writel(gotgctl, hsotg->regs + GOTGCTL);
1456 		hsotg->op_state = OTG_STATE_A_SUSPEND;
1457 	}
1458 
1459 	hprt0 = dwc2_read_hprt0(hsotg);
1460 	hprt0 |= HPRT0_SUSP;
1461 	writel(hprt0, hsotg->regs + HPRT0);
1462 
1463 	/* Update lx_state */
1464 	hsotg->lx_state = DWC2_L2;
1465 
1466 	/* Suspend the Phy Clock */
1467 	pcgctl = readl(hsotg->regs + PCGCTL);
1468 	pcgctl |= PCGCTL_STOPPCLK;
1469 	writel(pcgctl, hsotg->regs + PCGCTL);
1470 	udelay(10);
1471 
1472 	/* For HNP the bus must be suspended for at least 200ms */
1473 	if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1474 		pcgctl = readl(hsotg->regs + PCGCTL);
1475 		pcgctl &= ~PCGCTL_STOPPCLK;
1476 		writel(pcgctl, hsotg->regs + PCGCTL);
1477 
1478 		spin_unlock_irqrestore(&hsotg->lock, flags);
1479 
1480 		usleep_range(200000, 250000);
1481 	} else {
1482 		spin_unlock_irqrestore(&hsotg->lock, flags);
1483 	}
1484 }
1485 
1486 /* Handles hub class-specific requests */
1487 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1488 				u16 wvalue, u16 windex, char *buf, u16 wlength)
1489 {
1490 	struct usb_hub_descriptor *hub_desc;
1491 	int retval = 0;
1492 	u32 hprt0;
1493 	u32 port_status;
1494 	u32 speed;
1495 	u32 pcgctl;
1496 
1497 	switch (typereq) {
1498 	case ClearHubFeature:
1499 		dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1500 
1501 		switch (wvalue) {
1502 		case C_HUB_LOCAL_POWER:
1503 		case C_HUB_OVER_CURRENT:
1504 			/* Nothing required here */
1505 			break;
1506 
1507 		default:
1508 			retval = -EINVAL;
1509 			dev_err(hsotg->dev,
1510 				"ClearHubFeature request %1xh unknown\n",
1511 				wvalue);
1512 		}
1513 		break;
1514 
1515 	case ClearPortFeature:
1516 		if (wvalue != USB_PORT_FEAT_L1)
1517 			if (!windex || windex > 1)
1518 				goto error;
1519 		switch (wvalue) {
1520 		case USB_PORT_FEAT_ENABLE:
1521 			dev_dbg(hsotg->dev,
1522 				"ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1523 			hprt0 = dwc2_read_hprt0(hsotg);
1524 			hprt0 |= HPRT0_ENA;
1525 			writel(hprt0, hsotg->regs + HPRT0);
1526 			break;
1527 
1528 		case USB_PORT_FEAT_SUSPEND:
1529 			dev_dbg(hsotg->dev,
1530 				"ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1531 			writel(0, hsotg->regs + PCGCTL);
1532 			usleep_range(20000, 40000);
1533 
1534 			hprt0 = dwc2_read_hprt0(hsotg);
1535 			hprt0 |= HPRT0_RES;
1536 			writel(hprt0, hsotg->regs + HPRT0);
1537 			hprt0 &= ~HPRT0_SUSP;
1538 			msleep(USB_RESUME_TIMEOUT);
1539 
1540 			hprt0 &= ~HPRT0_RES;
1541 			writel(hprt0, hsotg->regs + HPRT0);
1542 			break;
1543 
1544 		case USB_PORT_FEAT_POWER:
1545 			dev_dbg(hsotg->dev,
1546 				"ClearPortFeature USB_PORT_FEAT_POWER\n");
1547 			hprt0 = dwc2_read_hprt0(hsotg);
1548 			hprt0 &= ~HPRT0_PWR;
1549 			writel(hprt0, hsotg->regs + HPRT0);
1550 			break;
1551 
1552 		case USB_PORT_FEAT_INDICATOR:
1553 			dev_dbg(hsotg->dev,
1554 				"ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1555 			/* Port indicator not supported */
1556 			break;
1557 
1558 		case USB_PORT_FEAT_C_CONNECTION:
1559 			/*
1560 			 * Clears driver's internal Connect Status Change flag
1561 			 */
1562 			dev_dbg(hsotg->dev,
1563 				"ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1564 			hsotg->flags.b.port_connect_status_change = 0;
1565 			break;
1566 
1567 		case USB_PORT_FEAT_C_RESET:
1568 			/* Clears driver's internal Port Reset Change flag */
1569 			dev_dbg(hsotg->dev,
1570 				"ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1571 			hsotg->flags.b.port_reset_change = 0;
1572 			break;
1573 
1574 		case USB_PORT_FEAT_C_ENABLE:
1575 			/*
1576 			 * Clears the driver's internal Port Enable/Disable
1577 			 * Change flag
1578 			 */
1579 			dev_dbg(hsotg->dev,
1580 				"ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1581 			hsotg->flags.b.port_enable_change = 0;
1582 			break;
1583 
1584 		case USB_PORT_FEAT_C_SUSPEND:
1585 			/*
1586 			 * Clears the driver's internal Port Suspend Change
1587 			 * flag, which is set when resume signaling on the host
1588 			 * port is complete
1589 			 */
1590 			dev_dbg(hsotg->dev,
1591 				"ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1592 			hsotg->flags.b.port_suspend_change = 0;
1593 			break;
1594 
1595 		case USB_PORT_FEAT_C_PORT_L1:
1596 			dev_dbg(hsotg->dev,
1597 				"ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1598 			hsotg->flags.b.port_l1_change = 0;
1599 			break;
1600 
1601 		case USB_PORT_FEAT_C_OVER_CURRENT:
1602 			dev_dbg(hsotg->dev,
1603 				"ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1604 			hsotg->flags.b.port_over_current_change = 0;
1605 			break;
1606 
1607 		default:
1608 			retval = -EINVAL;
1609 			dev_err(hsotg->dev,
1610 				"ClearPortFeature request %1xh unknown or unsupported\n",
1611 				wvalue);
1612 		}
1613 		break;
1614 
1615 	case GetHubDescriptor:
1616 		dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1617 		hub_desc = (struct usb_hub_descriptor *)buf;
1618 		hub_desc->bDescLength = 9;
1619 		hub_desc->bDescriptorType = USB_DT_HUB;
1620 		hub_desc->bNbrPorts = 1;
1621 		hub_desc->wHubCharacteristics =
1622 			cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1623 				    HUB_CHAR_INDV_PORT_OCPM);
1624 		hub_desc->bPwrOn2PwrGood = 1;
1625 		hub_desc->bHubContrCurrent = 0;
1626 		hub_desc->u.hs.DeviceRemovable[0] = 0;
1627 		hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1628 		break;
1629 
1630 	case GetHubStatus:
1631 		dev_dbg(hsotg->dev, "GetHubStatus\n");
1632 		memset(buf, 0, 4);
1633 		break;
1634 
1635 	case GetPortStatus:
1636 		dev_vdbg(hsotg->dev,
1637 			 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1638 			 hsotg->flags.d32);
1639 		if (!windex || windex > 1)
1640 			goto error;
1641 
1642 		port_status = 0;
1643 		if (hsotg->flags.b.port_connect_status_change)
1644 			port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1645 		if (hsotg->flags.b.port_enable_change)
1646 			port_status |= USB_PORT_STAT_C_ENABLE << 16;
1647 		if (hsotg->flags.b.port_suspend_change)
1648 			port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1649 		if (hsotg->flags.b.port_l1_change)
1650 			port_status |= USB_PORT_STAT_C_L1 << 16;
1651 		if (hsotg->flags.b.port_reset_change)
1652 			port_status |= USB_PORT_STAT_C_RESET << 16;
1653 		if (hsotg->flags.b.port_over_current_change) {
1654 			dev_warn(hsotg->dev, "Overcurrent change detected\n");
1655 			port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1656 		}
1657 
1658 		if (!hsotg->flags.b.port_connect_status) {
1659 			/*
1660 			 * The port is disconnected, which means the core is
1661 			 * either in device mode or it soon will be. Just
1662 			 * return 0's for the remainder of the port status
1663 			 * since the port register can't be read if the core
1664 			 * is in device mode.
1665 			 */
1666 			*(__le32 *)buf = cpu_to_le32(port_status);
1667 			break;
1668 		}
1669 
1670 		hprt0 = readl(hsotg->regs + HPRT0);
1671 		dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1672 
1673 		if (hprt0 & HPRT0_CONNSTS)
1674 			port_status |= USB_PORT_STAT_CONNECTION;
1675 		if (hprt0 & HPRT0_ENA)
1676 			port_status |= USB_PORT_STAT_ENABLE;
1677 		if (hprt0 & HPRT0_SUSP)
1678 			port_status |= USB_PORT_STAT_SUSPEND;
1679 		if (hprt0 & HPRT0_OVRCURRACT)
1680 			port_status |= USB_PORT_STAT_OVERCURRENT;
1681 		if (hprt0 & HPRT0_RST)
1682 			port_status |= USB_PORT_STAT_RESET;
1683 		if (hprt0 & HPRT0_PWR)
1684 			port_status |= USB_PORT_STAT_POWER;
1685 
1686 		speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1687 		if (speed == HPRT0_SPD_HIGH_SPEED)
1688 			port_status |= USB_PORT_STAT_HIGH_SPEED;
1689 		else if (speed == HPRT0_SPD_LOW_SPEED)
1690 			port_status |= USB_PORT_STAT_LOW_SPEED;
1691 
1692 		if (hprt0 & HPRT0_TSTCTL_MASK)
1693 			port_status |= USB_PORT_STAT_TEST;
1694 		/* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1695 
1696 		dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1697 		*(__le32 *)buf = cpu_to_le32(port_status);
1698 		break;
1699 
1700 	case SetHubFeature:
1701 		dev_dbg(hsotg->dev, "SetHubFeature\n");
1702 		/* No HUB features supported */
1703 		break;
1704 
1705 	case SetPortFeature:
1706 		dev_dbg(hsotg->dev, "SetPortFeature\n");
1707 		if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1708 			goto error;
1709 
1710 		if (!hsotg->flags.b.port_connect_status) {
1711 			/*
1712 			 * The port is disconnected, which means the core is
1713 			 * either in device mode or it soon will be. Just
1714 			 * return without doing anything since the port
1715 			 * register can't be written if the core is in device
1716 			 * mode.
1717 			 */
1718 			break;
1719 		}
1720 
1721 		switch (wvalue) {
1722 		case USB_PORT_FEAT_SUSPEND:
1723 			dev_dbg(hsotg->dev,
1724 				"SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1725 			if (windex != hsotg->otg_port)
1726 				goto error;
1727 			dwc2_port_suspend(hsotg, windex);
1728 			break;
1729 
1730 		case USB_PORT_FEAT_POWER:
1731 			dev_dbg(hsotg->dev,
1732 				"SetPortFeature - USB_PORT_FEAT_POWER\n");
1733 			hprt0 = dwc2_read_hprt0(hsotg);
1734 			hprt0 |= HPRT0_PWR;
1735 			writel(hprt0, hsotg->regs + HPRT0);
1736 			break;
1737 
1738 		case USB_PORT_FEAT_RESET:
1739 			hprt0 = dwc2_read_hprt0(hsotg);
1740 			dev_dbg(hsotg->dev,
1741 				"SetPortFeature - USB_PORT_FEAT_RESET\n");
1742 			pcgctl = readl(hsotg->regs + PCGCTL);
1743 			pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1744 			writel(pcgctl, hsotg->regs + PCGCTL);
1745 			/* ??? Original driver does this */
1746 			writel(0, hsotg->regs + PCGCTL);
1747 
1748 			hprt0 = dwc2_read_hprt0(hsotg);
1749 			/* Clear suspend bit if resetting from suspend state */
1750 			hprt0 &= ~HPRT0_SUSP;
1751 
1752 			/*
1753 			 * When B-Host the Port reset bit is set in the Start
1754 			 * HCD Callback function, so that the reset is started
1755 			 * within 1ms of the HNP success interrupt
1756 			 */
1757 			if (!dwc2_hcd_is_b_host(hsotg)) {
1758 				hprt0 |= HPRT0_PWR | HPRT0_RST;
1759 				dev_dbg(hsotg->dev,
1760 					"In host mode, hprt0=%08x\n", hprt0);
1761 				writel(hprt0, hsotg->regs + HPRT0);
1762 			}
1763 
1764 			/* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1765 			usleep_range(50000, 70000);
1766 			hprt0 &= ~HPRT0_RST;
1767 			writel(hprt0, hsotg->regs + HPRT0);
1768 			hsotg->lx_state = DWC2_L0; /* Now back to On state */
1769 			break;
1770 
1771 		case USB_PORT_FEAT_INDICATOR:
1772 			dev_dbg(hsotg->dev,
1773 				"SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1774 			/* Not supported */
1775 			break;
1776 
1777 		default:
1778 			retval = -EINVAL;
1779 			dev_err(hsotg->dev,
1780 				"SetPortFeature %1xh unknown or unsupported\n",
1781 				wvalue);
1782 			break;
1783 		}
1784 		break;
1785 
1786 	default:
1787 error:
1788 		retval = -EINVAL;
1789 		dev_dbg(hsotg->dev,
1790 			"Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1791 			typereq, windex, wvalue);
1792 		break;
1793 	}
1794 
1795 	return retval;
1796 }
1797 
1798 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1799 {
1800 	int retval;
1801 
1802 	if (port != 1)
1803 		return -EINVAL;
1804 
1805 	retval = (hsotg->flags.b.port_connect_status_change ||
1806 		  hsotg->flags.b.port_reset_change ||
1807 		  hsotg->flags.b.port_enable_change ||
1808 		  hsotg->flags.b.port_suspend_change ||
1809 		  hsotg->flags.b.port_over_current_change);
1810 
1811 	if (retval) {
1812 		dev_dbg(hsotg->dev,
1813 			"DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1814 		dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1815 			hsotg->flags.b.port_connect_status_change);
1816 		dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1817 			hsotg->flags.b.port_reset_change);
1818 		dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1819 			hsotg->flags.b.port_enable_change);
1820 		dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1821 			hsotg->flags.b.port_suspend_change);
1822 		dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1823 			hsotg->flags.b.port_over_current_change);
1824 	}
1825 
1826 	return retval;
1827 }
1828 
1829 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1830 {
1831 	u32 hfnum = readl(hsotg->regs + HFNUM);
1832 
1833 #ifdef DWC2_DEBUG_SOF
1834 	dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1835 		 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1836 #endif
1837 	return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1838 }
1839 
1840 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1841 {
1842 	return hsotg->op_state == OTG_STATE_B_HOST;
1843 }
1844 
1845 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1846 					       int iso_desc_count,
1847 					       gfp_t mem_flags)
1848 {
1849 	struct dwc2_hcd_urb *urb;
1850 	u32 size = sizeof(*urb) + iso_desc_count *
1851 		   sizeof(struct dwc2_hcd_iso_packet_desc);
1852 
1853 	urb = kzalloc(size, mem_flags);
1854 	if (urb)
1855 		urb->packet_count = iso_desc_count;
1856 	return urb;
1857 }
1858 
1859 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1860 				      struct dwc2_hcd_urb *urb, u8 dev_addr,
1861 				      u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1862 {
1863 	if (dbg_perio() ||
1864 	    ep_type == USB_ENDPOINT_XFER_BULK ||
1865 	    ep_type == USB_ENDPOINT_XFER_CONTROL)
1866 		dev_vdbg(hsotg->dev,
1867 			 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1868 			 dev_addr, ep_num, ep_dir, ep_type, mps);
1869 	urb->pipe_info.dev_addr = dev_addr;
1870 	urb->pipe_info.ep_num = ep_num;
1871 	urb->pipe_info.pipe_type = ep_type;
1872 	urb->pipe_info.pipe_dir = ep_dir;
1873 	urb->pipe_info.mps = mps;
1874 }
1875 
1876 /*
1877  * NOTE: This function will be removed once the peripheral controller code
1878  * is integrated and the driver is stable
1879  */
1880 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1881 {
1882 #ifdef DEBUG
1883 	struct dwc2_host_chan *chan;
1884 	struct dwc2_hcd_urb *urb;
1885 	struct dwc2_qtd *qtd;
1886 	int num_channels;
1887 	u32 np_tx_status;
1888 	u32 p_tx_status;
1889 	int i;
1890 
1891 	num_channels = hsotg->core_params->host_channels;
1892 	dev_dbg(hsotg->dev, "\n");
1893 	dev_dbg(hsotg->dev,
1894 		"************************************************************\n");
1895 	dev_dbg(hsotg->dev, "HCD State:\n");
1896 	dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1897 
1898 	for (i = 0; i < num_channels; i++) {
1899 		chan = hsotg->hc_ptr_array[i];
1900 		dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1901 		dev_dbg(hsotg->dev,
1902 			"    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1903 			chan->dev_addr, chan->ep_num, chan->ep_is_in);
1904 		dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1905 		dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1906 		dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1907 		dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1908 			chan->data_pid_start);
1909 		dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1910 		dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1911 			chan->xfer_started);
1912 		dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1913 		dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1914 			(unsigned long)chan->xfer_dma);
1915 		dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1916 		dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1917 		dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1918 			chan->halt_on_queue);
1919 		dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1920 			chan->halt_pending);
1921 		dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1922 		dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1923 		dev_dbg(hsotg->dev, "    complete_split: %d\n",
1924 			chan->complete_split);
1925 		dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1926 		dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1927 		dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1928 		dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1929 		dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1930 
1931 		if (chan->xfer_started) {
1932 			u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1933 
1934 			hfnum = readl(hsotg->regs + HFNUM);
1935 			hcchar = readl(hsotg->regs + HCCHAR(i));
1936 			hctsiz = readl(hsotg->regs + HCTSIZ(i));
1937 			hcint = readl(hsotg->regs + HCINT(i));
1938 			hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1939 			dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1940 			dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1941 			dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1942 			dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1943 			dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1944 		}
1945 
1946 		if (!(chan->xfer_started && chan->qh))
1947 			continue;
1948 
1949 		list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1950 			if (!qtd->in_process)
1951 				break;
1952 			urb = qtd->urb;
1953 			dev_dbg(hsotg->dev, "    URB Info:\n");
1954 			dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
1955 				qtd, urb);
1956 			if (urb) {
1957 				dev_dbg(hsotg->dev,
1958 					"      Dev: %d, EP: %d %s\n",
1959 					dwc2_hcd_get_dev_addr(&urb->pipe_info),
1960 					dwc2_hcd_get_ep_num(&urb->pipe_info),
1961 					dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1962 					"IN" : "OUT");
1963 				dev_dbg(hsotg->dev,
1964 					"      Max packet size: %d\n",
1965 					dwc2_hcd_get_mps(&urb->pipe_info));
1966 				dev_dbg(hsotg->dev,
1967 					"      transfer_buffer: %p\n",
1968 					urb->buf);
1969 				dev_dbg(hsotg->dev,
1970 					"      transfer_dma: %08lx\n",
1971 					(unsigned long)urb->dma);
1972 				dev_dbg(hsotg->dev,
1973 					"      transfer_buffer_length: %d\n",
1974 					urb->length);
1975 				dev_dbg(hsotg->dev, "      actual_length: %d\n",
1976 					urb->actual_length);
1977 			}
1978 		}
1979 	}
1980 
1981 	dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
1982 		hsotg->non_periodic_channels);
1983 	dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
1984 		hsotg->periodic_channels);
1985 	dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
1986 	np_tx_status = readl(hsotg->regs + GNPTXSTS);
1987 	dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
1988 		(np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1989 	dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
1990 		(np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1991 	p_tx_status = readl(hsotg->regs + HPTXSTS);
1992 	dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
1993 		(p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1994 	dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
1995 		(p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
1996 	dwc2_hcd_dump_frrem(hsotg);
1997 	dwc2_dump_global_registers(hsotg);
1998 	dwc2_dump_host_registers(hsotg);
1999 	dev_dbg(hsotg->dev,
2000 		"************************************************************\n");
2001 	dev_dbg(hsotg->dev, "\n");
2002 #endif
2003 }
2004 
2005 /*
2006  * NOTE: This function will be removed once the peripheral controller code
2007  * is integrated and the driver is stable
2008  */
2009 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2010 {
2011 #ifdef DWC2_DUMP_FRREM
2012 	dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2013 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2014 		hsotg->frrem_samples, hsotg->frrem_accum,
2015 		hsotg->frrem_samples > 0 ?
2016 		hsotg->frrem_accum / hsotg->frrem_samples : 0);
2017 	dev_dbg(hsotg->dev, "\n");
2018 	dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2019 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2020 		hsotg->hfnum_7_samples,
2021 		hsotg->hfnum_7_frrem_accum,
2022 		hsotg->hfnum_7_samples > 0 ?
2023 		hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2024 	dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2025 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2026 		hsotg->hfnum_0_samples,
2027 		hsotg->hfnum_0_frrem_accum,
2028 		hsotg->hfnum_0_samples > 0 ?
2029 		hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2030 	dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2031 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2032 		hsotg->hfnum_other_samples,
2033 		hsotg->hfnum_other_frrem_accum,
2034 		hsotg->hfnum_other_samples > 0 ?
2035 		hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2036 		0);
2037 	dev_dbg(hsotg->dev, "\n");
2038 	dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2039 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2040 		hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2041 		hsotg->hfnum_7_samples_a > 0 ?
2042 		hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2043 	dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2044 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2045 		hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2046 		hsotg->hfnum_0_samples_a > 0 ?
2047 		hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2048 	dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2049 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2050 		hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2051 		hsotg->hfnum_other_samples_a > 0 ?
2052 		hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2053 		: 0);
2054 	dev_dbg(hsotg->dev, "\n");
2055 	dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2056 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2057 		hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2058 		hsotg->hfnum_7_samples_b > 0 ?
2059 		hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2060 	dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2061 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2062 		hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2063 		(hsotg->hfnum_0_samples_b > 0) ?
2064 		hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2065 	dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2066 	dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2067 		hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2068 		(hsotg->hfnum_other_samples_b > 0) ?
2069 		hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2070 		: 0);
2071 #endif
2072 }
2073 
2074 struct wrapper_priv_data {
2075 	struct dwc2_hsotg *hsotg;
2076 };
2077 
2078 /* Gets the dwc2_hsotg from a usb_hcd */
2079 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2080 {
2081 	struct wrapper_priv_data *p;
2082 
2083 	p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2084 	return p->hsotg;
2085 }
2086 
2087 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2088 
2089 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2090 {
2091 	struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2092 
2093 	hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2094 	_dwc2_hcd_start(hcd);
2095 }
2096 
2097 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2098 {
2099 	struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2100 
2101 	hcd->self.is_b_host = 0;
2102 }
2103 
2104 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2105 			int *hub_port)
2106 {
2107 	struct urb *urb = context;
2108 
2109 	if (urb->dev->tt)
2110 		*hub_addr = urb->dev->tt->hub->devnum;
2111 	else
2112 		*hub_addr = 0;
2113 	*hub_port = urb->dev->ttport;
2114 }
2115 
2116 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2117 {
2118 	struct urb *urb = context;
2119 
2120 	return urb->dev->speed;
2121 }
2122 
2123 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2124 					struct urb *urb)
2125 {
2126 	struct usb_bus *bus = hcd_to_bus(hcd);
2127 
2128 	if (urb->interval)
2129 		bus->bandwidth_allocated += bw / urb->interval;
2130 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2131 		bus->bandwidth_isoc_reqs++;
2132 	else
2133 		bus->bandwidth_int_reqs++;
2134 }
2135 
2136 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2137 				    struct urb *urb)
2138 {
2139 	struct usb_bus *bus = hcd_to_bus(hcd);
2140 
2141 	if (urb->interval)
2142 		bus->bandwidth_allocated -= bw / urb->interval;
2143 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2144 		bus->bandwidth_isoc_reqs--;
2145 	else
2146 		bus->bandwidth_int_reqs--;
2147 }
2148 
2149 /*
2150  * Sets the final status of an URB and returns it to the upper layer. Any
2151  * required cleanup of the URB is performed.
2152  *
2153  * Must be called with interrupt disabled and spinlock held
2154  */
2155 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2156 			int status)
2157 {
2158 	struct urb *urb;
2159 	int i;
2160 
2161 	if (!qtd) {
2162 		dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2163 		return;
2164 	}
2165 
2166 	if (!qtd->urb) {
2167 		dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2168 		return;
2169 	}
2170 
2171 	urb = qtd->urb->priv;
2172 	if (!urb) {
2173 		dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2174 		return;
2175 	}
2176 
2177 	urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2178 
2179 	if (dbg_urb(urb))
2180 		dev_vdbg(hsotg->dev,
2181 			 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2182 			 __func__, urb, usb_pipedevice(urb->pipe),
2183 			 usb_pipeendpoint(urb->pipe),
2184 			 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2185 			 urb->actual_length);
2186 
2187 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2188 		for (i = 0; i < urb->number_of_packets; i++)
2189 			dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2190 				 i, urb->iso_frame_desc[i].status);
2191 	}
2192 
2193 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2194 		urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2195 		for (i = 0; i < urb->number_of_packets; ++i) {
2196 			urb->iso_frame_desc[i].actual_length =
2197 				dwc2_hcd_urb_get_iso_desc_actual_length(
2198 						qtd->urb, i);
2199 			urb->iso_frame_desc[i].status =
2200 				dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2201 		}
2202 	}
2203 
2204 	urb->status = status;
2205 	if (!status) {
2206 		if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2207 		    urb->actual_length < urb->transfer_buffer_length)
2208 			urb->status = -EREMOTEIO;
2209 	}
2210 
2211 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2212 	    usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2213 		struct usb_host_endpoint *ep = urb->ep;
2214 
2215 		if (ep)
2216 			dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2217 					dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2218 					urb);
2219 	}
2220 
2221 	usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2222 	urb->hcpriv = NULL;
2223 	kfree(qtd->urb);
2224 	qtd->urb = NULL;
2225 
2226 	spin_unlock(&hsotg->lock);
2227 	usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2228 	spin_lock(&hsotg->lock);
2229 }
2230 
2231 /*
2232  * Work queue function for starting the HCD when A-Cable is connected
2233  */
2234 static void dwc2_hcd_start_func(struct work_struct *work)
2235 {
2236 	struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2237 						start_work.work);
2238 
2239 	dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2240 	dwc2_host_start(hsotg);
2241 }
2242 
2243 /*
2244  * Reset work queue function
2245  */
2246 static void dwc2_hcd_reset_func(struct work_struct *work)
2247 {
2248 	struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2249 						reset_work.work);
2250 	u32 hprt0;
2251 
2252 	dev_dbg(hsotg->dev, "USB RESET function called\n");
2253 	hprt0 = dwc2_read_hprt0(hsotg);
2254 	hprt0 &= ~HPRT0_RST;
2255 	writel(hprt0, hsotg->regs + HPRT0);
2256 	hsotg->flags.b.port_reset_change = 1;
2257 }
2258 
2259 /*
2260  * =========================================================================
2261  *  Linux HC Driver Functions
2262  * =========================================================================
2263  */
2264 
2265 /*
2266  * Initializes the DWC_otg controller and its root hub and prepares it for host
2267  * mode operation. Activates the root port. Returns 0 on success and a negative
2268  * error code on failure.
2269  */
2270 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2271 {
2272 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2273 	struct usb_bus *bus = hcd_to_bus(hcd);
2274 	unsigned long flags;
2275 
2276 	dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2277 
2278 	spin_lock_irqsave(&hsotg->lock, flags);
2279 
2280 	hcd->state = HC_STATE_RUNNING;
2281 
2282 	if (dwc2_is_device_mode(hsotg)) {
2283 		spin_unlock_irqrestore(&hsotg->lock, flags);
2284 		return 0;	/* why 0 ?? */
2285 	}
2286 
2287 	dwc2_hcd_reinit(hsotg);
2288 
2289 	/* Initialize and connect root hub if one is not already attached */
2290 	if (bus->root_hub) {
2291 		dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2292 		/* Inform the HUB driver to resume */
2293 		usb_hcd_resume_root_hub(hcd);
2294 	}
2295 
2296 	spin_unlock_irqrestore(&hsotg->lock, flags);
2297 	return 0;
2298 }
2299 
2300 /*
2301  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2302  * stopped.
2303  */
2304 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2305 {
2306 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2307 	unsigned long flags;
2308 
2309 	spin_lock_irqsave(&hsotg->lock, flags);
2310 	dwc2_hcd_stop(hsotg);
2311 	spin_unlock_irqrestore(&hsotg->lock, flags);
2312 
2313 	usleep_range(1000, 3000);
2314 }
2315 
2316 /* Returns the current frame number */
2317 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2318 {
2319 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2320 
2321 	return dwc2_hcd_get_frame_number(hsotg);
2322 }
2323 
2324 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2325 			       char *fn_name)
2326 {
2327 #ifdef VERBOSE_DEBUG
2328 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2329 	char *pipetype;
2330 	char *speed;
2331 
2332 	dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2333 	dev_vdbg(hsotg->dev, "  Device address: %d\n",
2334 		 usb_pipedevice(urb->pipe));
2335 	dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2336 		 usb_pipeendpoint(urb->pipe),
2337 		 usb_pipein(urb->pipe) ? "IN" : "OUT");
2338 
2339 	switch (usb_pipetype(urb->pipe)) {
2340 	case PIPE_CONTROL:
2341 		pipetype = "CONTROL";
2342 		break;
2343 	case PIPE_BULK:
2344 		pipetype = "BULK";
2345 		break;
2346 	case PIPE_INTERRUPT:
2347 		pipetype = "INTERRUPT";
2348 		break;
2349 	case PIPE_ISOCHRONOUS:
2350 		pipetype = "ISOCHRONOUS";
2351 		break;
2352 	default:
2353 		pipetype = "UNKNOWN";
2354 		break;
2355 	}
2356 
2357 	dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2358 		 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2359 		 "IN" : "OUT");
2360 
2361 	switch (urb->dev->speed) {
2362 	case USB_SPEED_HIGH:
2363 		speed = "HIGH";
2364 		break;
2365 	case USB_SPEED_FULL:
2366 		speed = "FULL";
2367 		break;
2368 	case USB_SPEED_LOW:
2369 		speed = "LOW";
2370 		break;
2371 	default:
2372 		speed = "UNKNOWN";
2373 		break;
2374 	}
2375 
2376 	dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2377 	dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2378 		 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2379 	dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2380 		 urb->transfer_buffer_length);
2381 	dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2382 		 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2383 	dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2384 		 urb->setup_packet, (unsigned long)urb->setup_dma);
2385 	dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2386 
2387 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2388 		int i;
2389 
2390 		for (i = 0; i < urb->number_of_packets; i++) {
2391 			dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2392 			dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2393 				 urb->iso_frame_desc[i].offset,
2394 				 urb->iso_frame_desc[i].length);
2395 		}
2396 	}
2397 #endif
2398 }
2399 
2400 /*
2401  * Starts processing a USB transfer request specified by a USB Request Block
2402  * (URB). mem_flags indicates the type of memory allocation to use while
2403  * processing this URB.
2404  */
2405 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2406 				 gfp_t mem_flags)
2407 {
2408 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2409 	struct usb_host_endpoint *ep = urb->ep;
2410 	struct dwc2_hcd_urb *dwc2_urb;
2411 	int i;
2412 	int retval;
2413 	int alloc_bandwidth = 0;
2414 	u8 ep_type = 0;
2415 	u32 tflags = 0;
2416 	void *buf;
2417 	unsigned long flags;
2418 
2419 	if (dbg_urb(urb)) {
2420 		dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2421 		dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2422 	}
2423 
2424 	if (ep == NULL)
2425 		return -EINVAL;
2426 
2427 	if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2428 	    usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2429 		spin_lock_irqsave(&hsotg->lock, flags);
2430 		if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2431 			alloc_bandwidth = 1;
2432 		spin_unlock_irqrestore(&hsotg->lock, flags);
2433 	}
2434 
2435 	switch (usb_pipetype(urb->pipe)) {
2436 	case PIPE_CONTROL:
2437 		ep_type = USB_ENDPOINT_XFER_CONTROL;
2438 		break;
2439 	case PIPE_ISOCHRONOUS:
2440 		ep_type = USB_ENDPOINT_XFER_ISOC;
2441 		break;
2442 	case PIPE_BULK:
2443 		ep_type = USB_ENDPOINT_XFER_BULK;
2444 		break;
2445 	case PIPE_INTERRUPT:
2446 		ep_type = USB_ENDPOINT_XFER_INT;
2447 		break;
2448 	default:
2449 		dev_warn(hsotg->dev, "Wrong ep type\n");
2450 	}
2451 
2452 	dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2453 				      mem_flags);
2454 	if (!dwc2_urb)
2455 		return -ENOMEM;
2456 
2457 	dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2458 				  usb_pipeendpoint(urb->pipe), ep_type,
2459 				  usb_pipein(urb->pipe),
2460 				  usb_maxpacket(urb->dev, urb->pipe,
2461 						!(usb_pipein(urb->pipe))));
2462 
2463 	buf = urb->transfer_buffer;
2464 
2465 	if (hcd->self.uses_dma) {
2466 		if (!buf && (urb->transfer_dma & 3)) {
2467 			dev_err(hsotg->dev,
2468 				"%s: unaligned transfer with no transfer_buffer",
2469 				__func__);
2470 			retval = -EINVAL;
2471 			goto fail1;
2472 		}
2473 	}
2474 
2475 	if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2476 		tflags |= URB_GIVEBACK_ASAP;
2477 	if (urb->transfer_flags & URB_ZERO_PACKET)
2478 		tflags |= URB_SEND_ZERO_PACKET;
2479 
2480 	dwc2_urb->priv = urb;
2481 	dwc2_urb->buf = buf;
2482 	dwc2_urb->dma = urb->transfer_dma;
2483 	dwc2_urb->length = urb->transfer_buffer_length;
2484 	dwc2_urb->setup_packet = urb->setup_packet;
2485 	dwc2_urb->setup_dma = urb->setup_dma;
2486 	dwc2_urb->flags = tflags;
2487 	dwc2_urb->interval = urb->interval;
2488 	dwc2_urb->status = -EINPROGRESS;
2489 
2490 	for (i = 0; i < urb->number_of_packets; ++i)
2491 		dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2492 						 urb->iso_frame_desc[i].offset,
2493 						 urb->iso_frame_desc[i].length);
2494 
2495 	urb->hcpriv = dwc2_urb;
2496 
2497 	spin_lock_irqsave(&hsotg->lock, flags);
2498 	retval = usb_hcd_link_urb_to_ep(hcd, urb);
2499 	spin_unlock_irqrestore(&hsotg->lock, flags);
2500 	if (retval)
2501 		goto fail1;
2502 
2503 	retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags);
2504 	if (retval)
2505 		goto fail2;
2506 
2507 	if (alloc_bandwidth) {
2508 		spin_lock_irqsave(&hsotg->lock, flags);
2509 		dwc2_allocate_bus_bandwidth(hcd,
2510 				dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2511 				urb);
2512 		spin_unlock_irqrestore(&hsotg->lock, flags);
2513 	}
2514 
2515 	return 0;
2516 
2517 fail2:
2518 	spin_lock_irqsave(&hsotg->lock, flags);
2519 	dwc2_urb->priv = NULL;
2520 	usb_hcd_unlink_urb_from_ep(hcd, urb);
2521 	spin_unlock_irqrestore(&hsotg->lock, flags);
2522 fail1:
2523 	urb->hcpriv = NULL;
2524 	kfree(dwc2_urb);
2525 
2526 	return retval;
2527 }
2528 
2529 /*
2530  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2531  */
2532 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2533 				 int status)
2534 {
2535 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2536 	int rc;
2537 	unsigned long flags;
2538 
2539 	dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2540 	dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2541 
2542 	spin_lock_irqsave(&hsotg->lock, flags);
2543 
2544 	rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2545 	if (rc)
2546 		goto out;
2547 
2548 	if (!urb->hcpriv) {
2549 		dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2550 		goto out;
2551 	}
2552 
2553 	rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2554 
2555 	usb_hcd_unlink_urb_from_ep(hcd, urb);
2556 
2557 	kfree(urb->hcpriv);
2558 	urb->hcpriv = NULL;
2559 
2560 	/* Higher layer software sets URB status */
2561 	spin_unlock(&hsotg->lock);
2562 	usb_hcd_giveback_urb(hcd, urb, status);
2563 	spin_lock(&hsotg->lock);
2564 
2565 	dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2566 	dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2567 out:
2568 	spin_unlock_irqrestore(&hsotg->lock, flags);
2569 
2570 	return rc;
2571 }
2572 
2573 /*
2574  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2575  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2576  * must already be dequeued.
2577  */
2578 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2579 				       struct usb_host_endpoint *ep)
2580 {
2581 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2582 
2583 	dev_dbg(hsotg->dev,
2584 		"DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2585 		ep->desc.bEndpointAddress, ep->hcpriv);
2586 	dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2587 }
2588 
2589 /*
2590  * Resets endpoint specific parameter values, in current version used to reset
2591  * the data toggle (as a WA). This function can be called from usb_clear_halt
2592  * routine.
2593  */
2594 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2595 				     struct usb_host_endpoint *ep)
2596 {
2597 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2598 	unsigned long flags;
2599 
2600 	dev_dbg(hsotg->dev,
2601 		"DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2602 		ep->desc.bEndpointAddress);
2603 
2604 	spin_lock_irqsave(&hsotg->lock, flags);
2605 	dwc2_hcd_endpoint_reset(hsotg, ep);
2606 	spin_unlock_irqrestore(&hsotg->lock, flags);
2607 }
2608 
2609 /*
2610  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2611  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2612  * interrupt.
2613  *
2614  * This function is called by the USB core when an interrupt occurs
2615  */
2616 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2617 {
2618 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2619 
2620 	return dwc2_handle_hcd_intr(hsotg);
2621 }
2622 
2623 /*
2624  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2625  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2626  * is the status change indicator for the single root port. Returns 1 if either
2627  * change indicator is 1, otherwise returns 0.
2628  */
2629 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2630 {
2631 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2632 
2633 	buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2634 	return buf[0] != 0;
2635 }
2636 
2637 /* Handles hub class-specific requests */
2638 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2639 				 u16 windex, char *buf, u16 wlength)
2640 {
2641 	int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2642 					  wvalue, windex, buf, wlength);
2643 	return retval;
2644 }
2645 
2646 /* Handles hub TT buffer clear completions */
2647 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2648 					       struct usb_host_endpoint *ep)
2649 {
2650 	struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2651 	struct dwc2_qh *qh;
2652 	unsigned long flags;
2653 
2654 	qh = ep->hcpriv;
2655 	if (!qh)
2656 		return;
2657 
2658 	spin_lock_irqsave(&hsotg->lock, flags);
2659 	qh->tt_buffer_dirty = 0;
2660 
2661 	if (hsotg->flags.b.port_connect_status)
2662 		dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2663 
2664 	spin_unlock_irqrestore(&hsotg->lock, flags);
2665 }
2666 
2667 static struct hc_driver dwc2_hc_driver = {
2668 	.description = "dwc2_hsotg",
2669 	.product_desc = "DWC OTG Controller",
2670 	.hcd_priv_size = sizeof(struct wrapper_priv_data),
2671 
2672 	.irq = _dwc2_hcd_irq,
2673 	.flags = HCD_MEMORY | HCD_USB2,
2674 
2675 	.start = _dwc2_hcd_start,
2676 	.stop = _dwc2_hcd_stop,
2677 	.urb_enqueue = _dwc2_hcd_urb_enqueue,
2678 	.urb_dequeue = _dwc2_hcd_urb_dequeue,
2679 	.endpoint_disable = _dwc2_hcd_endpoint_disable,
2680 	.endpoint_reset = _dwc2_hcd_endpoint_reset,
2681 	.get_frame_number = _dwc2_hcd_get_frame_number,
2682 
2683 	.hub_status_data = _dwc2_hcd_hub_status_data,
2684 	.hub_control = _dwc2_hcd_hub_control,
2685 	.clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2686 };
2687 
2688 /*
2689  * Frees secondary storage associated with the dwc2_hsotg structure contained
2690  * in the struct usb_hcd field
2691  */
2692 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2693 {
2694 	u32 ahbcfg;
2695 	u32 dctl;
2696 	int i;
2697 
2698 	dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2699 
2700 	/* Free memory for QH/QTD lists */
2701 	dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2702 	dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2703 	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2704 	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2705 	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2706 	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2707 
2708 	/* Free memory for the host channels */
2709 	for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2710 		struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2711 
2712 		if (chan != NULL) {
2713 			dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2714 				i, chan);
2715 			hsotg->hc_ptr_array[i] = NULL;
2716 			kfree(chan);
2717 		}
2718 	}
2719 
2720 	if (hsotg->core_params->dma_enable > 0) {
2721 		if (hsotg->status_buf) {
2722 			dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2723 					  hsotg->status_buf,
2724 					  hsotg->status_buf_dma);
2725 			hsotg->status_buf = NULL;
2726 		}
2727 	} else {
2728 		kfree(hsotg->status_buf);
2729 		hsotg->status_buf = NULL;
2730 	}
2731 
2732 	ahbcfg = readl(hsotg->regs + GAHBCFG);
2733 
2734 	/* Disable all interrupts */
2735 	ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2736 	writel(ahbcfg, hsotg->regs + GAHBCFG);
2737 	writel(0, hsotg->regs + GINTMSK);
2738 
2739 	if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2740 		dctl = readl(hsotg->regs + DCTL);
2741 		dctl |= DCTL_SFTDISCON;
2742 		writel(dctl, hsotg->regs + DCTL);
2743 	}
2744 
2745 	if (hsotg->wq_otg) {
2746 		if (!cancel_work_sync(&hsotg->wf_otg))
2747 			flush_workqueue(hsotg->wq_otg);
2748 		destroy_workqueue(hsotg->wq_otg);
2749 	}
2750 
2751 	kfree(hsotg->core_params);
2752 	hsotg->core_params = NULL;
2753 	del_timer(&hsotg->wkp_timer);
2754 }
2755 
2756 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2757 {
2758 	/* Turn off all host-specific interrupts */
2759 	dwc2_disable_host_interrupts(hsotg);
2760 
2761 	dwc2_hcd_free(hsotg);
2762 }
2763 
2764 /*
2765  * Sets all parameters to the given value.
2766  *
2767  * Assumes that the dwc2_core_params struct contains only integers.
2768  */
2769 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
2770 {
2771 	int *p = (int *)params;
2772 	size_t size = sizeof(*params) / sizeof(*p);
2773 	int i;
2774 
2775 	for (i = 0; i < size; i++)
2776 		p[i] = value;
2777 }
2778 EXPORT_SYMBOL_GPL(dwc2_set_all_params);
2779 
2780 /*
2781  * Initializes the HCD. This function allocates memory for and initializes the
2782  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2783  * USB bus with the core and calls the hc_driver->start() function. It returns
2784  * a negative error on failure.
2785  */
2786 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
2787 		  const struct dwc2_core_params *params)
2788 {
2789 	struct usb_hcd *hcd;
2790 	struct dwc2_host_chan *channel;
2791 	u32 hcfg;
2792 	int i, num_channels;
2793 	int retval;
2794 
2795 	if (usb_disabled())
2796 		return -ENODEV;
2797 
2798 	dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2799 
2800 	/* Detect config values from hardware */
2801 	retval = dwc2_get_hwparams(hsotg);
2802 
2803 	if (retval)
2804 		return retval;
2805 
2806 	retval = -ENOMEM;
2807 
2808 	hcfg = readl(hsotg->regs + HCFG);
2809 	dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2810 
2811 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2812 	hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2813 					 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2814 	if (!hsotg->frame_num_array)
2815 		goto error1;
2816 	hsotg->last_frame_num_array = kzalloc(
2817 			sizeof(*hsotg->last_frame_num_array) *
2818 			FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2819 	if (!hsotg->last_frame_num_array)
2820 		goto error1;
2821 	hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2822 #endif
2823 
2824 	hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2825 	if (!hsotg->core_params)
2826 		goto error1;
2827 
2828 	dwc2_set_all_params(hsotg->core_params, -1);
2829 
2830 	/* Validate parameter values */
2831 	dwc2_set_parameters(hsotg, params);
2832 
2833 	/* Check if the bus driver or platform code has setup a dma_mask */
2834 	if (hsotg->core_params->dma_enable > 0 &&
2835 	    hsotg->dev->dma_mask == NULL) {
2836 		dev_warn(hsotg->dev,
2837 			 "dma_mask not set, disabling DMA\n");
2838 		hsotg->core_params->dma_enable = 0;
2839 		hsotg->core_params->dma_desc_enable = 0;
2840 	}
2841 
2842 	/* Set device flags indicating whether the HCD supports DMA */
2843 	if (hsotg->core_params->dma_enable > 0) {
2844 		if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2845 			dev_warn(hsotg->dev, "can't set DMA mask\n");
2846 		if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2847 			dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2848 	}
2849 
2850 	hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2851 	if (!hcd)
2852 		goto error1;
2853 
2854 	if (hsotg->core_params->dma_enable <= 0)
2855 		hcd->self.uses_dma = 0;
2856 
2857 	hcd->has_tt = 1;
2858 
2859 	((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2860 	hsotg->priv = hcd;
2861 
2862 	/*
2863 	 * Disable the global interrupt until all the interrupt handlers are
2864 	 * installed
2865 	 */
2866 	dwc2_disable_global_interrupts(hsotg);
2867 
2868 	/* Initialize the DWC_otg core, and select the Phy type */
2869 	retval = dwc2_core_init(hsotg, true, irq);
2870 	if (retval)
2871 		goto error2;
2872 
2873 	/* Create new workqueue and init work */
2874 	retval = -ENOMEM;
2875 	hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2876 	if (!hsotg->wq_otg) {
2877 		dev_err(hsotg->dev, "Failed to create workqueue\n");
2878 		goto error2;
2879 	}
2880 	INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2881 
2882 	setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2883 		    (unsigned long)hsotg);
2884 
2885 	/* Initialize the non-periodic schedule */
2886 	INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2887 	INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2888 
2889 	/* Initialize the periodic schedule */
2890 	INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2891 	INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2892 	INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2893 	INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2894 
2895 	/*
2896 	 * Create a host channel descriptor for each host channel implemented
2897 	 * in the controller. Initialize the channel descriptor array.
2898 	 */
2899 	INIT_LIST_HEAD(&hsotg->free_hc_list);
2900 	num_channels = hsotg->core_params->host_channels;
2901 	memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2902 
2903 	for (i = 0; i < num_channels; i++) {
2904 		channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2905 		if (channel == NULL)
2906 			goto error3;
2907 		channel->hc_num = i;
2908 		hsotg->hc_ptr_array[i] = channel;
2909 	}
2910 
2911 	if (hsotg->core_params->uframe_sched > 0)
2912 		dwc2_hcd_init_usecs(hsotg);
2913 
2914 	/* Initialize hsotg start work */
2915 	INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2916 
2917 	/* Initialize port reset work */
2918 	INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2919 
2920 	/*
2921 	 * Allocate space for storing data on status transactions. Normally no
2922 	 * data is sent, but this space acts as a bit bucket. This must be
2923 	 * done after usb_add_hcd since that function allocates the DMA buffer
2924 	 * pool.
2925 	 */
2926 	if (hsotg->core_params->dma_enable > 0)
2927 		hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2928 					DWC2_HCD_STATUS_BUF_SIZE,
2929 					&hsotg->status_buf_dma, GFP_KERNEL);
2930 	else
2931 		hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2932 					  GFP_KERNEL);
2933 
2934 	if (!hsotg->status_buf)
2935 		goto error3;
2936 
2937 	hsotg->otg_port = 1;
2938 	hsotg->frame_list = NULL;
2939 	hsotg->frame_list_dma = 0;
2940 	hsotg->periodic_qh_count = 0;
2941 
2942 	/* Initiate lx_state to L3 disconnected state */
2943 	hsotg->lx_state = DWC2_L3;
2944 
2945 	hcd->self.otg_port = hsotg->otg_port;
2946 
2947 	/* Don't support SG list at this point */
2948 	hcd->self.sg_tablesize = 0;
2949 
2950 	/*
2951 	 * Finish generic HCD initialization and start the HCD. This function
2952 	 * allocates the DMA buffer pool, registers the USB bus, requests the
2953 	 * IRQ line, and calls hcd_start method.
2954 	 */
2955 	retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2956 	if (retval < 0)
2957 		goto error3;
2958 
2959 	device_wakeup_enable(hcd->self.controller);
2960 
2961 	dwc2_hcd_dump_state(hsotg);
2962 
2963 	dwc2_enable_global_interrupts(hsotg);
2964 
2965 	return 0;
2966 
2967 error3:
2968 	dwc2_hcd_release(hsotg);
2969 error2:
2970 	usb_put_hcd(hcd);
2971 error1:
2972 	kfree(hsotg->core_params);
2973 
2974 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2975 	kfree(hsotg->last_frame_num_array);
2976 	kfree(hsotg->frame_num_array);
2977 #endif
2978 
2979 	dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
2980 	return retval;
2981 }
2982 EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2983 
2984 /*
2985  * Removes the HCD.
2986  * Frees memory and resources associated with the HCD and deregisters the bus.
2987  */
2988 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
2989 {
2990 	struct usb_hcd *hcd;
2991 
2992 	dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
2993 
2994 	hcd = dwc2_hsotg_to_hcd(hsotg);
2995 	dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
2996 
2997 	if (!hcd) {
2998 		dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
2999 			__func__);
3000 		return;
3001 	}
3002 
3003 	usb_remove_hcd(hcd);
3004 	hsotg->priv = NULL;
3005 	dwc2_hcd_release(hsotg);
3006 	usb_put_hcd(hcd);
3007 
3008 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3009 	kfree(hsotg->last_frame_num_array);
3010 	kfree(hsotg->frame_num_array);
3011 #endif
3012 }
3013 EXPORT_SYMBOL_GPL(dwc2_hcd_remove);
3014