1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * hcd.c - DesignWare HS OTG Controller host-mode routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The names of the above-listed copyright holders may not be used 17 * to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * ALTERNATIVELY, this software may be distributed under the terms of the 21 * GNU General Public License ("GPL") as published by the Free Software 22 * Foundation; either version 2 of the License, or (at your option) any 23 * later version. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * This file contains the core HCD code, and implements the Linux hc_driver 40 * API 41 */ 42 #include <linux/kernel.h> 43 #include <linux/module.h> 44 #include <linux/spinlock.h> 45 #include <linux/interrupt.h> 46 #include <linux/platform_device.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/delay.h> 49 #include <linux/io.h> 50 #include <linux/slab.h> 51 #include <linux/usb.h> 52 53 #include <linux/usb/hcd.h> 54 #include <linux/usb/ch11.h> 55 56 #include "core.h" 57 #include "hcd.h" 58 59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg); 60 61 /* 62 * ========================================================================= 63 * Host Core Layer Functions 64 * ========================================================================= 65 */ 66 67 /** 68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts, 69 * used in both device and host modes 70 * 71 * @hsotg: Programming view of the DWC_otg controller 72 */ 73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) 74 { 75 u32 intmsk; 76 77 /* Clear any pending OTG Interrupts */ 78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); 79 80 /* Clear any pending interrupts */ 81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); 82 83 /* Enable the interrupts in the GINTMSK */ 84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; 85 86 if (!hsotg->params.host_dma) 87 intmsk |= GINTSTS_RXFLVL; 88 if (!hsotg->params.external_id_pin_ctl) 89 intmsk |= GINTSTS_CONIDSTSCHNG; 90 91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP | 92 GINTSTS_SESSREQINT; 93 94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) 95 intmsk |= GINTSTS_LPMTRANRCVD; 96 97 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 98 } 99 100 /* 101 * Initializes the FSLSPClkSel field of the HCFG register depending on the 102 * PHY type 103 */ 104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 105 { 106 u32 hcfg, val; 107 108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 110 hsotg->params.ulpi_fs_ls) || 111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 112 /* Full speed PHY */ 113 val = HCFG_FSLSPCLKSEL_48_MHZ; 114 } else { 115 /* High speed PHY running at full speed or high speed */ 116 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 117 } 118 119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 120 hcfg = dwc2_readl(hsotg->regs + HCFG); 121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 123 dwc2_writel(hcfg, hsotg->regs + HCFG); 124 } 125 126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 127 { 128 u32 usbcfg, ggpio, i2cctl; 129 int retval = 0; 130 131 /* 132 * core_init() is now called on every switch so only call the 133 * following for the first time through 134 */ 135 if (select_phy) { 136 dev_dbg(hsotg->dev, "FS PHY selected\n"); 137 138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 139 if (!(usbcfg & GUSBCFG_PHYSEL)) { 140 usbcfg |= GUSBCFG_PHYSEL; 141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 142 143 /* Reset after a PHY select */ 144 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 145 146 if (retval) { 147 dev_err(hsotg->dev, 148 "%s: Reset failed, aborting", __func__); 149 return retval; 150 } 151 } 152 153 if (hsotg->params.activate_stm_fs_transceiver) { 154 ggpio = dwc2_readl(hsotg->regs + GGPIO); 155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 156 dev_dbg(hsotg->dev, "Activating transceiver\n"); 157 /* 158 * STM32F4x9 uses the GGPIO register as general 159 * core configuration register. 160 */ 161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 162 dwc2_writel(ggpio, hsotg->regs + GGPIO); 163 } 164 } 165 } 166 167 /* 168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 169 * do this on HNP Dev/Host mode switches (done in dev_init and 170 * host_init). 171 */ 172 if (dwc2_is_host_mode(hsotg)) 173 dwc2_init_fs_ls_pclk_sel(hsotg); 174 175 if (hsotg->params.i2c_enable) { 176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 177 178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 182 183 /* Program GI2CCTL.I2CEn */ 184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); 185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 187 i2cctl &= ~GI2CCTL_I2CEN; 188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 189 i2cctl |= GI2CCTL_I2CEN; 190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); 191 } 192 193 return retval; 194 } 195 196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 197 { 198 u32 usbcfg, usbcfg_old; 199 int retval = 0; 200 201 if (!select_phy) 202 return 0; 203 204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 205 usbcfg_old = usbcfg; 206 207 /* 208 * HS PHY parameters. These parameters are preserved during soft reset 209 * so only program the first time. Do a soft reset immediately after 210 * setting phyif. 211 */ 212 switch (hsotg->params.phy_type) { 213 case DWC2_PHY_TYPE_PARAM_ULPI: 214 /* ULPI interface */ 215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 218 if (hsotg->params.phy_ulpi_ddr) 219 usbcfg |= GUSBCFG_DDRSEL; 220 221 /* Set external VBUS indicator as needed. */ 222 if (hsotg->params.oc_disable) 223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 224 GUSBCFG_INDICATORPASSTHROUGH); 225 break; 226 case DWC2_PHY_TYPE_PARAM_UTMI: 227 /* UTMI+ interface */ 228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 230 if (hsotg->params.phy_utmi_width == 16) 231 usbcfg |= GUSBCFG_PHYIF16; 232 break; 233 default: 234 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 235 break; 236 } 237 238 if (usbcfg != usbcfg_old) { 239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 240 241 /* Reset after setting the PHY parameters */ 242 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 243 if (retval) { 244 dev_err(hsotg->dev, 245 "%s: Reset failed, aborting", __func__); 246 return retval; 247 } 248 } 249 250 return retval; 251 } 252 253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 254 { 255 u32 usbcfg; 256 int retval = 0; 257 258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 261 /* If FS/LS mode with FS/LS PHY */ 262 retval = dwc2_fs_phy_init(hsotg, select_phy); 263 if (retval) 264 return retval; 265 } else { 266 /* High speed PHY */ 267 retval = dwc2_hs_phy_init(hsotg, select_phy); 268 if (retval) 269 return retval; 270 } 271 272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 274 hsotg->params.ulpi_fs_ls) { 275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 277 usbcfg |= GUSBCFG_ULPI_FS_LS; 278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 280 } else { 281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 282 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 285 } 286 287 return retval; 288 } 289 290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) 291 { 292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 293 294 switch (hsotg->hw_params.arch) { 295 case GHWCFG2_EXT_DMA_ARCH: 296 dev_err(hsotg->dev, "External DMA Mode not supported\n"); 297 return -EINVAL; 298 299 case GHWCFG2_INT_DMA_ARCH: 300 dev_dbg(hsotg->dev, "Internal DMA Mode\n"); 301 if (hsotg->params.ahbcfg != -1) { 302 ahbcfg &= GAHBCFG_CTRL_MASK; 303 ahbcfg |= hsotg->params.ahbcfg & 304 ~GAHBCFG_CTRL_MASK; 305 } 306 break; 307 308 case GHWCFG2_SLAVE_ONLY_ARCH: 309 default: 310 dev_dbg(hsotg->dev, "Slave Only Mode\n"); 311 break; 312 } 313 314 if (hsotg->params.host_dma) 315 ahbcfg |= GAHBCFG_DMA_EN; 316 else 317 hsotg->params.dma_desc_enable = false; 318 319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 320 321 return 0; 322 } 323 324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) 325 { 326 u32 usbcfg; 327 328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); 330 331 switch (hsotg->hw_params.op_mode) { 332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE: 333 if (hsotg->params.otg_cap == 334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE) 335 usbcfg |= GUSBCFG_HNPCAP; 336 if (hsotg->params.otg_cap != 337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 338 usbcfg |= GUSBCFG_SRPCAP; 339 break; 340 341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE: 342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE: 343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST: 344 if (hsotg->params.otg_cap != 345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) 346 usbcfg |= GUSBCFG_SRPCAP; 347 break; 348 349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE: 350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE: 351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST: 352 default: 353 break; 354 } 355 356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 357 } 358 359 /** 360 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts 361 * 362 * @hsotg: Programming view of DWC_otg controller 363 */ 364 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) 365 { 366 u32 intmsk; 367 368 dev_dbg(hsotg->dev, "%s()\n", __func__); 369 370 /* Disable all interrupts */ 371 dwc2_writel(0, hsotg->regs + GINTMSK); 372 dwc2_writel(0, hsotg->regs + HAINTMSK); 373 374 /* Enable the common interrupts */ 375 dwc2_enable_common_interrupts(hsotg); 376 377 /* Enable host mode interrupts without disturbing common interrupts */ 378 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 379 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; 380 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 381 } 382 383 /** 384 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts 385 * 386 * @hsotg: Programming view of DWC_otg controller 387 */ 388 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) 389 { 390 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 391 392 /* Disable host mode interrupts without disturbing common interrupts */ 393 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | 394 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); 395 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 396 } 397 398 /* 399 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size 400 * For system that have a total fifo depth that is smaller than the default 401 * RX + TX fifo size. 402 * 403 * @hsotg: Programming view of DWC_otg controller 404 */ 405 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg) 406 { 407 struct dwc2_core_params *params = &hsotg->params; 408 struct dwc2_hw_params *hw = &hsotg->hw_params; 409 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size; 410 411 total_fifo_size = hw->total_fifo_size; 412 rxfsiz = params->host_rx_fifo_size; 413 nptxfsiz = params->host_nperio_tx_fifo_size; 414 ptxfsiz = params->host_perio_tx_fifo_size; 415 416 /* 417 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth 418 * allocation with support for high bandwidth endpoints. Synopsys 419 * defines MPS(Max Packet size) for a periodic EP=1024, and for 420 * non-periodic as 512. 421 */ 422 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) { 423 /* 424 * For Buffer DMA mode/Scatter Gather DMA mode 425 * 2 * ((Largest Packet size / 4) + 1 + 1) + n 426 * with n = number of host channel. 427 * 2 * ((1024/4) + 2) = 516 428 */ 429 rxfsiz = 516 + hw->host_channels; 430 431 /* 432 * min non-periodic tx fifo depth 433 * 2 * (largest non-periodic USB packet used / 4) 434 * 2 * (512/4) = 256 435 */ 436 nptxfsiz = 256; 437 438 /* 439 * min periodic tx fifo depth 440 * (largest packet size*MC)/4 441 * (1024 * 3)/4 = 768 442 */ 443 ptxfsiz = 768; 444 445 params->host_rx_fifo_size = rxfsiz; 446 params->host_nperio_tx_fifo_size = nptxfsiz; 447 params->host_perio_tx_fifo_size = ptxfsiz; 448 } 449 450 /* 451 * If the summation of RX, NPTX and PTX fifo sizes is still 452 * bigger than the total_fifo_size, then we have a problem. 453 * 454 * We won't be able to allocate as many endpoints. Right now, 455 * we're just printing an error message, but ideally this FIFO 456 * allocation algorithm would be improved in the future. 457 * 458 * FIXME improve this FIFO allocation algorithm. 459 */ 460 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz))) 461 dev_err(hsotg->dev, "invalid fifo sizes\n"); 462 } 463 464 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) 465 { 466 struct dwc2_core_params *params = &hsotg->params; 467 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz; 468 469 if (!params->enable_dynamic_fifo) 470 return; 471 472 dwc2_calculate_dynamic_fifo(hsotg); 473 474 /* Rx FIFO */ 475 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); 476 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); 477 grxfsiz &= ~GRXFSIZ_DEPTH_MASK; 478 grxfsiz |= params->host_rx_fifo_size << 479 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; 480 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); 481 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", 482 dwc2_readl(hsotg->regs + GRXFSIZ)); 483 484 /* Non-periodic Tx FIFO */ 485 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", 486 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 487 nptxfsiz = params->host_nperio_tx_fifo_size << 488 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 489 nptxfsiz |= params->host_rx_fifo_size << 490 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 491 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); 492 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", 493 dwc2_readl(hsotg->regs + GNPTXFSIZ)); 494 495 /* Periodic Tx FIFO */ 496 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", 497 dwc2_readl(hsotg->regs + HPTXFSIZ)); 498 hptxfsiz = params->host_perio_tx_fifo_size << 499 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; 500 hptxfsiz |= (params->host_rx_fifo_size + 501 params->host_nperio_tx_fifo_size) << 502 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; 503 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); 504 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", 505 dwc2_readl(hsotg->regs + HPTXFSIZ)); 506 507 if (hsotg->params.en_multiple_tx_fifo && 508 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { 509 /* 510 * This feature was implemented in 2.91a version 511 * Global DFIFOCFG calculation for Host mode - 512 * include RxFIFO, NPTXFIFO and HPTXFIFO 513 */ 514 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); 515 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; 516 dfifocfg |= (params->host_rx_fifo_size + 517 params->host_nperio_tx_fifo_size + 518 params->host_perio_tx_fifo_size) << 519 GDFIFOCFG_EPINFOBASE_SHIFT & 520 GDFIFOCFG_EPINFOBASE_MASK; 521 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); 522 } 523 } 524 525 /** 526 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for 527 * the HFIR register according to PHY type and speed 528 * 529 * @hsotg: Programming view of DWC_otg controller 530 * 531 * NOTE: The caller can modify the value of the HFIR register only after the 532 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort) 533 * has been set 534 */ 535 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) 536 { 537 u32 usbcfg; 538 u32 hprt0; 539 int clock = 60; /* default value */ 540 541 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 542 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 543 544 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && 545 !(usbcfg & GUSBCFG_PHYIF16)) 546 clock = 60; 547 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type == 548 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI) 549 clock = 48; 550 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 551 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 552 clock = 30; 553 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 554 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) 555 clock = 60; 556 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) && 557 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16)) 558 clock = 48; 559 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) && 560 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI) 561 clock = 48; 562 if ((usbcfg & GUSBCFG_PHYSEL) && 563 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) 564 clock = 48; 565 566 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED) 567 /* High speed case */ 568 return 125 * clock - 1; 569 570 /* FS/LS case */ 571 return 1000 * clock - 1; 572 } 573 574 /** 575 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination 576 * buffer 577 * 578 * @core_if: Programming view of DWC_otg controller 579 * @dest: Destination buffer for the packet 580 * @bytes: Number of bytes to copy to the destination 581 */ 582 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) 583 { 584 u32 __iomem *fifo = hsotg->regs + HCFIFO(0); 585 u32 *data_buf = (u32 *)dest; 586 int word_count = (bytes + 3) / 4; 587 int i; 588 589 /* 590 * Todo: Account for the case where dest is not dword aligned. This 591 * requires reading data from the FIFO into a u32 temp buffer, then 592 * moving it into the data buffer. 593 */ 594 595 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); 596 597 for (i = 0; i < word_count; i++, data_buf++) 598 *data_buf = dwc2_readl(fifo); 599 } 600 601 /** 602 * dwc2_dump_channel_info() - Prints the state of a host channel 603 * 604 * @hsotg: Programming view of DWC_otg controller 605 * @chan: Pointer to the channel to dump 606 * 607 * Must be called with interrupt disabled and spinlock held 608 * 609 * NOTE: This function will be removed once the peripheral controller code 610 * is integrated and the driver is stable 611 */ 612 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 613 struct dwc2_host_chan *chan) 614 { 615 #ifdef VERBOSE_DEBUG 616 int num_channels = hsotg->params.host_channels; 617 struct dwc2_qh *qh; 618 u32 hcchar; 619 u32 hcsplt; 620 u32 hctsiz; 621 u32 hc_dma; 622 int i; 623 624 if (!chan) 625 return; 626 627 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 628 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 629 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 630 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 631 632 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 633 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 634 hcchar, hcsplt); 635 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 636 hctsiz, hc_dma); 637 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 638 chan->dev_addr, chan->ep_num, chan->ep_is_in); 639 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 640 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 641 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 642 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 643 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 644 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 645 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 646 (unsigned long)chan->xfer_dma); 647 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 648 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 649 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 650 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 651 qh_list_entry) 652 dev_dbg(hsotg->dev, " %p\n", qh); 653 dev_dbg(hsotg->dev, " NP waiting sched:\n"); 654 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting, 655 qh_list_entry) 656 dev_dbg(hsotg->dev, " %p\n", qh); 657 dev_dbg(hsotg->dev, " NP active sched:\n"); 658 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 659 qh_list_entry) 660 dev_dbg(hsotg->dev, " %p\n", qh); 661 dev_dbg(hsotg->dev, " Channels:\n"); 662 for (i = 0; i < num_channels; i++) { 663 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 664 665 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 666 } 667 #endif /* VERBOSE_DEBUG */ 668 } 669 670 static int _dwc2_hcd_start(struct usb_hcd *hcd); 671 672 static void dwc2_host_start(struct dwc2_hsotg *hsotg) 673 { 674 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 675 676 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 677 _dwc2_hcd_start(hcd); 678 } 679 680 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 681 { 682 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 683 684 hcd->self.is_b_host = 0; 685 } 686 687 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, 688 int *hub_addr, int *hub_port) 689 { 690 struct urb *urb = context; 691 692 if (urb->dev->tt) 693 *hub_addr = urb->dev->tt->hub->devnum; 694 else 695 *hub_addr = 0; 696 *hub_port = urb->dev->ttport; 697 } 698 699 /* 700 * ========================================================================= 701 * Low Level Host Channel Access Functions 702 * ========================================================================= 703 */ 704 705 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, 706 struct dwc2_host_chan *chan) 707 { 708 u32 hcintmsk = HCINTMSK_CHHLTD; 709 710 switch (chan->ep_type) { 711 case USB_ENDPOINT_XFER_CONTROL: 712 case USB_ENDPOINT_XFER_BULK: 713 dev_vdbg(hsotg->dev, "control/bulk\n"); 714 hcintmsk |= HCINTMSK_XFERCOMPL; 715 hcintmsk |= HCINTMSK_STALL; 716 hcintmsk |= HCINTMSK_XACTERR; 717 hcintmsk |= HCINTMSK_DATATGLERR; 718 if (chan->ep_is_in) { 719 hcintmsk |= HCINTMSK_BBLERR; 720 } else { 721 hcintmsk |= HCINTMSK_NAK; 722 hcintmsk |= HCINTMSK_NYET; 723 if (chan->do_ping) 724 hcintmsk |= HCINTMSK_ACK; 725 } 726 727 if (chan->do_split) { 728 hcintmsk |= HCINTMSK_NAK; 729 if (chan->complete_split) 730 hcintmsk |= HCINTMSK_NYET; 731 else 732 hcintmsk |= HCINTMSK_ACK; 733 } 734 735 if (chan->error_state) 736 hcintmsk |= HCINTMSK_ACK; 737 break; 738 739 case USB_ENDPOINT_XFER_INT: 740 if (dbg_perio()) 741 dev_vdbg(hsotg->dev, "intr\n"); 742 hcintmsk |= HCINTMSK_XFERCOMPL; 743 hcintmsk |= HCINTMSK_NAK; 744 hcintmsk |= HCINTMSK_STALL; 745 hcintmsk |= HCINTMSK_XACTERR; 746 hcintmsk |= HCINTMSK_DATATGLERR; 747 hcintmsk |= HCINTMSK_FRMOVRUN; 748 749 if (chan->ep_is_in) 750 hcintmsk |= HCINTMSK_BBLERR; 751 if (chan->error_state) 752 hcintmsk |= HCINTMSK_ACK; 753 if (chan->do_split) { 754 if (chan->complete_split) 755 hcintmsk |= HCINTMSK_NYET; 756 else 757 hcintmsk |= HCINTMSK_ACK; 758 } 759 break; 760 761 case USB_ENDPOINT_XFER_ISOC: 762 if (dbg_perio()) 763 dev_vdbg(hsotg->dev, "isoc\n"); 764 hcintmsk |= HCINTMSK_XFERCOMPL; 765 hcintmsk |= HCINTMSK_FRMOVRUN; 766 hcintmsk |= HCINTMSK_ACK; 767 768 if (chan->ep_is_in) { 769 hcintmsk |= HCINTMSK_XACTERR; 770 hcintmsk |= HCINTMSK_BBLERR; 771 } 772 break; 773 default: 774 dev_err(hsotg->dev, "## Unknown EP type ##\n"); 775 break; 776 } 777 778 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 779 if (dbg_hc(chan)) 780 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 781 } 782 783 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, 784 struct dwc2_host_chan *chan) 785 { 786 u32 hcintmsk = HCINTMSK_CHHLTD; 787 788 /* 789 * For Descriptor DMA mode core halts the channel on AHB error. 790 * Interrupt is not required. 791 */ 792 if (!hsotg->params.dma_desc_enable) { 793 if (dbg_hc(chan)) 794 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 795 hcintmsk |= HCINTMSK_AHBERR; 796 } else { 797 if (dbg_hc(chan)) 798 dev_vdbg(hsotg->dev, "desc DMA enabled\n"); 799 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 800 hcintmsk |= HCINTMSK_XFERCOMPL; 801 } 802 803 if (chan->error_state && !chan->do_split && 804 chan->ep_type != USB_ENDPOINT_XFER_ISOC) { 805 if (dbg_hc(chan)) 806 dev_vdbg(hsotg->dev, "setting ACK\n"); 807 hcintmsk |= HCINTMSK_ACK; 808 if (chan->ep_is_in) { 809 hcintmsk |= HCINTMSK_DATATGLERR; 810 if (chan->ep_type != USB_ENDPOINT_XFER_INT) 811 hcintmsk |= HCINTMSK_NAK; 812 } 813 } 814 815 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 816 if (dbg_hc(chan)) 817 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); 818 } 819 820 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, 821 struct dwc2_host_chan *chan) 822 { 823 u32 intmsk; 824 825 if (hsotg->params.host_dma) { 826 if (dbg_hc(chan)) 827 dev_vdbg(hsotg->dev, "DMA enabled\n"); 828 dwc2_hc_enable_dma_ints(hsotg, chan); 829 } else { 830 if (dbg_hc(chan)) 831 dev_vdbg(hsotg->dev, "DMA disabled\n"); 832 dwc2_hc_enable_slave_ints(hsotg, chan); 833 } 834 835 /* Enable the top level host channel interrupt */ 836 intmsk = dwc2_readl(hsotg->regs + HAINTMSK); 837 intmsk |= 1 << chan->hc_num; 838 dwc2_writel(intmsk, hsotg->regs + HAINTMSK); 839 if (dbg_hc(chan)) 840 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); 841 842 /* Make sure host channel interrupts are enabled */ 843 intmsk = dwc2_readl(hsotg->regs + GINTMSK); 844 intmsk |= GINTSTS_HCHINT; 845 dwc2_writel(intmsk, hsotg->regs + GINTMSK); 846 if (dbg_hc(chan)) 847 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); 848 } 849 850 /** 851 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from 852 * a specific endpoint 853 * 854 * @hsotg: Programming view of DWC_otg controller 855 * @chan: Information needed to initialize the host channel 856 * 857 * The HCCHARn register is set up with the characteristics specified in chan. 858 * Host channel interrupts that may need to be serviced while this transfer is 859 * in progress are enabled. 860 */ 861 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 862 { 863 u8 hc_num = chan->hc_num; 864 u32 hcintmsk; 865 u32 hcchar; 866 u32 hcsplt = 0; 867 868 if (dbg_hc(chan)) 869 dev_vdbg(hsotg->dev, "%s()\n", __func__); 870 871 /* Clear old interrupt conditions for this host channel */ 872 hcintmsk = 0xffffffff; 873 hcintmsk &= ~HCINTMSK_RESERVED14_31; 874 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); 875 876 /* Enable channel interrupts required for this transfer */ 877 dwc2_hc_enable_ints(hsotg, chan); 878 879 /* 880 * Program the HCCHARn register with the endpoint characteristics for 881 * the current transfer 882 */ 883 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK; 884 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK; 885 if (chan->ep_is_in) 886 hcchar |= HCCHAR_EPDIR; 887 if (chan->speed == USB_SPEED_LOW) 888 hcchar |= HCCHAR_LSPDDEV; 889 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; 890 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; 891 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); 892 if (dbg_hc(chan)) { 893 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", 894 hc_num, hcchar); 895 896 dev_vdbg(hsotg->dev, "%s: Channel %d\n", 897 __func__, hc_num); 898 dev_vdbg(hsotg->dev, " Dev Addr: %d\n", 899 chan->dev_addr); 900 dev_vdbg(hsotg->dev, " Ep Num: %d\n", 901 chan->ep_num); 902 dev_vdbg(hsotg->dev, " Is In: %d\n", 903 chan->ep_is_in); 904 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n", 905 chan->speed == USB_SPEED_LOW); 906 dev_vdbg(hsotg->dev, " Ep Type: %d\n", 907 chan->ep_type); 908 dev_vdbg(hsotg->dev, " Max Pkt: %d\n", 909 chan->max_packet); 910 } 911 912 /* Program the HCSPLT register for SPLITs */ 913 if (chan->do_split) { 914 if (dbg_hc(chan)) 915 dev_vdbg(hsotg->dev, 916 "Programming HC %d with split --> %s\n", 917 hc_num, 918 chan->complete_split ? "CSPLIT" : "SSPLIT"); 919 if (chan->complete_split) 920 hcsplt |= HCSPLT_COMPSPLT; 921 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT & 922 HCSPLT_XACTPOS_MASK; 923 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT & 924 HCSPLT_HUBADDR_MASK; 925 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT & 926 HCSPLT_PRTADDR_MASK; 927 if (dbg_hc(chan)) { 928 dev_vdbg(hsotg->dev, " comp split %d\n", 929 chan->complete_split); 930 dev_vdbg(hsotg->dev, " xact pos %d\n", 931 chan->xact_pos); 932 dev_vdbg(hsotg->dev, " hub addr %d\n", 933 chan->hub_addr); 934 dev_vdbg(hsotg->dev, " hub port %d\n", 935 chan->hub_port); 936 dev_vdbg(hsotg->dev, " is_in %d\n", 937 chan->ep_is_in); 938 dev_vdbg(hsotg->dev, " Max Pkt %d\n", 939 chan->max_packet); 940 dev_vdbg(hsotg->dev, " xferlen %d\n", 941 chan->xfer_len); 942 } 943 } 944 945 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); 946 } 947 948 /** 949 * dwc2_hc_halt() - Attempts to halt a host channel 950 * 951 * @hsotg: Controller register interface 952 * @chan: Host channel to halt 953 * @halt_status: Reason for halting the channel 954 * 955 * This function should only be called in Slave mode or to abort a transfer in 956 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the 957 * controller halts the channel when the transfer is complete or a condition 958 * occurs that requires application intervention. 959 * 960 * In slave mode, checks for a free request queue entry, then sets the Channel 961 * Enable and Channel Disable bits of the Host Channel Characteristics 962 * register of the specified channel to intiate the halt. If there is no free 963 * request queue entry, sets only the Channel Disable bit of the HCCHARn 964 * register to flush requests for this channel. In the latter case, sets a 965 * flag to indicate that the host channel needs to be halted when a request 966 * queue slot is open. 967 * 968 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the 969 * HCCHARn register. The controller ensures there is space in the request 970 * queue before submitting the halt request. 971 * 972 * Some time may elapse before the core flushes any posted requests for this 973 * host channel and halts. The Channel Halted interrupt handler completes the 974 * deactivation of the host channel. 975 */ 976 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, 977 enum dwc2_halt_status halt_status) 978 { 979 u32 nptxsts, hptxsts, hcchar; 980 981 if (dbg_hc(chan)) 982 dev_vdbg(hsotg->dev, "%s()\n", __func__); 983 984 /* 985 * In buffer DMA or external DMA mode channel can't be halted 986 * for non-split periodic channels. At the end of the next 987 * uframe/frame (in the worst case), the core generates a channel 988 * halted and disables the channel automatically. 989 */ 990 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) || 991 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) { 992 if (!chan->do_split && 993 (chan->ep_type == USB_ENDPOINT_XFER_ISOC || 994 chan->ep_type == USB_ENDPOINT_XFER_INT)) { 995 dev_err(hsotg->dev, "%s() Channel can't be halted\n", 996 __func__); 997 return; 998 } 999 } 1000 1001 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS) 1002 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status); 1003 1004 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE || 1005 halt_status == DWC2_HC_XFER_AHB_ERR) { 1006 /* 1007 * Disable all channel interrupts except Ch Halted. The QTD 1008 * and QH state associated with this transfer has been cleared 1009 * (in the case of URB_DEQUEUE), so the channel needs to be 1010 * shut down carefully to prevent crashes. 1011 */ 1012 u32 hcintmsk = HCINTMSK_CHHLTD; 1013 1014 dev_vdbg(hsotg->dev, "dequeue/error\n"); 1015 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); 1016 1017 /* 1018 * Make sure no other interrupts besides halt are currently 1019 * pending. Handling another interrupt could cause a crash due 1020 * to the QTD and QH state. 1021 */ 1022 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1023 1024 /* 1025 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR 1026 * even if the channel was already halted for some other 1027 * reason 1028 */ 1029 chan->halt_status = halt_status; 1030 1031 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1032 if (!(hcchar & HCCHAR_CHENA)) { 1033 /* 1034 * The channel is either already halted or it hasn't 1035 * started yet. In DMA mode, the transfer may halt if 1036 * it finishes normally or a condition occurs that 1037 * requires driver intervention. Don't want to halt 1038 * the channel again. In either Slave or DMA mode, 1039 * it's possible that the transfer has been assigned 1040 * to a channel, but not started yet when an URB is 1041 * dequeued. Don't want to halt a channel that hasn't 1042 * started yet. 1043 */ 1044 return; 1045 } 1046 } 1047 if (chan->halt_pending) { 1048 /* 1049 * A halt has already been issued for this channel. This might 1050 * happen when a transfer is aborted by a higher level in 1051 * the stack. 1052 */ 1053 dev_vdbg(hsotg->dev, 1054 "*** %s: Channel %d, chan->halt_pending already set ***\n", 1055 __func__, chan->hc_num); 1056 return; 1057 } 1058 1059 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1060 1061 /* No need to set the bit in DDMA for disabling the channel */ 1062 /* TODO check it everywhere channel is disabled */ 1063 if (!hsotg->params.dma_desc_enable) { 1064 if (dbg_hc(chan)) 1065 dev_vdbg(hsotg->dev, "desc DMA disabled\n"); 1066 hcchar |= HCCHAR_CHENA; 1067 } else { 1068 if (dbg_hc(chan)) 1069 dev_dbg(hsotg->dev, "desc DMA enabled\n"); 1070 } 1071 hcchar |= HCCHAR_CHDIS; 1072 1073 if (!hsotg->params.host_dma) { 1074 if (dbg_hc(chan)) 1075 dev_vdbg(hsotg->dev, "DMA not enabled\n"); 1076 hcchar |= HCCHAR_CHENA; 1077 1078 /* Check for space in the request queue to issue the halt */ 1079 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || 1080 chan->ep_type == USB_ENDPOINT_XFER_BULK) { 1081 dev_vdbg(hsotg->dev, "control/bulk\n"); 1082 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); 1083 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { 1084 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1085 hcchar &= ~HCCHAR_CHENA; 1086 } 1087 } else { 1088 if (dbg_perio()) 1089 dev_vdbg(hsotg->dev, "isoc/intr\n"); 1090 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); 1091 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || 1092 hsotg->queuing_high_bandwidth) { 1093 if (dbg_perio()) 1094 dev_vdbg(hsotg->dev, "Disabling channel\n"); 1095 hcchar &= ~HCCHAR_CHENA; 1096 } 1097 } 1098 } else { 1099 if (dbg_hc(chan)) 1100 dev_vdbg(hsotg->dev, "DMA enabled\n"); 1101 } 1102 1103 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1104 chan->halt_status = halt_status; 1105 1106 if (hcchar & HCCHAR_CHENA) { 1107 if (dbg_hc(chan)) 1108 dev_vdbg(hsotg->dev, "Channel enabled\n"); 1109 chan->halt_pending = 1; 1110 chan->halt_on_queue = 0; 1111 } else { 1112 if (dbg_hc(chan)) 1113 dev_vdbg(hsotg->dev, "Channel disabled\n"); 1114 chan->halt_on_queue = 1; 1115 } 1116 1117 if (dbg_hc(chan)) { 1118 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1119 chan->hc_num); 1120 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n", 1121 hcchar); 1122 dev_vdbg(hsotg->dev, " halt_pending: %d\n", 1123 chan->halt_pending); 1124 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n", 1125 chan->halt_on_queue); 1126 dev_vdbg(hsotg->dev, " halt_status: %d\n", 1127 chan->halt_status); 1128 } 1129 } 1130 1131 /** 1132 * dwc2_hc_cleanup() - Clears the transfer state for a host channel 1133 * 1134 * @hsotg: Programming view of DWC_otg controller 1135 * @chan: Identifies the host channel to clean up 1136 * 1137 * This function is normally called after a transfer is done and the host 1138 * channel is being released 1139 */ 1140 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) 1141 { 1142 u32 hcintmsk; 1143 1144 chan->xfer_started = 0; 1145 1146 list_del_init(&chan->split_order_list_entry); 1147 1148 /* 1149 * Clear channel interrupt enables and any unhandled channel interrupt 1150 * conditions 1151 */ 1152 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); 1153 hcintmsk = 0xffffffff; 1154 hcintmsk &= ~HCINTMSK_RESERVED14_31; 1155 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); 1156 } 1157 1158 /** 1159 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in 1160 * which frame a periodic transfer should occur 1161 * 1162 * @hsotg: Programming view of DWC_otg controller 1163 * @chan: Identifies the host channel to set up and its properties 1164 * @hcchar: Current value of the HCCHAR register for the specified host channel 1165 * 1166 * This function has no effect on non-periodic transfers 1167 */ 1168 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, 1169 struct dwc2_host_chan *chan, u32 *hcchar) 1170 { 1171 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1172 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1173 int host_speed; 1174 int xfer_ns; 1175 int xfer_us; 1176 int bytes_in_fifo; 1177 u16 fifo_space; 1178 u16 frame_number; 1179 u16 wire_frame; 1180 1181 /* 1182 * Try to figure out if we're an even or odd frame. If we set 1183 * even and the current frame number is even the the transfer 1184 * will happen immediately. Similar if both are odd. If one is 1185 * even and the other is odd then the transfer will happen when 1186 * the frame number ticks. 1187 * 1188 * There's a bit of a balancing act to get this right. 1189 * Sometimes we may want to send data in the current frame (AK 1190 * right away). We might want to do this if the frame number 1191 * _just_ ticked, but we might also want to do this in order 1192 * to continue a split transaction that happened late in a 1193 * microframe (so we didn't know to queue the next transfer 1194 * until the frame number had ticked). The problem is that we 1195 * need a lot of knowledge to know if there's actually still 1196 * time to send things or if it would be better to wait until 1197 * the next frame. 1198 * 1199 * We can look at how much time is left in the current frame 1200 * and make a guess about whether we'll have time to transfer. 1201 * We'll do that. 1202 */ 1203 1204 /* Get speed host is running at */ 1205 host_speed = (chan->speed != USB_SPEED_HIGH && 1206 !chan->do_split) ? chan->speed : USB_SPEED_HIGH; 1207 1208 /* See how many bytes are in the periodic FIFO right now */ 1209 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & 1210 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; 1211 bytes_in_fifo = sizeof(u32) * 1212 (hsotg->params.host_perio_tx_fifo_size - 1213 fifo_space); 1214 1215 /* 1216 * Roughly estimate bus time for everything in the periodic 1217 * queue + our new transfer. This is "rough" because we're 1218 * using a function that makes takes into account IN/OUT 1219 * and INT/ISO and we're just slamming in one value for all 1220 * transfers. This should be an over-estimate and that should 1221 * be OK, but we can probably tighten it. 1222 */ 1223 xfer_ns = usb_calc_bus_time(host_speed, false, false, 1224 chan->xfer_len + bytes_in_fifo); 1225 xfer_us = NS_TO_US(xfer_ns); 1226 1227 /* See what frame number we'll be at by the time we finish */ 1228 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us); 1229 1230 /* This is when we were scheduled to be on the wire */ 1231 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1); 1232 1233 /* 1234 * If we'd finish _after_ the frame we're scheduled in then 1235 * it's hopeless. Just schedule right away and hope for the 1236 * best. Note that it _might_ be wise to call back into the 1237 * scheduler to pick a better frame, but this is better than 1238 * nothing. 1239 */ 1240 if (dwc2_frame_num_gt(frame_number, wire_frame)) { 1241 dwc2_sch_vdbg(hsotg, 1242 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n", 1243 chan->qh, wire_frame, frame_number, 1244 dwc2_frame_num_dec(frame_number, 1245 wire_frame)); 1246 wire_frame = frame_number; 1247 1248 /* 1249 * We picked a different frame number; communicate this 1250 * back to the scheduler so it doesn't try to schedule 1251 * another in the same frame. 1252 * 1253 * Remember that next_active_frame is 1 before the wire 1254 * frame. 1255 */ 1256 chan->qh->next_active_frame = 1257 dwc2_frame_num_dec(frame_number, 1); 1258 } 1259 1260 if (wire_frame & 1) 1261 *hcchar |= HCCHAR_ODDFRM; 1262 else 1263 *hcchar &= ~HCCHAR_ODDFRM; 1264 } 1265 } 1266 1267 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan) 1268 { 1269 /* Set up the initial PID for the transfer */ 1270 if (chan->speed == USB_SPEED_HIGH) { 1271 if (chan->ep_is_in) { 1272 if (chan->multi_count == 1) 1273 chan->data_pid_start = DWC2_HC_PID_DATA0; 1274 else if (chan->multi_count == 2) 1275 chan->data_pid_start = DWC2_HC_PID_DATA1; 1276 else 1277 chan->data_pid_start = DWC2_HC_PID_DATA2; 1278 } else { 1279 if (chan->multi_count == 1) 1280 chan->data_pid_start = DWC2_HC_PID_DATA0; 1281 else 1282 chan->data_pid_start = DWC2_HC_PID_MDATA; 1283 } 1284 } else { 1285 chan->data_pid_start = DWC2_HC_PID_DATA0; 1286 } 1287 } 1288 1289 /** 1290 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with 1291 * the Host Channel 1292 * 1293 * @hsotg: Programming view of DWC_otg controller 1294 * @chan: Information needed to initialize the host channel 1295 * 1296 * This function should only be called in Slave mode. For a channel associated 1297 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel 1298 * associated with a periodic EP, the periodic Tx FIFO is written. 1299 * 1300 * Upon return the xfer_buf and xfer_count fields in chan are incremented by 1301 * the number of bytes written to the Tx FIFO. 1302 */ 1303 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, 1304 struct dwc2_host_chan *chan) 1305 { 1306 u32 i; 1307 u32 remaining_count; 1308 u32 byte_count; 1309 u32 dword_count; 1310 u32 __iomem *data_fifo; 1311 u32 *data_buf = (u32 *)chan->xfer_buf; 1312 1313 if (dbg_hc(chan)) 1314 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1315 1316 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num)); 1317 1318 remaining_count = chan->xfer_len - chan->xfer_count; 1319 if (remaining_count > chan->max_packet) 1320 byte_count = chan->max_packet; 1321 else 1322 byte_count = remaining_count; 1323 1324 dword_count = (byte_count + 3) / 4; 1325 1326 if (((unsigned long)data_buf & 0x3) == 0) { 1327 /* xfer_buf is DWORD aligned */ 1328 for (i = 0; i < dword_count; i++, data_buf++) 1329 dwc2_writel(*data_buf, data_fifo); 1330 } else { 1331 /* xfer_buf is not DWORD aligned */ 1332 for (i = 0; i < dword_count; i++, data_buf++) { 1333 u32 data = data_buf[0] | data_buf[1] << 8 | 1334 data_buf[2] << 16 | data_buf[3] << 24; 1335 dwc2_writel(data, data_fifo); 1336 } 1337 } 1338 1339 chan->xfer_count += byte_count; 1340 chan->xfer_buf += byte_count; 1341 } 1342 1343 /** 1344 * dwc2_hc_do_ping() - Starts a PING transfer 1345 * 1346 * @hsotg: Programming view of DWC_otg controller 1347 * @chan: Information needed to initialize the host channel 1348 * 1349 * This function should only be called in Slave mode. The Do Ping bit is set in 1350 * the HCTSIZ register, then the channel is enabled. 1351 */ 1352 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, 1353 struct dwc2_host_chan *chan) 1354 { 1355 u32 hcchar; 1356 u32 hctsiz; 1357 1358 if (dbg_hc(chan)) 1359 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1360 chan->hc_num); 1361 1362 hctsiz = TSIZ_DOPNG; 1363 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; 1364 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1365 1366 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1367 hcchar |= HCCHAR_CHENA; 1368 hcchar &= ~HCCHAR_CHDIS; 1369 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1370 } 1371 1372 /** 1373 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host 1374 * channel and starts the transfer 1375 * 1376 * @hsotg: Programming view of DWC_otg controller 1377 * @chan: Information needed to initialize the host channel. The xfer_len value 1378 * may be reduced to accommodate the max widths of the XferSize and 1379 * PktCnt fields in the HCTSIZn register. The multi_count value may be 1380 * changed to reflect the final xfer_len value. 1381 * 1382 * This function may be called in either Slave mode or DMA mode. In Slave mode, 1383 * the caller must ensure that there is sufficient space in the request queue 1384 * and Tx Data FIFO. 1385 * 1386 * For an OUT transfer in Slave mode, it loads a data packet into the 1387 * appropriate FIFO. If necessary, additional data packets are loaded in the 1388 * Host ISR. 1389 * 1390 * For an IN transfer in Slave mode, a data packet is requested. The data 1391 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, 1392 * additional data packets are requested in the Host ISR. 1393 * 1394 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ 1395 * register along with a packet count of 1 and the channel is enabled. This 1396 * causes a single PING transaction to occur. Other fields in HCTSIZ are 1397 * simply set to 0 since no data transfer occurs in this case. 1398 * 1399 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with 1400 * all the information required to perform the subsequent data transfer. In 1401 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the 1402 * controller performs the entire PING protocol, then starts the data 1403 * transfer. 1404 */ 1405 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, 1406 struct dwc2_host_chan *chan) 1407 { 1408 u32 max_hc_xfer_size = hsotg->params.max_transfer_size; 1409 u16 max_hc_pkt_count = hsotg->params.max_packet_count; 1410 u32 hcchar; 1411 u32 hctsiz = 0; 1412 u16 num_packets; 1413 u32 ec_mc; 1414 1415 if (dbg_hc(chan)) 1416 dev_vdbg(hsotg->dev, "%s()\n", __func__); 1417 1418 if (chan->do_ping) { 1419 if (!hsotg->params.host_dma) { 1420 if (dbg_hc(chan)) 1421 dev_vdbg(hsotg->dev, "ping, no DMA\n"); 1422 dwc2_hc_do_ping(hsotg, chan); 1423 chan->xfer_started = 1; 1424 return; 1425 } 1426 1427 if (dbg_hc(chan)) 1428 dev_vdbg(hsotg->dev, "ping, DMA\n"); 1429 1430 hctsiz |= TSIZ_DOPNG; 1431 } 1432 1433 if (chan->do_split) { 1434 if (dbg_hc(chan)) 1435 dev_vdbg(hsotg->dev, "split\n"); 1436 num_packets = 1; 1437 1438 if (chan->complete_split && !chan->ep_is_in) 1439 /* 1440 * For CSPLIT OUT Transfer, set the size to 0 so the 1441 * core doesn't expect any data written to the FIFO 1442 */ 1443 chan->xfer_len = 0; 1444 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet) 1445 chan->xfer_len = chan->max_packet; 1446 else if (!chan->ep_is_in && chan->xfer_len > 188) 1447 chan->xfer_len = 188; 1448 1449 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1450 TSIZ_XFERSIZE_MASK; 1451 1452 /* For split set ec_mc for immediate retries */ 1453 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1454 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1455 ec_mc = 3; 1456 else 1457 ec_mc = 1; 1458 } else { 1459 if (dbg_hc(chan)) 1460 dev_vdbg(hsotg->dev, "no split\n"); 1461 /* 1462 * Ensure that the transfer length and packet count will fit 1463 * in the widths allocated for them in the HCTSIZn register 1464 */ 1465 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1466 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1467 /* 1468 * Make sure the transfer size is no larger than one 1469 * (micro)frame's worth of data. (A check was done 1470 * when the periodic transfer was accepted to ensure 1471 * that a (micro)frame's worth of data can be 1472 * programmed into a channel.) 1473 */ 1474 u32 max_periodic_len = 1475 chan->multi_count * chan->max_packet; 1476 1477 if (chan->xfer_len > max_periodic_len) 1478 chan->xfer_len = max_periodic_len; 1479 } else if (chan->xfer_len > max_hc_xfer_size) { 1480 /* 1481 * Make sure that xfer_len is a multiple of max packet 1482 * size 1483 */ 1484 chan->xfer_len = 1485 max_hc_xfer_size - chan->max_packet + 1; 1486 } 1487 1488 if (chan->xfer_len > 0) { 1489 num_packets = (chan->xfer_len + chan->max_packet - 1) / 1490 chan->max_packet; 1491 if (num_packets > max_hc_pkt_count) { 1492 num_packets = max_hc_pkt_count; 1493 chan->xfer_len = num_packets * chan->max_packet; 1494 } 1495 } else { 1496 /* Need 1 packet for transfer length of 0 */ 1497 num_packets = 1; 1498 } 1499 1500 if (chan->ep_is_in) 1501 /* 1502 * Always program an integral # of max packets for IN 1503 * transfers 1504 */ 1505 chan->xfer_len = num_packets * chan->max_packet; 1506 1507 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1508 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1509 /* 1510 * Make sure that the multi_count field matches the 1511 * actual transfer length 1512 */ 1513 chan->multi_count = num_packets; 1514 1515 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1516 dwc2_set_pid_isoc(chan); 1517 1518 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT & 1519 TSIZ_XFERSIZE_MASK; 1520 1521 /* The ec_mc gets the multi_count for non-split */ 1522 ec_mc = chan->multi_count; 1523 } 1524 1525 chan->start_pkt_count = num_packets; 1526 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; 1527 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1528 TSIZ_SC_MC_PID_MASK; 1529 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1530 if (dbg_hc(chan)) { 1531 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", 1532 hctsiz, chan->hc_num); 1533 1534 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1535 chan->hc_num); 1536 dev_vdbg(hsotg->dev, " Xfer Size: %d\n", 1537 (hctsiz & TSIZ_XFERSIZE_MASK) >> 1538 TSIZ_XFERSIZE_SHIFT); 1539 dev_vdbg(hsotg->dev, " Num Pkts: %d\n", 1540 (hctsiz & TSIZ_PKTCNT_MASK) >> 1541 TSIZ_PKTCNT_SHIFT); 1542 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1543 (hctsiz & TSIZ_SC_MC_PID_MASK) >> 1544 TSIZ_SC_MC_PID_SHIFT); 1545 } 1546 1547 if (hsotg->params.host_dma) { 1548 dwc2_writel((u32)chan->xfer_dma, 1549 hsotg->regs + HCDMA(chan->hc_num)); 1550 if (dbg_hc(chan)) 1551 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", 1552 (unsigned long)chan->xfer_dma, chan->hc_num); 1553 } 1554 1555 /* Start the split */ 1556 if (chan->do_split) { 1557 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 1558 1559 hcsplt |= HCSPLT_SPLTENA; 1560 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); 1561 } 1562 1563 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1564 hcchar &= ~HCCHAR_MULTICNT_MASK; 1565 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; 1566 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1567 1568 if (hcchar & HCCHAR_CHDIS) 1569 dev_warn(hsotg->dev, 1570 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1571 __func__, chan->hc_num, hcchar); 1572 1573 /* Set host channel enable after all other setup is complete */ 1574 hcchar |= HCCHAR_CHENA; 1575 hcchar &= ~HCCHAR_CHDIS; 1576 1577 if (dbg_hc(chan)) 1578 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1579 (hcchar & HCCHAR_MULTICNT_MASK) >> 1580 HCCHAR_MULTICNT_SHIFT); 1581 1582 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1583 if (dbg_hc(chan)) 1584 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1585 chan->hc_num); 1586 1587 chan->xfer_started = 1; 1588 chan->requests++; 1589 1590 if (!hsotg->params.host_dma && 1591 !chan->ep_is_in && chan->xfer_len > 0) 1592 /* Load OUT packet into the appropriate Tx FIFO */ 1593 dwc2_hc_write_packet(hsotg, chan); 1594 } 1595 1596 /** 1597 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a 1598 * host channel and starts the transfer in Descriptor DMA mode 1599 * 1600 * @hsotg: Programming view of DWC_otg controller 1601 * @chan: Information needed to initialize the host channel 1602 * 1603 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. 1604 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field 1605 * with micro-frame bitmap. 1606 * 1607 * Initializes HCDMA register with descriptor list address and CTD value then 1608 * starts the transfer via enabling the channel. 1609 */ 1610 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, 1611 struct dwc2_host_chan *chan) 1612 { 1613 u32 hcchar; 1614 u32 hctsiz = 0; 1615 1616 if (chan->do_ping) 1617 hctsiz |= TSIZ_DOPNG; 1618 1619 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) 1620 dwc2_set_pid_isoc(chan); 1621 1622 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ 1623 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & 1624 TSIZ_SC_MC_PID_MASK; 1625 1626 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */ 1627 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK; 1628 1629 /* Non-zero only for high-speed interrupt endpoints */ 1630 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK; 1631 1632 if (dbg_hc(chan)) { 1633 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1634 chan->hc_num); 1635 dev_vdbg(hsotg->dev, " Start PID: %d\n", 1636 chan->data_pid_start); 1637 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); 1638 } 1639 1640 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); 1641 1642 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, 1643 chan->desc_list_sz, DMA_TO_DEVICE); 1644 1645 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); 1646 1647 if (dbg_hc(chan)) 1648 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", 1649 &chan->desc_list_addr, chan->hc_num); 1650 1651 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1652 hcchar &= ~HCCHAR_MULTICNT_MASK; 1653 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & 1654 HCCHAR_MULTICNT_MASK; 1655 1656 if (hcchar & HCCHAR_CHDIS) 1657 dev_warn(hsotg->dev, 1658 "%s: chdis set, channel %d, hcchar 0x%08x\n", 1659 __func__, chan->hc_num, hcchar); 1660 1661 /* Set host channel enable after all other setup is complete */ 1662 hcchar |= HCCHAR_CHENA; 1663 hcchar &= ~HCCHAR_CHDIS; 1664 1665 if (dbg_hc(chan)) 1666 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n", 1667 (hcchar & HCCHAR_MULTICNT_MASK) >> 1668 HCCHAR_MULTICNT_SHIFT); 1669 1670 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1671 if (dbg_hc(chan)) 1672 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, 1673 chan->hc_num); 1674 1675 chan->xfer_started = 1; 1676 chan->requests++; 1677 } 1678 1679 /** 1680 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by 1681 * a previous call to dwc2_hc_start_transfer() 1682 * 1683 * @hsotg: Programming view of DWC_otg controller 1684 * @chan: Information needed to initialize the host channel 1685 * 1686 * The caller must ensure there is sufficient space in the request queue and Tx 1687 * Data FIFO. This function should only be called in Slave mode. In DMA mode, 1688 * the controller acts autonomously to complete transfers programmed to a host 1689 * channel. 1690 * 1691 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO 1692 * if there is any data remaining to be queued. For an IN transfer, another 1693 * data packet is always requested. For the SETUP phase of a control transfer, 1694 * this function does nothing. 1695 * 1696 * Return: 1 if a new request is queued, 0 if no more requests are required 1697 * for this transfer 1698 */ 1699 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, 1700 struct dwc2_host_chan *chan) 1701 { 1702 if (dbg_hc(chan)) 1703 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, 1704 chan->hc_num); 1705 1706 if (chan->do_split) 1707 /* SPLITs always queue just once per channel */ 1708 return 0; 1709 1710 if (chan->data_pid_start == DWC2_HC_PID_SETUP) 1711 /* SETUPs are queued only once since they can't be NAK'd */ 1712 return 0; 1713 1714 if (chan->ep_is_in) { 1715 /* 1716 * Always queue another request for other IN transfers. If 1717 * back-to-back INs are issued and NAKs are received for both, 1718 * the driver may still be processing the first NAK when the 1719 * second NAK is received. When the interrupt handler clears 1720 * the NAK interrupt for the first NAK, the second NAK will 1721 * not be seen. So we can't depend on the NAK interrupt 1722 * handler to requeue a NAK'd request. Instead, IN requests 1723 * are issued each time this function is called. When the 1724 * transfer completes, the extra requests for the channel will 1725 * be flushed. 1726 */ 1727 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 1728 1729 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); 1730 hcchar |= HCCHAR_CHENA; 1731 hcchar &= ~HCCHAR_CHDIS; 1732 if (dbg_hc(chan)) 1733 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", 1734 hcchar); 1735 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); 1736 chan->requests++; 1737 return 1; 1738 } 1739 1740 /* OUT transfers */ 1741 1742 if (chan->xfer_count < chan->xfer_len) { 1743 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 1744 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1745 u32 hcchar = dwc2_readl(hsotg->regs + 1746 HCCHAR(chan->hc_num)); 1747 1748 dwc2_hc_set_even_odd_frame(hsotg, chan, 1749 &hcchar); 1750 } 1751 1752 /* Load OUT packet into the appropriate Tx FIFO */ 1753 dwc2_hc_write_packet(hsotg, chan); 1754 chan->requests++; 1755 return 1; 1756 } 1757 1758 return 0; 1759 } 1760 1761 /* 1762 * ========================================================================= 1763 * HCD 1764 * ========================================================================= 1765 */ 1766 1767 /* 1768 * Processes all the URBs in a single list of QHs. Completes them with 1769 * -ETIMEDOUT and frees the QTD. 1770 * 1771 * Must be called with interrupt disabled and spinlock held 1772 */ 1773 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 1774 struct list_head *qh_list) 1775 { 1776 struct dwc2_qh *qh, *qh_tmp; 1777 struct dwc2_qtd *qtd, *qtd_tmp; 1778 1779 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1780 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1781 qtd_list_entry) { 1782 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 1783 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1784 } 1785 } 1786 } 1787 1788 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 1789 struct list_head *qh_list) 1790 { 1791 struct dwc2_qtd *qtd, *qtd_tmp; 1792 struct dwc2_qh *qh, *qh_tmp; 1793 unsigned long flags; 1794 1795 if (!qh_list->next) 1796 /* The list hasn't been initialized yet */ 1797 return; 1798 1799 spin_lock_irqsave(&hsotg->lock, flags); 1800 1801 /* Ensure there are no QTDs or URBs left */ 1802 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 1803 1804 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 1805 dwc2_hcd_qh_unlink(hsotg, qh); 1806 1807 /* Free each QTD in the QH's QTD list */ 1808 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 1809 qtd_list_entry) 1810 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 1811 1812 if (qh->channel && qh->channel->qh == qh) 1813 qh->channel->qh = NULL; 1814 1815 spin_unlock_irqrestore(&hsotg->lock, flags); 1816 dwc2_hcd_qh_free(hsotg, qh); 1817 spin_lock_irqsave(&hsotg->lock, flags); 1818 } 1819 1820 spin_unlock_irqrestore(&hsotg->lock, flags); 1821 } 1822 1823 /* 1824 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 1825 * and periodic schedules. The QTD associated with each URB is removed from 1826 * the schedule and freed. This function may be called when a disconnect is 1827 * detected or when the HCD is being stopped. 1828 * 1829 * Must be called with interrupt disabled and spinlock held 1830 */ 1831 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 1832 { 1833 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 1834 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting); 1835 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 1836 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 1837 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 1838 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 1839 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 1840 } 1841 1842 /** 1843 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 1844 * 1845 * @hsotg: Pointer to struct dwc2_hsotg 1846 */ 1847 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 1848 { 1849 u32 hprt0; 1850 1851 if (hsotg->op_state == OTG_STATE_B_HOST) { 1852 /* 1853 * Reset the port. During a HNP mode switch the reset 1854 * needs to occur within 1ms and have a duration of at 1855 * least 50ms. 1856 */ 1857 hprt0 = dwc2_read_hprt0(hsotg); 1858 hprt0 |= HPRT0_RST; 1859 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1860 } 1861 1862 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 1863 msecs_to_jiffies(50)); 1864 } 1865 1866 /* Must be called with interrupt disabled and spinlock held */ 1867 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 1868 { 1869 int num_channels = hsotg->params.host_channels; 1870 struct dwc2_host_chan *channel; 1871 u32 hcchar; 1872 int i; 1873 1874 if (!hsotg->params.host_dma) { 1875 /* Flush out any channel requests in slave mode */ 1876 for (i = 0; i < num_channels; i++) { 1877 channel = hsotg->hc_ptr_array[i]; 1878 if (!list_empty(&channel->hc_list_entry)) 1879 continue; 1880 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1881 if (hcchar & HCCHAR_CHENA) { 1882 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 1883 hcchar |= HCCHAR_CHDIS; 1884 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1885 } 1886 } 1887 } 1888 1889 for (i = 0; i < num_channels; i++) { 1890 channel = hsotg->hc_ptr_array[i]; 1891 if (!list_empty(&channel->hc_list_entry)) 1892 continue; 1893 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 1894 if (hcchar & HCCHAR_CHENA) { 1895 /* Halt the channel */ 1896 hcchar |= HCCHAR_CHDIS; 1897 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 1898 } 1899 1900 dwc2_hc_cleanup(hsotg, channel); 1901 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 1902 /* 1903 * Added for Descriptor DMA to prevent channel double cleanup in 1904 * release_channel_ddma(), which is called from ep_disable when 1905 * device disconnects 1906 */ 1907 channel->qh = NULL; 1908 } 1909 /* All channels have been freed, mark them available */ 1910 if (hsotg->params.uframe_sched) { 1911 hsotg->available_host_channels = 1912 hsotg->params.host_channels; 1913 } else { 1914 hsotg->non_periodic_channels = 0; 1915 hsotg->periodic_channels = 0; 1916 } 1917 } 1918 1919 /** 1920 * dwc2_hcd_connect() - Handles connect of the HCD 1921 * 1922 * @hsotg: Pointer to struct dwc2_hsotg 1923 * 1924 * Must be called with interrupt disabled and spinlock held 1925 */ 1926 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 1927 { 1928 if (hsotg->lx_state != DWC2_L0) 1929 usb_hcd_resume_root_hub(hsotg->priv); 1930 1931 hsotg->flags.b.port_connect_status_change = 1; 1932 hsotg->flags.b.port_connect_status = 1; 1933 } 1934 1935 /** 1936 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 1937 * 1938 * @hsotg: Pointer to struct dwc2_hsotg 1939 * @force: If true, we won't try to reconnect even if we see device connected. 1940 * 1941 * Must be called with interrupt disabled and spinlock held 1942 */ 1943 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 1944 { 1945 u32 intr; 1946 u32 hprt0; 1947 1948 /* Set status flags for the hub driver */ 1949 hsotg->flags.b.port_connect_status_change = 1; 1950 hsotg->flags.b.port_connect_status = 0; 1951 1952 /* 1953 * Shutdown any transfers in process by clearing the Tx FIFO Empty 1954 * interrupt mask and status bits and disabling subsequent host 1955 * channel interrupts. 1956 */ 1957 intr = dwc2_readl(hsotg->regs + GINTMSK); 1958 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 1959 dwc2_writel(intr, hsotg->regs + GINTMSK); 1960 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 1961 dwc2_writel(intr, hsotg->regs + GINTSTS); 1962 1963 /* 1964 * Turn off the vbus power only if the core has transitioned to device 1965 * mode. If still in host mode, need to keep power on to detect a 1966 * reconnection. 1967 */ 1968 if (dwc2_is_device_mode(hsotg)) { 1969 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 1970 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 1971 dwc2_writel(0, hsotg->regs + HPRT0); 1972 } 1973 1974 dwc2_disable_host_interrupts(hsotg); 1975 } 1976 1977 /* Respond with an error status to all URBs in the schedule */ 1978 dwc2_kill_all_urbs(hsotg); 1979 1980 if (dwc2_is_host_mode(hsotg)) 1981 /* Clean up any host channels that were in use */ 1982 dwc2_hcd_cleanup_channels(hsotg); 1983 1984 dwc2_host_disconnect(hsotg); 1985 1986 /* 1987 * Add an extra check here to see if we're actually connected but 1988 * we don't have a detection interrupt pending. This can happen if: 1989 * 1. hardware sees connect 1990 * 2. hardware sees disconnect 1991 * 3. hardware sees connect 1992 * 4. dwc2_port_intr() - clears connect interrupt 1993 * 5. dwc2_handle_common_intr() - calls here 1994 * 1995 * Without the extra check here we will end calling disconnect 1996 * and won't get any future interrupts to handle the connect. 1997 */ 1998 if (!force) { 1999 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2000 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 2001 dwc2_hcd_connect(hsotg); 2002 } 2003 } 2004 2005 /** 2006 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 2007 * 2008 * @hsotg: Pointer to struct dwc2_hsotg 2009 */ 2010 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 2011 { 2012 if (hsotg->bus_suspended) { 2013 hsotg->flags.b.port_suspend_change = 1; 2014 usb_hcd_resume_root_hub(hsotg->priv); 2015 } 2016 2017 if (hsotg->lx_state == DWC2_L1) 2018 hsotg->flags.b.port_l1_change = 1; 2019 } 2020 2021 /** 2022 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 2023 * 2024 * @hsotg: Pointer to struct dwc2_hsotg 2025 * 2026 * Must be called with interrupt disabled and spinlock held 2027 */ 2028 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 2029 { 2030 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 2031 2032 /* 2033 * The root hub should be disconnected before this function is called. 2034 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 2035 * and the QH lists (via ..._hcd_endpoint_disable). 2036 */ 2037 2038 /* Turn off all host-specific interrupts */ 2039 dwc2_disable_host_interrupts(hsotg); 2040 2041 /* Turn off the vbus power */ 2042 dev_dbg(hsotg->dev, "PortPower off\n"); 2043 dwc2_writel(0, hsotg->regs + HPRT0); 2044 } 2045 2046 /* Caller must hold driver lock */ 2047 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 2048 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 2049 struct dwc2_qtd *qtd) 2050 { 2051 u32 intr_mask; 2052 int retval; 2053 int dev_speed; 2054 2055 if (!hsotg->flags.b.port_connect_status) { 2056 /* No longer connected */ 2057 dev_err(hsotg->dev, "Not connected\n"); 2058 return -ENODEV; 2059 } 2060 2061 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 2062 2063 /* Some configurations cannot support LS traffic on a FS root port */ 2064 if ((dev_speed == USB_SPEED_LOW) && 2065 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 2066 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 2067 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 2068 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 2069 2070 if (prtspd == HPRT0_SPD_FULL_SPEED) 2071 return -ENODEV; 2072 } 2073 2074 if (!qtd) 2075 return -EINVAL; 2076 2077 dwc2_hcd_qtd_init(qtd, urb); 2078 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 2079 if (retval) { 2080 dev_err(hsotg->dev, 2081 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 2082 retval); 2083 return retval; 2084 } 2085 2086 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 2087 if (!(intr_mask & GINTSTS_SOF)) { 2088 enum dwc2_transaction_type tr_type; 2089 2090 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 2091 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 2092 /* 2093 * Do not schedule SG transactions until qtd has 2094 * URB_GIVEBACK_ASAP set 2095 */ 2096 return 0; 2097 2098 tr_type = dwc2_hcd_select_transactions(hsotg); 2099 if (tr_type != DWC2_TRANSACTION_NONE) 2100 dwc2_hcd_queue_transactions(hsotg, tr_type); 2101 } 2102 2103 return 0; 2104 } 2105 2106 /* Must be called with interrupt disabled and spinlock held */ 2107 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 2108 struct dwc2_hcd_urb *urb) 2109 { 2110 struct dwc2_qh *qh; 2111 struct dwc2_qtd *urb_qtd; 2112 2113 urb_qtd = urb->qtd; 2114 if (!urb_qtd) { 2115 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 2116 return -EINVAL; 2117 } 2118 2119 qh = urb_qtd->qh; 2120 if (!qh) { 2121 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 2122 return -EINVAL; 2123 } 2124 2125 urb->priv = NULL; 2126 2127 if (urb_qtd->in_process && qh->channel) { 2128 dwc2_dump_channel_info(hsotg, qh->channel); 2129 2130 /* The QTD is in process (it has been assigned to a channel) */ 2131 if (hsotg->flags.b.port_connect_status) 2132 /* 2133 * If still connected (i.e. in host mode), halt the 2134 * channel so it can be used for other transfers. If 2135 * no longer connected, the host registers can't be 2136 * written to halt the channel since the core is in 2137 * device mode. 2138 */ 2139 dwc2_hc_halt(hsotg, qh->channel, 2140 DWC2_HC_XFER_URB_DEQUEUE); 2141 } 2142 2143 /* 2144 * Free the QTD and clean up the associated QH. Leave the QH in the 2145 * schedule if it has any remaining QTDs. 2146 */ 2147 if (!hsotg->params.dma_desc_enable) { 2148 u8 in_process = urb_qtd->in_process; 2149 2150 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2151 if (in_process) { 2152 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 2153 qh->channel = NULL; 2154 } else if (list_empty(&qh->qtd_list)) { 2155 dwc2_hcd_qh_unlink(hsotg, qh); 2156 } 2157 } else { 2158 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 2159 } 2160 2161 return 0; 2162 } 2163 2164 /* Must NOT be called with interrupt disabled or spinlock held */ 2165 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 2166 struct usb_host_endpoint *ep, int retry) 2167 { 2168 struct dwc2_qtd *qtd, *qtd_tmp; 2169 struct dwc2_qh *qh; 2170 unsigned long flags; 2171 int rc; 2172 2173 spin_lock_irqsave(&hsotg->lock, flags); 2174 2175 qh = ep->hcpriv; 2176 if (!qh) { 2177 rc = -EINVAL; 2178 goto err; 2179 } 2180 2181 while (!list_empty(&qh->qtd_list) && retry--) { 2182 if (retry == 0) { 2183 dev_err(hsotg->dev, 2184 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 2185 rc = -EBUSY; 2186 goto err; 2187 } 2188 2189 spin_unlock_irqrestore(&hsotg->lock, flags); 2190 msleep(20); 2191 spin_lock_irqsave(&hsotg->lock, flags); 2192 qh = ep->hcpriv; 2193 if (!qh) { 2194 rc = -EINVAL; 2195 goto err; 2196 } 2197 } 2198 2199 dwc2_hcd_qh_unlink(hsotg, qh); 2200 2201 /* Free each QTD in the QH's QTD list */ 2202 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 2203 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 2204 2205 ep->hcpriv = NULL; 2206 2207 if (qh->channel && qh->channel->qh == qh) 2208 qh->channel->qh = NULL; 2209 2210 spin_unlock_irqrestore(&hsotg->lock, flags); 2211 2212 dwc2_hcd_qh_free(hsotg, qh); 2213 2214 return 0; 2215 2216 err: 2217 ep->hcpriv = NULL; 2218 spin_unlock_irqrestore(&hsotg->lock, flags); 2219 2220 return rc; 2221 } 2222 2223 /* Must be called with interrupt disabled and spinlock held */ 2224 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 2225 struct usb_host_endpoint *ep) 2226 { 2227 struct dwc2_qh *qh = ep->hcpriv; 2228 2229 if (!qh) 2230 return -EINVAL; 2231 2232 qh->data_toggle = DWC2_HC_PID_DATA0; 2233 2234 return 0; 2235 } 2236 2237 /** 2238 * dwc2_core_init() - Initializes the DWC_otg controller registers and 2239 * prepares the core for device mode or host mode operation 2240 * 2241 * @hsotg: Programming view of the DWC_otg controller 2242 * @initial_setup: If true then this is the first init for this instance. 2243 */ 2244 static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) 2245 { 2246 u32 usbcfg, otgctl; 2247 int retval; 2248 2249 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2250 2251 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2252 2253 /* Set ULPI External VBUS bit if needed */ 2254 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; 2255 if (hsotg->params.phy_ulpi_ext_vbus) 2256 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV; 2257 2258 /* Set external TS Dline pulsing bit if needed */ 2259 usbcfg &= ~GUSBCFG_TERMSELDLPULSE; 2260 if (hsotg->params.ts_dline) 2261 usbcfg |= GUSBCFG_TERMSELDLPULSE; 2262 2263 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2264 2265 /* 2266 * Reset the Controller 2267 * 2268 * We only need to reset the controller if this is a re-init. 2269 * For the first init we know for sure that earlier code reset us (it 2270 * needed to in order to properly detect various parameters). 2271 */ 2272 if (!initial_setup) { 2273 retval = dwc2_core_reset_and_force_dr_mode(hsotg); 2274 if (retval) { 2275 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n", 2276 __func__); 2277 return retval; 2278 } 2279 } 2280 2281 /* 2282 * This needs to happen in FS mode before any other programming occurs 2283 */ 2284 retval = dwc2_phy_init(hsotg, initial_setup); 2285 if (retval) 2286 return retval; 2287 2288 /* Program the GAHBCFG Register */ 2289 retval = dwc2_gahbcfg_init(hsotg); 2290 if (retval) 2291 return retval; 2292 2293 /* Program the GUSBCFG register */ 2294 dwc2_gusbcfg_init(hsotg); 2295 2296 /* Program the GOTGCTL register */ 2297 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2298 otgctl &= ~GOTGCTL_OTGVER; 2299 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2300 2301 /* Clear the SRP success bit for FS-I2c */ 2302 hsotg->srp_success = 0; 2303 2304 /* Enable common interrupts */ 2305 dwc2_enable_common_interrupts(hsotg); 2306 2307 /* 2308 * Do device or host initialization based on mode during PCD and 2309 * HCD initialization 2310 */ 2311 if (dwc2_is_host_mode(hsotg)) { 2312 dev_dbg(hsotg->dev, "Host Mode\n"); 2313 hsotg->op_state = OTG_STATE_A_HOST; 2314 } else { 2315 dev_dbg(hsotg->dev, "Device Mode\n"); 2316 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 2317 } 2318 2319 return 0; 2320 } 2321 2322 /** 2323 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for 2324 * Host mode 2325 * 2326 * @hsotg: Programming view of DWC_otg controller 2327 * 2328 * This function flushes the Tx and Rx FIFOs and flushes any entries in the 2329 * request queues. Host channels are reset to ensure that they are ready for 2330 * performing transfers. 2331 */ 2332 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) 2333 { 2334 u32 hcfg, hfir, otgctl, usbcfg; 2335 2336 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); 2337 2338 /* Set HS/FS Timeout Calibration to 7 (max available value). 2339 * The number of PHY clocks that the application programs in 2340 * this field is added to the high/full speed interpacket timeout 2341 * duration in the core to account for any additional delays 2342 * introduced by the PHY. This can be required, because the delay 2343 * introduced by the PHY in generating the linestate condition 2344 * can vary from one PHY to another. 2345 */ 2346 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); 2347 usbcfg |= GUSBCFG_TOUTCAL(7); 2348 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); 2349 2350 /* Restart the Phy Clock */ 2351 dwc2_writel(0, hsotg->regs + PCGCTL); 2352 2353 /* Initialize Host Configuration Register */ 2354 dwc2_init_fs_ls_pclk_sel(hsotg); 2355 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 2356 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { 2357 hcfg = dwc2_readl(hsotg->regs + HCFG); 2358 hcfg |= HCFG_FSLSSUPP; 2359 dwc2_writel(hcfg, hsotg->regs + HCFG); 2360 } 2361 2362 /* 2363 * This bit allows dynamic reloading of the HFIR register during 2364 * runtime. This bit needs to be programmed during initial configuration 2365 * and its value must not be changed during runtime. 2366 */ 2367 if (hsotg->params.reload_ctl) { 2368 hfir = dwc2_readl(hsotg->regs + HFIR); 2369 hfir |= HFIR_RLDCTRL; 2370 dwc2_writel(hfir, hsotg->regs + HFIR); 2371 } 2372 2373 if (hsotg->params.dma_desc_enable) { 2374 u32 op_mode = hsotg->hw_params.op_mode; 2375 2376 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a || 2377 !hsotg->hw_params.dma_desc_enable || 2378 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE || 2379 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE || 2380 op_mode == GHWCFG2_OP_MODE_UNDEFINED) { 2381 dev_err(hsotg->dev, 2382 "Hardware does not support descriptor DMA mode -\n"); 2383 dev_err(hsotg->dev, 2384 "falling back to buffer DMA mode.\n"); 2385 hsotg->params.dma_desc_enable = false; 2386 } else { 2387 hcfg = dwc2_readl(hsotg->regs + HCFG); 2388 hcfg |= HCFG_DESCDMA; 2389 dwc2_writel(hcfg, hsotg->regs + HCFG); 2390 } 2391 } 2392 2393 /* Configure data FIFO sizes */ 2394 dwc2_config_fifos(hsotg); 2395 2396 /* TODO - check this */ 2397 /* Clear Host Set HNP Enable in the OTG Control Register */ 2398 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2399 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2400 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2401 2402 /* Make sure the FIFOs are flushed */ 2403 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); 2404 dwc2_flush_rx_fifo(hsotg); 2405 2406 /* Clear Host Set HNP Enable in the OTG Control Register */ 2407 otgctl = dwc2_readl(hsotg->regs + GOTGCTL); 2408 otgctl &= ~GOTGCTL_HSTSETHNPEN; 2409 dwc2_writel(otgctl, hsotg->regs + GOTGCTL); 2410 2411 if (!hsotg->params.dma_desc_enable) { 2412 int num_channels, i; 2413 u32 hcchar; 2414 2415 /* Flush out any leftover queued requests */ 2416 num_channels = hsotg->params.host_channels; 2417 for (i = 0; i < num_channels; i++) { 2418 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2419 hcchar &= ~HCCHAR_CHENA; 2420 hcchar |= HCCHAR_CHDIS; 2421 hcchar &= ~HCCHAR_EPDIR; 2422 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2423 } 2424 2425 /* Halt all channels to put them into a known state */ 2426 for (i = 0; i < num_channels; i++) { 2427 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2428 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; 2429 hcchar &= ~HCCHAR_EPDIR; 2430 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 2431 dev_dbg(hsotg->dev, "%s: Halt channel %d\n", 2432 __func__, i); 2433 2434 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i), 2435 HCCHAR_CHENA, 1000)) { 2436 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n", 2437 i); 2438 } 2439 } 2440 } 2441 2442 /* Enable ACG feature in host mode, if supported */ 2443 dwc2_enable_acg(hsotg); 2444 2445 /* Turn on the vbus power */ 2446 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state); 2447 if (hsotg->op_state == OTG_STATE_A_HOST) { 2448 u32 hprt0 = dwc2_read_hprt0(hsotg); 2449 2450 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n", 2451 !!(hprt0 & HPRT0_PWR)); 2452 if (!(hprt0 & HPRT0_PWR)) { 2453 hprt0 |= HPRT0_PWR; 2454 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2455 } 2456 } 2457 2458 dwc2_enable_host_interrupts(hsotg); 2459 } 2460 2461 /* 2462 * Initializes dynamic portions of the DWC_otg HCD state 2463 * 2464 * Must be called with interrupt disabled and spinlock held 2465 */ 2466 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 2467 { 2468 struct dwc2_host_chan *chan, *chan_tmp; 2469 int num_channels; 2470 int i; 2471 2472 hsotg->flags.d32 = 0; 2473 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 2474 2475 if (hsotg->params.uframe_sched) { 2476 hsotg->available_host_channels = 2477 hsotg->params.host_channels; 2478 } else { 2479 hsotg->non_periodic_channels = 0; 2480 hsotg->periodic_channels = 0; 2481 } 2482 2483 /* 2484 * Put all channels in the free channel list and clean up channel 2485 * states 2486 */ 2487 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 2488 hc_list_entry) 2489 list_del_init(&chan->hc_list_entry); 2490 2491 num_channels = hsotg->params.host_channels; 2492 for (i = 0; i < num_channels; i++) { 2493 chan = hsotg->hc_ptr_array[i]; 2494 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 2495 dwc2_hc_cleanup(hsotg, chan); 2496 } 2497 2498 /* Initialize the DWC core for host mode operation */ 2499 dwc2_core_host_init(hsotg); 2500 } 2501 2502 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 2503 struct dwc2_host_chan *chan, 2504 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 2505 { 2506 int hub_addr, hub_port; 2507 2508 chan->do_split = 1; 2509 chan->xact_pos = qtd->isoc_split_pos; 2510 chan->complete_split = qtd->complete_split; 2511 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 2512 chan->hub_addr = (u8)hub_addr; 2513 chan->hub_port = (u8)hub_port; 2514 } 2515 2516 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 2517 struct dwc2_host_chan *chan, 2518 struct dwc2_qtd *qtd) 2519 { 2520 struct dwc2_hcd_urb *urb = qtd->urb; 2521 struct dwc2_hcd_iso_packet_desc *frame_desc; 2522 2523 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 2524 case USB_ENDPOINT_XFER_CONTROL: 2525 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 2526 2527 switch (qtd->control_phase) { 2528 case DWC2_CONTROL_SETUP: 2529 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 2530 chan->do_ping = 0; 2531 chan->ep_is_in = 0; 2532 chan->data_pid_start = DWC2_HC_PID_SETUP; 2533 if (hsotg->params.host_dma) 2534 chan->xfer_dma = urb->setup_dma; 2535 else 2536 chan->xfer_buf = urb->setup_packet; 2537 chan->xfer_len = 8; 2538 break; 2539 2540 case DWC2_CONTROL_DATA: 2541 dev_vdbg(hsotg->dev, " Control data transaction\n"); 2542 chan->data_pid_start = qtd->data_toggle; 2543 break; 2544 2545 case DWC2_CONTROL_STATUS: 2546 /* 2547 * Direction is opposite of data direction or IN if no 2548 * data 2549 */ 2550 dev_vdbg(hsotg->dev, " Control status transaction\n"); 2551 if (urb->length == 0) 2552 chan->ep_is_in = 1; 2553 else 2554 chan->ep_is_in = 2555 dwc2_hcd_is_pipe_out(&urb->pipe_info); 2556 if (chan->ep_is_in) 2557 chan->do_ping = 0; 2558 chan->data_pid_start = DWC2_HC_PID_DATA1; 2559 chan->xfer_len = 0; 2560 if (hsotg->params.host_dma) 2561 chan->xfer_dma = hsotg->status_buf_dma; 2562 else 2563 chan->xfer_buf = hsotg->status_buf; 2564 break; 2565 } 2566 break; 2567 2568 case USB_ENDPOINT_XFER_BULK: 2569 chan->ep_type = USB_ENDPOINT_XFER_BULK; 2570 break; 2571 2572 case USB_ENDPOINT_XFER_INT: 2573 chan->ep_type = USB_ENDPOINT_XFER_INT; 2574 break; 2575 2576 case USB_ENDPOINT_XFER_ISOC: 2577 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 2578 if (hsotg->params.dma_desc_enable) 2579 break; 2580 2581 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 2582 frame_desc->status = 0; 2583 2584 if (hsotg->params.host_dma) { 2585 chan->xfer_dma = urb->dma; 2586 chan->xfer_dma += frame_desc->offset + 2587 qtd->isoc_split_offset; 2588 } else { 2589 chan->xfer_buf = urb->buf; 2590 chan->xfer_buf += frame_desc->offset + 2591 qtd->isoc_split_offset; 2592 } 2593 2594 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 2595 2596 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 2597 if (chan->xfer_len <= 188) 2598 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 2599 else 2600 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 2601 } 2602 break; 2603 } 2604 } 2605 2606 #define DWC2_USB_DMA_ALIGN 4 2607 2608 struct dma_aligned_buffer { 2609 void *kmalloc_ptr; 2610 void *old_xfer_buffer; 2611 u8 data[0]; 2612 }; 2613 2614 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 2615 { 2616 struct dma_aligned_buffer *temp; 2617 2618 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 2619 return; 2620 2621 temp = container_of(urb->transfer_buffer, 2622 struct dma_aligned_buffer, data); 2623 2624 if (usb_urb_dir_in(urb)) 2625 memcpy(temp->old_xfer_buffer, temp->data, 2626 urb->transfer_buffer_length); 2627 urb->transfer_buffer = temp->old_xfer_buffer; 2628 kfree(temp->kmalloc_ptr); 2629 2630 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 2631 } 2632 2633 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 2634 { 2635 struct dma_aligned_buffer *temp, *kmalloc_ptr; 2636 size_t kmalloc_size; 2637 2638 if (urb->num_sgs || urb->sg || 2639 urb->transfer_buffer_length == 0 || 2640 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 2641 return 0; 2642 2643 /* Allocate a buffer with enough padding for alignment */ 2644 kmalloc_size = urb->transfer_buffer_length + 2645 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 2646 2647 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 2648 if (!kmalloc_ptr) 2649 return -ENOMEM; 2650 2651 /* Position our struct dma_aligned_buffer such that data is aligned */ 2652 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 2653 temp->kmalloc_ptr = kmalloc_ptr; 2654 temp->old_xfer_buffer = urb->transfer_buffer; 2655 if (usb_urb_dir_out(urb)) 2656 memcpy(temp->data, urb->transfer_buffer, 2657 urb->transfer_buffer_length); 2658 urb->transfer_buffer = temp->data; 2659 2660 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 2661 2662 return 0; 2663 } 2664 2665 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 2666 gfp_t mem_flags) 2667 { 2668 int ret; 2669 2670 /* We assume setup_dma is always aligned; warn if not */ 2671 WARN_ON_ONCE(urb->setup_dma && 2672 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 2673 2674 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 2675 if (ret) 2676 return ret; 2677 2678 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 2679 if (ret) 2680 dwc2_free_dma_aligned_buffer(urb); 2681 2682 return ret; 2683 } 2684 2685 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 2686 { 2687 usb_hcd_unmap_urb_for_dma(hcd, urb); 2688 dwc2_free_dma_aligned_buffer(urb); 2689 } 2690 2691 /** 2692 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 2693 * channel and initializes the host channel to perform the transactions. The 2694 * host channel is removed from the free list. 2695 * 2696 * @hsotg: The HCD state structure 2697 * @qh: Transactions from the first QTD for this QH are selected and assigned 2698 * to a free host channel 2699 */ 2700 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 2701 { 2702 struct dwc2_host_chan *chan; 2703 struct dwc2_hcd_urb *urb; 2704 struct dwc2_qtd *qtd; 2705 2706 if (dbg_qh(qh)) 2707 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 2708 2709 if (list_empty(&qh->qtd_list)) { 2710 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 2711 return -ENOMEM; 2712 } 2713 2714 if (list_empty(&hsotg->free_hc_list)) { 2715 dev_dbg(hsotg->dev, "No free channel to assign\n"); 2716 return -ENOMEM; 2717 } 2718 2719 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 2720 hc_list_entry); 2721 2722 /* Remove host channel from free list */ 2723 list_del_init(&chan->hc_list_entry); 2724 2725 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 2726 urb = qtd->urb; 2727 qh->channel = chan; 2728 qtd->in_process = 1; 2729 2730 /* 2731 * Use usb_pipedevice to determine device address. This address is 2732 * 0 before the SET_ADDRESS command and the correct address afterward. 2733 */ 2734 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 2735 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 2736 chan->speed = qh->dev_speed; 2737 chan->max_packet = dwc2_max_packet(qh->maxp); 2738 2739 chan->xfer_started = 0; 2740 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 2741 chan->error_state = (qtd->error_count > 0); 2742 chan->halt_on_queue = 0; 2743 chan->halt_pending = 0; 2744 chan->requests = 0; 2745 2746 /* 2747 * The following values may be modified in the transfer type section 2748 * below. The xfer_len value may be reduced when the transfer is 2749 * started to accommodate the max widths of the XferSize and PktCnt 2750 * fields in the HCTSIZn register. 2751 */ 2752 2753 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 2754 if (chan->ep_is_in) 2755 chan->do_ping = 0; 2756 else 2757 chan->do_ping = qh->ping_state; 2758 2759 chan->data_pid_start = qh->data_toggle; 2760 chan->multi_count = 1; 2761 2762 if (urb->actual_length > urb->length && 2763 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 2764 urb->actual_length = urb->length; 2765 2766 if (hsotg->params.host_dma) 2767 chan->xfer_dma = urb->dma + urb->actual_length; 2768 else 2769 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 2770 2771 chan->xfer_len = urb->length - urb->actual_length; 2772 chan->xfer_count = 0; 2773 2774 /* Set the split attributes if required */ 2775 if (qh->do_split) 2776 dwc2_hc_init_split(hsotg, chan, qtd, urb); 2777 else 2778 chan->do_split = 0; 2779 2780 /* Set the transfer attributes */ 2781 dwc2_hc_init_xfer(hsotg, chan, qtd); 2782 2783 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 2784 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 2785 /* 2786 * This value may be modified when the transfer is started 2787 * to reflect the actual transfer length 2788 */ 2789 chan->multi_count = dwc2_hb_mult(qh->maxp); 2790 2791 if (hsotg->params.dma_desc_enable) { 2792 chan->desc_list_addr = qh->desc_list_dma; 2793 chan->desc_list_sz = qh->desc_list_sz; 2794 } 2795 2796 dwc2_hc_init(hsotg, chan); 2797 chan->qh = qh; 2798 2799 return 0; 2800 } 2801 2802 /** 2803 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 2804 * schedule and assigns them to available host channels. Called from the HCD 2805 * interrupt handler functions. 2806 * 2807 * @hsotg: The HCD state structure 2808 * 2809 * Return: The types of new transactions that were assigned to host channels 2810 */ 2811 enum dwc2_transaction_type dwc2_hcd_select_transactions( 2812 struct dwc2_hsotg *hsotg) 2813 { 2814 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 2815 struct list_head *qh_ptr; 2816 struct dwc2_qh *qh; 2817 int num_channels; 2818 2819 #ifdef DWC2_DEBUG_SOF 2820 dev_vdbg(hsotg->dev, " Select Transactions\n"); 2821 #endif 2822 2823 /* Process entries in the periodic ready list */ 2824 qh_ptr = hsotg->periodic_sched_ready.next; 2825 while (qh_ptr != &hsotg->periodic_sched_ready) { 2826 if (list_empty(&hsotg->free_hc_list)) 2827 break; 2828 if (hsotg->params.uframe_sched) { 2829 if (hsotg->available_host_channels <= 1) 2830 break; 2831 hsotg->available_host_channels--; 2832 } 2833 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2834 if (dwc2_assign_and_init_hc(hsotg, qh)) 2835 break; 2836 2837 /* 2838 * Move the QH from the periodic ready schedule to the 2839 * periodic assigned schedule 2840 */ 2841 qh_ptr = qh_ptr->next; 2842 list_move_tail(&qh->qh_list_entry, 2843 &hsotg->periodic_sched_assigned); 2844 ret_val = DWC2_TRANSACTION_PERIODIC; 2845 } 2846 2847 /* 2848 * Process entries in the inactive portion of the non-periodic 2849 * schedule. Some free host channels may not be used if they are 2850 * reserved for periodic transfers. 2851 */ 2852 num_channels = hsotg->params.host_channels; 2853 qh_ptr = hsotg->non_periodic_sched_inactive.next; 2854 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 2855 if (!hsotg->params.uframe_sched && 2856 hsotg->non_periodic_channels >= num_channels - 2857 hsotg->periodic_channels) 2858 break; 2859 if (list_empty(&hsotg->free_hc_list)) 2860 break; 2861 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 2862 if (hsotg->params.uframe_sched) { 2863 if (hsotg->available_host_channels < 1) 2864 break; 2865 hsotg->available_host_channels--; 2866 } 2867 2868 if (dwc2_assign_and_init_hc(hsotg, qh)) 2869 break; 2870 2871 /* 2872 * Move the QH from the non-periodic inactive schedule to the 2873 * non-periodic active schedule 2874 */ 2875 qh_ptr = qh_ptr->next; 2876 list_move_tail(&qh->qh_list_entry, 2877 &hsotg->non_periodic_sched_active); 2878 2879 if (ret_val == DWC2_TRANSACTION_NONE) 2880 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 2881 else 2882 ret_val = DWC2_TRANSACTION_ALL; 2883 2884 if (!hsotg->params.uframe_sched) 2885 hsotg->non_periodic_channels++; 2886 } 2887 2888 return ret_val; 2889 } 2890 2891 /** 2892 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 2893 * a host channel associated with either a periodic or non-periodic transfer 2894 * 2895 * @hsotg: The HCD state structure 2896 * @chan: Host channel descriptor associated with either a periodic or 2897 * non-periodic transfer 2898 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 2899 * for periodic transfers or the non-periodic Tx FIFO 2900 * for non-periodic transfers 2901 * 2902 * Return: 1 if a request is queued and more requests may be needed to 2903 * complete the transfer, 0 if no more requests are required for this 2904 * transfer, -1 if there is insufficient space in the Tx FIFO 2905 * 2906 * This function assumes that there is space available in the appropriate 2907 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 2908 * it checks whether space is available in the appropriate Tx FIFO. 2909 * 2910 * Must be called with interrupt disabled and spinlock held 2911 */ 2912 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 2913 struct dwc2_host_chan *chan, 2914 u16 fifo_dwords_avail) 2915 { 2916 int retval = 0; 2917 2918 if (chan->do_split) 2919 /* Put ourselves on the list to keep order straight */ 2920 list_move_tail(&chan->split_order_list_entry, 2921 &hsotg->split_order); 2922 2923 if (hsotg->params.host_dma) { 2924 if (hsotg->params.dma_desc_enable) { 2925 if (!chan->xfer_started || 2926 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 2927 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 2928 chan->qh->ping_state = 0; 2929 } 2930 } else if (!chan->xfer_started) { 2931 dwc2_hc_start_transfer(hsotg, chan); 2932 chan->qh->ping_state = 0; 2933 } 2934 } else if (chan->halt_pending) { 2935 /* Don't queue a request if the channel has been halted */ 2936 } else if (chan->halt_on_queue) { 2937 dwc2_hc_halt(hsotg, chan, chan->halt_status); 2938 } else if (chan->do_ping) { 2939 if (!chan->xfer_started) 2940 dwc2_hc_start_transfer(hsotg, chan); 2941 } else if (!chan->ep_is_in || 2942 chan->data_pid_start == DWC2_HC_PID_SETUP) { 2943 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 2944 if (!chan->xfer_started) { 2945 dwc2_hc_start_transfer(hsotg, chan); 2946 retval = 1; 2947 } else { 2948 retval = dwc2_hc_continue_transfer(hsotg, chan); 2949 } 2950 } else { 2951 retval = -1; 2952 } 2953 } else { 2954 if (!chan->xfer_started) { 2955 dwc2_hc_start_transfer(hsotg, chan); 2956 retval = 1; 2957 } else { 2958 retval = dwc2_hc_continue_transfer(hsotg, chan); 2959 } 2960 } 2961 2962 return retval; 2963 } 2964 2965 /* 2966 * Processes periodic channels for the next frame and queues transactions for 2967 * these channels to the DWC_otg controller. After queueing transactions, the 2968 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 2969 * to queue as Periodic Tx FIFO or request queue space becomes available. 2970 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 2971 * 2972 * Must be called with interrupt disabled and spinlock held 2973 */ 2974 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 2975 { 2976 struct list_head *qh_ptr; 2977 struct dwc2_qh *qh; 2978 u32 tx_status; 2979 u32 fspcavail; 2980 u32 gintmsk; 2981 int status; 2982 bool no_queue_space = false; 2983 bool no_fifo_space = false; 2984 u32 qspcavail; 2985 2986 /* If empty list then just adjust interrupt enables */ 2987 if (list_empty(&hsotg->periodic_sched_assigned)) 2988 goto exit; 2989 2990 if (dbg_perio()) 2991 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 2992 2993 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2994 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 2995 TXSTS_QSPCAVAIL_SHIFT; 2996 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 2997 TXSTS_FSPCAVAIL_SHIFT; 2998 2999 if (dbg_perio()) { 3000 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 3001 qspcavail); 3002 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 3003 fspcavail); 3004 } 3005 3006 qh_ptr = hsotg->periodic_sched_assigned.next; 3007 while (qh_ptr != &hsotg->periodic_sched_assigned) { 3008 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 3009 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3010 TXSTS_QSPCAVAIL_SHIFT; 3011 if (qspcavail == 0) { 3012 no_queue_space = true; 3013 break; 3014 } 3015 3016 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 3017 if (!qh->channel) { 3018 qh_ptr = qh_ptr->next; 3019 continue; 3020 } 3021 3022 /* Make sure EP's TT buffer is clean before queueing qtds */ 3023 if (qh->tt_buffer_dirty) { 3024 qh_ptr = qh_ptr->next; 3025 continue; 3026 } 3027 3028 /* 3029 * Set a flag if we're queuing high-bandwidth in slave mode. 3030 * The flag prevents any halts to get into the request queue in 3031 * the middle of multiple high-bandwidth packets getting queued. 3032 */ 3033 if (!hsotg->params.host_dma && 3034 qh->channel->multi_count > 1) 3035 hsotg->queuing_high_bandwidth = 1; 3036 3037 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3038 TXSTS_FSPCAVAIL_SHIFT; 3039 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3040 if (status < 0) { 3041 no_fifo_space = true; 3042 break; 3043 } 3044 3045 /* 3046 * In Slave mode, stay on the current transfer until there is 3047 * nothing more to do or the high-bandwidth request count is 3048 * reached. In DMA mode, only need to queue one request. The 3049 * controller automatically handles multiple packets for 3050 * high-bandwidth transfers. 3051 */ 3052 if (hsotg->params.host_dma || status == 0 || 3053 qh->channel->requests == qh->channel->multi_count) { 3054 qh_ptr = qh_ptr->next; 3055 /* 3056 * Move the QH from the periodic assigned schedule to 3057 * the periodic queued schedule 3058 */ 3059 list_move_tail(&qh->qh_list_entry, 3060 &hsotg->periodic_sched_queued); 3061 3062 /* done queuing high bandwidth */ 3063 hsotg->queuing_high_bandwidth = 0; 3064 } 3065 } 3066 3067 exit: 3068 if (no_queue_space || no_fifo_space || 3069 (!hsotg->params.host_dma && 3070 !list_empty(&hsotg->periodic_sched_assigned))) { 3071 /* 3072 * May need to queue more transactions as the request 3073 * queue or Tx FIFO empties. Enable the periodic Tx 3074 * FIFO empty interrupt. (Always use the half-empty 3075 * level to ensure that new requests are loaded as 3076 * soon as possible.) 3077 */ 3078 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3079 if (!(gintmsk & GINTSTS_PTXFEMP)) { 3080 gintmsk |= GINTSTS_PTXFEMP; 3081 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3082 } 3083 } else { 3084 /* 3085 * Disable the Tx FIFO empty interrupt since there are 3086 * no more transactions that need to be queued right 3087 * now. This function is called from interrupt 3088 * handlers to queue more transactions as transfer 3089 * states change. 3090 */ 3091 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3092 if (gintmsk & GINTSTS_PTXFEMP) { 3093 gintmsk &= ~GINTSTS_PTXFEMP; 3094 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3095 } 3096 } 3097 } 3098 3099 /* 3100 * Processes active non-periodic channels and queues transactions for these 3101 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 3102 * FIFO Empty interrupt is enabled if there are more transactions to queue as 3103 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 3104 * FIFO Empty interrupt is disabled. 3105 * 3106 * Must be called with interrupt disabled and spinlock held 3107 */ 3108 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 3109 { 3110 struct list_head *orig_qh_ptr; 3111 struct dwc2_qh *qh; 3112 u32 tx_status; 3113 u32 qspcavail; 3114 u32 fspcavail; 3115 u32 gintmsk; 3116 int status; 3117 int no_queue_space = 0; 3118 int no_fifo_space = 0; 3119 int more_to_do = 0; 3120 3121 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 3122 3123 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3124 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3125 TXSTS_QSPCAVAIL_SHIFT; 3126 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3127 TXSTS_FSPCAVAIL_SHIFT; 3128 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 3129 qspcavail); 3130 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 3131 fspcavail); 3132 3133 /* 3134 * Keep track of the starting point. Skip over the start-of-list 3135 * entry. 3136 */ 3137 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 3138 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3139 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 3140 3141 /* 3142 * Process once through the active list or until no more space is 3143 * available in the request queue or the Tx FIFO 3144 */ 3145 do { 3146 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3147 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3148 TXSTS_QSPCAVAIL_SHIFT; 3149 if (!hsotg->params.host_dma && qspcavail == 0) { 3150 no_queue_space = 1; 3151 break; 3152 } 3153 3154 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 3155 qh_list_entry); 3156 if (!qh->channel) 3157 goto next; 3158 3159 /* Make sure EP's TT buffer is clean before queueing qtds */ 3160 if (qh->tt_buffer_dirty) 3161 goto next; 3162 3163 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3164 TXSTS_FSPCAVAIL_SHIFT; 3165 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 3166 3167 if (status > 0) { 3168 more_to_do = 1; 3169 } else if (status < 0) { 3170 no_fifo_space = 1; 3171 break; 3172 } 3173 next: 3174 /* Advance to next QH, skipping start-of-list entry */ 3175 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 3176 if (hsotg->non_periodic_qh_ptr == 3177 &hsotg->non_periodic_sched_active) 3178 hsotg->non_periodic_qh_ptr = 3179 hsotg->non_periodic_qh_ptr->next; 3180 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 3181 3182 if (!hsotg->params.host_dma) { 3183 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 3184 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 3185 TXSTS_QSPCAVAIL_SHIFT; 3186 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 3187 TXSTS_FSPCAVAIL_SHIFT; 3188 dev_vdbg(hsotg->dev, 3189 " NP Tx Req Queue Space Avail (after queue): %d\n", 3190 qspcavail); 3191 dev_vdbg(hsotg->dev, 3192 " NP Tx FIFO Space Avail (after queue): %d\n", 3193 fspcavail); 3194 3195 if (more_to_do || no_queue_space || no_fifo_space) { 3196 /* 3197 * May need to queue more transactions as the request 3198 * queue or Tx FIFO empties. Enable the non-periodic 3199 * Tx FIFO empty interrupt. (Always use the half-empty 3200 * level to ensure that new requests are loaded as 3201 * soon as possible.) 3202 */ 3203 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3204 gintmsk |= GINTSTS_NPTXFEMP; 3205 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3206 } else { 3207 /* 3208 * Disable the Tx FIFO empty interrupt since there are 3209 * no more transactions that need to be queued right 3210 * now. This function is called from interrupt 3211 * handlers to queue more transactions as transfer 3212 * states change. 3213 */ 3214 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3215 gintmsk &= ~GINTSTS_NPTXFEMP; 3216 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3217 } 3218 } 3219 } 3220 3221 /** 3222 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 3223 * and queues transactions for these channels to the DWC_otg controller. Called 3224 * from the HCD interrupt handler functions. 3225 * 3226 * @hsotg: The HCD state structure 3227 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 3228 * or both) 3229 * 3230 * Must be called with interrupt disabled and spinlock held 3231 */ 3232 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 3233 enum dwc2_transaction_type tr_type) 3234 { 3235 #ifdef DWC2_DEBUG_SOF 3236 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 3237 #endif 3238 /* Process host channels associated with periodic transfers */ 3239 if (tr_type == DWC2_TRANSACTION_PERIODIC || 3240 tr_type == DWC2_TRANSACTION_ALL) 3241 dwc2_process_periodic_channels(hsotg); 3242 3243 /* Process host channels associated with non-periodic transfers */ 3244 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 3245 tr_type == DWC2_TRANSACTION_ALL) { 3246 if (!list_empty(&hsotg->non_periodic_sched_active)) { 3247 dwc2_process_non_periodic_channels(hsotg); 3248 } else { 3249 /* 3250 * Ensure NP Tx FIFO empty interrupt is disabled when 3251 * there are no non-periodic transfers to process 3252 */ 3253 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 3254 3255 gintmsk &= ~GINTSTS_NPTXFEMP; 3256 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 3257 } 3258 } 3259 } 3260 3261 static void dwc2_conn_id_status_change(struct work_struct *work) 3262 { 3263 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 3264 wf_otg); 3265 u32 count = 0; 3266 u32 gotgctl; 3267 unsigned long flags; 3268 3269 dev_dbg(hsotg->dev, "%s()\n", __func__); 3270 3271 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3272 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 3273 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 3274 !!(gotgctl & GOTGCTL_CONID_B)); 3275 3276 /* B-Device connector (Device Mode) */ 3277 if (gotgctl & GOTGCTL_CONID_B) { 3278 /* Wait for switch to device mode */ 3279 dev_dbg(hsotg->dev, "connId B\n"); 3280 if (hsotg->bus_suspended) { 3281 dev_info(hsotg->dev, 3282 "Do port resume before switching to device mode\n"); 3283 dwc2_port_resume(hsotg); 3284 } 3285 while (!dwc2_is_device_mode(hsotg)) { 3286 dev_info(hsotg->dev, 3287 "Waiting for Peripheral Mode, Mode=%s\n", 3288 dwc2_is_host_mode(hsotg) ? "Host" : 3289 "Peripheral"); 3290 msleep(20); 3291 /* 3292 * Sometimes the initial GOTGCTRL read is wrong, so 3293 * check it again and jump to host mode if that was 3294 * the case. 3295 */ 3296 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3297 if (!(gotgctl & GOTGCTL_CONID_B)) 3298 goto host; 3299 if (++count > 250) 3300 break; 3301 } 3302 if (count > 250) 3303 dev_err(hsotg->dev, 3304 "Connection id status change timed out\n"); 3305 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 3306 dwc2_core_init(hsotg, false); 3307 dwc2_enable_global_interrupts(hsotg); 3308 spin_lock_irqsave(&hsotg->lock, flags); 3309 dwc2_hsotg_core_init_disconnected(hsotg, false); 3310 spin_unlock_irqrestore(&hsotg->lock, flags); 3311 /* Enable ACG feature in device mode,if supported */ 3312 dwc2_enable_acg(hsotg); 3313 dwc2_hsotg_core_connect(hsotg); 3314 } else { 3315 host: 3316 /* A-Device connector (Host Mode) */ 3317 dev_dbg(hsotg->dev, "connId A\n"); 3318 while (!dwc2_is_host_mode(hsotg)) { 3319 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 3320 dwc2_is_host_mode(hsotg) ? 3321 "Host" : "Peripheral"); 3322 msleep(20); 3323 if (++count > 250) 3324 break; 3325 } 3326 if (count > 250) 3327 dev_err(hsotg->dev, 3328 "Connection id status change timed out\n"); 3329 3330 spin_lock_irqsave(&hsotg->lock, flags); 3331 dwc2_hsotg_disconnect(hsotg); 3332 spin_unlock_irqrestore(&hsotg->lock, flags); 3333 3334 hsotg->op_state = OTG_STATE_A_HOST; 3335 /* Initialize the Core for Host mode */ 3336 dwc2_core_init(hsotg, false); 3337 dwc2_enable_global_interrupts(hsotg); 3338 dwc2_hcd_start(hsotg); 3339 } 3340 } 3341 3342 static void dwc2_wakeup_detected(struct timer_list *t) 3343 { 3344 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer); 3345 u32 hprt0; 3346 3347 dev_dbg(hsotg->dev, "%s()\n", __func__); 3348 3349 /* 3350 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 3351 * so that OPT tests pass with all PHYs.) 3352 */ 3353 hprt0 = dwc2_read_hprt0(hsotg); 3354 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 3355 hprt0 &= ~HPRT0_RES; 3356 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3357 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 3358 dwc2_readl(hsotg->regs + HPRT0)); 3359 3360 dwc2_hcd_rem_wakeup(hsotg); 3361 hsotg->bus_suspended = false; 3362 3363 /* Change to L0 state */ 3364 hsotg->lx_state = DWC2_L0; 3365 } 3366 3367 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 3368 { 3369 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 3370 3371 return hcd->self.b_hnp_enable; 3372 } 3373 3374 /* Must NOT be called with interrupt disabled or spinlock held */ 3375 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 3376 { 3377 unsigned long flags; 3378 u32 hprt0; 3379 u32 pcgctl; 3380 u32 gotgctl; 3381 3382 dev_dbg(hsotg->dev, "%s()\n", __func__); 3383 3384 spin_lock_irqsave(&hsotg->lock, flags); 3385 3386 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 3387 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 3388 gotgctl |= GOTGCTL_HSTSETHNPEN; 3389 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 3390 hsotg->op_state = OTG_STATE_A_SUSPEND; 3391 } 3392 3393 hprt0 = dwc2_read_hprt0(hsotg); 3394 hprt0 |= HPRT0_SUSP; 3395 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3396 3397 hsotg->bus_suspended = true; 3398 3399 /* 3400 * If power_down is supported, Phy clock will be suspended 3401 * after registers are backuped. 3402 */ 3403 if (!hsotg->params.power_down) { 3404 /* Suspend the Phy Clock */ 3405 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3406 pcgctl |= PCGCTL_STOPPCLK; 3407 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3408 udelay(10); 3409 } 3410 3411 /* For HNP the bus must be suspended for at least 200ms */ 3412 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 3413 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3414 pcgctl &= ~PCGCTL_STOPPCLK; 3415 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3416 3417 spin_unlock_irqrestore(&hsotg->lock, flags); 3418 3419 msleep(200); 3420 } else { 3421 spin_unlock_irqrestore(&hsotg->lock, flags); 3422 } 3423 } 3424 3425 /* Must NOT be called with interrupt disabled or spinlock held */ 3426 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 3427 { 3428 unsigned long flags; 3429 u32 hprt0; 3430 u32 pcgctl; 3431 3432 spin_lock_irqsave(&hsotg->lock, flags); 3433 3434 /* 3435 * If power_down is supported, Phy clock is already resumed 3436 * after registers restore. 3437 */ 3438 if (!hsotg->params.power_down) { 3439 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3440 pcgctl &= ~PCGCTL_STOPPCLK; 3441 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3442 spin_unlock_irqrestore(&hsotg->lock, flags); 3443 msleep(20); 3444 spin_lock_irqsave(&hsotg->lock, flags); 3445 } 3446 3447 hprt0 = dwc2_read_hprt0(hsotg); 3448 hprt0 |= HPRT0_RES; 3449 hprt0 &= ~HPRT0_SUSP; 3450 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3451 spin_unlock_irqrestore(&hsotg->lock, flags); 3452 3453 msleep(USB_RESUME_TIMEOUT); 3454 3455 spin_lock_irqsave(&hsotg->lock, flags); 3456 hprt0 = dwc2_read_hprt0(hsotg); 3457 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 3458 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3459 hsotg->bus_suspended = false; 3460 spin_unlock_irqrestore(&hsotg->lock, flags); 3461 } 3462 3463 /* Handles hub class-specific requests */ 3464 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 3465 u16 wvalue, u16 windex, char *buf, u16 wlength) 3466 { 3467 struct usb_hub_descriptor *hub_desc; 3468 int retval = 0; 3469 u32 hprt0; 3470 u32 port_status; 3471 u32 speed; 3472 u32 pcgctl; 3473 3474 switch (typereq) { 3475 case ClearHubFeature: 3476 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 3477 3478 switch (wvalue) { 3479 case C_HUB_LOCAL_POWER: 3480 case C_HUB_OVER_CURRENT: 3481 /* Nothing required here */ 3482 break; 3483 3484 default: 3485 retval = -EINVAL; 3486 dev_err(hsotg->dev, 3487 "ClearHubFeature request %1xh unknown\n", 3488 wvalue); 3489 } 3490 break; 3491 3492 case ClearPortFeature: 3493 if (wvalue != USB_PORT_FEAT_L1) 3494 if (!windex || windex > 1) 3495 goto error; 3496 switch (wvalue) { 3497 case USB_PORT_FEAT_ENABLE: 3498 dev_dbg(hsotg->dev, 3499 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 3500 hprt0 = dwc2_read_hprt0(hsotg); 3501 hprt0 |= HPRT0_ENA; 3502 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3503 break; 3504 3505 case USB_PORT_FEAT_SUSPEND: 3506 dev_dbg(hsotg->dev, 3507 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 3508 3509 if (hsotg->bus_suspended) 3510 dwc2_port_resume(hsotg); 3511 break; 3512 3513 case USB_PORT_FEAT_POWER: 3514 dev_dbg(hsotg->dev, 3515 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 3516 hprt0 = dwc2_read_hprt0(hsotg); 3517 hprt0 &= ~HPRT0_PWR; 3518 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3519 break; 3520 3521 case USB_PORT_FEAT_INDICATOR: 3522 dev_dbg(hsotg->dev, 3523 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 3524 /* Port indicator not supported */ 3525 break; 3526 3527 case USB_PORT_FEAT_C_CONNECTION: 3528 /* 3529 * Clears driver's internal Connect Status Change flag 3530 */ 3531 dev_dbg(hsotg->dev, 3532 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 3533 hsotg->flags.b.port_connect_status_change = 0; 3534 break; 3535 3536 case USB_PORT_FEAT_C_RESET: 3537 /* Clears driver's internal Port Reset Change flag */ 3538 dev_dbg(hsotg->dev, 3539 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 3540 hsotg->flags.b.port_reset_change = 0; 3541 break; 3542 3543 case USB_PORT_FEAT_C_ENABLE: 3544 /* 3545 * Clears the driver's internal Port Enable/Disable 3546 * Change flag 3547 */ 3548 dev_dbg(hsotg->dev, 3549 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 3550 hsotg->flags.b.port_enable_change = 0; 3551 break; 3552 3553 case USB_PORT_FEAT_C_SUSPEND: 3554 /* 3555 * Clears the driver's internal Port Suspend Change 3556 * flag, which is set when resume signaling on the host 3557 * port is complete 3558 */ 3559 dev_dbg(hsotg->dev, 3560 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 3561 hsotg->flags.b.port_suspend_change = 0; 3562 break; 3563 3564 case USB_PORT_FEAT_C_PORT_L1: 3565 dev_dbg(hsotg->dev, 3566 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 3567 hsotg->flags.b.port_l1_change = 0; 3568 break; 3569 3570 case USB_PORT_FEAT_C_OVER_CURRENT: 3571 dev_dbg(hsotg->dev, 3572 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 3573 hsotg->flags.b.port_over_current_change = 0; 3574 break; 3575 3576 default: 3577 retval = -EINVAL; 3578 dev_err(hsotg->dev, 3579 "ClearPortFeature request %1xh unknown or unsupported\n", 3580 wvalue); 3581 } 3582 break; 3583 3584 case GetHubDescriptor: 3585 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 3586 hub_desc = (struct usb_hub_descriptor *)buf; 3587 hub_desc->bDescLength = 9; 3588 hub_desc->bDescriptorType = USB_DT_HUB; 3589 hub_desc->bNbrPorts = 1; 3590 hub_desc->wHubCharacteristics = 3591 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 3592 HUB_CHAR_INDV_PORT_OCPM); 3593 hub_desc->bPwrOn2PwrGood = 1; 3594 hub_desc->bHubContrCurrent = 0; 3595 hub_desc->u.hs.DeviceRemovable[0] = 0; 3596 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 3597 break; 3598 3599 case GetHubStatus: 3600 dev_dbg(hsotg->dev, "GetHubStatus\n"); 3601 memset(buf, 0, 4); 3602 break; 3603 3604 case GetPortStatus: 3605 dev_vdbg(hsotg->dev, 3606 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 3607 hsotg->flags.d32); 3608 if (!windex || windex > 1) 3609 goto error; 3610 3611 port_status = 0; 3612 if (hsotg->flags.b.port_connect_status_change) 3613 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 3614 if (hsotg->flags.b.port_enable_change) 3615 port_status |= USB_PORT_STAT_C_ENABLE << 16; 3616 if (hsotg->flags.b.port_suspend_change) 3617 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 3618 if (hsotg->flags.b.port_l1_change) 3619 port_status |= USB_PORT_STAT_C_L1 << 16; 3620 if (hsotg->flags.b.port_reset_change) 3621 port_status |= USB_PORT_STAT_C_RESET << 16; 3622 if (hsotg->flags.b.port_over_current_change) { 3623 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 3624 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 3625 } 3626 3627 if (!hsotg->flags.b.port_connect_status) { 3628 /* 3629 * The port is disconnected, which means the core is 3630 * either in device mode or it soon will be. Just 3631 * return 0's for the remainder of the port status 3632 * since the port register can't be read if the core 3633 * is in device mode. 3634 */ 3635 *(__le32 *)buf = cpu_to_le32(port_status); 3636 break; 3637 } 3638 3639 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 3640 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 3641 3642 if (hprt0 & HPRT0_CONNSTS) 3643 port_status |= USB_PORT_STAT_CONNECTION; 3644 if (hprt0 & HPRT0_ENA) 3645 port_status |= USB_PORT_STAT_ENABLE; 3646 if (hprt0 & HPRT0_SUSP) 3647 port_status |= USB_PORT_STAT_SUSPEND; 3648 if (hprt0 & HPRT0_OVRCURRACT) 3649 port_status |= USB_PORT_STAT_OVERCURRENT; 3650 if (hprt0 & HPRT0_RST) 3651 port_status |= USB_PORT_STAT_RESET; 3652 if (hprt0 & HPRT0_PWR) 3653 port_status |= USB_PORT_STAT_POWER; 3654 3655 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 3656 if (speed == HPRT0_SPD_HIGH_SPEED) 3657 port_status |= USB_PORT_STAT_HIGH_SPEED; 3658 else if (speed == HPRT0_SPD_LOW_SPEED) 3659 port_status |= USB_PORT_STAT_LOW_SPEED; 3660 3661 if (hprt0 & HPRT0_TSTCTL_MASK) 3662 port_status |= USB_PORT_STAT_TEST; 3663 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 3664 3665 if (hsotg->params.dma_desc_fs_enable) { 3666 /* 3667 * Enable descriptor DMA only if a full speed 3668 * device is connected. 3669 */ 3670 if (hsotg->new_connection && 3671 ((port_status & 3672 (USB_PORT_STAT_CONNECTION | 3673 USB_PORT_STAT_HIGH_SPEED | 3674 USB_PORT_STAT_LOW_SPEED)) == 3675 USB_PORT_STAT_CONNECTION)) { 3676 u32 hcfg; 3677 3678 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 3679 hsotg->params.dma_desc_enable = true; 3680 hcfg = dwc2_readl(hsotg->regs + HCFG); 3681 hcfg |= HCFG_DESCDMA; 3682 dwc2_writel(hcfg, hsotg->regs + HCFG); 3683 hsotg->new_connection = false; 3684 } 3685 } 3686 3687 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 3688 *(__le32 *)buf = cpu_to_le32(port_status); 3689 break; 3690 3691 case SetHubFeature: 3692 dev_dbg(hsotg->dev, "SetHubFeature\n"); 3693 /* No HUB features supported */ 3694 break; 3695 3696 case SetPortFeature: 3697 dev_dbg(hsotg->dev, "SetPortFeature\n"); 3698 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 3699 goto error; 3700 3701 if (!hsotg->flags.b.port_connect_status) { 3702 /* 3703 * The port is disconnected, which means the core is 3704 * either in device mode or it soon will be. Just 3705 * return without doing anything since the port 3706 * register can't be written if the core is in device 3707 * mode. 3708 */ 3709 break; 3710 } 3711 3712 switch (wvalue) { 3713 case USB_PORT_FEAT_SUSPEND: 3714 dev_dbg(hsotg->dev, 3715 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 3716 if (windex != hsotg->otg_port) 3717 goto error; 3718 dwc2_port_suspend(hsotg, windex); 3719 break; 3720 3721 case USB_PORT_FEAT_POWER: 3722 dev_dbg(hsotg->dev, 3723 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 3724 hprt0 = dwc2_read_hprt0(hsotg); 3725 hprt0 |= HPRT0_PWR; 3726 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3727 break; 3728 3729 case USB_PORT_FEAT_RESET: 3730 hprt0 = dwc2_read_hprt0(hsotg); 3731 dev_dbg(hsotg->dev, 3732 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 3733 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 3734 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 3735 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 3736 /* ??? Original driver does this */ 3737 dwc2_writel(0, hsotg->regs + PCGCTL); 3738 3739 hprt0 = dwc2_read_hprt0(hsotg); 3740 /* Clear suspend bit if resetting from suspend state */ 3741 hprt0 &= ~HPRT0_SUSP; 3742 3743 /* 3744 * When B-Host the Port reset bit is set in the Start 3745 * HCD Callback function, so that the reset is started 3746 * within 1ms of the HNP success interrupt 3747 */ 3748 if (!dwc2_hcd_is_b_host(hsotg)) { 3749 hprt0 |= HPRT0_PWR | HPRT0_RST; 3750 dev_dbg(hsotg->dev, 3751 "In host mode, hprt0=%08x\n", hprt0); 3752 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3753 } 3754 3755 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 3756 msleep(50); 3757 hprt0 &= ~HPRT0_RST; 3758 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3759 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 3760 break; 3761 3762 case USB_PORT_FEAT_INDICATOR: 3763 dev_dbg(hsotg->dev, 3764 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 3765 /* Not supported */ 3766 break; 3767 3768 case USB_PORT_FEAT_TEST: 3769 hprt0 = dwc2_read_hprt0(hsotg); 3770 dev_dbg(hsotg->dev, 3771 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 3772 hprt0 &= ~HPRT0_TSTCTL_MASK; 3773 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 3774 dwc2_writel(hprt0, hsotg->regs + HPRT0); 3775 break; 3776 3777 default: 3778 retval = -EINVAL; 3779 dev_err(hsotg->dev, 3780 "SetPortFeature %1xh unknown or unsupported\n", 3781 wvalue); 3782 break; 3783 } 3784 break; 3785 3786 default: 3787 error: 3788 retval = -EINVAL; 3789 dev_dbg(hsotg->dev, 3790 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 3791 typereq, windex, wvalue); 3792 break; 3793 } 3794 3795 return retval; 3796 } 3797 3798 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 3799 { 3800 int retval; 3801 3802 if (port != 1) 3803 return -EINVAL; 3804 3805 retval = (hsotg->flags.b.port_connect_status_change || 3806 hsotg->flags.b.port_reset_change || 3807 hsotg->flags.b.port_enable_change || 3808 hsotg->flags.b.port_suspend_change || 3809 hsotg->flags.b.port_over_current_change); 3810 3811 if (retval) { 3812 dev_dbg(hsotg->dev, 3813 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 3814 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 3815 hsotg->flags.b.port_connect_status_change); 3816 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 3817 hsotg->flags.b.port_reset_change); 3818 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 3819 hsotg->flags.b.port_enable_change); 3820 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 3821 hsotg->flags.b.port_suspend_change); 3822 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 3823 hsotg->flags.b.port_over_current_change); 3824 } 3825 3826 return retval; 3827 } 3828 3829 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 3830 { 3831 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3832 3833 #ifdef DWC2_DEBUG_SOF 3834 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 3835 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 3836 #endif 3837 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3838 } 3839 3840 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) 3841 { 3842 u32 hprt = dwc2_readl(hsotg->regs + HPRT0); 3843 u32 hfir = dwc2_readl(hsotg->regs + HFIR); 3844 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3845 unsigned int us_per_frame; 3846 unsigned int frame_number; 3847 unsigned int remaining; 3848 unsigned int interval; 3849 unsigned int phy_clks; 3850 3851 /* High speed has 125 us per (micro) frame; others are 1 ms per */ 3852 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125; 3853 3854 /* Extract fields */ 3855 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 3856 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT; 3857 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT; 3858 3859 /* 3860 * Number of phy clocks since the last tick of the frame number after 3861 * "us" has passed. 3862 */ 3863 phy_clks = (interval - remaining) + 3864 DIV_ROUND_UP(interval * us, us_per_frame); 3865 3866 return dwc2_frame_num_inc(frame_number, phy_clks / interval); 3867 } 3868 3869 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 3870 { 3871 return hsotg->op_state == OTG_STATE_B_HOST; 3872 } 3873 3874 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 3875 int iso_desc_count, 3876 gfp_t mem_flags) 3877 { 3878 struct dwc2_hcd_urb *urb; 3879 u32 size = sizeof(*urb) + iso_desc_count * 3880 sizeof(struct dwc2_hcd_iso_packet_desc); 3881 3882 urb = kzalloc(size, mem_flags); 3883 if (urb) 3884 urb->packet_count = iso_desc_count; 3885 return urb; 3886 } 3887 3888 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 3889 struct dwc2_hcd_urb *urb, u8 dev_addr, 3890 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 3891 { 3892 if (dbg_perio() || 3893 ep_type == USB_ENDPOINT_XFER_BULK || 3894 ep_type == USB_ENDPOINT_XFER_CONTROL) 3895 dev_vdbg(hsotg->dev, 3896 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 3897 dev_addr, ep_num, ep_dir, ep_type, mps); 3898 urb->pipe_info.dev_addr = dev_addr; 3899 urb->pipe_info.ep_num = ep_num; 3900 urb->pipe_info.pipe_type = ep_type; 3901 urb->pipe_info.pipe_dir = ep_dir; 3902 urb->pipe_info.mps = mps; 3903 } 3904 3905 /* 3906 * NOTE: This function will be removed once the peripheral controller code 3907 * is integrated and the driver is stable 3908 */ 3909 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 3910 { 3911 #ifdef DEBUG 3912 struct dwc2_host_chan *chan; 3913 struct dwc2_hcd_urb *urb; 3914 struct dwc2_qtd *qtd; 3915 int num_channels; 3916 u32 np_tx_status; 3917 u32 p_tx_status; 3918 int i; 3919 3920 num_channels = hsotg->params.host_channels; 3921 dev_dbg(hsotg->dev, "\n"); 3922 dev_dbg(hsotg->dev, 3923 "************************************************************\n"); 3924 dev_dbg(hsotg->dev, "HCD State:\n"); 3925 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 3926 3927 for (i = 0; i < num_channels; i++) { 3928 chan = hsotg->hc_ptr_array[i]; 3929 dev_dbg(hsotg->dev, " Channel %d:\n", i); 3930 dev_dbg(hsotg->dev, 3931 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 3932 chan->dev_addr, chan->ep_num, chan->ep_is_in); 3933 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 3934 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 3935 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 3936 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 3937 chan->data_pid_start); 3938 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 3939 dev_dbg(hsotg->dev, " xfer_started: %d\n", 3940 chan->xfer_started); 3941 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 3942 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 3943 (unsigned long)chan->xfer_dma); 3944 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 3945 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 3946 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 3947 chan->halt_on_queue); 3948 dev_dbg(hsotg->dev, " halt_pending: %d\n", 3949 chan->halt_pending); 3950 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 3951 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 3952 dev_dbg(hsotg->dev, " complete_split: %d\n", 3953 chan->complete_split); 3954 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 3955 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 3956 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 3957 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 3958 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 3959 3960 if (chan->xfer_started) { 3961 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 3962 3963 hfnum = dwc2_readl(hsotg->regs + HFNUM); 3964 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 3965 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 3966 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 3967 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 3968 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 3969 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 3970 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 3971 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 3972 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 3973 } 3974 3975 if (!(chan->xfer_started && chan->qh)) 3976 continue; 3977 3978 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 3979 if (!qtd->in_process) 3980 break; 3981 urb = qtd->urb; 3982 dev_dbg(hsotg->dev, " URB Info:\n"); 3983 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 3984 qtd, urb); 3985 if (urb) { 3986 dev_dbg(hsotg->dev, 3987 " Dev: %d, EP: %d %s\n", 3988 dwc2_hcd_get_dev_addr(&urb->pipe_info), 3989 dwc2_hcd_get_ep_num(&urb->pipe_info), 3990 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 3991 "IN" : "OUT"); 3992 dev_dbg(hsotg->dev, 3993 " Max packet size: %d\n", 3994 dwc2_hcd_get_mps(&urb->pipe_info)); 3995 dev_dbg(hsotg->dev, 3996 " transfer_buffer: %p\n", 3997 urb->buf); 3998 dev_dbg(hsotg->dev, 3999 " transfer_dma: %08lx\n", 4000 (unsigned long)urb->dma); 4001 dev_dbg(hsotg->dev, 4002 " transfer_buffer_length: %d\n", 4003 urb->length); 4004 dev_dbg(hsotg->dev, " actual_length: %d\n", 4005 urb->actual_length); 4006 } 4007 } 4008 } 4009 4010 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 4011 hsotg->non_periodic_channels); 4012 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 4013 hsotg->periodic_channels); 4014 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 4015 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 4016 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 4017 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4018 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 4019 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4020 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 4021 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 4022 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 4023 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 4024 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 4025 dwc2_dump_global_registers(hsotg); 4026 dwc2_dump_host_registers(hsotg); 4027 dev_dbg(hsotg->dev, 4028 "************************************************************\n"); 4029 dev_dbg(hsotg->dev, "\n"); 4030 #endif 4031 } 4032 4033 struct wrapper_priv_data { 4034 struct dwc2_hsotg *hsotg; 4035 }; 4036 4037 /* Gets the dwc2_hsotg from a usb_hcd */ 4038 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 4039 { 4040 struct wrapper_priv_data *p; 4041 4042 p = (struct wrapper_priv_data *)&hcd->hcd_priv; 4043 return p->hsotg; 4044 } 4045 4046 /** 4047 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context 4048 * 4049 * This will get the dwc2_tt structure (and ttport) associated with the given 4050 * context (which is really just a struct urb pointer). 4051 * 4052 * The first time this is called for a given TT we allocate memory for our 4053 * structure. When everyone is done and has called dwc2_host_put_tt_info() 4054 * then the refcount for the structure will go to 0 and we'll free it. 4055 * 4056 * @hsotg: The HCD state structure for the DWC OTG controller. 4057 * @qh: The QH structure. 4058 * @context: The priv pointer from a struct dwc2_hcd_urb. 4059 * @mem_flags: Flags for allocating memory. 4060 * @ttport: We'll return this device's port number here. That's used to 4061 * reference into the bitmap if we're on a multi_tt hub. 4062 * 4063 * Return: a pointer to a struct dwc2_tt. Don't forget to call 4064 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure. 4065 */ 4066 4067 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context, 4068 gfp_t mem_flags, int *ttport) 4069 { 4070 struct urb *urb = context; 4071 struct dwc2_tt *dwc_tt = NULL; 4072 4073 if (urb->dev->tt) { 4074 *ttport = urb->dev->ttport; 4075 4076 dwc_tt = urb->dev->tt->hcpriv; 4077 if (!dwc_tt) { 4078 size_t bitmap_size; 4079 4080 /* 4081 * For single_tt we need one schedule. For multi_tt 4082 * we need one per port. 4083 */ 4084 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP * 4085 sizeof(dwc_tt->periodic_bitmaps[0]); 4086 if (urb->dev->tt->multi) 4087 bitmap_size *= urb->dev->tt->hub->maxchild; 4088 4089 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size, 4090 mem_flags); 4091 if (!dwc_tt) 4092 return NULL; 4093 4094 dwc_tt->usb_tt = urb->dev->tt; 4095 dwc_tt->usb_tt->hcpriv = dwc_tt; 4096 } 4097 4098 dwc_tt->refcount++; 4099 } 4100 4101 return dwc_tt; 4102 } 4103 4104 /** 4105 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info() 4106 * 4107 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders 4108 * of the structure are done. 4109 * 4110 * It's OK to call this with NULL. 4111 * 4112 * @hsotg: The HCD state structure for the DWC OTG controller. 4113 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info. 4114 */ 4115 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt) 4116 { 4117 /* Model kfree and make put of NULL a no-op */ 4118 if (!dwc_tt) 4119 return; 4120 4121 WARN_ON(dwc_tt->refcount < 1); 4122 4123 dwc_tt->refcount--; 4124 if (!dwc_tt->refcount) { 4125 dwc_tt->usb_tt->hcpriv = NULL; 4126 kfree(dwc_tt); 4127 } 4128 } 4129 4130 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 4131 { 4132 struct urb *urb = context; 4133 4134 return urb->dev->speed; 4135 } 4136 4137 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4138 struct urb *urb) 4139 { 4140 struct usb_bus *bus = hcd_to_bus(hcd); 4141 4142 if (urb->interval) 4143 bus->bandwidth_allocated += bw / urb->interval; 4144 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4145 bus->bandwidth_isoc_reqs++; 4146 else 4147 bus->bandwidth_int_reqs++; 4148 } 4149 4150 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 4151 struct urb *urb) 4152 { 4153 struct usb_bus *bus = hcd_to_bus(hcd); 4154 4155 if (urb->interval) 4156 bus->bandwidth_allocated -= bw / urb->interval; 4157 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 4158 bus->bandwidth_isoc_reqs--; 4159 else 4160 bus->bandwidth_int_reqs--; 4161 } 4162 4163 /* 4164 * Sets the final status of an URB and returns it to the upper layer. Any 4165 * required cleanup of the URB is performed. 4166 * 4167 * Must be called with interrupt disabled and spinlock held 4168 */ 4169 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 4170 int status) 4171 { 4172 struct urb *urb; 4173 int i; 4174 4175 if (!qtd) { 4176 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 4177 return; 4178 } 4179 4180 if (!qtd->urb) { 4181 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 4182 return; 4183 } 4184 4185 urb = qtd->urb->priv; 4186 if (!urb) { 4187 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 4188 return; 4189 } 4190 4191 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 4192 4193 if (dbg_urb(urb)) 4194 dev_vdbg(hsotg->dev, 4195 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 4196 __func__, urb, usb_pipedevice(urb->pipe), 4197 usb_pipeendpoint(urb->pipe), 4198 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 4199 urb->actual_length); 4200 4201 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4202 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 4203 for (i = 0; i < urb->number_of_packets; ++i) { 4204 urb->iso_frame_desc[i].actual_length = 4205 dwc2_hcd_urb_get_iso_desc_actual_length( 4206 qtd->urb, i); 4207 urb->iso_frame_desc[i].status = 4208 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 4209 } 4210 } 4211 4212 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 4213 for (i = 0; i < urb->number_of_packets; i++) 4214 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 4215 i, urb->iso_frame_desc[i].status); 4216 } 4217 4218 urb->status = status; 4219 if (!status) { 4220 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 4221 urb->actual_length < urb->transfer_buffer_length) 4222 urb->status = -EREMOTEIO; 4223 } 4224 4225 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4226 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4227 struct usb_host_endpoint *ep = urb->ep; 4228 4229 if (ep) 4230 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 4231 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4232 urb); 4233 } 4234 4235 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 4236 urb->hcpriv = NULL; 4237 kfree(qtd->urb); 4238 qtd->urb = NULL; 4239 4240 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 4241 } 4242 4243 /* 4244 * Work queue function for starting the HCD when A-Cable is connected 4245 */ 4246 static void dwc2_hcd_start_func(struct work_struct *work) 4247 { 4248 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4249 start_work.work); 4250 4251 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 4252 dwc2_host_start(hsotg); 4253 } 4254 4255 /* 4256 * Reset work queue function 4257 */ 4258 static void dwc2_hcd_reset_func(struct work_struct *work) 4259 { 4260 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 4261 reset_work.work); 4262 unsigned long flags; 4263 u32 hprt0; 4264 4265 dev_dbg(hsotg->dev, "USB RESET function called\n"); 4266 4267 spin_lock_irqsave(&hsotg->lock, flags); 4268 4269 hprt0 = dwc2_read_hprt0(hsotg); 4270 hprt0 &= ~HPRT0_RST; 4271 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4272 hsotg->flags.b.port_reset_change = 1; 4273 4274 spin_unlock_irqrestore(&hsotg->lock, flags); 4275 } 4276 4277 /* 4278 * ========================================================================= 4279 * Linux HC Driver Functions 4280 * ========================================================================= 4281 */ 4282 4283 /* 4284 * Initializes the DWC_otg controller and its root hub and prepares it for host 4285 * mode operation. Activates the root port. Returns 0 on success and a negative 4286 * error code on failure. 4287 */ 4288 static int _dwc2_hcd_start(struct usb_hcd *hcd) 4289 { 4290 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4291 struct usb_bus *bus = hcd_to_bus(hcd); 4292 unsigned long flags; 4293 4294 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 4295 4296 spin_lock_irqsave(&hsotg->lock, flags); 4297 hsotg->lx_state = DWC2_L0; 4298 hcd->state = HC_STATE_RUNNING; 4299 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4300 4301 if (dwc2_is_device_mode(hsotg)) { 4302 spin_unlock_irqrestore(&hsotg->lock, flags); 4303 return 0; /* why 0 ?? */ 4304 } 4305 4306 dwc2_hcd_reinit(hsotg); 4307 4308 /* Initialize and connect root hub if one is not already attached */ 4309 if (bus->root_hub) { 4310 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 4311 /* Inform the HUB driver to resume */ 4312 usb_hcd_resume_root_hub(hcd); 4313 } 4314 4315 spin_unlock_irqrestore(&hsotg->lock, flags); 4316 return 0; 4317 } 4318 4319 /* 4320 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 4321 * stopped. 4322 */ 4323 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 4324 { 4325 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4326 unsigned long flags; 4327 4328 /* Turn off all host-specific interrupts */ 4329 dwc2_disable_host_interrupts(hsotg); 4330 4331 /* Wait for interrupt processing to finish */ 4332 synchronize_irq(hcd->irq); 4333 4334 spin_lock_irqsave(&hsotg->lock, flags); 4335 /* Ensure hcd is disconnected */ 4336 dwc2_hcd_disconnect(hsotg, true); 4337 dwc2_hcd_stop(hsotg); 4338 hsotg->lx_state = DWC2_L3; 4339 hcd->state = HC_STATE_HALT; 4340 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4341 spin_unlock_irqrestore(&hsotg->lock, flags); 4342 4343 usleep_range(1000, 3000); 4344 } 4345 4346 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 4347 { 4348 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4349 unsigned long flags; 4350 int ret = 0; 4351 u32 hprt0; 4352 4353 spin_lock_irqsave(&hsotg->lock, flags); 4354 4355 if (dwc2_is_device_mode(hsotg)) 4356 goto unlock; 4357 4358 if (hsotg->lx_state != DWC2_L0) 4359 goto unlock; 4360 4361 if (!HCD_HW_ACCESSIBLE(hcd)) 4362 goto unlock; 4363 4364 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL) 4365 goto unlock; 4366 4367 if (!hsotg->params.power_down) 4368 goto skip_power_saving; 4369 4370 /* 4371 * Drive USB suspend and disable port Power 4372 * if usb bus is not suspended. 4373 */ 4374 if (!hsotg->bus_suspended) { 4375 hprt0 = dwc2_read_hprt0(hsotg); 4376 hprt0 |= HPRT0_SUSP; 4377 hprt0 &= ~HPRT0_PWR; 4378 dwc2_writel(hprt0, hsotg->regs + HPRT0); 4379 } 4380 4381 /* Enter partial_power_down */ 4382 ret = dwc2_enter_partial_power_down(hsotg); 4383 if (ret) { 4384 if (ret != -ENOTSUPP) 4385 dev_err(hsotg->dev, 4386 "enter partial_power_down failed\n"); 4387 goto skip_power_saving; 4388 } 4389 4390 /* Ask phy to be suspended */ 4391 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4392 spin_unlock_irqrestore(&hsotg->lock, flags); 4393 usb_phy_set_suspend(hsotg->uphy, true); 4394 spin_lock_irqsave(&hsotg->lock, flags); 4395 } 4396 4397 /* After entering partial_power_down, hardware is no more accessible */ 4398 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4399 4400 skip_power_saving: 4401 hsotg->lx_state = DWC2_L2; 4402 unlock: 4403 spin_unlock_irqrestore(&hsotg->lock, flags); 4404 4405 return ret; 4406 } 4407 4408 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 4409 { 4410 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4411 unsigned long flags; 4412 int ret = 0; 4413 4414 spin_lock_irqsave(&hsotg->lock, flags); 4415 4416 if (dwc2_is_device_mode(hsotg)) 4417 goto unlock; 4418 4419 if (hsotg->lx_state != DWC2_L2) 4420 goto unlock; 4421 4422 if (!hsotg->params.power_down) { 4423 hsotg->lx_state = DWC2_L0; 4424 goto unlock; 4425 } 4426 4427 /* 4428 * Set HW accessible bit before powering on the controller 4429 * since an interrupt may rise. 4430 */ 4431 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 4432 4433 /* 4434 * Enable power if not already done. 4435 * This must not be spinlocked since duration 4436 * of this call is unknown. 4437 */ 4438 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 4439 spin_unlock_irqrestore(&hsotg->lock, flags); 4440 usb_phy_set_suspend(hsotg->uphy, false); 4441 spin_lock_irqsave(&hsotg->lock, flags); 4442 } 4443 4444 /* Exit partial_power_down */ 4445 ret = dwc2_exit_partial_power_down(hsotg, true); 4446 if (ret && (ret != -ENOTSUPP)) 4447 dev_err(hsotg->dev, "exit partial_power_down failed\n"); 4448 4449 hsotg->lx_state = DWC2_L0; 4450 4451 spin_unlock_irqrestore(&hsotg->lock, flags); 4452 4453 if (hsotg->bus_suspended) { 4454 spin_lock_irqsave(&hsotg->lock, flags); 4455 hsotg->flags.b.port_suspend_change = 1; 4456 spin_unlock_irqrestore(&hsotg->lock, flags); 4457 dwc2_port_resume(hsotg); 4458 } else { 4459 /* Wait for controller to correctly update D+/D- level */ 4460 usleep_range(3000, 5000); 4461 4462 /* 4463 * Clear Port Enable and Port Status changes. 4464 * Enable Port Power. 4465 */ 4466 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 4467 HPRT0_ENACHG, hsotg->regs + HPRT0); 4468 /* Wait for controller to detect Port Connect */ 4469 usleep_range(5000, 7000); 4470 } 4471 4472 return ret; 4473 unlock: 4474 spin_unlock_irqrestore(&hsotg->lock, flags); 4475 4476 return ret; 4477 } 4478 4479 /* Returns the current frame number */ 4480 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 4481 { 4482 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4483 4484 return dwc2_hcd_get_frame_number(hsotg); 4485 } 4486 4487 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 4488 char *fn_name) 4489 { 4490 #ifdef VERBOSE_DEBUG 4491 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4492 char *pipetype = NULL; 4493 char *speed = NULL; 4494 4495 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 4496 dev_vdbg(hsotg->dev, " Device address: %d\n", 4497 usb_pipedevice(urb->pipe)); 4498 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 4499 usb_pipeendpoint(urb->pipe), 4500 usb_pipein(urb->pipe) ? "IN" : "OUT"); 4501 4502 switch (usb_pipetype(urb->pipe)) { 4503 case PIPE_CONTROL: 4504 pipetype = "CONTROL"; 4505 break; 4506 case PIPE_BULK: 4507 pipetype = "BULK"; 4508 break; 4509 case PIPE_INTERRUPT: 4510 pipetype = "INTERRUPT"; 4511 break; 4512 case PIPE_ISOCHRONOUS: 4513 pipetype = "ISOCHRONOUS"; 4514 break; 4515 } 4516 4517 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 4518 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 4519 "IN" : "OUT"); 4520 4521 switch (urb->dev->speed) { 4522 case USB_SPEED_HIGH: 4523 speed = "HIGH"; 4524 break; 4525 case USB_SPEED_FULL: 4526 speed = "FULL"; 4527 break; 4528 case USB_SPEED_LOW: 4529 speed = "LOW"; 4530 break; 4531 default: 4532 speed = "UNKNOWN"; 4533 break; 4534 } 4535 4536 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 4537 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 4538 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 4539 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 4540 urb->transfer_buffer_length); 4541 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 4542 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 4543 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 4544 urb->setup_packet, (unsigned long)urb->setup_dma); 4545 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 4546 4547 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 4548 int i; 4549 4550 for (i = 0; i < urb->number_of_packets; i++) { 4551 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 4552 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 4553 urb->iso_frame_desc[i].offset, 4554 urb->iso_frame_desc[i].length); 4555 } 4556 } 4557 #endif 4558 } 4559 4560 /* 4561 * Starts processing a USB transfer request specified by a USB Request Block 4562 * (URB). mem_flags indicates the type of memory allocation to use while 4563 * processing this URB. 4564 */ 4565 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 4566 gfp_t mem_flags) 4567 { 4568 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4569 struct usb_host_endpoint *ep = urb->ep; 4570 struct dwc2_hcd_urb *dwc2_urb; 4571 int i; 4572 int retval; 4573 int alloc_bandwidth = 0; 4574 u8 ep_type = 0; 4575 u32 tflags = 0; 4576 void *buf; 4577 unsigned long flags; 4578 struct dwc2_qh *qh; 4579 bool qh_allocated = false; 4580 struct dwc2_qtd *qtd; 4581 4582 if (dbg_urb(urb)) { 4583 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 4584 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 4585 } 4586 4587 if (!ep) 4588 return -EINVAL; 4589 4590 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 4591 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 4592 spin_lock_irqsave(&hsotg->lock, flags); 4593 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 4594 alloc_bandwidth = 1; 4595 spin_unlock_irqrestore(&hsotg->lock, flags); 4596 } 4597 4598 switch (usb_pipetype(urb->pipe)) { 4599 case PIPE_CONTROL: 4600 ep_type = USB_ENDPOINT_XFER_CONTROL; 4601 break; 4602 case PIPE_ISOCHRONOUS: 4603 ep_type = USB_ENDPOINT_XFER_ISOC; 4604 break; 4605 case PIPE_BULK: 4606 ep_type = USB_ENDPOINT_XFER_BULK; 4607 break; 4608 case PIPE_INTERRUPT: 4609 ep_type = USB_ENDPOINT_XFER_INT; 4610 break; 4611 } 4612 4613 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 4614 mem_flags); 4615 if (!dwc2_urb) 4616 return -ENOMEM; 4617 4618 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 4619 usb_pipeendpoint(urb->pipe), ep_type, 4620 usb_pipein(urb->pipe), 4621 usb_maxpacket(urb->dev, urb->pipe, 4622 !(usb_pipein(urb->pipe)))); 4623 4624 buf = urb->transfer_buffer; 4625 4626 if (hcd->self.uses_dma) { 4627 if (!buf && (urb->transfer_dma & 3)) { 4628 dev_err(hsotg->dev, 4629 "%s: unaligned transfer with no transfer_buffer", 4630 __func__); 4631 retval = -EINVAL; 4632 goto fail0; 4633 } 4634 } 4635 4636 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 4637 tflags |= URB_GIVEBACK_ASAP; 4638 if (urb->transfer_flags & URB_ZERO_PACKET) 4639 tflags |= URB_SEND_ZERO_PACKET; 4640 4641 dwc2_urb->priv = urb; 4642 dwc2_urb->buf = buf; 4643 dwc2_urb->dma = urb->transfer_dma; 4644 dwc2_urb->length = urb->transfer_buffer_length; 4645 dwc2_urb->setup_packet = urb->setup_packet; 4646 dwc2_urb->setup_dma = urb->setup_dma; 4647 dwc2_urb->flags = tflags; 4648 dwc2_urb->interval = urb->interval; 4649 dwc2_urb->status = -EINPROGRESS; 4650 4651 for (i = 0; i < urb->number_of_packets; ++i) 4652 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 4653 urb->iso_frame_desc[i].offset, 4654 urb->iso_frame_desc[i].length); 4655 4656 urb->hcpriv = dwc2_urb; 4657 qh = (struct dwc2_qh *)ep->hcpriv; 4658 /* Create QH for the endpoint if it doesn't exist */ 4659 if (!qh) { 4660 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 4661 if (!qh) { 4662 retval = -ENOMEM; 4663 goto fail0; 4664 } 4665 ep->hcpriv = qh; 4666 qh_allocated = true; 4667 } 4668 4669 qtd = kzalloc(sizeof(*qtd), mem_flags); 4670 if (!qtd) { 4671 retval = -ENOMEM; 4672 goto fail1; 4673 } 4674 4675 spin_lock_irqsave(&hsotg->lock, flags); 4676 retval = usb_hcd_link_urb_to_ep(hcd, urb); 4677 if (retval) 4678 goto fail2; 4679 4680 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 4681 if (retval) 4682 goto fail3; 4683 4684 if (alloc_bandwidth) { 4685 dwc2_allocate_bus_bandwidth(hcd, 4686 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 4687 urb); 4688 } 4689 4690 spin_unlock_irqrestore(&hsotg->lock, flags); 4691 4692 return 0; 4693 4694 fail3: 4695 dwc2_urb->priv = NULL; 4696 usb_hcd_unlink_urb_from_ep(hcd, urb); 4697 if (qh_allocated && qh->channel && qh->channel->qh == qh) 4698 qh->channel->qh = NULL; 4699 fail2: 4700 spin_unlock_irqrestore(&hsotg->lock, flags); 4701 urb->hcpriv = NULL; 4702 kfree(qtd); 4703 qtd = NULL; 4704 fail1: 4705 if (qh_allocated) { 4706 struct dwc2_qtd *qtd2, *qtd2_tmp; 4707 4708 ep->hcpriv = NULL; 4709 dwc2_hcd_qh_unlink(hsotg, qh); 4710 /* Free each QTD in the QH's QTD list */ 4711 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 4712 qtd_list_entry) 4713 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 4714 dwc2_hcd_qh_free(hsotg, qh); 4715 } 4716 fail0: 4717 kfree(dwc2_urb); 4718 4719 return retval; 4720 } 4721 4722 /* 4723 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 4724 */ 4725 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 4726 int status) 4727 { 4728 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4729 int rc; 4730 unsigned long flags; 4731 4732 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 4733 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 4734 4735 spin_lock_irqsave(&hsotg->lock, flags); 4736 4737 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 4738 if (rc) 4739 goto out; 4740 4741 if (!urb->hcpriv) { 4742 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 4743 goto out; 4744 } 4745 4746 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 4747 4748 usb_hcd_unlink_urb_from_ep(hcd, urb); 4749 4750 kfree(urb->hcpriv); 4751 urb->hcpriv = NULL; 4752 4753 /* Higher layer software sets URB status */ 4754 spin_unlock(&hsotg->lock); 4755 usb_hcd_giveback_urb(hcd, urb, status); 4756 spin_lock(&hsotg->lock); 4757 4758 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 4759 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 4760 out: 4761 spin_unlock_irqrestore(&hsotg->lock, flags); 4762 4763 return rc; 4764 } 4765 4766 /* 4767 * Frees resources in the DWC_otg controller related to a given endpoint. Also 4768 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 4769 * must already be dequeued. 4770 */ 4771 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 4772 struct usb_host_endpoint *ep) 4773 { 4774 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4775 4776 dev_dbg(hsotg->dev, 4777 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 4778 ep->desc.bEndpointAddress, ep->hcpriv); 4779 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 4780 } 4781 4782 /* 4783 * Resets endpoint specific parameter values, in current version used to reset 4784 * the data toggle (as a WA). This function can be called from usb_clear_halt 4785 * routine. 4786 */ 4787 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 4788 struct usb_host_endpoint *ep) 4789 { 4790 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4791 unsigned long flags; 4792 4793 dev_dbg(hsotg->dev, 4794 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 4795 ep->desc.bEndpointAddress); 4796 4797 spin_lock_irqsave(&hsotg->lock, flags); 4798 dwc2_hcd_endpoint_reset(hsotg, ep); 4799 spin_unlock_irqrestore(&hsotg->lock, flags); 4800 } 4801 4802 /* 4803 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 4804 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 4805 * interrupt. 4806 * 4807 * This function is called by the USB core when an interrupt occurs 4808 */ 4809 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 4810 { 4811 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4812 4813 return dwc2_handle_hcd_intr(hsotg); 4814 } 4815 4816 /* 4817 * Creates Status Change bitmap for the root hub and root port. The bitmap is 4818 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 4819 * is the status change indicator for the single root port. Returns 1 if either 4820 * change indicator is 1, otherwise returns 0. 4821 */ 4822 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 4823 { 4824 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4825 4826 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 4827 return buf[0] != 0; 4828 } 4829 4830 /* Handles hub class-specific requests */ 4831 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 4832 u16 windex, char *buf, u16 wlength) 4833 { 4834 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 4835 wvalue, windex, buf, wlength); 4836 return retval; 4837 } 4838 4839 /* Handles hub TT buffer clear completions */ 4840 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 4841 struct usb_host_endpoint *ep) 4842 { 4843 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4844 struct dwc2_qh *qh; 4845 unsigned long flags; 4846 4847 qh = ep->hcpriv; 4848 if (!qh) 4849 return; 4850 4851 spin_lock_irqsave(&hsotg->lock, flags); 4852 qh->tt_buffer_dirty = 0; 4853 4854 if (hsotg->flags.b.port_connect_status) 4855 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 4856 4857 spin_unlock_irqrestore(&hsotg->lock, flags); 4858 } 4859 4860 /* 4861 * HPRT0_SPD_HIGH_SPEED: high speed 4862 * HPRT0_SPD_FULL_SPEED: full speed 4863 */ 4864 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed) 4865 { 4866 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4867 4868 if (hsotg->params.speed == speed) 4869 return; 4870 4871 hsotg->params.speed = speed; 4872 queue_work(hsotg->wq_otg, &hsotg->wf_otg); 4873 } 4874 4875 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev) 4876 { 4877 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4878 4879 if (!hsotg->params.change_speed_quirk) 4880 return; 4881 4882 /* 4883 * On removal, set speed to default high-speed. 4884 */ 4885 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN && 4886 udev->parent->speed < USB_SPEED_HIGH) { 4887 dev_info(hsotg->dev, "Set speed to default high-speed\n"); 4888 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4889 } 4890 } 4891 4892 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev) 4893 { 4894 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 4895 4896 if (!hsotg->params.change_speed_quirk) 4897 return 0; 4898 4899 if (udev->speed == USB_SPEED_HIGH) { 4900 dev_info(hsotg->dev, "Set speed to high-speed\n"); 4901 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED); 4902 } else if ((udev->speed == USB_SPEED_FULL || 4903 udev->speed == USB_SPEED_LOW)) { 4904 /* 4905 * Change speed setting to full-speed if there's 4906 * a full-speed or low-speed device plugged in. 4907 */ 4908 dev_info(hsotg->dev, "Set speed to full-speed\n"); 4909 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED); 4910 } 4911 4912 return 0; 4913 } 4914 4915 static struct hc_driver dwc2_hc_driver = { 4916 .description = "dwc2_hsotg", 4917 .product_desc = "DWC OTG Controller", 4918 .hcd_priv_size = sizeof(struct wrapper_priv_data), 4919 4920 .irq = _dwc2_hcd_irq, 4921 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH, 4922 4923 .start = _dwc2_hcd_start, 4924 .stop = _dwc2_hcd_stop, 4925 .urb_enqueue = _dwc2_hcd_urb_enqueue, 4926 .urb_dequeue = _dwc2_hcd_urb_dequeue, 4927 .endpoint_disable = _dwc2_hcd_endpoint_disable, 4928 .endpoint_reset = _dwc2_hcd_endpoint_reset, 4929 .get_frame_number = _dwc2_hcd_get_frame_number, 4930 4931 .hub_status_data = _dwc2_hcd_hub_status_data, 4932 .hub_control = _dwc2_hcd_hub_control, 4933 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 4934 4935 .bus_suspend = _dwc2_hcd_suspend, 4936 .bus_resume = _dwc2_hcd_resume, 4937 4938 .map_urb_for_dma = dwc2_map_urb_for_dma, 4939 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 4940 }; 4941 4942 /* 4943 * Frees secondary storage associated with the dwc2_hsotg structure contained 4944 * in the struct usb_hcd field 4945 */ 4946 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 4947 { 4948 u32 ahbcfg; 4949 u32 dctl; 4950 int i; 4951 4952 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 4953 4954 /* Free memory for QH/QTD lists */ 4955 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 4956 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting); 4957 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 4958 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 4959 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 4960 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 4961 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 4962 4963 /* Free memory for the host channels */ 4964 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 4965 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 4966 4967 if (chan) { 4968 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 4969 i, chan); 4970 hsotg->hc_ptr_array[i] = NULL; 4971 kfree(chan); 4972 } 4973 } 4974 4975 if (hsotg->params.host_dma) { 4976 if (hsotg->status_buf) { 4977 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 4978 hsotg->status_buf, 4979 hsotg->status_buf_dma); 4980 hsotg->status_buf = NULL; 4981 } 4982 } else { 4983 kfree(hsotg->status_buf); 4984 hsotg->status_buf = NULL; 4985 } 4986 4987 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 4988 4989 /* Disable all interrupts */ 4990 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 4991 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 4992 dwc2_writel(0, hsotg->regs + GINTMSK); 4993 4994 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 4995 dctl = dwc2_readl(hsotg->regs + DCTL); 4996 dctl |= DCTL_SFTDISCON; 4997 dwc2_writel(dctl, hsotg->regs + DCTL); 4998 } 4999 5000 if (hsotg->wq_otg) { 5001 if (!cancel_work_sync(&hsotg->wf_otg)) 5002 flush_workqueue(hsotg->wq_otg); 5003 destroy_workqueue(hsotg->wq_otg); 5004 } 5005 5006 del_timer(&hsotg->wkp_timer); 5007 } 5008 5009 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 5010 { 5011 /* Turn off all host-specific interrupts */ 5012 dwc2_disable_host_interrupts(hsotg); 5013 5014 dwc2_hcd_free(hsotg); 5015 } 5016 5017 /* 5018 * Initializes the HCD. This function allocates memory for and initializes the 5019 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 5020 * USB bus with the core and calls the hc_driver->start() function. It returns 5021 * a negative error on failure. 5022 */ 5023 int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 5024 { 5025 struct platform_device *pdev = to_platform_device(hsotg->dev); 5026 struct resource *res; 5027 struct usb_hcd *hcd; 5028 struct dwc2_host_chan *channel; 5029 u32 hcfg; 5030 int i, num_channels; 5031 int retval; 5032 5033 if (usb_disabled()) 5034 return -ENODEV; 5035 5036 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 5037 5038 retval = -ENOMEM; 5039 5040 hcfg = dwc2_readl(hsotg->regs + HCFG); 5041 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 5042 5043 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5044 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 5045 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5046 if (!hsotg->frame_num_array) 5047 goto error1; 5048 hsotg->last_frame_num_array = kzalloc( 5049 sizeof(*hsotg->last_frame_num_array) * 5050 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 5051 if (!hsotg->last_frame_num_array) 5052 goto error1; 5053 #endif 5054 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 5055 5056 /* Check if the bus driver or platform code has setup a dma_mask */ 5057 if (hsotg->params.host_dma && 5058 !hsotg->dev->dma_mask) { 5059 dev_warn(hsotg->dev, 5060 "dma_mask not set, disabling DMA\n"); 5061 hsotg->params.host_dma = false; 5062 hsotg->params.dma_desc_enable = false; 5063 } 5064 5065 /* Set device flags indicating whether the HCD supports DMA */ 5066 if (hsotg->params.host_dma) { 5067 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5068 dev_warn(hsotg->dev, "can't set DMA mask\n"); 5069 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 5070 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 5071 } 5072 5073 if (hsotg->params.change_speed_quirk) { 5074 dwc2_hc_driver.free_dev = dwc2_free_dev; 5075 dwc2_hc_driver.reset_device = dwc2_reset_device; 5076 } 5077 5078 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 5079 if (!hcd) 5080 goto error1; 5081 5082 if (!hsotg->params.host_dma) 5083 hcd->self.uses_dma = 0; 5084 5085 hcd->has_tt = 1; 5086 5087 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 5088 hcd->rsrc_start = res->start; 5089 hcd->rsrc_len = resource_size(res); 5090 5091 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg; 5092 hsotg->priv = hcd; 5093 5094 /* 5095 * Disable the global interrupt until all the interrupt handlers are 5096 * installed 5097 */ 5098 dwc2_disable_global_interrupts(hsotg); 5099 5100 /* Initialize the DWC_otg core, and select the Phy type */ 5101 retval = dwc2_core_init(hsotg, true); 5102 if (retval) 5103 goto error2; 5104 5105 /* Create new workqueue and init work */ 5106 retval = -ENOMEM; 5107 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0); 5108 if (!hsotg->wq_otg) { 5109 dev_err(hsotg->dev, "Failed to create workqueue\n"); 5110 goto error2; 5111 } 5112 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 5113 5114 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0); 5115 5116 /* Initialize the non-periodic schedule */ 5117 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 5118 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting); 5119 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 5120 5121 /* Initialize the periodic schedule */ 5122 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 5123 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 5124 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 5125 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 5126 5127 INIT_LIST_HEAD(&hsotg->split_order); 5128 5129 /* 5130 * Create a host channel descriptor for each host channel implemented 5131 * in the controller. Initialize the channel descriptor array. 5132 */ 5133 INIT_LIST_HEAD(&hsotg->free_hc_list); 5134 num_channels = hsotg->params.host_channels; 5135 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 5136 5137 for (i = 0; i < num_channels; i++) { 5138 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 5139 if (!channel) 5140 goto error3; 5141 channel->hc_num = i; 5142 INIT_LIST_HEAD(&channel->split_order_list_entry); 5143 hsotg->hc_ptr_array[i] = channel; 5144 } 5145 5146 /* Initialize hsotg start work */ 5147 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 5148 5149 /* Initialize port reset work */ 5150 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 5151 5152 /* 5153 * Allocate space for storing data on status transactions. Normally no 5154 * data is sent, but this space acts as a bit bucket. This must be 5155 * done after usb_add_hcd since that function allocates the DMA buffer 5156 * pool. 5157 */ 5158 if (hsotg->params.host_dma) 5159 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 5160 DWC2_HCD_STATUS_BUF_SIZE, 5161 &hsotg->status_buf_dma, GFP_KERNEL); 5162 else 5163 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 5164 GFP_KERNEL); 5165 5166 if (!hsotg->status_buf) 5167 goto error3; 5168 5169 /* 5170 * Create kmem caches to handle descriptor buffers in descriptor 5171 * DMA mode. 5172 * Alignment must be set to 512 bytes. 5173 */ 5174 if (hsotg->params.dma_desc_enable || 5175 hsotg->params.dma_desc_fs_enable) { 5176 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 5177 sizeof(struct dwc2_dma_desc) * 5178 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 5179 NULL); 5180 if (!hsotg->desc_gen_cache) { 5181 dev_err(hsotg->dev, 5182 "unable to create dwc2 generic desc cache\n"); 5183 5184 /* 5185 * Disable descriptor dma mode since it will not be 5186 * usable. 5187 */ 5188 hsotg->params.dma_desc_enable = false; 5189 hsotg->params.dma_desc_fs_enable = false; 5190 } 5191 5192 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 5193 sizeof(struct dwc2_dma_desc) * 5194 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 5195 if (!hsotg->desc_hsisoc_cache) { 5196 dev_err(hsotg->dev, 5197 "unable to create dwc2 hs isoc desc cache\n"); 5198 5199 kmem_cache_destroy(hsotg->desc_gen_cache); 5200 5201 /* 5202 * Disable descriptor dma mode since it will not be 5203 * usable. 5204 */ 5205 hsotg->params.dma_desc_enable = false; 5206 hsotg->params.dma_desc_fs_enable = false; 5207 } 5208 } 5209 5210 hsotg->otg_port = 1; 5211 hsotg->frame_list = NULL; 5212 hsotg->frame_list_dma = 0; 5213 hsotg->periodic_qh_count = 0; 5214 5215 /* Initiate lx_state to L3 disconnected state */ 5216 hsotg->lx_state = DWC2_L3; 5217 5218 hcd->self.otg_port = hsotg->otg_port; 5219 5220 /* Don't support SG list at this point */ 5221 hcd->self.sg_tablesize = 0; 5222 5223 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5224 otg_set_host(hsotg->uphy->otg, &hcd->self); 5225 5226 /* 5227 * Finish generic HCD initialization and start the HCD. This function 5228 * allocates the DMA buffer pool, registers the USB bus, requests the 5229 * IRQ line, and calls hcd_start method. 5230 */ 5231 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED); 5232 if (retval < 0) 5233 goto error4; 5234 5235 device_wakeup_enable(hcd->self.controller); 5236 5237 dwc2_hcd_dump_state(hsotg); 5238 5239 dwc2_enable_global_interrupts(hsotg); 5240 5241 return 0; 5242 5243 error4: 5244 kmem_cache_destroy(hsotg->desc_gen_cache); 5245 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5246 error3: 5247 dwc2_hcd_release(hsotg); 5248 error2: 5249 usb_put_hcd(hcd); 5250 error1: 5251 5252 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5253 kfree(hsotg->last_frame_num_array); 5254 kfree(hsotg->frame_num_array); 5255 #endif 5256 5257 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 5258 return retval; 5259 } 5260 5261 /* 5262 * Removes the HCD. 5263 * Frees memory and resources associated with the HCD and deregisters the bus. 5264 */ 5265 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 5266 { 5267 struct usb_hcd *hcd; 5268 5269 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 5270 5271 hcd = dwc2_hsotg_to_hcd(hsotg); 5272 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 5273 5274 if (!hcd) { 5275 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 5276 __func__); 5277 return; 5278 } 5279 5280 if (!IS_ERR_OR_NULL(hsotg->uphy)) 5281 otg_set_host(hsotg->uphy->otg, NULL); 5282 5283 usb_remove_hcd(hcd); 5284 hsotg->priv = NULL; 5285 5286 kmem_cache_destroy(hsotg->desc_gen_cache); 5287 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 5288 5289 dwc2_hcd_release(hsotg); 5290 usb_put_hcd(hcd); 5291 5292 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 5293 kfree(hsotg->last_frame_num_array); 5294 kfree(hsotg->frame_num_array); 5295 #endif 5296 } 5297 5298 /** 5299 * dwc2_backup_host_registers() - Backup controller host registers. 5300 * When suspending usb bus, registers needs to be backuped 5301 * if controller power is disabled once suspended. 5302 * 5303 * @hsotg: Programming view of the DWC_otg controller 5304 */ 5305 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) 5306 { 5307 struct dwc2_hregs_backup *hr; 5308 int i; 5309 5310 dev_dbg(hsotg->dev, "%s\n", __func__); 5311 5312 /* Backup Host regs */ 5313 hr = &hsotg->hr_backup; 5314 hr->hcfg = dwc2_readl(hsotg->regs + HCFG); 5315 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); 5316 for (i = 0; i < hsotg->params.host_channels; ++i) 5317 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); 5318 5319 hr->hprt0 = dwc2_read_hprt0(hsotg); 5320 hr->hfir = dwc2_readl(hsotg->regs + HFIR); 5321 hr->valid = true; 5322 5323 return 0; 5324 } 5325 5326 /** 5327 * dwc2_restore_host_registers() - Restore controller host registers. 5328 * When resuming usb bus, device registers needs to be restored 5329 * if controller power were disabled. 5330 * 5331 * @hsotg: Programming view of the DWC_otg controller 5332 */ 5333 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) 5334 { 5335 struct dwc2_hregs_backup *hr; 5336 int i; 5337 5338 dev_dbg(hsotg->dev, "%s\n", __func__); 5339 5340 /* Restore host regs */ 5341 hr = &hsotg->hr_backup; 5342 if (!hr->valid) { 5343 dev_err(hsotg->dev, "%s: no host registers to restore\n", 5344 __func__); 5345 return -EINVAL; 5346 } 5347 hr->valid = false; 5348 5349 dwc2_writel(hr->hcfg, hsotg->regs + HCFG); 5350 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); 5351 5352 for (i = 0; i < hsotg->params.host_channels; ++i) 5353 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); 5354 5355 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); 5356 dwc2_writel(hr->hfir, hsotg->regs + HFIR); 5357 hsotg->frame_number = 0; 5358 5359 return 0; 5360 } 5361