1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 spin_unlock_irqrestore(&hsotg->lock, flags); 168 dwc2_hcd_qh_free(hsotg, qh); 169 spin_lock_irqsave(&hsotg->lock, flags); 170 } 171 172 spin_unlock_irqrestore(&hsotg->lock, flags); 173 } 174 175 /* 176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 177 * and periodic schedules. The QTD associated with each URB is removed from 178 * the schedule and freed. This function may be called when a disconnect is 179 * detected or when the HCD is being stopped. 180 * 181 * Must be called with interrupt disabled and spinlock held 182 */ 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 184 { 185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 191 } 192 193 /** 194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 195 * 196 * @hsotg: Pointer to struct dwc2_hsotg 197 */ 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 199 { 200 u32 hprt0; 201 202 if (hsotg->op_state == OTG_STATE_B_HOST) { 203 /* 204 * Reset the port. During a HNP mode switch the reset 205 * needs to occur within 1ms and have a duration of at 206 * least 50ms. 207 */ 208 hprt0 = dwc2_read_hprt0(hsotg); 209 hprt0 |= HPRT0_RST; 210 writel(hprt0, hsotg->regs + HPRT0); 211 } 212 213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 214 msecs_to_jiffies(50)); 215 } 216 217 /* Must be called with interrupt disabled and spinlock held */ 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 219 { 220 int num_channels = hsotg->core_params->host_channels; 221 struct dwc2_host_chan *channel; 222 u32 hcchar; 223 int i; 224 225 if (hsotg->core_params->dma_enable <= 0) { 226 /* Flush out any channel requests in slave mode */ 227 for (i = 0; i < num_channels; i++) { 228 channel = hsotg->hc_ptr_array[i]; 229 if (!list_empty(&channel->hc_list_entry)) 230 continue; 231 hcchar = readl(hsotg->regs + HCCHAR(i)); 232 if (hcchar & HCCHAR_CHENA) { 233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 234 hcchar |= HCCHAR_CHDIS; 235 writel(hcchar, hsotg->regs + HCCHAR(i)); 236 } 237 } 238 } 239 240 for (i = 0; i < num_channels; i++) { 241 channel = hsotg->hc_ptr_array[i]; 242 if (!list_empty(&channel->hc_list_entry)) 243 continue; 244 hcchar = readl(hsotg->regs + HCCHAR(i)); 245 if (hcchar & HCCHAR_CHENA) { 246 /* Halt the channel */ 247 hcchar |= HCCHAR_CHDIS; 248 writel(hcchar, hsotg->regs + HCCHAR(i)); 249 } 250 251 dwc2_hc_cleanup(hsotg, channel); 252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 253 /* 254 * Added for Descriptor DMA to prevent channel double cleanup in 255 * release_channel_ddma(), which is called from ep_disable when 256 * device disconnects 257 */ 258 channel->qh = NULL; 259 } 260 /* All channels have been freed, mark them available */ 261 if (hsotg->core_params->uframe_sched > 0) { 262 hsotg->available_host_channels = 263 hsotg->core_params->host_channels; 264 } else { 265 hsotg->non_periodic_channels = 0; 266 hsotg->periodic_channels = 0; 267 } 268 } 269 270 /** 271 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 272 * 273 * @hsotg: Pointer to struct dwc2_hsotg 274 * 275 * Must be called with interrupt disabled and spinlock held 276 */ 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg) 278 { 279 u32 intr; 280 281 /* Set status flags for the hub driver */ 282 hsotg->flags.b.port_connect_status_change = 1; 283 hsotg->flags.b.port_connect_status = 0; 284 285 /* 286 * Shutdown any transfers in process by clearing the Tx FIFO Empty 287 * interrupt mask and status bits and disabling subsequent host 288 * channel interrupts. 289 */ 290 intr = readl(hsotg->regs + GINTMSK); 291 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 292 writel(intr, hsotg->regs + GINTMSK); 293 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 294 writel(intr, hsotg->regs + GINTSTS); 295 296 /* 297 * Turn off the vbus power only if the core has transitioned to device 298 * mode. If still in host mode, need to keep power on to detect a 299 * reconnection. 300 */ 301 if (dwc2_is_device_mode(hsotg)) { 302 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 303 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 304 writel(0, hsotg->regs + HPRT0); 305 } 306 307 dwc2_disable_host_interrupts(hsotg); 308 } 309 310 /* Respond with an error status to all URBs in the schedule */ 311 dwc2_kill_all_urbs(hsotg); 312 313 if (dwc2_is_host_mode(hsotg)) 314 /* Clean up any host channels that were in use */ 315 dwc2_hcd_cleanup_channels(hsotg); 316 317 dwc2_host_disconnect(hsotg); 318 } 319 320 /** 321 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 322 * 323 * @hsotg: Pointer to struct dwc2_hsotg 324 */ 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 326 { 327 if (hsotg->lx_state == DWC2_L2) { 328 hsotg->flags.b.port_suspend_change = 1; 329 usb_hcd_resume_root_hub(hsotg->priv); 330 } else { 331 hsotg->flags.b.port_l1_change = 1; 332 } 333 } 334 335 /** 336 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 337 * 338 * @hsotg: Pointer to struct dwc2_hsotg 339 * 340 * Must be called with interrupt disabled and spinlock held 341 */ 342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 343 { 344 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 345 346 /* 347 * The root hub should be disconnected before this function is called. 348 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 349 * and the QH lists (via ..._hcd_endpoint_disable). 350 */ 351 352 /* Turn off all host-specific interrupts */ 353 dwc2_disable_host_interrupts(hsotg); 354 355 /* Turn off the vbus power */ 356 dev_dbg(hsotg->dev, "PortPower off\n"); 357 writel(0, hsotg->regs + HPRT0); 358 } 359 360 /* Caller must hold driver lock */ 361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 362 struct dwc2_hcd_urb *urb, void **ep_handle, 363 gfp_t mem_flags) 364 { 365 struct dwc2_qtd *qtd; 366 u32 intr_mask; 367 int retval; 368 int dev_speed; 369 370 if (!hsotg->flags.b.port_connect_status) { 371 /* No longer connected */ 372 dev_err(hsotg->dev, "Not connected\n"); 373 return -ENODEV; 374 } 375 376 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 377 378 /* Some configurations cannot support LS traffic on a FS root port */ 379 if ((dev_speed == USB_SPEED_LOW) && 380 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 381 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 382 u32 hprt0 = readl(hsotg->regs + HPRT0); 383 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 384 385 if (prtspd == HPRT0_SPD_FULL_SPEED) 386 return -ENODEV; 387 } 388 389 qtd = kzalloc(sizeof(*qtd), mem_flags); 390 if (!qtd) 391 return -ENOMEM; 392 393 dwc2_hcd_qtd_init(qtd, urb); 394 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle, 395 mem_flags); 396 if (retval) { 397 dev_err(hsotg->dev, 398 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 399 retval); 400 kfree(qtd); 401 return retval; 402 } 403 404 intr_mask = readl(hsotg->regs + GINTMSK); 405 if (!(intr_mask & GINTSTS_SOF)) { 406 enum dwc2_transaction_type tr_type; 407 408 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 409 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 410 /* 411 * Do not schedule SG transactions until qtd has 412 * URB_GIVEBACK_ASAP set 413 */ 414 return 0; 415 416 tr_type = dwc2_hcd_select_transactions(hsotg); 417 if (tr_type != DWC2_TRANSACTION_NONE) 418 dwc2_hcd_queue_transactions(hsotg, tr_type); 419 } 420 421 return 0; 422 } 423 424 /* Must be called with interrupt disabled and spinlock held */ 425 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 426 struct dwc2_hcd_urb *urb) 427 { 428 struct dwc2_qh *qh; 429 struct dwc2_qtd *urb_qtd; 430 431 urb_qtd = urb->qtd; 432 if (!urb_qtd) { 433 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 434 return -EINVAL; 435 } 436 437 qh = urb_qtd->qh; 438 if (!qh) { 439 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 440 return -EINVAL; 441 } 442 443 urb->priv = NULL; 444 445 if (urb_qtd->in_process && qh->channel) { 446 dwc2_dump_channel_info(hsotg, qh->channel); 447 448 /* The QTD is in process (it has been assigned to a channel) */ 449 if (hsotg->flags.b.port_connect_status) 450 /* 451 * If still connected (i.e. in host mode), halt the 452 * channel so it can be used for other transfers. If 453 * no longer connected, the host registers can't be 454 * written to halt the channel since the core is in 455 * device mode. 456 */ 457 dwc2_hc_halt(hsotg, qh->channel, 458 DWC2_HC_XFER_URB_DEQUEUE); 459 } 460 461 /* 462 * Free the QTD and clean up the associated QH. Leave the QH in the 463 * schedule if it has any remaining QTDs. 464 */ 465 if (hsotg->core_params->dma_desc_enable <= 0) { 466 u8 in_process = urb_qtd->in_process; 467 468 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 469 if (in_process) { 470 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 471 qh->channel = NULL; 472 } else if (list_empty(&qh->qtd_list)) { 473 dwc2_hcd_qh_unlink(hsotg, qh); 474 } 475 } else { 476 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 477 } 478 479 return 0; 480 } 481 482 /* Must NOT be called with interrupt disabled or spinlock held */ 483 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 484 struct usb_host_endpoint *ep, int retry) 485 { 486 struct dwc2_qtd *qtd, *qtd_tmp; 487 struct dwc2_qh *qh; 488 unsigned long flags; 489 int rc; 490 491 spin_lock_irqsave(&hsotg->lock, flags); 492 493 qh = ep->hcpriv; 494 if (!qh) { 495 rc = -EINVAL; 496 goto err; 497 } 498 499 while (!list_empty(&qh->qtd_list) && retry--) { 500 if (retry == 0) { 501 dev_err(hsotg->dev, 502 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 503 rc = -EBUSY; 504 goto err; 505 } 506 507 spin_unlock_irqrestore(&hsotg->lock, flags); 508 usleep_range(20000, 40000); 509 spin_lock_irqsave(&hsotg->lock, flags); 510 qh = ep->hcpriv; 511 if (!qh) { 512 rc = -EINVAL; 513 goto err; 514 } 515 } 516 517 dwc2_hcd_qh_unlink(hsotg, qh); 518 519 /* Free each QTD in the QH's QTD list */ 520 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 521 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 522 523 ep->hcpriv = NULL; 524 spin_unlock_irqrestore(&hsotg->lock, flags); 525 dwc2_hcd_qh_free(hsotg, qh); 526 527 return 0; 528 529 err: 530 ep->hcpriv = NULL; 531 spin_unlock_irqrestore(&hsotg->lock, flags); 532 533 return rc; 534 } 535 536 /* Must be called with interrupt disabled and spinlock held */ 537 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 538 struct usb_host_endpoint *ep) 539 { 540 struct dwc2_qh *qh = ep->hcpriv; 541 542 if (!qh) 543 return -EINVAL; 544 545 qh->data_toggle = DWC2_HC_PID_DATA0; 546 547 return 0; 548 } 549 550 /* 551 * Initializes dynamic portions of the DWC_otg HCD state 552 * 553 * Must be called with interrupt disabled and spinlock held 554 */ 555 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 556 { 557 struct dwc2_host_chan *chan, *chan_tmp; 558 int num_channels; 559 int i; 560 561 hsotg->flags.d32 = 0; 562 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 563 564 if (hsotg->core_params->uframe_sched > 0) { 565 hsotg->available_host_channels = 566 hsotg->core_params->host_channels; 567 } else { 568 hsotg->non_periodic_channels = 0; 569 hsotg->periodic_channels = 0; 570 } 571 572 /* 573 * Put all channels in the free channel list and clean up channel 574 * states 575 */ 576 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 577 hc_list_entry) 578 list_del_init(&chan->hc_list_entry); 579 580 num_channels = hsotg->core_params->host_channels; 581 for (i = 0; i < num_channels; i++) { 582 chan = hsotg->hc_ptr_array[i]; 583 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 584 dwc2_hc_cleanup(hsotg, chan); 585 } 586 587 /* Initialize the DWC core for host mode operation */ 588 dwc2_core_host_init(hsotg); 589 } 590 591 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 592 struct dwc2_host_chan *chan, 593 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 594 { 595 int hub_addr, hub_port; 596 597 chan->do_split = 1; 598 chan->xact_pos = qtd->isoc_split_pos; 599 chan->complete_split = qtd->complete_split; 600 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 601 chan->hub_addr = (u8)hub_addr; 602 chan->hub_port = (u8)hub_port; 603 } 604 605 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 606 struct dwc2_host_chan *chan, 607 struct dwc2_qtd *qtd, void *bufptr) 608 { 609 struct dwc2_hcd_urb *urb = qtd->urb; 610 struct dwc2_hcd_iso_packet_desc *frame_desc; 611 612 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 613 case USB_ENDPOINT_XFER_CONTROL: 614 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 615 616 switch (qtd->control_phase) { 617 case DWC2_CONTROL_SETUP: 618 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 619 chan->do_ping = 0; 620 chan->ep_is_in = 0; 621 chan->data_pid_start = DWC2_HC_PID_SETUP; 622 if (hsotg->core_params->dma_enable > 0) 623 chan->xfer_dma = urb->setup_dma; 624 else 625 chan->xfer_buf = urb->setup_packet; 626 chan->xfer_len = 8; 627 bufptr = NULL; 628 break; 629 630 case DWC2_CONTROL_DATA: 631 dev_vdbg(hsotg->dev, " Control data transaction\n"); 632 chan->data_pid_start = qtd->data_toggle; 633 break; 634 635 case DWC2_CONTROL_STATUS: 636 /* 637 * Direction is opposite of data direction or IN if no 638 * data 639 */ 640 dev_vdbg(hsotg->dev, " Control status transaction\n"); 641 if (urb->length == 0) 642 chan->ep_is_in = 1; 643 else 644 chan->ep_is_in = 645 dwc2_hcd_is_pipe_out(&urb->pipe_info); 646 if (chan->ep_is_in) 647 chan->do_ping = 0; 648 chan->data_pid_start = DWC2_HC_PID_DATA1; 649 chan->xfer_len = 0; 650 if (hsotg->core_params->dma_enable > 0) 651 chan->xfer_dma = hsotg->status_buf_dma; 652 else 653 chan->xfer_buf = hsotg->status_buf; 654 bufptr = NULL; 655 break; 656 } 657 break; 658 659 case USB_ENDPOINT_XFER_BULK: 660 chan->ep_type = USB_ENDPOINT_XFER_BULK; 661 break; 662 663 case USB_ENDPOINT_XFER_INT: 664 chan->ep_type = USB_ENDPOINT_XFER_INT; 665 break; 666 667 case USB_ENDPOINT_XFER_ISOC: 668 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 669 if (hsotg->core_params->dma_desc_enable > 0) 670 break; 671 672 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 673 frame_desc->status = 0; 674 675 if (hsotg->core_params->dma_enable > 0) { 676 chan->xfer_dma = urb->dma; 677 chan->xfer_dma += frame_desc->offset + 678 qtd->isoc_split_offset; 679 } else { 680 chan->xfer_buf = urb->buf; 681 chan->xfer_buf += frame_desc->offset + 682 qtd->isoc_split_offset; 683 } 684 685 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 686 687 /* For non-dword aligned buffers */ 688 if (hsotg->core_params->dma_enable > 0 && 689 (chan->xfer_dma & 0x3)) 690 bufptr = (u8 *)urb->buf + frame_desc->offset + 691 qtd->isoc_split_offset; 692 else 693 bufptr = NULL; 694 695 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 696 if (chan->xfer_len <= 188) 697 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 698 else 699 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 700 } 701 break; 702 } 703 704 return bufptr; 705 } 706 707 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 708 struct dwc2_host_chan *chan, 709 struct dwc2_hcd_urb *urb, void *bufptr) 710 { 711 u32 buf_size; 712 struct urb *usb_urb; 713 struct usb_hcd *hcd; 714 715 if (!qh->dw_align_buf) { 716 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) 717 buf_size = hsotg->core_params->max_transfer_size; 718 else 719 /* 3072 = 3 max-size Isoc packets */ 720 buf_size = 3072; 721 722 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA); 723 if (!qh->dw_align_buf) 724 return -ENOMEM; 725 qh->dw_align_buf_size = buf_size; 726 } 727 728 if (chan->xfer_len) { 729 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__); 730 usb_urb = urb->priv; 731 732 if (usb_urb) { 733 if (usb_urb->transfer_flags & 734 (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG | 735 URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) { 736 hcd = dwc2_hsotg_to_hcd(hsotg); 737 usb_hcd_unmap_urb_for_dma(hcd, usb_urb); 738 } 739 if (!chan->ep_is_in) 740 memcpy(qh->dw_align_buf, bufptr, 741 chan->xfer_len); 742 } else { 743 dev_warn(hsotg->dev, "no URB in dwc2_urb\n"); 744 } 745 } 746 747 qh->dw_align_buf_dma = dma_map_single(hsotg->dev, 748 qh->dw_align_buf, qh->dw_align_buf_size, 749 chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 750 if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) { 751 dev_err(hsotg->dev, "can't map align_buf\n"); 752 chan->align_buf = 0; 753 return -EINVAL; 754 } 755 756 chan->align_buf = qh->dw_align_buf_dma; 757 return 0; 758 } 759 760 /** 761 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 762 * channel and initializes the host channel to perform the transactions. The 763 * host channel is removed from the free list. 764 * 765 * @hsotg: The HCD state structure 766 * @qh: Transactions from the first QTD for this QH are selected and assigned 767 * to a free host channel 768 */ 769 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 770 { 771 struct dwc2_host_chan *chan; 772 struct dwc2_hcd_urb *urb; 773 struct dwc2_qtd *qtd; 774 void *bufptr = NULL; 775 776 if (dbg_qh(qh)) 777 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 778 779 if (list_empty(&qh->qtd_list)) { 780 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 781 return -ENOMEM; 782 } 783 784 if (list_empty(&hsotg->free_hc_list)) { 785 dev_dbg(hsotg->dev, "No free channel to assign\n"); 786 return -ENOMEM; 787 } 788 789 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 790 hc_list_entry); 791 792 /* Remove host channel from free list */ 793 list_del_init(&chan->hc_list_entry); 794 795 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 796 urb = qtd->urb; 797 qh->channel = chan; 798 qtd->in_process = 1; 799 800 /* 801 * Use usb_pipedevice to determine device address. This address is 802 * 0 before the SET_ADDRESS command and the correct address afterward. 803 */ 804 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 805 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 806 chan->speed = qh->dev_speed; 807 chan->max_packet = dwc2_max_packet(qh->maxp); 808 809 chan->xfer_started = 0; 810 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 811 chan->error_state = (qtd->error_count > 0); 812 chan->halt_on_queue = 0; 813 chan->halt_pending = 0; 814 chan->requests = 0; 815 816 /* 817 * The following values may be modified in the transfer type section 818 * below. The xfer_len value may be reduced when the transfer is 819 * started to accommodate the max widths of the XferSize and PktCnt 820 * fields in the HCTSIZn register. 821 */ 822 823 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 824 if (chan->ep_is_in) 825 chan->do_ping = 0; 826 else 827 chan->do_ping = qh->ping_state; 828 829 chan->data_pid_start = qh->data_toggle; 830 chan->multi_count = 1; 831 832 if (urb->actual_length > urb->length && 833 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 834 urb->actual_length = urb->length; 835 836 if (hsotg->core_params->dma_enable > 0) { 837 chan->xfer_dma = urb->dma + urb->actual_length; 838 839 /* For non-dword aligned case */ 840 if (hsotg->core_params->dma_desc_enable <= 0 && 841 (chan->xfer_dma & 0x3)) 842 bufptr = (u8 *)urb->buf + urb->actual_length; 843 } else { 844 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 845 } 846 847 chan->xfer_len = urb->length - urb->actual_length; 848 chan->xfer_count = 0; 849 850 /* Set the split attributes if required */ 851 if (qh->do_split) 852 dwc2_hc_init_split(hsotg, chan, qtd, urb); 853 else 854 chan->do_split = 0; 855 856 /* Set the transfer attributes */ 857 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr); 858 859 /* Non DWORD-aligned buffer case */ 860 if (bufptr) { 861 dev_vdbg(hsotg->dev, "Non-aligned buffer\n"); 862 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) { 863 dev_err(hsotg->dev, 864 "%s: Failed to allocate memory to handle non-dword aligned buffer\n", 865 __func__); 866 /* Add channel back to free list */ 867 chan->align_buf = 0; 868 chan->multi_count = 0; 869 list_add_tail(&chan->hc_list_entry, 870 &hsotg->free_hc_list); 871 qtd->in_process = 0; 872 qh->channel = NULL; 873 return -ENOMEM; 874 } 875 } else { 876 chan->align_buf = 0; 877 } 878 879 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 880 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 881 /* 882 * This value may be modified when the transfer is started 883 * to reflect the actual transfer length 884 */ 885 chan->multi_count = dwc2_hb_mult(qh->maxp); 886 887 if (hsotg->core_params->dma_desc_enable > 0) 888 chan->desc_list_addr = qh->desc_list_dma; 889 890 dwc2_hc_init(hsotg, chan); 891 chan->qh = qh; 892 893 return 0; 894 } 895 896 /** 897 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 898 * schedule and assigns them to available host channels. Called from the HCD 899 * interrupt handler functions. 900 * 901 * @hsotg: The HCD state structure 902 * 903 * Return: The types of new transactions that were assigned to host channels 904 */ 905 enum dwc2_transaction_type dwc2_hcd_select_transactions( 906 struct dwc2_hsotg *hsotg) 907 { 908 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 909 struct list_head *qh_ptr; 910 struct dwc2_qh *qh; 911 int num_channels; 912 913 #ifdef DWC2_DEBUG_SOF 914 dev_vdbg(hsotg->dev, " Select Transactions\n"); 915 #endif 916 917 /* Process entries in the periodic ready list */ 918 qh_ptr = hsotg->periodic_sched_ready.next; 919 while (qh_ptr != &hsotg->periodic_sched_ready) { 920 if (list_empty(&hsotg->free_hc_list)) 921 break; 922 if (hsotg->core_params->uframe_sched > 0) { 923 if (hsotg->available_host_channels <= 1) 924 break; 925 hsotg->available_host_channels--; 926 } 927 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 928 if (dwc2_assign_and_init_hc(hsotg, qh)) 929 break; 930 931 /* 932 * Move the QH from the periodic ready schedule to the 933 * periodic assigned schedule 934 */ 935 qh_ptr = qh_ptr->next; 936 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 937 ret_val = DWC2_TRANSACTION_PERIODIC; 938 } 939 940 /* 941 * Process entries in the inactive portion of the non-periodic 942 * schedule. Some free host channels may not be used if they are 943 * reserved for periodic transfers. 944 */ 945 num_channels = hsotg->core_params->host_channels; 946 qh_ptr = hsotg->non_periodic_sched_inactive.next; 947 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 948 if (hsotg->core_params->uframe_sched <= 0 && 949 hsotg->non_periodic_channels >= num_channels - 950 hsotg->periodic_channels) 951 break; 952 if (list_empty(&hsotg->free_hc_list)) 953 break; 954 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 955 if (hsotg->core_params->uframe_sched > 0) { 956 if (hsotg->available_host_channels < 1) 957 break; 958 hsotg->available_host_channels--; 959 } 960 961 if (dwc2_assign_and_init_hc(hsotg, qh)) 962 break; 963 964 /* 965 * Move the QH from the non-periodic inactive schedule to the 966 * non-periodic active schedule 967 */ 968 qh_ptr = qh_ptr->next; 969 list_move(&qh->qh_list_entry, 970 &hsotg->non_periodic_sched_active); 971 972 if (ret_val == DWC2_TRANSACTION_NONE) 973 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 974 else 975 ret_val = DWC2_TRANSACTION_ALL; 976 977 if (hsotg->core_params->uframe_sched <= 0) 978 hsotg->non_periodic_channels++; 979 } 980 981 return ret_val; 982 } 983 984 /** 985 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 986 * a host channel associated with either a periodic or non-periodic transfer 987 * 988 * @hsotg: The HCD state structure 989 * @chan: Host channel descriptor associated with either a periodic or 990 * non-periodic transfer 991 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 992 * for periodic transfers or the non-periodic Tx FIFO 993 * for non-periodic transfers 994 * 995 * Return: 1 if a request is queued and more requests may be needed to 996 * complete the transfer, 0 if no more requests are required for this 997 * transfer, -1 if there is insufficient space in the Tx FIFO 998 * 999 * This function assumes that there is space available in the appropriate 1000 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1001 * it checks whether space is available in the appropriate Tx FIFO. 1002 * 1003 * Must be called with interrupt disabled and spinlock held 1004 */ 1005 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1006 struct dwc2_host_chan *chan, 1007 u16 fifo_dwords_avail) 1008 { 1009 int retval = 0; 1010 1011 if (hsotg->core_params->dma_enable > 0) { 1012 if (hsotg->core_params->dma_desc_enable > 0) { 1013 if (!chan->xfer_started || 1014 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1015 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1016 chan->qh->ping_state = 0; 1017 } 1018 } else if (!chan->xfer_started) { 1019 dwc2_hc_start_transfer(hsotg, chan); 1020 chan->qh->ping_state = 0; 1021 } 1022 } else if (chan->halt_pending) { 1023 /* Don't queue a request if the channel has been halted */ 1024 } else if (chan->halt_on_queue) { 1025 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1026 } else if (chan->do_ping) { 1027 if (!chan->xfer_started) 1028 dwc2_hc_start_transfer(hsotg, chan); 1029 } else if (!chan->ep_is_in || 1030 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1031 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1032 if (!chan->xfer_started) { 1033 dwc2_hc_start_transfer(hsotg, chan); 1034 retval = 1; 1035 } else { 1036 retval = dwc2_hc_continue_transfer(hsotg, chan); 1037 } 1038 } else { 1039 retval = -1; 1040 } 1041 } else { 1042 if (!chan->xfer_started) { 1043 dwc2_hc_start_transfer(hsotg, chan); 1044 retval = 1; 1045 } else { 1046 retval = dwc2_hc_continue_transfer(hsotg, chan); 1047 } 1048 } 1049 1050 return retval; 1051 } 1052 1053 /* 1054 * Processes periodic channels for the next frame and queues transactions for 1055 * these channels to the DWC_otg controller. After queueing transactions, the 1056 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1057 * to queue as Periodic Tx FIFO or request queue space becomes available. 1058 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1059 * 1060 * Must be called with interrupt disabled and spinlock held 1061 */ 1062 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1063 { 1064 struct list_head *qh_ptr; 1065 struct dwc2_qh *qh; 1066 u32 tx_status; 1067 u32 fspcavail; 1068 u32 gintmsk; 1069 int status; 1070 int no_queue_space = 0; 1071 int no_fifo_space = 0; 1072 u32 qspcavail; 1073 1074 if (dbg_perio()) 1075 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1076 1077 tx_status = readl(hsotg->regs + HPTXSTS); 1078 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1079 TXSTS_QSPCAVAIL_SHIFT; 1080 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1081 TXSTS_FSPCAVAIL_SHIFT; 1082 1083 if (dbg_perio()) { 1084 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1085 qspcavail); 1086 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1087 fspcavail); 1088 } 1089 1090 qh_ptr = hsotg->periodic_sched_assigned.next; 1091 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1092 tx_status = readl(hsotg->regs + HPTXSTS); 1093 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1094 TXSTS_QSPCAVAIL_SHIFT; 1095 if (qspcavail == 0) { 1096 no_queue_space = 1; 1097 break; 1098 } 1099 1100 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1101 if (!qh->channel) { 1102 qh_ptr = qh_ptr->next; 1103 continue; 1104 } 1105 1106 /* Make sure EP's TT buffer is clean before queueing qtds */ 1107 if (qh->tt_buffer_dirty) { 1108 qh_ptr = qh_ptr->next; 1109 continue; 1110 } 1111 1112 /* 1113 * Set a flag if we're queuing high-bandwidth in slave mode. 1114 * The flag prevents any halts to get into the request queue in 1115 * the middle of multiple high-bandwidth packets getting queued. 1116 */ 1117 if (hsotg->core_params->dma_enable <= 0 && 1118 qh->channel->multi_count > 1) 1119 hsotg->queuing_high_bandwidth = 1; 1120 1121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1122 TXSTS_FSPCAVAIL_SHIFT; 1123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1124 if (status < 0) { 1125 no_fifo_space = 1; 1126 break; 1127 } 1128 1129 /* 1130 * In Slave mode, stay on the current transfer until there is 1131 * nothing more to do or the high-bandwidth request count is 1132 * reached. In DMA mode, only need to queue one request. The 1133 * controller automatically handles multiple packets for 1134 * high-bandwidth transfers. 1135 */ 1136 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1137 qh->channel->requests == qh->channel->multi_count) { 1138 qh_ptr = qh_ptr->next; 1139 /* 1140 * Move the QH from the periodic assigned schedule to 1141 * the periodic queued schedule 1142 */ 1143 list_move(&qh->qh_list_entry, 1144 &hsotg->periodic_sched_queued); 1145 1146 /* done queuing high bandwidth */ 1147 hsotg->queuing_high_bandwidth = 0; 1148 } 1149 } 1150 1151 if (hsotg->core_params->dma_enable <= 0) { 1152 tx_status = readl(hsotg->regs + HPTXSTS); 1153 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1154 TXSTS_QSPCAVAIL_SHIFT; 1155 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1156 TXSTS_FSPCAVAIL_SHIFT; 1157 if (dbg_perio()) { 1158 dev_vdbg(hsotg->dev, 1159 " P Tx Req Queue Space Avail (after queue): %d\n", 1160 qspcavail); 1161 dev_vdbg(hsotg->dev, 1162 " P Tx FIFO Space Avail (after queue): %d\n", 1163 fspcavail); 1164 } 1165 1166 if (!list_empty(&hsotg->periodic_sched_assigned) || 1167 no_queue_space || no_fifo_space) { 1168 /* 1169 * May need to queue more transactions as the request 1170 * queue or Tx FIFO empties. Enable the periodic Tx 1171 * FIFO empty interrupt. (Always use the half-empty 1172 * level to ensure that new requests are loaded as 1173 * soon as possible.) 1174 */ 1175 gintmsk = readl(hsotg->regs + GINTMSK); 1176 gintmsk |= GINTSTS_PTXFEMP; 1177 writel(gintmsk, hsotg->regs + GINTMSK); 1178 } else { 1179 /* 1180 * Disable the Tx FIFO empty interrupt since there are 1181 * no more transactions that need to be queued right 1182 * now. This function is called from interrupt 1183 * handlers to queue more transactions as transfer 1184 * states change. 1185 */ 1186 gintmsk = readl(hsotg->regs + GINTMSK); 1187 gintmsk &= ~GINTSTS_PTXFEMP; 1188 writel(gintmsk, hsotg->regs + GINTMSK); 1189 } 1190 } 1191 } 1192 1193 /* 1194 * Processes active non-periodic channels and queues transactions for these 1195 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1196 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1197 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1198 * FIFO Empty interrupt is disabled. 1199 * 1200 * Must be called with interrupt disabled and spinlock held 1201 */ 1202 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1203 { 1204 struct list_head *orig_qh_ptr; 1205 struct dwc2_qh *qh; 1206 u32 tx_status; 1207 u32 qspcavail; 1208 u32 fspcavail; 1209 u32 gintmsk; 1210 int status; 1211 int no_queue_space = 0; 1212 int no_fifo_space = 0; 1213 int more_to_do = 0; 1214 1215 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1216 1217 tx_status = readl(hsotg->regs + GNPTXSTS); 1218 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1219 TXSTS_QSPCAVAIL_SHIFT; 1220 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1221 TXSTS_FSPCAVAIL_SHIFT; 1222 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1223 qspcavail); 1224 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1225 fspcavail); 1226 1227 /* 1228 * Keep track of the starting point. Skip over the start-of-list 1229 * entry. 1230 */ 1231 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1232 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1233 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1234 1235 /* 1236 * Process once through the active list or until no more space is 1237 * available in the request queue or the Tx FIFO 1238 */ 1239 do { 1240 tx_status = readl(hsotg->regs + GNPTXSTS); 1241 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1242 TXSTS_QSPCAVAIL_SHIFT; 1243 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1244 no_queue_space = 1; 1245 break; 1246 } 1247 1248 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1249 qh_list_entry); 1250 if (!qh->channel) 1251 goto next; 1252 1253 /* Make sure EP's TT buffer is clean before queueing qtds */ 1254 if (qh->tt_buffer_dirty) 1255 goto next; 1256 1257 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1258 TXSTS_FSPCAVAIL_SHIFT; 1259 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1260 1261 if (status > 0) { 1262 more_to_do = 1; 1263 } else if (status < 0) { 1264 no_fifo_space = 1; 1265 break; 1266 } 1267 next: 1268 /* Advance to next QH, skipping start-of-list entry */ 1269 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1270 if (hsotg->non_periodic_qh_ptr == 1271 &hsotg->non_periodic_sched_active) 1272 hsotg->non_periodic_qh_ptr = 1273 hsotg->non_periodic_qh_ptr->next; 1274 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1275 1276 if (hsotg->core_params->dma_enable <= 0) { 1277 tx_status = readl(hsotg->regs + GNPTXSTS); 1278 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1279 TXSTS_QSPCAVAIL_SHIFT; 1280 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1281 TXSTS_FSPCAVAIL_SHIFT; 1282 dev_vdbg(hsotg->dev, 1283 " NP Tx Req Queue Space Avail (after queue): %d\n", 1284 qspcavail); 1285 dev_vdbg(hsotg->dev, 1286 " NP Tx FIFO Space Avail (after queue): %d\n", 1287 fspcavail); 1288 1289 if (more_to_do || no_queue_space || no_fifo_space) { 1290 /* 1291 * May need to queue more transactions as the request 1292 * queue or Tx FIFO empties. Enable the non-periodic 1293 * Tx FIFO empty interrupt. (Always use the half-empty 1294 * level to ensure that new requests are loaded as 1295 * soon as possible.) 1296 */ 1297 gintmsk = readl(hsotg->regs + GINTMSK); 1298 gintmsk |= GINTSTS_NPTXFEMP; 1299 writel(gintmsk, hsotg->regs + GINTMSK); 1300 } else { 1301 /* 1302 * Disable the Tx FIFO empty interrupt since there are 1303 * no more transactions that need to be queued right 1304 * now. This function is called from interrupt 1305 * handlers to queue more transactions as transfer 1306 * states change. 1307 */ 1308 gintmsk = readl(hsotg->regs + GINTMSK); 1309 gintmsk &= ~GINTSTS_NPTXFEMP; 1310 writel(gintmsk, hsotg->regs + GINTMSK); 1311 } 1312 } 1313 } 1314 1315 /** 1316 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1317 * and queues transactions for these channels to the DWC_otg controller. Called 1318 * from the HCD interrupt handler functions. 1319 * 1320 * @hsotg: The HCD state structure 1321 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1322 * or both) 1323 * 1324 * Must be called with interrupt disabled and spinlock held 1325 */ 1326 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1327 enum dwc2_transaction_type tr_type) 1328 { 1329 #ifdef DWC2_DEBUG_SOF 1330 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1331 #endif 1332 /* Process host channels associated with periodic transfers */ 1333 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1334 tr_type == DWC2_TRANSACTION_ALL) && 1335 !list_empty(&hsotg->periodic_sched_assigned)) 1336 dwc2_process_periodic_channels(hsotg); 1337 1338 /* Process host channels associated with non-periodic transfers */ 1339 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1340 tr_type == DWC2_TRANSACTION_ALL) { 1341 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1342 dwc2_process_non_periodic_channels(hsotg); 1343 } else { 1344 /* 1345 * Ensure NP Tx FIFO empty interrupt is disabled when 1346 * there are no non-periodic transfers to process 1347 */ 1348 u32 gintmsk = readl(hsotg->regs + GINTMSK); 1349 1350 gintmsk &= ~GINTSTS_NPTXFEMP; 1351 writel(gintmsk, hsotg->regs + GINTMSK); 1352 } 1353 } 1354 } 1355 1356 static void dwc2_conn_id_status_change(struct work_struct *work) 1357 { 1358 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1359 wf_otg); 1360 u32 count = 0; 1361 u32 gotgctl; 1362 1363 dev_dbg(hsotg->dev, "%s()\n", __func__); 1364 1365 gotgctl = readl(hsotg->regs + GOTGCTL); 1366 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1367 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1368 !!(gotgctl & GOTGCTL_CONID_B)); 1369 1370 /* B-Device connector (Device Mode) */ 1371 if (gotgctl & GOTGCTL_CONID_B) { 1372 /* Wait for switch to device mode */ 1373 dev_dbg(hsotg->dev, "connId B\n"); 1374 while (!dwc2_is_device_mode(hsotg)) { 1375 dev_info(hsotg->dev, 1376 "Waiting for Peripheral Mode, Mode=%s\n", 1377 dwc2_is_host_mode(hsotg) ? "Host" : 1378 "Peripheral"); 1379 usleep_range(20000, 40000); 1380 if (++count > 250) 1381 break; 1382 } 1383 if (count > 250) 1384 dev_err(hsotg->dev, 1385 "Connection id status change timed out\n"); 1386 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1387 dwc2_core_init(hsotg, false, -1); 1388 dwc2_enable_global_interrupts(hsotg); 1389 s3c_hsotg_core_init_disconnected(hsotg, false); 1390 s3c_hsotg_core_connect(hsotg); 1391 } else { 1392 /* A-Device connector (Host Mode) */ 1393 dev_dbg(hsotg->dev, "connId A\n"); 1394 while (!dwc2_is_host_mode(hsotg)) { 1395 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1396 dwc2_is_host_mode(hsotg) ? 1397 "Host" : "Peripheral"); 1398 usleep_range(20000, 40000); 1399 if (++count > 250) 1400 break; 1401 } 1402 if (count > 250) 1403 dev_err(hsotg->dev, 1404 "Connection id status change timed out\n"); 1405 hsotg->op_state = OTG_STATE_A_HOST; 1406 1407 /* Initialize the Core for Host mode */ 1408 dwc2_core_init(hsotg, false, -1); 1409 dwc2_enable_global_interrupts(hsotg); 1410 dwc2_hcd_start(hsotg); 1411 } 1412 } 1413 1414 static void dwc2_wakeup_detected(unsigned long data) 1415 { 1416 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1417 u32 hprt0; 1418 1419 dev_dbg(hsotg->dev, "%s()\n", __func__); 1420 1421 /* 1422 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1423 * so that OPT tests pass with all PHYs.) 1424 */ 1425 hprt0 = dwc2_read_hprt0(hsotg); 1426 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1427 hprt0 &= ~HPRT0_RES; 1428 writel(hprt0, hsotg->regs + HPRT0); 1429 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1430 readl(hsotg->regs + HPRT0)); 1431 1432 dwc2_hcd_rem_wakeup(hsotg); 1433 1434 /* Change to L0 state */ 1435 hsotg->lx_state = DWC2_L0; 1436 } 1437 1438 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1439 { 1440 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1441 1442 return hcd->self.b_hnp_enable; 1443 } 1444 1445 /* Must NOT be called with interrupt disabled or spinlock held */ 1446 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1447 { 1448 unsigned long flags; 1449 u32 hprt0; 1450 u32 pcgctl; 1451 u32 gotgctl; 1452 1453 dev_dbg(hsotg->dev, "%s()\n", __func__); 1454 1455 spin_lock_irqsave(&hsotg->lock, flags); 1456 1457 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1458 gotgctl = readl(hsotg->regs + GOTGCTL); 1459 gotgctl |= GOTGCTL_HSTSETHNPEN; 1460 writel(gotgctl, hsotg->regs + GOTGCTL); 1461 hsotg->op_state = OTG_STATE_A_SUSPEND; 1462 } 1463 1464 hprt0 = dwc2_read_hprt0(hsotg); 1465 hprt0 |= HPRT0_SUSP; 1466 writel(hprt0, hsotg->regs + HPRT0); 1467 1468 /* Update lx_state */ 1469 hsotg->lx_state = DWC2_L2; 1470 1471 /* Suspend the Phy Clock */ 1472 pcgctl = readl(hsotg->regs + PCGCTL); 1473 pcgctl |= PCGCTL_STOPPCLK; 1474 writel(pcgctl, hsotg->regs + PCGCTL); 1475 udelay(10); 1476 1477 /* For HNP the bus must be suspended for at least 200ms */ 1478 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1479 pcgctl = readl(hsotg->regs + PCGCTL); 1480 pcgctl &= ~PCGCTL_STOPPCLK; 1481 writel(pcgctl, hsotg->regs + PCGCTL); 1482 1483 spin_unlock_irqrestore(&hsotg->lock, flags); 1484 1485 usleep_range(200000, 250000); 1486 } else { 1487 spin_unlock_irqrestore(&hsotg->lock, flags); 1488 } 1489 } 1490 1491 /* Handles hub class-specific requests */ 1492 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1493 u16 wvalue, u16 windex, char *buf, u16 wlength) 1494 { 1495 struct usb_hub_descriptor *hub_desc; 1496 int retval = 0; 1497 u32 hprt0; 1498 u32 port_status; 1499 u32 speed; 1500 u32 pcgctl; 1501 1502 switch (typereq) { 1503 case ClearHubFeature: 1504 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1505 1506 switch (wvalue) { 1507 case C_HUB_LOCAL_POWER: 1508 case C_HUB_OVER_CURRENT: 1509 /* Nothing required here */ 1510 break; 1511 1512 default: 1513 retval = -EINVAL; 1514 dev_err(hsotg->dev, 1515 "ClearHubFeature request %1xh unknown\n", 1516 wvalue); 1517 } 1518 break; 1519 1520 case ClearPortFeature: 1521 if (wvalue != USB_PORT_FEAT_L1) 1522 if (!windex || windex > 1) 1523 goto error; 1524 switch (wvalue) { 1525 case USB_PORT_FEAT_ENABLE: 1526 dev_dbg(hsotg->dev, 1527 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1528 hprt0 = dwc2_read_hprt0(hsotg); 1529 hprt0 |= HPRT0_ENA; 1530 writel(hprt0, hsotg->regs + HPRT0); 1531 break; 1532 1533 case USB_PORT_FEAT_SUSPEND: 1534 dev_dbg(hsotg->dev, 1535 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1536 writel(0, hsotg->regs + PCGCTL); 1537 usleep_range(20000, 40000); 1538 1539 hprt0 = dwc2_read_hprt0(hsotg); 1540 hprt0 |= HPRT0_RES; 1541 writel(hprt0, hsotg->regs + HPRT0); 1542 hprt0 &= ~HPRT0_SUSP; 1543 msleep(USB_RESUME_TIMEOUT); 1544 1545 hprt0 &= ~HPRT0_RES; 1546 writel(hprt0, hsotg->regs + HPRT0); 1547 break; 1548 1549 case USB_PORT_FEAT_POWER: 1550 dev_dbg(hsotg->dev, 1551 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1552 hprt0 = dwc2_read_hprt0(hsotg); 1553 hprt0 &= ~HPRT0_PWR; 1554 writel(hprt0, hsotg->regs + HPRT0); 1555 break; 1556 1557 case USB_PORT_FEAT_INDICATOR: 1558 dev_dbg(hsotg->dev, 1559 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1560 /* Port indicator not supported */ 1561 break; 1562 1563 case USB_PORT_FEAT_C_CONNECTION: 1564 /* 1565 * Clears driver's internal Connect Status Change flag 1566 */ 1567 dev_dbg(hsotg->dev, 1568 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1569 hsotg->flags.b.port_connect_status_change = 0; 1570 break; 1571 1572 case USB_PORT_FEAT_C_RESET: 1573 /* Clears driver's internal Port Reset Change flag */ 1574 dev_dbg(hsotg->dev, 1575 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1576 hsotg->flags.b.port_reset_change = 0; 1577 break; 1578 1579 case USB_PORT_FEAT_C_ENABLE: 1580 /* 1581 * Clears the driver's internal Port Enable/Disable 1582 * Change flag 1583 */ 1584 dev_dbg(hsotg->dev, 1585 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1586 hsotg->flags.b.port_enable_change = 0; 1587 break; 1588 1589 case USB_PORT_FEAT_C_SUSPEND: 1590 /* 1591 * Clears the driver's internal Port Suspend Change 1592 * flag, which is set when resume signaling on the host 1593 * port is complete 1594 */ 1595 dev_dbg(hsotg->dev, 1596 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1597 hsotg->flags.b.port_suspend_change = 0; 1598 break; 1599 1600 case USB_PORT_FEAT_C_PORT_L1: 1601 dev_dbg(hsotg->dev, 1602 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1603 hsotg->flags.b.port_l1_change = 0; 1604 break; 1605 1606 case USB_PORT_FEAT_C_OVER_CURRENT: 1607 dev_dbg(hsotg->dev, 1608 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1609 hsotg->flags.b.port_over_current_change = 0; 1610 break; 1611 1612 default: 1613 retval = -EINVAL; 1614 dev_err(hsotg->dev, 1615 "ClearPortFeature request %1xh unknown or unsupported\n", 1616 wvalue); 1617 } 1618 break; 1619 1620 case GetHubDescriptor: 1621 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1622 hub_desc = (struct usb_hub_descriptor *)buf; 1623 hub_desc->bDescLength = 9; 1624 hub_desc->bDescriptorType = USB_DT_HUB; 1625 hub_desc->bNbrPorts = 1; 1626 hub_desc->wHubCharacteristics = 1627 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1628 HUB_CHAR_INDV_PORT_OCPM); 1629 hub_desc->bPwrOn2PwrGood = 1; 1630 hub_desc->bHubContrCurrent = 0; 1631 hub_desc->u.hs.DeviceRemovable[0] = 0; 1632 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1633 break; 1634 1635 case GetHubStatus: 1636 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1637 memset(buf, 0, 4); 1638 break; 1639 1640 case GetPortStatus: 1641 dev_vdbg(hsotg->dev, 1642 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1643 hsotg->flags.d32); 1644 if (!windex || windex > 1) 1645 goto error; 1646 1647 port_status = 0; 1648 if (hsotg->flags.b.port_connect_status_change) 1649 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1650 if (hsotg->flags.b.port_enable_change) 1651 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1652 if (hsotg->flags.b.port_suspend_change) 1653 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1654 if (hsotg->flags.b.port_l1_change) 1655 port_status |= USB_PORT_STAT_C_L1 << 16; 1656 if (hsotg->flags.b.port_reset_change) 1657 port_status |= USB_PORT_STAT_C_RESET << 16; 1658 if (hsotg->flags.b.port_over_current_change) { 1659 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1660 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1661 } 1662 1663 if (!hsotg->flags.b.port_connect_status) { 1664 /* 1665 * The port is disconnected, which means the core is 1666 * either in device mode or it soon will be. Just 1667 * return 0's for the remainder of the port status 1668 * since the port register can't be read if the core 1669 * is in device mode. 1670 */ 1671 *(__le32 *)buf = cpu_to_le32(port_status); 1672 break; 1673 } 1674 1675 hprt0 = readl(hsotg->regs + HPRT0); 1676 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1677 1678 if (hprt0 & HPRT0_CONNSTS) 1679 port_status |= USB_PORT_STAT_CONNECTION; 1680 if (hprt0 & HPRT0_ENA) 1681 port_status |= USB_PORT_STAT_ENABLE; 1682 if (hprt0 & HPRT0_SUSP) 1683 port_status |= USB_PORT_STAT_SUSPEND; 1684 if (hprt0 & HPRT0_OVRCURRACT) 1685 port_status |= USB_PORT_STAT_OVERCURRENT; 1686 if (hprt0 & HPRT0_RST) 1687 port_status |= USB_PORT_STAT_RESET; 1688 if (hprt0 & HPRT0_PWR) 1689 port_status |= USB_PORT_STAT_POWER; 1690 1691 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1692 if (speed == HPRT0_SPD_HIGH_SPEED) 1693 port_status |= USB_PORT_STAT_HIGH_SPEED; 1694 else if (speed == HPRT0_SPD_LOW_SPEED) 1695 port_status |= USB_PORT_STAT_LOW_SPEED; 1696 1697 if (hprt0 & HPRT0_TSTCTL_MASK) 1698 port_status |= USB_PORT_STAT_TEST; 1699 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1700 1701 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1702 *(__le32 *)buf = cpu_to_le32(port_status); 1703 break; 1704 1705 case SetHubFeature: 1706 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1707 /* No HUB features supported */ 1708 break; 1709 1710 case SetPortFeature: 1711 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1712 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1713 goto error; 1714 1715 if (!hsotg->flags.b.port_connect_status) { 1716 /* 1717 * The port is disconnected, which means the core is 1718 * either in device mode or it soon will be. Just 1719 * return without doing anything since the port 1720 * register can't be written if the core is in device 1721 * mode. 1722 */ 1723 break; 1724 } 1725 1726 switch (wvalue) { 1727 case USB_PORT_FEAT_SUSPEND: 1728 dev_dbg(hsotg->dev, 1729 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1730 if (windex != hsotg->otg_port) 1731 goto error; 1732 dwc2_port_suspend(hsotg, windex); 1733 break; 1734 1735 case USB_PORT_FEAT_POWER: 1736 dev_dbg(hsotg->dev, 1737 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1738 hprt0 = dwc2_read_hprt0(hsotg); 1739 hprt0 |= HPRT0_PWR; 1740 writel(hprt0, hsotg->regs + HPRT0); 1741 break; 1742 1743 case USB_PORT_FEAT_RESET: 1744 hprt0 = dwc2_read_hprt0(hsotg); 1745 dev_dbg(hsotg->dev, 1746 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1747 pcgctl = readl(hsotg->regs + PCGCTL); 1748 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1749 writel(pcgctl, hsotg->regs + PCGCTL); 1750 /* ??? Original driver does this */ 1751 writel(0, hsotg->regs + PCGCTL); 1752 1753 hprt0 = dwc2_read_hprt0(hsotg); 1754 /* Clear suspend bit if resetting from suspend state */ 1755 hprt0 &= ~HPRT0_SUSP; 1756 1757 /* 1758 * When B-Host the Port reset bit is set in the Start 1759 * HCD Callback function, so that the reset is started 1760 * within 1ms of the HNP success interrupt 1761 */ 1762 if (!dwc2_hcd_is_b_host(hsotg)) { 1763 hprt0 |= HPRT0_PWR | HPRT0_RST; 1764 dev_dbg(hsotg->dev, 1765 "In host mode, hprt0=%08x\n", hprt0); 1766 writel(hprt0, hsotg->regs + HPRT0); 1767 } 1768 1769 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1770 usleep_range(50000, 70000); 1771 hprt0 &= ~HPRT0_RST; 1772 writel(hprt0, hsotg->regs + HPRT0); 1773 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1774 break; 1775 1776 case USB_PORT_FEAT_INDICATOR: 1777 dev_dbg(hsotg->dev, 1778 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1779 /* Not supported */ 1780 break; 1781 1782 case USB_PORT_FEAT_TEST: 1783 hprt0 = dwc2_read_hprt0(hsotg); 1784 dev_dbg(hsotg->dev, 1785 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1786 hprt0 &= ~HPRT0_TSTCTL_MASK; 1787 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1788 writel(hprt0, hsotg->regs + HPRT0); 1789 break; 1790 1791 default: 1792 retval = -EINVAL; 1793 dev_err(hsotg->dev, 1794 "SetPortFeature %1xh unknown or unsupported\n", 1795 wvalue); 1796 break; 1797 } 1798 break; 1799 1800 default: 1801 error: 1802 retval = -EINVAL; 1803 dev_dbg(hsotg->dev, 1804 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1805 typereq, windex, wvalue); 1806 break; 1807 } 1808 1809 return retval; 1810 } 1811 1812 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1813 { 1814 int retval; 1815 1816 if (port != 1) 1817 return -EINVAL; 1818 1819 retval = (hsotg->flags.b.port_connect_status_change || 1820 hsotg->flags.b.port_reset_change || 1821 hsotg->flags.b.port_enable_change || 1822 hsotg->flags.b.port_suspend_change || 1823 hsotg->flags.b.port_over_current_change); 1824 1825 if (retval) { 1826 dev_dbg(hsotg->dev, 1827 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1828 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1829 hsotg->flags.b.port_connect_status_change); 1830 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1831 hsotg->flags.b.port_reset_change); 1832 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1833 hsotg->flags.b.port_enable_change); 1834 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1835 hsotg->flags.b.port_suspend_change); 1836 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1837 hsotg->flags.b.port_over_current_change); 1838 } 1839 1840 return retval; 1841 } 1842 1843 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1844 { 1845 u32 hfnum = readl(hsotg->regs + HFNUM); 1846 1847 #ifdef DWC2_DEBUG_SOF 1848 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1849 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1850 #endif 1851 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1852 } 1853 1854 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1855 { 1856 return hsotg->op_state == OTG_STATE_B_HOST; 1857 } 1858 1859 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1860 int iso_desc_count, 1861 gfp_t mem_flags) 1862 { 1863 struct dwc2_hcd_urb *urb; 1864 u32 size = sizeof(*urb) + iso_desc_count * 1865 sizeof(struct dwc2_hcd_iso_packet_desc); 1866 1867 urb = kzalloc(size, mem_flags); 1868 if (urb) 1869 urb->packet_count = iso_desc_count; 1870 return urb; 1871 } 1872 1873 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1874 struct dwc2_hcd_urb *urb, u8 dev_addr, 1875 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1876 { 1877 if (dbg_perio() || 1878 ep_type == USB_ENDPOINT_XFER_BULK || 1879 ep_type == USB_ENDPOINT_XFER_CONTROL) 1880 dev_vdbg(hsotg->dev, 1881 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1882 dev_addr, ep_num, ep_dir, ep_type, mps); 1883 urb->pipe_info.dev_addr = dev_addr; 1884 urb->pipe_info.ep_num = ep_num; 1885 urb->pipe_info.pipe_type = ep_type; 1886 urb->pipe_info.pipe_dir = ep_dir; 1887 urb->pipe_info.mps = mps; 1888 } 1889 1890 /* 1891 * NOTE: This function will be removed once the peripheral controller code 1892 * is integrated and the driver is stable 1893 */ 1894 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1895 { 1896 #ifdef DEBUG 1897 struct dwc2_host_chan *chan; 1898 struct dwc2_hcd_urb *urb; 1899 struct dwc2_qtd *qtd; 1900 int num_channels; 1901 u32 np_tx_status; 1902 u32 p_tx_status; 1903 int i; 1904 1905 num_channels = hsotg->core_params->host_channels; 1906 dev_dbg(hsotg->dev, "\n"); 1907 dev_dbg(hsotg->dev, 1908 "************************************************************\n"); 1909 dev_dbg(hsotg->dev, "HCD State:\n"); 1910 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 1911 1912 for (i = 0; i < num_channels; i++) { 1913 chan = hsotg->hc_ptr_array[i]; 1914 dev_dbg(hsotg->dev, " Channel %d:\n", i); 1915 dev_dbg(hsotg->dev, 1916 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 1917 chan->dev_addr, chan->ep_num, chan->ep_is_in); 1918 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 1919 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 1920 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 1921 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 1922 chan->data_pid_start); 1923 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 1924 dev_dbg(hsotg->dev, " xfer_started: %d\n", 1925 chan->xfer_started); 1926 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 1927 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 1928 (unsigned long)chan->xfer_dma); 1929 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 1930 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 1931 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 1932 chan->halt_on_queue); 1933 dev_dbg(hsotg->dev, " halt_pending: %d\n", 1934 chan->halt_pending); 1935 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 1936 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 1937 dev_dbg(hsotg->dev, " complete_split: %d\n", 1938 chan->complete_split); 1939 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 1940 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 1941 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 1942 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 1943 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 1944 1945 if (chan->xfer_started) { 1946 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 1947 1948 hfnum = readl(hsotg->regs + HFNUM); 1949 hcchar = readl(hsotg->regs + HCCHAR(i)); 1950 hctsiz = readl(hsotg->regs + HCTSIZ(i)); 1951 hcint = readl(hsotg->regs + HCINT(i)); 1952 hcintmsk = readl(hsotg->regs + HCINTMSK(i)); 1953 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 1954 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 1955 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 1956 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 1957 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 1958 } 1959 1960 if (!(chan->xfer_started && chan->qh)) 1961 continue; 1962 1963 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 1964 if (!qtd->in_process) 1965 break; 1966 urb = qtd->urb; 1967 dev_dbg(hsotg->dev, " URB Info:\n"); 1968 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 1969 qtd, urb); 1970 if (urb) { 1971 dev_dbg(hsotg->dev, 1972 " Dev: %d, EP: %d %s\n", 1973 dwc2_hcd_get_dev_addr(&urb->pipe_info), 1974 dwc2_hcd_get_ep_num(&urb->pipe_info), 1975 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1976 "IN" : "OUT"); 1977 dev_dbg(hsotg->dev, 1978 " Max packet size: %d\n", 1979 dwc2_hcd_get_mps(&urb->pipe_info)); 1980 dev_dbg(hsotg->dev, 1981 " transfer_buffer: %p\n", 1982 urb->buf); 1983 dev_dbg(hsotg->dev, 1984 " transfer_dma: %08lx\n", 1985 (unsigned long)urb->dma); 1986 dev_dbg(hsotg->dev, 1987 " transfer_buffer_length: %d\n", 1988 urb->length); 1989 dev_dbg(hsotg->dev, " actual_length: %d\n", 1990 urb->actual_length); 1991 } 1992 } 1993 } 1994 1995 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 1996 hsotg->non_periodic_channels); 1997 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 1998 hsotg->periodic_channels); 1999 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2000 np_tx_status = readl(hsotg->regs + GNPTXSTS); 2001 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2002 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2003 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2004 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2005 p_tx_status = readl(hsotg->regs + HPTXSTS); 2006 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2007 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2008 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2009 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2010 dwc2_hcd_dump_frrem(hsotg); 2011 dwc2_dump_global_registers(hsotg); 2012 dwc2_dump_host_registers(hsotg); 2013 dev_dbg(hsotg->dev, 2014 "************************************************************\n"); 2015 dev_dbg(hsotg->dev, "\n"); 2016 #endif 2017 } 2018 2019 /* 2020 * NOTE: This function will be removed once the peripheral controller code 2021 * is integrated and the driver is stable 2022 */ 2023 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2024 { 2025 #ifdef DWC2_DUMP_FRREM 2026 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2027 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2028 hsotg->frrem_samples, hsotg->frrem_accum, 2029 hsotg->frrem_samples > 0 ? 2030 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2031 dev_dbg(hsotg->dev, "\n"); 2032 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2033 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2034 hsotg->hfnum_7_samples, 2035 hsotg->hfnum_7_frrem_accum, 2036 hsotg->hfnum_7_samples > 0 ? 2037 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2038 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2039 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2040 hsotg->hfnum_0_samples, 2041 hsotg->hfnum_0_frrem_accum, 2042 hsotg->hfnum_0_samples > 0 ? 2043 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2044 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2045 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2046 hsotg->hfnum_other_samples, 2047 hsotg->hfnum_other_frrem_accum, 2048 hsotg->hfnum_other_samples > 0 ? 2049 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2050 0); 2051 dev_dbg(hsotg->dev, "\n"); 2052 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2053 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2054 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2055 hsotg->hfnum_7_samples_a > 0 ? 2056 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2057 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2058 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2059 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2060 hsotg->hfnum_0_samples_a > 0 ? 2061 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2062 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2063 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2064 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2065 hsotg->hfnum_other_samples_a > 0 ? 2066 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2067 : 0); 2068 dev_dbg(hsotg->dev, "\n"); 2069 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2070 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2071 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2072 hsotg->hfnum_7_samples_b > 0 ? 2073 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2074 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2075 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2076 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2077 (hsotg->hfnum_0_samples_b > 0) ? 2078 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2079 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2080 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2081 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2082 (hsotg->hfnum_other_samples_b > 0) ? 2083 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2084 : 0); 2085 #endif 2086 } 2087 2088 struct wrapper_priv_data { 2089 struct dwc2_hsotg *hsotg; 2090 }; 2091 2092 /* Gets the dwc2_hsotg from a usb_hcd */ 2093 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2094 { 2095 struct wrapper_priv_data *p; 2096 2097 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2098 return p->hsotg; 2099 } 2100 2101 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2102 2103 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2104 { 2105 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2106 2107 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2108 _dwc2_hcd_start(hcd); 2109 } 2110 2111 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2112 { 2113 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2114 2115 hcd->self.is_b_host = 0; 2116 } 2117 2118 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2119 int *hub_port) 2120 { 2121 struct urb *urb = context; 2122 2123 if (urb->dev->tt) 2124 *hub_addr = urb->dev->tt->hub->devnum; 2125 else 2126 *hub_addr = 0; 2127 *hub_port = urb->dev->ttport; 2128 } 2129 2130 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2131 { 2132 struct urb *urb = context; 2133 2134 return urb->dev->speed; 2135 } 2136 2137 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2138 struct urb *urb) 2139 { 2140 struct usb_bus *bus = hcd_to_bus(hcd); 2141 2142 if (urb->interval) 2143 bus->bandwidth_allocated += bw / urb->interval; 2144 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2145 bus->bandwidth_isoc_reqs++; 2146 else 2147 bus->bandwidth_int_reqs++; 2148 } 2149 2150 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2151 struct urb *urb) 2152 { 2153 struct usb_bus *bus = hcd_to_bus(hcd); 2154 2155 if (urb->interval) 2156 bus->bandwidth_allocated -= bw / urb->interval; 2157 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2158 bus->bandwidth_isoc_reqs--; 2159 else 2160 bus->bandwidth_int_reqs--; 2161 } 2162 2163 /* 2164 * Sets the final status of an URB and returns it to the upper layer. Any 2165 * required cleanup of the URB is performed. 2166 * 2167 * Must be called with interrupt disabled and spinlock held 2168 */ 2169 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2170 int status) 2171 { 2172 struct urb *urb; 2173 int i; 2174 2175 if (!qtd) { 2176 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2177 return; 2178 } 2179 2180 if (!qtd->urb) { 2181 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2182 return; 2183 } 2184 2185 urb = qtd->urb->priv; 2186 if (!urb) { 2187 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2188 return; 2189 } 2190 2191 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2192 2193 if (dbg_urb(urb)) 2194 dev_vdbg(hsotg->dev, 2195 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2196 __func__, urb, usb_pipedevice(urb->pipe), 2197 usb_pipeendpoint(urb->pipe), 2198 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2199 urb->actual_length); 2200 2201 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2202 for (i = 0; i < urb->number_of_packets; i++) 2203 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2204 i, urb->iso_frame_desc[i].status); 2205 } 2206 2207 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2208 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2209 for (i = 0; i < urb->number_of_packets; ++i) { 2210 urb->iso_frame_desc[i].actual_length = 2211 dwc2_hcd_urb_get_iso_desc_actual_length( 2212 qtd->urb, i); 2213 urb->iso_frame_desc[i].status = 2214 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2215 } 2216 } 2217 2218 urb->status = status; 2219 if (!status) { 2220 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2221 urb->actual_length < urb->transfer_buffer_length) 2222 urb->status = -EREMOTEIO; 2223 } 2224 2225 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2226 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2227 struct usb_host_endpoint *ep = urb->ep; 2228 2229 if (ep) 2230 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2231 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2232 urb); 2233 } 2234 2235 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2236 urb->hcpriv = NULL; 2237 kfree(qtd->urb); 2238 qtd->urb = NULL; 2239 2240 spin_unlock(&hsotg->lock); 2241 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2242 spin_lock(&hsotg->lock); 2243 } 2244 2245 /* 2246 * Work queue function for starting the HCD when A-Cable is connected 2247 */ 2248 static void dwc2_hcd_start_func(struct work_struct *work) 2249 { 2250 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2251 start_work.work); 2252 2253 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2254 dwc2_host_start(hsotg); 2255 } 2256 2257 /* 2258 * Reset work queue function 2259 */ 2260 static void dwc2_hcd_reset_func(struct work_struct *work) 2261 { 2262 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2263 reset_work.work); 2264 u32 hprt0; 2265 2266 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2267 hprt0 = dwc2_read_hprt0(hsotg); 2268 hprt0 &= ~HPRT0_RST; 2269 writel(hprt0, hsotg->regs + HPRT0); 2270 hsotg->flags.b.port_reset_change = 1; 2271 } 2272 2273 /* 2274 * ========================================================================= 2275 * Linux HC Driver Functions 2276 * ========================================================================= 2277 */ 2278 2279 /* 2280 * Initializes the DWC_otg controller and its root hub and prepares it for host 2281 * mode operation. Activates the root port. Returns 0 on success and a negative 2282 * error code on failure. 2283 */ 2284 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2285 { 2286 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2287 struct usb_bus *bus = hcd_to_bus(hcd); 2288 unsigned long flags; 2289 2290 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2291 2292 spin_lock_irqsave(&hsotg->lock, flags); 2293 2294 hcd->state = HC_STATE_RUNNING; 2295 2296 if (dwc2_is_device_mode(hsotg)) { 2297 spin_unlock_irqrestore(&hsotg->lock, flags); 2298 return 0; /* why 0 ?? */ 2299 } 2300 2301 dwc2_hcd_reinit(hsotg); 2302 2303 /* Initialize and connect root hub if one is not already attached */ 2304 if (bus->root_hub) { 2305 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2306 /* Inform the HUB driver to resume */ 2307 usb_hcd_resume_root_hub(hcd); 2308 } 2309 2310 spin_unlock_irqrestore(&hsotg->lock, flags); 2311 return 0; 2312 } 2313 2314 /* 2315 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2316 * stopped. 2317 */ 2318 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2319 { 2320 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2321 unsigned long flags; 2322 2323 spin_lock_irqsave(&hsotg->lock, flags); 2324 dwc2_hcd_stop(hsotg); 2325 spin_unlock_irqrestore(&hsotg->lock, flags); 2326 2327 usleep_range(1000, 3000); 2328 } 2329 2330 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2331 { 2332 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2333 2334 hsotg->lx_state = DWC2_L2; 2335 return 0; 2336 } 2337 2338 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2339 { 2340 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2341 2342 hsotg->lx_state = DWC2_L0; 2343 return 0; 2344 } 2345 2346 /* Returns the current frame number */ 2347 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2348 { 2349 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2350 2351 return dwc2_hcd_get_frame_number(hsotg); 2352 } 2353 2354 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2355 char *fn_name) 2356 { 2357 #ifdef VERBOSE_DEBUG 2358 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2359 char *pipetype; 2360 char *speed; 2361 2362 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2363 dev_vdbg(hsotg->dev, " Device address: %d\n", 2364 usb_pipedevice(urb->pipe)); 2365 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2366 usb_pipeendpoint(urb->pipe), 2367 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2368 2369 switch (usb_pipetype(urb->pipe)) { 2370 case PIPE_CONTROL: 2371 pipetype = "CONTROL"; 2372 break; 2373 case PIPE_BULK: 2374 pipetype = "BULK"; 2375 break; 2376 case PIPE_INTERRUPT: 2377 pipetype = "INTERRUPT"; 2378 break; 2379 case PIPE_ISOCHRONOUS: 2380 pipetype = "ISOCHRONOUS"; 2381 break; 2382 default: 2383 pipetype = "UNKNOWN"; 2384 break; 2385 } 2386 2387 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2388 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2389 "IN" : "OUT"); 2390 2391 switch (urb->dev->speed) { 2392 case USB_SPEED_HIGH: 2393 speed = "HIGH"; 2394 break; 2395 case USB_SPEED_FULL: 2396 speed = "FULL"; 2397 break; 2398 case USB_SPEED_LOW: 2399 speed = "LOW"; 2400 break; 2401 default: 2402 speed = "UNKNOWN"; 2403 break; 2404 } 2405 2406 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2407 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2408 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2409 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2410 urb->transfer_buffer_length); 2411 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2412 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2413 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2414 urb->setup_packet, (unsigned long)urb->setup_dma); 2415 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2416 2417 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2418 int i; 2419 2420 for (i = 0; i < urb->number_of_packets; i++) { 2421 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2422 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2423 urb->iso_frame_desc[i].offset, 2424 urb->iso_frame_desc[i].length); 2425 } 2426 } 2427 #endif 2428 } 2429 2430 /* 2431 * Starts processing a USB transfer request specified by a USB Request Block 2432 * (URB). mem_flags indicates the type of memory allocation to use while 2433 * processing this URB. 2434 */ 2435 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2436 gfp_t mem_flags) 2437 { 2438 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2439 struct usb_host_endpoint *ep = urb->ep; 2440 struct dwc2_hcd_urb *dwc2_urb; 2441 int i; 2442 int retval; 2443 int alloc_bandwidth = 0; 2444 u8 ep_type = 0; 2445 u32 tflags = 0; 2446 void *buf; 2447 unsigned long flags; 2448 2449 if (dbg_urb(urb)) { 2450 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2451 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2452 } 2453 2454 if (ep == NULL) 2455 return -EINVAL; 2456 2457 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2458 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2459 spin_lock_irqsave(&hsotg->lock, flags); 2460 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2461 alloc_bandwidth = 1; 2462 spin_unlock_irqrestore(&hsotg->lock, flags); 2463 } 2464 2465 switch (usb_pipetype(urb->pipe)) { 2466 case PIPE_CONTROL: 2467 ep_type = USB_ENDPOINT_XFER_CONTROL; 2468 break; 2469 case PIPE_ISOCHRONOUS: 2470 ep_type = USB_ENDPOINT_XFER_ISOC; 2471 break; 2472 case PIPE_BULK: 2473 ep_type = USB_ENDPOINT_XFER_BULK; 2474 break; 2475 case PIPE_INTERRUPT: 2476 ep_type = USB_ENDPOINT_XFER_INT; 2477 break; 2478 default: 2479 dev_warn(hsotg->dev, "Wrong ep type\n"); 2480 } 2481 2482 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2483 mem_flags); 2484 if (!dwc2_urb) 2485 return -ENOMEM; 2486 2487 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2488 usb_pipeendpoint(urb->pipe), ep_type, 2489 usb_pipein(urb->pipe), 2490 usb_maxpacket(urb->dev, urb->pipe, 2491 !(usb_pipein(urb->pipe)))); 2492 2493 buf = urb->transfer_buffer; 2494 2495 if (hcd->self.uses_dma) { 2496 if (!buf && (urb->transfer_dma & 3)) { 2497 dev_err(hsotg->dev, 2498 "%s: unaligned transfer with no transfer_buffer", 2499 __func__); 2500 retval = -EINVAL; 2501 goto fail0; 2502 } 2503 } 2504 2505 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2506 tflags |= URB_GIVEBACK_ASAP; 2507 if (urb->transfer_flags & URB_ZERO_PACKET) 2508 tflags |= URB_SEND_ZERO_PACKET; 2509 2510 dwc2_urb->priv = urb; 2511 dwc2_urb->buf = buf; 2512 dwc2_urb->dma = urb->transfer_dma; 2513 dwc2_urb->length = urb->transfer_buffer_length; 2514 dwc2_urb->setup_packet = urb->setup_packet; 2515 dwc2_urb->setup_dma = urb->setup_dma; 2516 dwc2_urb->flags = tflags; 2517 dwc2_urb->interval = urb->interval; 2518 dwc2_urb->status = -EINPROGRESS; 2519 2520 for (i = 0; i < urb->number_of_packets; ++i) 2521 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2522 urb->iso_frame_desc[i].offset, 2523 urb->iso_frame_desc[i].length); 2524 2525 urb->hcpriv = dwc2_urb; 2526 2527 spin_lock_irqsave(&hsotg->lock, flags); 2528 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2529 if (retval) 2530 goto fail1; 2531 2532 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv, mem_flags); 2533 if (retval) 2534 goto fail2; 2535 2536 if (alloc_bandwidth) { 2537 dwc2_allocate_bus_bandwidth(hcd, 2538 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2539 urb); 2540 } 2541 2542 spin_unlock_irqrestore(&hsotg->lock, flags); 2543 2544 return 0; 2545 2546 fail2: 2547 dwc2_urb->priv = NULL; 2548 usb_hcd_unlink_urb_from_ep(hcd, urb); 2549 fail1: 2550 spin_unlock_irqrestore(&hsotg->lock, flags); 2551 urb->hcpriv = NULL; 2552 fail0: 2553 kfree(dwc2_urb); 2554 2555 return retval; 2556 } 2557 2558 /* 2559 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2560 */ 2561 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2562 int status) 2563 { 2564 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2565 int rc; 2566 unsigned long flags; 2567 2568 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2569 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2570 2571 spin_lock_irqsave(&hsotg->lock, flags); 2572 2573 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2574 if (rc) 2575 goto out; 2576 2577 if (!urb->hcpriv) { 2578 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2579 goto out; 2580 } 2581 2582 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2583 2584 usb_hcd_unlink_urb_from_ep(hcd, urb); 2585 2586 kfree(urb->hcpriv); 2587 urb->hcpriv = NULL; 2588 2589 /* Higher layer software sets URB status */ 2590 spin_unlock(&hsotg->lock); 2591 usb_hcd_giveback_urb(hcd, urb, status); 2592 spin_lock(&hsotg->lock); 2593 2594 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2595 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2596 out: 2597 spin_unlock_irqrestore(&hsotg->lock, flags); 2598 2599 return rc; 2600 } 2601 2602 /* 2603 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2604 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2605 * must already be dequeued. 2606 */ 2607 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2608 struct usb_host_endpoint *ep) 2609 { 2610 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2611 2612 dev_dbg(hsotg->dev, 2613 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2614 ep->desc.bEndpointAddress, ep->hcpriv); 2615 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2616 } 2617 2618 /* 2619 * Resets endpoint specific parameter values, in current version used to reset 2620 * the data toggle (as a WA). This function can be called from usb_clear_halt 2621 * routine. 2622 */ 2623 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2624 struct usb_host_endpoint *ep) 2625 { 2626 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2627 unsigned long flags; 2628 2629 dev_dbg(hsotg->dev, 2630 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2631 ep->desc.bEndpointAddress); 2632 2633 spin_lock_irqsave(&hsotg->lock, flags); 2634 dwc2_hcd_endpoint_reset(hsotg, ep); 2635 spin_unlock_irqrestore(&hsotg->lock, flags); 2636 } 2637 2638 /* 2639 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2640 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2641 * interrupt. 2642 * 2643 * This function is called by the USB core when an interrupt occurs 2644 */ 2645 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2646 { 2647 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2648 2649 return dwc2_handle_hcd_intr(hsotg); 2650 } 2651 2652 /* 2653 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2654 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2655 * is the status change indicator for the single root port. Returns 1 if either 2656 * change indicator is 1, otherwise returns 0. 2657 */ 2658 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2659 { 2660 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2661 2662 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2663 return buf[0] != 0; 2664 } 2665 2666 /* Handles hub class-specific requests */ 2667 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2668 u16 windex, char *buf, u16 wlength) 2669 { 2670 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2671 wvalue, windex, buf, wlength); 2672 return retval; 2673 } 2674 2675 /* Handles hub TT buffer clear completions */ 2676 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2677 struct usb_host_endpoint *ep) 2678 { 2679 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2680 struct dwc2_qh *qh; 2681 unsigned long flags; 2682 2683 qh = ep->hcpriv; 2684 if (!qh) 2685 return; 2686 2687 spin_lock_irqsave(&hsotg->lock, flags); 2688 qh->tt_buffer_dirty = 0; 2689 2690 if (hsotg->flags.b.port_connect_status) 2691 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2692 2693 spin_unlock_irqrestore(&hsotg->lock, flags); 2694 } 2695 2696 static struct hc_driver dwc2_hc_driver = { 2697 .description = "dwc2_hsotg", 2698 .product_desc = "DWC OTG Controller", 2699 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2700 2701 .irq = _dwc2_hcd_irq, 2702 .flags = HCD_MEMORY | HCD_USB2, 2703 2704 .start = _dwc2_hcd_start, 2705 .stop = _dwc2_hcd_stop, 2706 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2707 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2708 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2709 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2710 .get_frame_number = _dwc2_hcd_get_frame_number, 2711 2712 .hub_status_data = _dwc2_hcd_hub_status_data, 2713 .hub_control = _dwc2_hcd_hub_control, 2714 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2715 2716 .bus_suspend = _dwc2_hcd_suspend, 2717 .bus_resume = _dwc2_hcd_resume, 2718 }; 2719 2720 /* 2721 * Frees secondary storage associated with the dwc2_hsotg structure contained 2722 * in the struct usb_hcd field 2723 */ 2724 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2725 { 2726 u32 ahbcfg; 2727 u32 dctl; 2728 int i; 2729 2730 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2731 2732 /* Free memory for QH/QTD lists */ 2733 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2734 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2735 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2736 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2737 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 2738 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 2739 2740 /* Free memory for the host channels */ 2741 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 2742 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 2743 2744 if (chan != NULL) { 2745 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 2746 i, chan); 2747 hsotg->hc_ptr_array[i] = NULL; 2748 kfree(chan); 2749 } 2750 } 2751 2752 if (hsotg->core_params->dma_enable > 0) { 2753 if (hsotg->status_buf) { 2754 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 2755 hsotg->status_buf, 2756 hsotg->status_buf_dma); 2757 hsotg->status_buf = NULL; 2758 } 2759 } else { 2760 kfree(hsotg->status_buf); 2761 hsotg->status_buf = NULL; 2762 } 2763 2764 ahbcfg = readl(hsotg->regs + GAHBCFG); 2765 2766 /* Disable all interrupts */ 2767 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 2768 writel(ahbcfg, hsotg->regs + GAHBCFG); 2769 writel(0, hsotg->regs + GINTMSK); 2770 2771 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 2772 dctl = readl(hsotg->regs + DCTL); 2773 dctl |= DCTL_SFTDISCON; 2774 writel(dctl, hsotg->regs + DCTL); 2775 } 2776 2777 if (hsotg->wq_otg) { 2778 if (!cancel_work_sync(&hsotg->wf_otg)) 2779 flush_workqueue(hsotg->wq_otg); 2780 destroy_workqueue(hsotg->wq_otg); 2781 } 2782 2783 del_timer(&hsotg->wkp_timer); 2784 } 2785 2786 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 2787 { 2788 /* Turn off all host-specific interrupts */ 2789 dwc2_disable_host_interrupts(hsotg); 2790 2791 dwc2_hcd_free(hsotg); 2792 } 2793 2794 /* 2795 * Initializes the HCD. This function allocates memory for and initializes the 2796 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 2797 * USB bus with the core and calls the hc_driver->start() function. It returns 2798 * a negative error on failure. 2799 */ 2800 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 2801 { 2802 struct usb_hcd *hcd; 2803 struct dwc2_host_chan *channel; 2804 u32 hcfg; 2805 int i, num_channels; 2806 int retval; 2807 2808 if (usb_disabled()) 2809 return -ENODEV; 2810 2811 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 2812 2813 retval = -ENOMEM; 2814 2815 hcfg = readl(hsotg->regs + HCFG); 2816 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 2817 2818 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2819 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 2820 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2821 if (!hsotg->frame_num_array) 2822 goto error1; 2823 hsotg->last_frame_num_array = kzalloc( 2824 sizeof(*hsotg->last_frame_num_array) * 2825 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 2826 if (!hsotg->last_frame_num_array) 2827 goto error1; 2828 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 2829 #endif 2830 2831 /* Check if the bus driver or platform code has setup a dma_mask */ 2832 if (hsotg->core_params->dma_enable > 0 && 2833 hsotg->dev->dma_mask == NULL) { 2834 dev_warn(hsotg->dev, 2835 "dma_mask not set, disabling DMA\n"); 2836 hsotg->core_params->dma_enable = 0; 2837 hsotg->core_params->dma_desc_enable = 0; 2838 } 2839 2840 /* Set device flags indicating whether the HCD supports DMA */ 2841 if (hsotg->core_params->dma_enable > 0) { 2842 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2843 dev_warn(hsotg->dev, "can't set DMA mask\n"); 2844 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 2845 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 2846 } 2847 2848 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 2849 if (!hcd) 2850 goto error1; 2851 2852 if (hsotg->core_params->dma_enable <= 0) 2853 hcd->self.uses_dma = 0; 2854 2855 hcd->has_tt = 1; 2856 2857 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 2858 hsotg->priv = hcd; 2859 2860 /* 2861 * Disable the global interrupt until all the interrupt handlers are 2862 * installed 2863 */ 2864 dwc2_disable_global_interrupts(hsotg); 2865 2866 /* Initialize the DWC_otg core, and select the Phy type */ 2867 retval = dwc2_core_init(hsotg, true, irq); 2868 if (retval) 2869 goto error2; 2870 2871 /* Create new workqueue and init work */ 2872 retval = -ENOMEM; 2873 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 2874 if (!hsotg->wq_otg) { 2875 dev_err(hsotg->dev, "Failed to create workqueue\n"); 2876 goto error2; 2877 } 2878 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 2879 2880 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 2881 (unsigned long)hsotg); 2882 2883 /* Initialize the non-periodic schedule */ 2884 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 2885 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 2886 2887 /* Initialize the periodic schedule */ 2888 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 2889 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 2890 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 2891 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 2892 2893 /* 2894 * Create a host channel descriptor for each host channel implemented 2895 * in the controller. Initialize the channel descriptor array. 2896 */ 2897 INIT_LIST_HEAD(&hsotg->free_hc_list); 2898 num_channels = hsotg->core_params->host_channels; 2899 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 2900 2901 for (i = 0; i < num_channels; i++) { 2902 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 2903 if (channel == NULL) 2904 goto error3; 2905 channel->hc_num = i; 2906 hsotg->hc_ptr_array[i] = channel; 2907 } 2908 2909 if (hsotg->core_params->uframe_sched > 0) 2910 dwc2_hcd_init_usecs(hsotg); 2911 2912 /* Initialize hsotg start work */ 2913 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 2914 2915 /* Initialize port reset work */ 2916 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 2917 2918 /* 2919 * Allocate space for storing data on status transactions. Normally no 2920 * data is sent, but this space acts as a bit bucket. This must be 2921 * done after usb_add_hcd since that function allocates the DMA buffer 2922 * pool. 2923 */ 2924 if (hsotg->core_params->dma_enable > 0) 2925 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 2926 DWC2_HCD_STATUS_BUF_SIZE, 2927 &hsotg->status_buf_dma, GFP_KERNEL); 2928 else 2929 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 2930 GFP_KERNEL); 2931 2932 if (!hsotg->status_buf) 2933 goto error3; 2934 2935 hsotg->otg_port = 1; 2936 hsotg->frame_list = NULL; 2937 hsotg->frame_list_dma = 0; 2938 hsotg->periodic_qh_count = 0; 2939 2940 /* Initiate lx_state to L3 disconnected state */ 2941 hsotg->lx_state = DWC2_L3; 2942 2943 hcd->self.otg_port = hsotg->otg_port; 2944 2945 /* Don't support SG list at this point */ 2946 hcd->self.sg_tablesize = 0; 2947 2948 if (!IS_ERR_OR_NULL(hsotg->uphy)) 2949 otg_set_host(hsotg->uphy->otg, &hcd->self); 2950 2951 /* 2952 * Finish generic HCD initialization and start the HCD. This function 2953 * allocates the DMA buffer pool, registers the USB bus, requests the 2954 * IRQ line, and calls hcd_start method. 2955 */ 2956 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 2957 if (retval < 0) 2958 goto error3; 2959 2960 device_wakeup_enable(hcd->self.controller); 2961 2962 dwc2_hcd_dump_state(hsotg); 2963 2964 dwc2_enable_global_interrupts(hsotg); 2965 2966 return 0; 2967 2968 error3: 2969 dwc2_hcd_release(hsotg); 2970 error2: 2971 usb_put_hcd(hcd); 2972 error1: 2973 kfree(hsotg->core_params); 2974 2975 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 2976 kfree(hsotg->last_frame_num_array); 2977 kfree(hsotg->frame_num_array); 2978 #endif 2979 2980 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 2981 return retval; 2982 } 2983 2984 /* 2985 * Removes the HCD. 2986 * Frees memory and resources associated with the HCD and deregisters the bus. 2987 */ 2988 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 2989 { 2990 struct usb_hcd *hcd; 2991 2992 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 2993 2994 hcd = dwc2_hsotg_to_hcd(hsotg); 2995 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 2996 2997 if (!hcd) { 2998 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 2999 __func__); 3000 return; 3001 } 3002 3003 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3004 otg_set_host(hsotg->uphy->otg, NULL); 3005 3006 usb_remove_hcd(hcd); 3007 hsotg->priv = NULL; 3008 dwc2_hcd_release(hsotg); 3009 usb_put_hcd(hcd); 3010 3011 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3012 kfree(hsotg->last_frame_num_array); 3013 kfree(hsotg->frame_num_array); 3014 #endif 3015 } 3016