1 /* 2 * hcd.c - DesignWare HS OTG Controller host-mode routines 3 * 4 * Copyright (C) 2004-2013 Synopsys, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The names of the above-listed copyright holders may not be used 16 * to endorse or promote products derived from this software without 17 * specific prior written permission. 18 * 19 * ALTERNATIVELY, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") as published by the Free Software 21 * Foundation; either version 2 of the License, or (at your option) any 22 * later version. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * This file contains the core HCD code, and implements the Linux hc_driver 39 * API 40 */ 41 #include <linux/kernel.h> 42 #include <linux/module.h> 43 #include <linux/spinlock.h> 44 #include <linux/interrupt.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/delay.h> 47 #include <linux/io.h> 48 #include <linux/slab.h> 49 #include <linux/usb.h> 50 51 #include <linux/usb/hcd.h> 52 #include <linux/usb/ch11.h> 53 54 #include "core.h" 55 #include "hcd.h" 56 57 /** 58 * dwc2_dump_channel_info() - Prints the state of a host channel 59 * 60 * @hsotg: Programming view of DWC_otg controller 61 * @chan: Pointer to the channel to dump 62 * 63 * Must be called with interrupt disabled and spinlock held 64 * 65 * NOTE: This function will be removed once the peripheral controller code 66 * is integrated and the driver is stable 67 */ 68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 69 struct dwc2_host_chan *chan) 70 { 71 #ifdef VERBOSE_DEBUG 72 int num_channels = hsotg->core_params->host_channels; 73 struct dwc2_qh *qh; 74 u32 hcchar; 75 u32 hcsplt; 76 u32 hctsiz; 77 u32 hc_dma; 78 int i; 79 80 if (chan == NULL) 81 return; 82 83 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); 84 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); 85 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); 86 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); 87 88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); 89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", 90 hcchar, hcsplt); 91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", 92 hctsiz, hc_dma); 93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 94 chan->dev_addr, chan->ep_num, chan->ep_is_in); 95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start); 98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started); 99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 102 (unsigned long)chan->xfer_dma); 103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 105 dev_dbg(hsotg->dev, " NP inactive sched:\n"); 106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive, 107 qh_list_entry) 108 dev_dbg(hsotg->dev, " %p\n", qh); 109 dev_dbg(hsotg->dev, " NP active sched:\n"); 110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active, 111 qh_list_entry) 112 dev_dbg(hsotg->dev, " %p\n", qh); 113 dev_dbg(hsotg->dev, " Channels:\n"); 114 for (i = 0; i < num_channels; i++) { 115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 116 117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan); 118 } 119 #endif /* VERBOSE_DEBUG */ 120 } 121 122 /* 123 * Processes all the URBs in a single list of QHs. Completes them with 124 * -ETIMEDOUT and frees the QTD. 125 * 126 * Must be called with interrupt disabled and spinlock held 127 */ 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg, 129 struct list_head *qh_list) 130 { 131 struct dwc2_qh *qh, *qh_tmp; 132 struct dwc2_qtd *qtd, *qtd_tmp; 133 134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 136 qtd_list_entry) { 137 dwc2_host_complete(hsotg, qtd, -ECONNRESET); 138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 139 } 140 } 141 } 142 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 144 struct list_head *qh_list) 145 { 146 struct dwc2_qtd *qtd, *qtd_tmp; 147 struct dwc2_qh *qh, *qh_tmp; 148 unsigned long flags; 149 150 if (!qh_list->next) 151 /* The list hasn't been initialized yet */ 152 return; 153 154 spin_lock_irqsave(&hsotg->lock, flags); 155 156 /* Ensure there are no QTDs or URBs left */ 157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list); 158 159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) { 160 dwc2_hcd_qh_unlink(hsotg, qh); 161 162 /* Free each QTD in the QH's QTD list */ 163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, 164 qtd_list_entry) 165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 166 167 if (qh->channel && qh->channel->qh == qh) 168 qh->channel->qh = NULL; 169 170 spin_unlock_irqrestore(&hsotg->lock, flags); 171 dwc2_hcd_qh_free(hsotg, qh); 172 spin_lock_irqsave(&hsotg->lock, flags); 173 } 174 175 spin_unlock_irqrestore(&hsotg->lock, flags); 176 } 177 178 /* 179 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic 180 * and periodic schedules. The QTD associated with each URB is removed from 181 * the schedule and freed. This function may be called when a disconnect is 182 * detected or when the HCD is being stopped. 183 * 184 * Must be called with interrupt disabled and spinlock held 185 */ 186 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg) 187 { 188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive); 189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active); 190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive); 191 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready); 192 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned); 193 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued); 194 } 195 196 /** 197 * dwc2_hcd_start() - Starts the HCD when switching to Host mode 198 * 199 * @hsotg: Pointer to struct dwc2_hsotg 200 */ 201 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) 202 { 203 u32 hprt0; 204 205 if (hsotg->op_state == OTG_STATE_B_HOST) { 206 /* 207 * Reset the port. During a HNP mode switch the reset 208 * needs to occur within 1ms and have a duration of at 209 * least 50ms. 210 */ 211 hprt0 = dwc2_read_hprt0(hsotg); 212 hprt0 |= HPRT0_RST; 213 dwc2_writel(hprt0, hsotg->regs + HPRT0); 214 } 215 216 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, 217 msecs_to_jiffies(50)); 218 } 219 220 /* Must be called with interrupt disabled and spinlock held */ 221 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) 222 { 223 int num_channels = hsotg->core_params->host_channels; 224 struct dwc2_host_chan *channel; 225 u32 hcchar; 226 int i; 227 228 if (hsotg->core_params->dma_enable <= 0) { 229 /* Flush out any channel requests in slave mode */ 230 for (i = 0; i < num_channels; i++) { 231 channel = hsotg->hc_ptr_array[i]; 232 if (!list_empty(&channel->hc_list_entry)) 233 continue; 234 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 235 if (hcchar & HCCHAR_CHENA) { 236 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); 237 hcchar |= HCCHAR_CHDIS; 238 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 239 } 240 } 241 } 242 243 for (i = 0; i < num_channels; i++) { 244 channel = hsotg->hc_ptr_array[i]; 245 if (!list_empty(&channel->hc_list_entry)) 246 continue; 247 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 248 if (hcchar & HCCHAR_CHENA) { 249 /* Halt the channel */ 250 hcchar |= HCCHAR_CHDIS; 251 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); 252 } 253 254 dwc2_hc_cleanup(hsotg, channel); 255 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list); 256 /* 257 * Added for Descriptor DMA to prevent channel double cleanup in 258 * release_channel_ddma(), which is called from ep_disable when 259 * device disconnects 260 */ 261 channel->qh = NULL; 262 } 263 /* All channels have been freed, mark them available */ 264 if (hsotg->core_params->uframe_sched > 0) { 265 hsotg->available_host_channels = 266 hsotg->core_params->host_channels; 267 } else { 268 hsotg->non_periodic_channels = 0; 269 hsotg->periodic_channels = 0; 270 } 271 } 272 273 /** 274 * dwc2_hcd_connect() - Handles connect of the HCD 275 * 276 * @hsotg: Pointer to struct dwc2_hsotg 277 * 278 * Must be called with interrupt disabled and spinlock held 279 */ 280 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) 281 { 282 if (hsotg->lx_state != DWC2_L0) 283 usb_hcd_resume_root_hub(hsotg->priv); 284 285 hsotg->flags.b.port_connect_status_change = 1; 286 hsotg->flags.b.port_connect_status = 1; 287 } 288 289 /** 290 * dwc2_hcd_disconnect() - Handles disconnect of the HCD 291 * 292 * @hsotg: Pointer to struct dwc2_hsotg 293 * @force: If true, we won't try to reconnect even if we see device connected. 294 * 295 * Must be called with interrupt disabled and spinlock held 296 */ 297 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) 298 { 299 u32 intr; 300 u32 hprt0; 301 302 /* Set status flags for the hub driver */ 303 hsotg->flags.b.port_connect_status_change = 1; 304 hsotg->flags.b.port_connect_status = 0; 305 306 /* 307 * Shutdown any transfers in process by clearing the Tx FIFO Empty 308 * interrupt mask and status bits and disabling subsequent host 309 * channel interrupts. 310 */ 311 intr = dwc2_readl(hsotg->regs + GINTMSK); 312 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); 313 dwc2_writel(intr, hsotg->regs + GINTMSK); 314 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; 315 dwc2_writel(intr, hsotg->regs + GINTSTS); 316 317 /* 318 * Turn off the vbus power only if the core has transitioned to device 319 * mode. If still in host mode, need to keep power on to detect a 320 * reconnection. 321 */ 322 if (dwc2_is_device_mode(hsotg)) { 323 if (hsotg->op_state != OTG_STATE_A_SUSPEND) { 324 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); 325 dwc2_writel(0, hsotg->regs + HPRT0); 326 } 327 328 dwc2_disable_host_interrupts(hsotg); 329 } 330 331 /* Respond with an error status to all URBs in the schedule */ 332 dwc2_kill_all_urbs(hsotg); 333 334 if (dwc2_is_host_mode(hsotg)) 335 /* Clean up any host channels that were in use */ 336 dwc2_hcd_cleanup_channels(hsotg); 337 338 dwc2_host_disconnect(hsotg); 339 340 /* 341 * Add an extra check here to see if we're actually connected but 342 * we don't have a detection interrupt pending. This can happen if: 343 * 1. hardware sees connect 344 * 2. hardware sees disconnect 345 * 3. hardware sees connect 346 * 4. dwc2_port_intr() - clears connect interrupt 347 * 5. dwc2_handle_common_intr() - calls here 348 * 349 * Without the extra check here we will end calling disconnect 350 * and won't get any future interrupts to handle the connect. 351 */ 352 if (!force) { 353 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 354 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) 355 dwc2_hcd_connect(hsotg); 356 } 357 } 358 359 /** 360 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup 361 * 362 * @hsotg: Pointer to struct dwc2_hsotg 363 */ 364 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg) 365 { 366 if (hsotg->bus_suspended) { 367 hsotg->flags.b.port_suspend_change = 1; 368 usb_hcd_resume_root_hub(hsotg->priv); 369 } 370 371 if (hsotg->lx_state == DWC2_L1) 372 hsotg->flags.b.port_l1_change = 1; 373 } 374 375 /** 376 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner 377 * 378 * @hsotg: Pointer to struct dwc2_hsotg 379 * 380 * Must be called with interrupt disabled and spinlock held 381 */ 382 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) 383 { 384 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n"); 385 386 /* 387 * The root hub should be disconnected before this function is called. 388 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) 389 * and the QH lists (via ..._hcd_endpoint_disable). 390 */ 391 392 /* Turn off all host-specific interrupts */ 393 dwc2_disable_host_interrupts(hsotg); 394 395 /* Turn off the vbus power */ 396 dev_dbg(hsotg->dev, "PortPower off\n"); 397 dwc2_writel(0, hsotg->regs + HPRT0); 398 } 399 400 /* Caller must hold driver lock */ 401 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, 402 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh, 403 struct dwc2_qtd *qtd) 404 { 405 u32 intr_mask; 406 int retval; 407 int dev_speed; 408 409 if (!hsotg->flags.b.port_connect_status) { 410 /* No longer connected */ 411 dev_err(hsotg->dev, "Not connected\n"); 412 return -ENODEV; 413 } 414 415 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 416 417 /* Some configurations cannot support LS traffic on a FS root port */ 418 if ((dev_speed == USB_SPEED_LOW) && 419 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && 420 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { 421 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 422 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 423 424 if (prtspd == HPRT0_SPD_FULL_SPEED) 425 return -ENODEV; 426 } 427 428 if (!qtd) 429 return -EINVAL; 430 431 dwc2_hcd_qtd_init(qtd, urb); 432 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh); 433 if (retval) { 434 dev_err(hsotg->dev, 435 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n", 436 retval); 437 return retval; 438 } 439 440 intr_mask = dwc2_readl(hsotg->regs + GINTMSK); 441 if (!(intr_mask & GINTSTS_SOF)) { 442 enum dwc2_transaction_type tr_type; 443 444 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK && 445 !(qtd->urb->flags & URB_GIVEBACK_ASAP)) 446 /* 447 * Do not schedule SG transactions until qtd has 448 * URB_GIVEBACK_ASAP set 449 */ 450 return 0; 451 452 tr_type = dwc2_hcd_select_transactions(hsotg); 453 if (tr_type != DWC2_TRANSACTION_NONE) 454 dwc2_hcd_queue_transactions(hsotg, tr_type); 455 } 456 457 return 0; 458 } 459 460 /* Must be called with interrupt disabled and spinlock held */ 461 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg, 462 struct dwc2_hcd_urb *urb) 463 { 464 struct dwc2_qh *qh; 465 struct dwc2_qtd *urb_qtd; 466 467 urb_qtd = urb->qtd; 468 if (!urb_qtd) { 469 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n"); 470 return -EINVAL; 471 } 472 473 qh = urb_qtd->qh; 474 if (!qh) { 475 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n"); 476 return -EINVAL; 477 } 478 479 urb->priv = NULL; 480 481 if (urb_qtd->in_process && qh->channel) { 482 dwc2_dump_channel_info(hsotg, qh->channel); 483 484 /* The QTD is in process (it has been assigned to a channel) */ 485 if (hsotg->flags.b.port_connect_status) 486 /* 487 * If still connected (i.e. in host mode), halt the 488 * channel so it can be used for other transfers. If 489 * no longer connected, the host registers can't be 490 * written to halt the channel since the core is in 491 * device mode. 492 */ 493 dwc2_hc_halt(hsotg, qh->channel, 494 DWC2_HC_XFER_URB_DEQUEUE); 495 } 496 497 /* 498 * Free the QTD and clean up the associated QH. Leave the QH in the 499 * schedule if it has any remaining QTDs. 500 */ 501 if (hsotg->core_params->dma_desc_enable <= 0) { 502 u8 in_process = urb_qtd->in_process; 503 504 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 505 if (in_process) { 506 dwc2_hcd_qh_deactivate(hsotg, qh, 0); 507 qh->channel = NULL; 508 } else if (list_empty(&qh->qtd_list)) { 509 dwc2_hcd_qh_unlink(hsotg, qh); 510 } 511 } else { 512 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh); 513 } 514 515 return 0; 516 } 517 518 /* Must NOT be called with interrupt disabled or spinlock held */ 519 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg, 520 struct usb_host_endpoint *ep, int retry) 521 { 522 struct dwc2_qtd *qtd, *qtd_tmp; 523 struct dwc2_qh *qh; 524 unsigned long flags; 525 int rc; 526 527 spin_lock_irqsave(&hsotg->lock, flags); 528 529 qh = ep->hcpriv; 530 if (!qh) { 531 rc = -EINVAL; 532 goto err; 533 } 534 535 while (!list_empty(&qh->qtd_list) && retry--) { 536 if (retry == 0) { 537 dev_err(hsotg->dev, 538 "## timeout in dwc2_hcd_endpoint_disable() ##\n"); 539 rc = -EBUSY; 540 goto err; 541 } 542 543 spin_unlock_irqrestore(&hsotg->lock, flags); 544 usleep_range(20000, 40000); 545 spin_lock_irqsave(&hsotg->lock, flags); 546 qh = ep->hcpriv; 547 if (!qh) { 548 rc = -EINVAL; 549 goto err; 550 } 551 } 552 553 dwc2_hcd_qh_unlink(hsotg, qh); 554 555 /* Free each QTD in the QH's QTD list */ 556 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) 557 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh); 558 559 ep->hcpriv = NULL; 560 561 if (qh->channel && qh->channel->qh == qh) 562 qh->channel->qh = NULL; 563 564 spin_unlock_irqrestore(&hsotg->lock, flags); 565 566 dwc2_hcd_qh_free(hsotg, qh); 567 568 return 0; 569 570 err: 571 ep->hcpriv = NULL; 572 spin_unlock_irqrestore(&hsotg->lock, flags); 573 574 return rc; 575 } 576 577 /* Must be called with interrupt disabled and spinlock held */ 578 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg, 579 struct usb_host_endpoint *ep) 580 { 581 struct dwc2_qh *qh = ep->hcpriv; 582 583 if (!qh) 584 return -EINVAL; 585 586 qh->data_toggle = DWC2_HC_PID_DATA0; 587 588 return 0; 589 } 590 591 /* 592 * Initializes dynamic portions of the DWC_otg HCD state 593 * 594 * Must be called with interrupt disabled and spinlock held 595 */ 596 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg) 597 { 598 struct dwc2_host_chan *chan, *chan_tmp; 599 int num_channels; 600 int i; 601 602 hsotg->flags.d32 = 0; 603 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active; 604 605 if (hsotg->core_params->uframe_sched > 0) { 606 hsotg->available_host_channels = 607 hsotg->core_params->host_channels; 608 } else { 609 hsotg->non_periodic_channels = 0; 610 hsotg->periodic_channels = 0; 611 } 612 613 /* 614 * Put all channels in the free channel list and clean up channel 615 * states 616 */ 617 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list, 618 hc_list_entry) 619 list_del_init(&chan->hc_list_entry); 620 621 num_channels = hsotg->core_params->host_channels; 622 for (i = 0; i < num_channels; i++) { 623 chan = hsotg->hc_ptr_array[i]; 624 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list); 625 dwc2_hc_cleanup(hsotg, chan); 626 } 627 628 /* Initialize the DWC core for host mode operation */ 629 dwc2_core_host_init(hsotg); 630 } 631 632 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg, 633 struct dwc2_host_chan *chan, 634 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 635 { 636 int hub_addr, hub_port; 637 638 chan->do_split = 1; 639 chan->xact_pos = qtd->isoc_split_pos; 640 chan->complete_split = qtd->complete_split; 641 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 642 chan->hub_addr = (u8)hub_addr; 643 chan->hub_port = (u8)hub_port; 644 } 645 646 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg, 647 struct dwc2_host_chan *chan, 648 struct dwc2_qtd *qtd) 649 { 650 struct dwc2_hcd_urb *urb = qtd->urb; 651 struct dwc2_hcd_iso_packet_desc *frame_desc; 652 653 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) { 654 case USB_ENDPOINT_XFER_CONTROL: 655 chan->ep_type = USB_ENDPOINT_XFER_CONTROL; 656 657 switch (qtd->control_phase) { 658 case DWC2_CONTROL_SETUP: 659 dev_vdbg(hsotg->dev, " Control setup transaction\n"); 660 chan->do_ping = 0; 661 chan->ep_is_in = 0; 662 chan->data_pid_start = DWC2_HC_PID_SETUP; 663 if (hsotg->core_params->dma_enable > 0) 664 chan->xfer_dma = urb->setup_dma; 665 else 666 chan->xfer_buf = urb->setup_packet; 667 chan->xfer_len = 8; 668 break; 669 670 case DWC2_CONTROL_DATA: 671 dev_vdbg(hsotg->dev, " Control data transaction\n"); 672 chan->data_pid_start = qtd->data_toggle; 673 break; 674 675 case DWC2_CONTROL_STATUS: 676 /* 677 * Direction is opposite of data direction or IN if no 678 * data 679 */ 680 dev_vdbg(hsotg->dev, " Control status transaction\n"); 681 if (urb->length == 0) 682 chan->ep_is_in = 1; 683 else 684 chan->ep_is_in = 685 dwc2_hcd_is_pipe_out(&urb->pipe_info); 686 if (chan->ep_is_in) 687 chan->do_ping = 0; 688 chan->data_pid_start = DWC2_HC_PID_DATA1; 689 chan->xfer_len = 0; 690 if (hsotg->core_params->dma_enable > 0) 691 chan->xfer_dma = hsotg->status_buf_dma; 692 else 693 chan->xfer_buf = hsotg->status_buf; 694 break; 695 } 696 break; 697 698 case USB_ENDPOINT_XFER_BULK: 699 chan->ep_type = USB_ENDPOINT_XFER_BULK; 700 break; 701 702 case USB_ENDPOINT_XFER_INT: 703 chan->ep_type = USB_ENDPOINT_XFER_INT; 704 break; 705 706 case USB_ENDPOINT_XFER_ISOC: 707 chan->ep_type = USB_ENDPOINT_XFER_ISOC; 708 if (hsotg->core_params->dma_desc_enable > 0) 709 break; 710 711 frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; 712 frame_desc->status = 0; 713 714 if (hsotg->core_params->dma_enable > 0) { 715 chan->xfer_dma = urb->dma; 716 chan->xfer_dma += frame_desc->offset + 717 qtd->isoc_split_offset; 718 } else { 719 chan->xfer_buf = urb->buf; 720 chan->xfer_buf += frame_desc->offset + 721 qtd->isoc_split_offset; 722 } 723 724 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset; 725 726 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) { 727 if (chan->xfer_len <= 188) 728 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL; 729 else 730 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN; 731 } 732 break; 733 } 734 } 735 736 #define DWC2_USB_DMA_ALIGN 4 737 738 struct dma_aligned_buffer { 739 void *kmalloc_ptr; 740 void *old_xfer_buffer; 741 u8 data[0]; 742 }; 743 744 static void dwc2_free_dma_aligned_buffer(struct urb *urb) 745 { 746 struct dma_aligned_buffer *temp; 747 748 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER)) 749 return; 750 751 temp = container_of(urb->transfer_buffer, 752 struct dma_aligned_buffer, data); 753 754 if (usb_urb_dir_in(urb)) 755 memcpy(temp->old_xfer_buffer, temp->data, 756 urb->transfer_buffer_length); 757 urb->transfer_buffer = temp->old_xfer_buffer; 758 kfree(temp->kmalloc_ptr); 759 760 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER; 761 } 762 763 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags) 764 { 765 struct dma_aligned_buffer *temp, *kmalloc_ptr; 766 size_t kmalloc_size; 767 768 if (urb->num_sgs || urb->sg || 769 urb->transfer_buffer_length == 0 || 770 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1))) 771 return 0; 772 773 /* Allocate a buffer with enough padding for alignment */ 774 kmalloc_size = urb->transfer_buffer_length + 775 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1; 776 777 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags); 778 if (!kmalloc_ptr) 779 return -ENOMEM; 780 781 /* Position our struct dma_aligned_buffer such that data is aligned */ 782 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1; 783 temp->kmalloc_ptr = kmalloc_ptr; 784 temp->old_xfer_buffer = urb->transfer_buffer; 785 if (usb_urb_dir_out(urb)) 786 memcpy(temp->data, urb->transfer_buffer, 787 urb->transfer_buffer_length); 788 urb->transfer_buffer = temp->data; 789 790 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER; 791 792 return 0; 793 } 794 795 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb, 796 gfp_t mem_flags) 797 { 798 int ret; 799 800 /* We assume setup_dma is always aligned; warn if not */ 801 WARN_ON_ONCE(urb->setup_dma && 802 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1))); 803 804 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags); 805 if (ret) 806 return ret; 807 808 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags); 809 if (ret) 810 dwc2_free_dma_aligned_buffer(urb); 811 812 return ret; 813 } 814 815 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb) 816 { 817 usb_hcd_unmap_urb_for_dma(hcd, urb); 818 dwc2_free_dma_aligned_buffer(urb); 819 } 820 821 /** 822 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host 823 * channel and initializes the host channel to perform the transactions. The 824 * host channel is removed from the free list. 825 * 826 * @hsotg: The HCD state structure 827 * @qh: Transactions from the first QTD for this QH are selected and assigned 828 * to a free host channel 829 */ 830 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 831 { 832 struct dwc2_host_chan *chan; 833 struct dwc2_hcd_urb *urb; 834 struct dwc2_qtd *qtd; 835 836 if (dbg_qh(qh)) 837 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh); 838 839 if (list_empty(&qh->qtd_list)) { 840 dev_dbg(hsotg->dev, "No QTDs in QH list\n"); 841 return -ENOMEM; 842 } 843 844 if (list_empty(&hsotg->free_hc_list)) { 845 dev_dbg(hsotg->dev, "No free channel to assign\n"); 846 return -ENOMEM; 847 } 848 849 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan, 850 hc_list_entry); 851 852 /* Remove host channel from free list */ 853 list_del_init(&chan->hc_list_entry); 854 855 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry); 856 urb = qtd->urb; 857 qh->channel = chan; 858 qtd->in_process = 1; 859 860 /* 861 * Use usb_pipedevice to determine device address. This address is 862 * 0 before the SET_ADDRESS command and the correct address afterward. 863 */ 864 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info); 865 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info); 866 chan->speed = qh->dev_speed; 867 chan->max_packet = dwc2_max_packet(qh->maxp); 868 869 chan->xfer_started = 0; 870 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS; 871 chan->error_state = (qtd->error_count > 0); 872 chan->halt_on_queue = 0; 873 chan->halt_pending = 0; 874 chan->requests = 0; 875 876 /* 877 * The following values may be modified in the transfer type section 878 * below. The xfer_len value may be reduced when the transfer is 879 * started to accommodate the max widths of the XferSize and PktCnt 880 * fields in the HCTSIZn register. 881 */ 882 883 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0); 884 if (chan->ep_is_in) 885 chan->do_ping = 0; 886 else 887 chan->do_ping = qh->ping_state; 888 889 chan->data_pid_start = qh->data_toggle; 890 chan->multi_count = 1; 891 892 if (urb->actual_length > urb->length && 893 !dwc2_hcd_is_pipe_in(&urb->pipe_info)) 894 urb->actual_length = urb->length; 895 896 if (hsotg->core_params->dma_enable > 0) 897 chan->xfer_dma = urb->dma + urb->actual_length; 898 else 899 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length; 900 901 chan->xfer_len = urb->length - urb->actual_length; 902 chan->xfer_count = 0; 903 904 /* Set the split attributes if required */ 905 if (qh->do_split) 906 dwc2_hc_init_split(hsotg, chan, qtd, urb); 907 else 908 chan->do_split = 0; 909 910 /* Set the transfer attributes */ 911 dwc2_hc_init_xfer(hsotg, chan, qtd); 912 913 if (chan->ep_type == USB_ENDPOINT_XFER_INT || 914 chan->ep_type == USB_ENDPOINT_XFER_ISOC) 915 /* 916 * This value may be modified when the transfer is started 917 * to reflect the actual transfer length 918 */ 919 chan->multi_count = dwc2_hb_mult(qh->maxp); 920 921 if (hsotg->core_params->dma_desc_enable > 0) { 922 chan->desc_list_addr = qh->desc_list_dma; 923 chan->desc_list_sz = qh->desc_list_sz; 924 } 925 926 dwc2_hc_init(hsotg, chan); 927 chan->qh = qh; 928 929 return 0; 930 } 931 932 /** 933 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer 934 * schedule and assigns them to available host channels. Called from the HCD 935 * interrupt handler functions. 936 * 937 * @hsotg: The HCD state structure 938 * 939 * Return: The types of new transactions that were assigned to host channels 940 */ 941 enum dwc2_transaction_type dwc2_hcd_select_transactions( 942 struct dwc2_hsotg *hsotg) 943 { 944 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE; 945 struct list_head *qh_ptr; 946 struct dwc2_qh *qh; 947 int num_channels; 948 949 #ifdef DWC2_DEBUG_SOF 950 dev_vdbg(hsotg->dev, " Select Transactions\n"); 951 #endif 952 953 /* Process entries in the periodic ready list */ 954 qh_ptr = hsotg->periodic_sched_ready.next; 955 while (qh_ptr != &hsotg->periodic_sched_ready) { 956 if (list_empty(&hsotg->free_hc_list)) 957 break; 958 if (hsotg->core_params->uframe_sched > 0) { 959 if (hsotg->available_host_channels <= 1) 960 break; 961 hsotg->available_host_channels--; 962 } 963 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 964 if (dwc2_assign_and_init_hc(hsotg, qh)) 965 break; 966 967 /* 968 * Move the QH from the periodic ready schedule to the 969 * periodic assigned schedule 970 */ 971 qh_ptr = qh_ptr->next; 972 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned); 973 ret_val = DWC2_TRANSACTION_PERIODIC; 974 } 975 976 /* 977 * Process entries in the inactive portion of the non-periodic 978 * schedule. Some free host channels may not be used if they are 979 * reserved for periodic transfers. 980 */ 981 num_channels = hsotg->core_params->host_channels; 982 qh_ptr = hsotg->non_periodic_sched_inactive.next; 983 while (qh_ptr != &hsotg->non_periodic_sched_inactive) { 984 if (hsotg->core_params->uframe_sched <= 0 && 985 hsotg->non_periodic_channels >= num_channels - 986 hsotg->periodic_channels) 987 break; 988 if (list_empty(&hsotg->free_hc_list)) 989 break; 990 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 991 if (hsotg->core_params->uframe_sched > 0) { 992 if (hsotg->available_host_channels < 1) 993 break; 994 hsotg->available_host_channels--; 995 } 996 997 if (dwc2_assign_and_init_hc(hsotg, qh)) 998 break; 999 1000 /* 1001 * Move the QH from the non-periodic inactive schedule to the 1002 * non-periodic active schedule 1003 */ 1004 qh_ptr = qh_ptr->next; 1005 list_move(&qh->qh_list_entry, 1006 &hsotg->non_periodic_sched_active); 1007 1008 if (ret_val == DWC2_TRANSACTION_NONE) 1009 ret_val = DWC2_TRANSACTION_NON_PERIODIC; 1010 else 1011 ret_val = DWC2_TRANSACTION_ALL; 1012 1013 if (hsotg->core_params->uframe_sched <= 0) 1014 hsotg->non_periodic_channels++; 1015 } 1016 1017 return ret_val; 1018 } 1019 1020 /** 1021 * dwc2_queue_transaction() - Attempts to queue a single transaction request for 1022 * a host channel associated with either a periodic or non-periodic transfer 1023 * 1024 * @hsotg: The HCD state structure 1025 * @chan: Host channel descriptor associated with either a periodic or 1026 * non-periodic transfer 1027 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO 1028 * for periodic transfers or the non-periodic Tx FIFO 1029 * for non-periodic transfers 1030 * 1031 * Return: 1 if a request is queued and more requests may be needed to 1032 * complete the transfer, 0 if no more requests are required for this 1033 * transfer, -1 if there is insufficient space in the Tx FIFO 1034 * 1035 * This function assumes that there is space available in the appropriate 1036 * request queue. For an OUT transfer or SETUP transaction in Slave mode, 1037 * it checks whether space is available in the appropriate Tx FIFO. 1038 * 1039 * Must be called with interrupt disabled and spinlock held 1040 */ 1041 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg, 1042 struct dwc2_host_chan *chan, 1043 u16 fifo_dwords_avail) 1044 { 1045 int retval = 0; 1046 1047 if (hsotg->core_params->dma_enable > 0) { 1048 if (hsotg->core_params->dma_desc_enable > 0) { 1049 if (!chan->xfer_started || 1050 chan->ep_type == USB_ENDPOINT_XFER_ISOC) { 1051 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh); 1052 chan->qh->ping_state = 0; 1053 } 1054 } else if (!chan->xfer_started) { 1055 dwc2_hc_start_transfer(hsotg, chan); 1056 chan->qh->ping_state = 0; 1057 } 1058 } else if (chan->halt_pending) { 1059 /* Don't queue a request if the channel has been halted */ 1060 } else if (chan->halt_on_queue) { 1061 dwc2_hc_halt(hsotg, chan, chan->halt_status); 1062 } else if (chan->do_ping) { 1063 if (!chan->xfer_started) 1064 dwc2_hc_start_transfer(hsotg, chan); 1065 } else if (!chan->ep_is_in || 1066 chan->data_pid_start == DWC2_HC_PID_SETUP) { 1067 if ((fifo_dwords_avail * 4) >= chan->max_packet) { 1068 if (!chan->xfer_started) { 1069 dwc2_hc_start_transfer(hsotg, chan); 1070 retval = 1; 1071 } else { 1072 retval = dwc2_hc_continue_transfer(hsotg, chan); 1073 } 1074 } else { 1075 retval = -1; 1076 } 1077 } else { 1078 if (!chan->xfer_started) { 1079 dwc2_hc_start_transfer(hsotg, chan); 1080 retval = 1; 1081 } else { 1082 retval = dwc2_hc_continue_transfer(hsotg, chan); 1083 } 1084 } 1085 1086 return retval; 1087 } 1088 1089 /* 1090 * Processes periodic channels for the next frame and queues transactions for 1091 * these channels to the DWC_otg controller. After queueing transactions, the 1092 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions 1093 * to queue as Periodic Tx FIFO or request queue space becomes available. 1094 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. 1095 * 1096 * Must be called with interrupt disabled and spinlock held 1097 */ 1098 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) 1099 { 1100 struct list_head *qh_ptr; 1101 struct dwc2_qh *qh; 1102 u32 tx_status; 1103 u32 fspcavail; 1104 u32 gintmsk; 1105 int status; 1106 int no_queue_space = 0; 1107 int no_fifo_space = 0; 1108 u32 qspcavail; 1109 1110 if (dbg_perio()) 1111 dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); 1112 1113 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1114 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1115 TXSTS_QSPCAVAIL_SHIFT; 1116 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1117 TXSTS_FSPCAVAIL_SHIFT; 1118 1119 if (dbg_perio()) { 1120 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n", 1121 qspcavail); 1122 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n", 1123 fspcavail); 1124 } 1125 1126 qh_ptr = hsotg->periodic_sched_assigned.next; 1127 while (qh_ptr != &hsotg->periodic_sched_assigned) { 1128 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1129 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1130 TXSTS_QSPCAVAIL_SHIFT; 1131 if (qspcavail == 0) { 1132 no_queue_space = 1; 1133 break; 1134 } 1135 1136 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry); 1137 if (!qh->channel) { 1138 qh_ptr = qh_ptr->next; 1139 continue; 1140 } 1141 1142 /* Make sure EP's TT buffer is clean before queueing qtds */ 1143 if (qh->tt_buffer_dirty) { 1144 qh_ptr = qh_ptr->next; 1145 continue; 1146 } 1147 1148 /* 1149 * Set a flag if we're queuing high-bandwidth in slave mode. 1150 * The flag prevents any halts to get into the request queue in 1151 * the middle of multiple high-bandwidth packets getting queued. 1152 */ 1153 if (hsotg->core_params->dma_enable <= 0 && 1154 qh->channel->multi_count > 1) 1155 hsotg->queuing_high_bandwidth = 1; 1156 1157 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1158 TXSTS_FSPCAVAIL_SHIFT; 1159 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1160 if (status < 0) { 1161 no_fifo_space = 1; 1162 break; 1163 } 1164 1165 /* 1166 * In Slave mode, stay on the current transfer until there is 1167 * nothing more to do or the high-bandwidth request count is 1168 * reached. In DMA mode, only need to queue one request. The 1169 * controller automatically handles multiple packets for 1170 * high-bandwidth transfers. 1171 */ 1172 if (hsotg->core_params->dma_enable > 0 || status == 0 || 1173 qh->channel->requests == qh->channel->multi_count) { 1174 qh_ptr = qh_ptr->next; 1175 /* 1176 * Move the QH from the periodic assigned schedule to 1177 * the periodic queued schedule 1178 */ 1179 list_move(&qh->qh_list_entry, 1180 &hsotg->periodic_sched_queued); 1181 1182 /* done queuing high bandwidth */ 1183 hsotg->queuing_high_bandwidth = 0; 1184 } 1185 } 1186 1187 if (hsotg->core_params->dma_enable <= 0) { 1188 tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 1189 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1190 TXSTS_QSPCAVAIL_SHIFT; 1191 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1192 TXSTS_FSPCAVAIL_SHIFT; 1193 if (dbg_perio()) { 1194 dev_vdbg(hsotg->dev, 1195 " P Tx Req Queue Space Avail (after queue): %d\n", 1196 qspcavail); 1197 dev_vdbg(hsotg->dev, 1198 " P Tx FIFO Space Avail (after queue): %d\n", 1199 fspcavail); 1200 } 1201 1202 if (!list_empty(&hsotg->periodic_sched_assigned) || 1203 no_queue_space || no_fifo_space) { 1204 /* 1205 * May need to queue more transactions as the request 1206 * queue or Tx FIFO empties. Enable the periodic Tx 1207 * FIFO empty interrupt. (Always use the half-empty 1208 * level to ensure that new requests are loaded as 1209 * soon as possible.) 1210 */ 1211 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1212 gintmsk |= GINTSTS_PTXFEMP; 1213 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1214 } else { 1215 /* 1216 * Disable the Tx FIFO empty interrupt since there are 1217 * no more transactions that need to be queued right 1218 * now. This function is called from interrupt 1219 * handlers to queue more transactions as transfer 1220 * states change. 1221 */ 1222 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1223 gintmsk &= ~GINTSTS_PTXFEMP; 1224 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1225 } 1226 } 1227 } 1228 1229 /* 1230 * Processes active non-periodic channels and queues transactions for these 1231 * channels to the DWC_otg controller. After queueing transactions, the NP Tx 1232 * FIFO Empty interrupt is enabled if there are more transactions to queue as 1233 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx 1234 * FIFO Empty interrupt is disabled. 1235 * 1236 * Must be called with interrupt disabled and spinlock held 1237 */ 1238 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) 1239 { 1240 struct list_head *orig_qh_ptr; 1241 struct dwc2_qh *qh; 1242 u32 tx_status; 1243 u32 qspcavail; 1244 u32 fspcavail; 1245 u32 gintmsk; 1246 int status; 1247 int no_queue_space = 0; 1248 int no_fifo_space = 0; 1249 int more_to_do = 0; 1250 1251 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); 1252 1253 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1254 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1255 TXSTS_QSPCAVAIL_SHIFT; 1256 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1257 TXSTS_FSPCAVAIL_SHIFT; 1258 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n", 1259 qspcavail); 1260 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n", 1261 fspcavail); 1262 1263 /* 1264 * Keep track of the starting point. Skip over the start-of-list 1265 * entry. 1266 */ 1267 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active) 1268 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1269 orig_qh_ptr = hsotg->non_periodic_qh_ptr; 1270 1271 /* 1272 * Process once through the active list or until no more space is 1273 * available in the request queue or the Tx FIFO 1274 */ 1275 do { 1276 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1277 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1278 TXSTS_QSPCAVAIL_SHIFT; 1279 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { 1280 no_queue_space = 1; 1281 break; 1282 } 1283 1284 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh, 1285 qh_list_entry); 1286 if (!qh->channel) 1287 goto next; 1288 1289 /* Make sure EP's TT buffer is clean before queueing qtds */ 1290 if (qh->tt_buffer_dirty) 1291 goto next; 1292 1293 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1294 TXSTS_FSPCAVAIL_SHIFT; 1295 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail); 1296 1297 if (status > 0) { 1298 more_to_do = 1; 1299 } else if (status < 0) { 1300 no_fifo_space = 1; 1301 break; 1302 } 1303 next: 1304 /* Advance to next QH, skipping start-of-list entry */ 1305 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next; 1306 if (hsotg->non_periodic_qh_ptr == 1307 &hsotg->non_periodic_sched_active) 1308 hsotg->non_periodic_qh_ptr = 1309 hsotg->non_periodic_qh_ptr->next; 1310 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); 1311 1312 if (hsotg->core_params->dma_enable <= 0) { 1313 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 1314 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> 1315 TXSTS_QSPCAVAIL_SHIFT; 1316 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> 1317 TXSTS_FSPCAVAIL_SHIFT; 1318 dev_vdbg(hsotg->dev, 1319 " NP Tx Req Queue Space Avail (after queue): %d\n", 1320 qspcavail); 1321 dev_vdbg(hsotg->dev, 1322 " NP Tx FIFO Space Avail (after queue): %d\n", 1323 fspcavail); 1324 1325 if (more_to_do || no_queue_space || no_fifo_space) { 1326 /* 1327 * May need to queue more transactions as the request 1328 * queue or Tx FIFO empties. Enable the non-periodic 1329 * Tx FIFO empty interrupt. (Always use the half-empty 1330 * level to ensure that new requests are loaded as 1331 * soon as possible.) 1332 */ 1333 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1334 gintmsk |= GINTSTS_NPTXFEMP; 1335 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1336 } else { 1337 /* 1338 * Disable the Tx FIFO empty interrupt since there are 1339 * no more transactions that need to be queued right 1340 * now. This function is called from interrupt 1341 * handlers to queue more transactions as transfer 1342 * states change. 1343 */ 1344 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1345 gintmsk &= ~GINTSTS_NPTXFEMP; 1346 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1347 } 1348 } 1349 } 1350 1351 /** 1352 * dwc2_hcd_queue_transactions() - Processes the currently active host channels 1353 * and queues transactions for these channels to the DWC_otg controller. Called 1354 * from the HCD interrupt handler functions. 1355 * 1356 * @hsotg: The HCD state structure 1357 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic, 1358 * or both) 1359 * 1360 * Must be called with interrupt disabled and spinlock held 1361 */ 1362 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, 1363 enum dwc2_transaction_type tr_type) 1364 { 1365 #ifdef DWC2_DEBUG_SOF 1366 dev_vdbg(hsotg->dev, "Queue Transactions\n"); 1367 #endif 1368 /* Process host channels associated with periodic transfers */ 1369 if ((tr_type == DWC2_TRANSACTION_PERIODIC || 1370 tr_type == DWC2_TRANSACTION_ALL) && 1371 !list_empty(&hsotg->periodic_sched_assigned)) 1372 dwc2_process_periodic_channels(hsotg); 1373 1374 /* Process host channels associated with non-periodic transfers */ 1375 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC || 1376 tr_type == DWC2_TRANSACTION_ALL) { 1377 if (!list_empty(&hsotg->non_periodic_sched_active)) { 1378 dwc2_process_non_periodic_channels(hsotg); 1379 } else { 1380 /* 1381 * Ensure NP Tx FIFO empty interrupt is disabled when 1382 * there are no non-periodic transfers to process 1383 */ 1384 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); 1385 1386 gintmsk &= ~GINTSTS_NPTXFEMP; 1387 dwc2_writel(gintmsk, hsotg->regs + GINTMSK); 1388 } 1389 } 1390 } 1391 1392 static void dwc2_conn_id_status_change(struct work_struct *work) 1393 { 1394 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 1395 wf_otg); 1396 u32 count = 0; 1397 u32 gotgctl; 1398 unsigned long flags; 1399 1400 dev_dbg(hsotg->dev, "%s()\n", __func__); 1401 1402 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1403 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); 1404 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", 1405 !!(gotgctl & GOTGCTL_CONID_B)); 1406 1407 /* B-Device connector (Device Mode) */ 1408 if (gotgctl & GOTGCTL_CONID_B) { 1409 /* Wait for switch to device mode */ 1410 dev_dbg(hsotg->dev, "connId B\n"); 1411 while (!dwc2_is_device_mode(hsotg)) { 1412 dev_info(hsotg->dev, 1413 "Waiting for Peripheral Mode, Mode=%s\n", 1414 dwc2_is_host_mode(hsotg) ? "Host" : 1415 "Peripheral"); 1416 usleep_range(20000, 40000); 1417 if (++count > 250) 1418 break; 1419 } 1420 if (count > 250) 1421 dev_err(hsotg->dev, 1422 "Connection id status change timed out\n"); 1423 hsotg->op_state = OTG_STATE_B_PERIPHERAL; 1424 dwc2_core_init(hsotg, false); 1425 dwc2_enable_global_interrupts(hsotg); 1426 spin_lock_irqsave(&hsotg->lock, flags); 1427 dwc2_hsotg_core_init_disconnected(hsotg, false); 1428 spin_unlock_irqrestore(&hsotg->lock, flags); 1429 dwc2_hsotg_core_connect(hsotg); 1430 } else { 1431 /* A-Device connector (Host Mode) */ 1432 dev_dbg(hsotg->dev, "connId A\n"); 1433 while (!dwc2_is_host_mode(hsotg)) { 1434 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n", 1435 dwc2_is_host_mode(hsotg) ? 1436 "Host" : "Peripheral"); 1437 usleep_range(20000, 40000); 1438 if (++count > 250) 1439 break; 1440 } 1441 if (count > 250) 1442 dev_err(hsotg->dev, 1443 "Connection id status change timed out\n"); 1444 hsotg->op_state = OTG_STATE_A_HOST; 1445 1446 /* Initialize the Core for Host mode */ 1447 dwc2_core_init(hsotg, false); 1448 dwc2_enable_global_interrupts(hsotg); 1449 dwc2_hcd_start(hsotg); 1450 } 1451 } 1452 1453 static void dwc2_wakeup_detected(unsigned long data) 1454 { 1455 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data; 1456 u32 hprt0; 1457 1458 dev_dbg(hsotg->dev, "%s()\n", __func__); 1459 1460 /* 1461 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms 1462 * so that OPT tests pass with all PHYs.) 1463 */ 1464 hprt0 = dwc2_read_hprt0(hsotg); 1465 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); 1466 hprt0 &= ~HPRT0_RES; 1467 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1468 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", 1469 dwc2_readl(hsotg->regs + HPRT0)); 1470 1471 dwc2_hcd_rem_wakeup(hsotg); 1472 hsotg->bus_suspended = 0; 1473 1474 /* Change to L0 state */ 1475 hsotg->lx_state = DWC2_L0; 1476 } 1477 1478 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg) 1479 { 1480 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 1481 1482 return hcd->self.b_hnp_enable; 1483 } 1484 1485 /* Must NOT be called with interrupt disabled or spinlock held */ 1486 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) 1487 { 1488 unsigned long flags; 1489 u32 hprt0; 1490 u32 pcgctl; 1491 u32 gotgctl; 1492 1493 dev_dbg(hsotg->dev, "%s()\n", __func__); 1494 1495 spin_lock_irqsave(&hsotg->lock, flags); 1496 1497 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { 1498 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); 1499 gotgctl |= GOTGCTL_HSTSETHNPEN; 1500 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); 1501 hsotg->op_state = OTG_STATE_A_SUSPEND; 1502 } 1503 1504 hprt0 = dwc2_read_hprt0(hsotg); 1505 hprt0 |= HPRT0_SUSP; 1506 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1507 1508 hsotg->bus_suspended = 1; 1509 1510 /* 1511 * If hibernation is supported, Phy clock will be suspended 1512 * after registers are backuped. 1513 */ 1514 if (!hsotg->core_params->hibernation) { 1515 /* Suspend the Phy Clock */ 1516 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1517 pcgctl |= PCGCTL_STOPPCLK; 1518 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1519 udelay(10); 1520 } 1521 1522 /* For HNP the bus must be suspended for at least 200ms */ 1523 if (dwc2_host_is_b_hnp_enabled(hsotg)) { 1524 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1525 pcgctl &= ~PCGCTL_STOPPCLK; 1526 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1527 1528 spin_unlock_irqrestore(&hsotg->lock, flags); 1529 1530 usleep_range(200000, 250000); 1531 } else { 1532 spin_unlock_irqrestore(&hsotg->lock, flags); 1533 } 1534 } 1535 1536 /* Must NOT be called with interrupt disabled or spinlock held */ 1537 static void dwc2_port_resume(struct dwc2_hsotg *hsotg) 1538 { 1539 unsigned long flags; 1540 u32 hprt0; 1541 u32 pcgctl; 1542 1543 spin_lock_irqsave(&hsotg->lock, flags); 1544 1545 /* 1546 * If hibernation is supported, Phy clock is already resumed 1547 * after registers restore. 1548 */ 1549 if (!hsotg->core_params->hibernation) { 1550 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1551 pcgctl &= ~PCGCTL_STOPPCLK; 1552 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1553 spin_unlock_irqrestore(&hsotg->lock, flags); 1554 usleep_range(20000, 40000); 1555 spin_lock_irqsave(&hsotg->lock, flags); 1556 } 1557 1558 hprt0 = dwc2_read_hprt0(hsotg); 1559 hprt0 |= HPRT0_RES; 1560 hprt0 &= ~HPRT0_SUSP; 1561 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1562 spin_unlock_irqrestore(&hsotg->lock, flags); 1563 1564 msleep(USB_RESUME_TIMEOUT); 1565 1566 spin_lock_irqsave(&hsotg->lock, flags); 1567 hprt0 = dwc2_read_hprt0(hsotg); 1568 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); 1569 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1570 hsotg->bus_suspended = 0; 1571 spin_unlock_irqrestore(&hsotg->lock, flags); 1572 } 1573 1574 /* Handles hub class-specific requests */ 1575 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, 1576 u16 wvalue, u16 windex, char *buf, u16 wlength) 1577 { 1578 struct usb_hub_descriptor *hub_desc; 1579 int retval = 0; 1580 u32 hprt0; 1581 u32 port_status; 1582 u32 speed; 1583 u32 pcgctl; 1584 1585 switch (typereq) { 1586 case ClearHubFeature: 1587 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue); 1588 1589 switch (wvalue) { 1590 case C_HUB_LOCAL_POWER: 1591 case C_HUB_OVER_CURRENT: 1592 /* Nothing required here */ 1593 break; 1594 1595 default: 1596 retval = -EINVAL; 1597 dev_err(hsotg->dev, 1598 "ClearHubFeature request %1xh unknown\n", 1599 wvalue); 1600 } 1601 break; 1602 1603 case ClearPortFeature: 1604 if (wvalue != USB_PORT_FEAT_L1) 1605 if (!windex || windex > 1) 1606 goto error; 1607 switch (wvalue) { 1608 case USB_PORT_FEAT_ENABLE: 1609 dev_dbg(hsotg->dev, 1610 "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); 1611 hprt0 = dwc2_read_hprt0(hsotg); 1612 hprt0 |= HPRT0_ENA; 1613 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1614 break; 1615 1616 case USB_PORT_FEAT_SUSPEND: 1617 dev_dbg(hsotg->dev, 1618 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); 1619 1620 if (hsotg->bus_suspended) 1621 dwc2_port_resume(hsotg); 1622 break; 1623 1624 case USB_PORT_FEAT_POWER: 1625 dev_dbg(hsotg->dev, 1626 "ClearPortFeature USB_PORT_FEAT_POWER\n"); 1627 hprt0 = dwc2_read_hprt0(hsotg); 1628 hprt0 &= ~HPRT0_PWR; 1629 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1630 break; 1631 1632 case USB_PORT_FEAT_INDICATOR: 1633 dev_dbg(hsotg->dev, 1634 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); 1635 /* Port indicator not supported */ 1636 break; 1637 1638 case USB_PORT_FEAT_C_CONNECTION: 1639 /* 1640 * Clears driver's internal Connect Status Change flag 1641 */ 1642 dev_dbg(hsotg->dev, 1643 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); 1644 hsotg->flags.b.port_connect_status_change = 0; 1645 break; 1646 1647 case USB_PORT_FEAT_C_RESET: 1648 /* Clears driver's internal Port Reset Change flag */ 1649 dev_dbg(hsotg->dev, 1650 "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); 1651 hsotg->flags.b.port_reset_change = 0; 1652 break; 1653 1654 case USB_PORT_FEAT_C_ENABLE: 1655 /* 1656 * Clears the driver's internal Port Enable/Disable 1657 * Change flag 1658 */ 1659 dev_dbg(hsotg->dev, 1660 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); 1661 hsotg->flags.b.port_enable_change = 0; 1662 break; 1663 1664 case USB_PORT_FEAT_C_SUSPEND: 1665 /* 1666 * Clears the driver's internal Port Suspend Change 1667 * flag, which is set when resume signaling on the host 1668 * port is complete 1669 */ 1670 dev_dbg(hsotg->dev, 1671 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); 1672 hsotg->flags.b.port_suspend_change = 0; 1673 break; 1674 1675 case USB_PORT_FEAT_C_PORT_L1: 1676 dev_dbg(hsotg->dev, 1677 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n"); 1678 hsotg->flags.b.port_l1_change = 0; 1679 break; 1680 1681 case USB_PORT_FEAT_C_OVER_CURRENT: 1682 dev_dbg(hsotg->dev, 1683 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); 1684 hsotg->flags.b.port_over_current_change = 0; 1685 break; 1686 1687 default: 1688 retval = -EINVAL; 1689 dev_err(hsotg->dev, 1690 "ClearPortFeature request %1xh unknown or unsupported\n", 1691 wvalue); 1692 } 1693 break; 1694 1695 case GetHubDescriptor: 1696 dev_dbg(hsotg->dev, "GetHubDescriptor\n"); 1697 hub_desc = (struct usb_hub_descriptor *)buf; 1698 hub_desc->bDescLength = 9; 1699 hub_desc->bDescriptorType = USB_DT_HUB; 1700 hub_desc->bNbrPorts = 1; 1701 hub_desc->wHubCharacteristics = 1702 cpu_to_le16(HUB_CHAR_COMMON_LPSM | 1703 HUB_CHAR_INDV_PORT_OCPM); 1704 hub_desc->bPwrOn2PwrGood = 1; 1705 hub_desc->bHubContrCurrent = 0; 1706 hub_desc->u.hs.DeviceRemovable[0] = 0; 1707 hub_desc->u.hs.DeviceRemovable[1] = 0xff; 1708 break; 1709 1710 case GetHubStatus: 1711 dev_dbg(hsotg->dev, "GetHubStatus\n"); 1712 memset(buf, 0, 4); 1713 break; 1714 1715 case GetPortStatus: 1716 dev_vdbg(hsotg->dev, 1717 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex, 1718 hsotg->flags.d32); 1719 if (!windex || windex > 1) 1720 goto error; 1721 1722 port_status = 0; 1723 if (hsotg->flags.b.port_connect_status_change) 1724 port_status |= USB_PORT_STAT_C_CONNECTION << 16; 1725 if (hsotg->flags.b.port_enable_change) 1726 port_status |= USB_PORT_STAT_C_ENABLE << 16; 1727 if (hsotg->flags.b.port_suspend_change) 1728 port_status |= USB_PORT_STAT_C_SUSPEND << 16; 1729 if (hsotg->flags.b.port_l1_change) 1730 port_status |= USB_PORT_STAT_C_L1 << 16; 1731 if (hsotg->flags.b.port_reset_change) 1732 port_status |= USB_PORT_STAT_C_RESET << 16; 1733 if (hsotg->flags.b.port_over_current_change) { 1734 dev_warn(hsotg->dev, "Overcurrent change detected\n"); 1735 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16; 1736 } 1737 1738 if (!hsotg->flags.b.port_connect_status) { 1739 /* 1740 * The port is disconnected, which means the core is 1741 * either in device mode or it soon will be. Just 1742 * return 0's for the remainder of the port status 1743 * since the port register can't be read if the core 1744 * is in device mode. 1745 */ 1746 *(__le32 *)buf = cpu_to_le32(port_status); 1747 break; 1748 } 1749 1750 hprt0 = dwc2_readl(hsotg->regs + HPRT0); 1751 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); 1752 1753 if (hprt0 & HPRT0_CONNSTS) 1754 port_status |= USB_PORT_STAT_CONNECTION; 1755 if (hprt0 & HPRT0_ENA) 1756 port_status |= USB_PORT_STAT_ENABLE; 1757 if (hprt0 & HPRT0_SUSP) 1758 port_status |= USB_PORT_STAT_SUSPEND; 1759 if (hprt0 & HPRT0_OVRCURRACT) 1760 port_status |= USB_PORT_STAT_OVERCURRENT; 1761 if (hprt0 & HPRT0_RST) 1762 port_status |= USB_PORT_STAT_RESET; 1763 if (hprt0 & HPRT0_PWR) 1764 port_status |= USB_PORT_STAT_POWER; 1765 1766 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 1767 if (speed == HPRT0_SPD_HIGH_SPEED) 1768 port_status |= USB_PORT_STAT_HIGH_SPEED; 1769 else if (speed == HPRT0_SPD_LOW_SPEED) 1770 port_status |= USB_PORT_STAT_LOW_SPEED; 1771 1772 if (hprt0 & HPRT0_TSTCTL_MASK) 1773 port_status |= USB_PORT_STAT_TEST; 1774 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ 1775 1776 if (hsotg->core_params->dma_desc_fs_enable) { 1777 /* 1778 * Enable descriptor DMA only if a full speed 1779 * device is connected. 1780 */ 1781 if (hsotg->new_connection && 1782 ((port_status & 1783 (USB_PORT_STAT_CONNECTION | 1784 USB_PORT_STAT_HIGH_SPEED | 1785 USB_PORT_STAT_LOW_SPEED)) == 1786 USB_PORT_STAT_CONNECTION)) { 1787 u32 hcfg; 1788 1789 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); 1790 hsotg->core_params->dma_desc_enable = 1; 1791 hcfg = dwc2_readl(hsotg->regs + HCFG); 1792 hcfg |= HCFG_DESCDMA; 1793 dwc2_writel(hcfg, hsotg->regs + HCFG); 1794 hsotg->new_connection = false; 1795 } 1796 } 1797 1798 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status); 1799 *(__le32 *)buf = cpu_to_le32(port_status); 1800 break; 1801 1802 case SetHubFeature: 1803 dev_dbg(hsotg->dev, "SetHubFeature\n"); 1804 /* No HUB features supported */ 1805 break; 1806 1807 case SetPortFeature: 1808 dev_dbg(hsotg->dev, "SetPortFeature\n"); 1809 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1)) 1810 goto error; 1811 1812 if (!hsotg->flags.b.port_connect_status) { 1813 /* 1814 * The port is disconnected, which means the core is 1815 * either in device mode or it soon will be. Just 1816 * return without doing anything since the port 1817 * register can't be written if the core is in device 1818 * mode. 1819 */ 1820 break; 1821 } 1822 1823 switch (wvalue) { 1824 case USB_PORT_FEAT_SUSPEND: 1825 dev_dbg(hsotg->dev, 1826 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); 1827 if (windex != hsotg->otg_port) 1828 goto error; 1829 dwc2_port_suspend(hsotg, windex); 1830 break; 1831 1832 case USB_PORT_FEAT_POWER: 1833 dev_dbg(hsotg->dev, 1834 "SetPortFeature - USB_PORT_FEAT_POWER\n"); 1835 hprt0 = dwc2_read_hprt0(hsotg); 1836 hprt0 |= HPRT0_PWR; 1837 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1838 break; 1839 1840 case USB_PORT_FEAT_RESET: 1841 hprt0 = dwc2_read_hprt0(hsotg); 1842 dev_dbg(hsotg->dev, 1843 "SetPortFeature - USB_PORT_FEAT_RESET\n"); 1844 pcgctl = dwc2_readl(hsotg->regs + PCGCTL); 1845 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); 1846 dwc2_writel(pcgctl, hsotg->regs + PCGCTL); 1847 /* ??? Original driver does this */ 1848 dwc2_writel(0, hsotg->regs + PCGCTL); 1849 1850 hprt0 = dwc2_read_hprt0(hsotg); 1851 /* Clear suspend bit if resetting from suspend state */ 1852 hprt0 &= ~HPRT0_SUSP; 1853 1854 /* 1855 * When B-Host the Port reset bit is set in the Start 1856 * HCD Callback function, so that the reset is started 1857 * within 1ms of the HNP success interrupt 1858 */ 1859 if (!dwc2_hcd_is_b_host(hsotg)) { 1860 hprt0 |= HPRT0_PWR | HPRT0_RST; 1861 dev_dbg(hsotg->dev, 1862 "In host mode, hprt0=%08x\n", hprt0); 1863 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1864 } 1865 1866 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ 1867 usleep_range(50000, 70000); 1868 hprt0 &= ~HPRT0_RST; 1869 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1870 hsotg->lx_state = DWC2_L0; /* Now back to On state */ 1871 break; 1872 1873 case USB_PORT_FEAT_INDICATOR: 1874 dev_dbg(hsotg->dev, 1875 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); 1876 /* Not supported */ 1877 break; 1878 1879 case USB_PORT_FEAT_TEST: 1880 hprt0 = dwc2_read_hprt0(hsotg); 1881 dev_dbg(hsotg->dev, 1882 "SetPortFeature - USB_PORT_FEAT_TEST\n"); 1883 hprt0 &= ~HPRT0_TSTCTL_MASK; 1884 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; 1885 dwc2_writel(hprt0, hsotg->regs + HPRT0); 1886 break; 1887 1888 default: 1889 retval = -EINVAL; 1890 dev_err(hsotg->dev, 1891 "SetPortFeature %1xh unknown or unsupported\n", 1892 wvalue); 1893 break; 1894 } 1895 break; 1896 1897 default: 1898 error: 1899 retval = -EINVAL; 1900 dev_dbg(hsotg->dev, 1901 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n", 1902 typereq, windex, wvalue); 1903 break; 1904 } 1905 1906 return retval; 1907 } 1908 1909 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) 1910 { 1911 int retval; 1912 1913 if (port != 1) 1914 return -EINVAL; 1915 1916 retval = (hsotg->flags.b.port_connect_status_change || 1917 hsotg->flags.b.port_reset_change || 1918 hsotg->flags.b.port_enable_change || 1919 hsotg->flags.b.port_suspend_change || 1920 hsotg->flags.b.port_over_current_change); 1921 1922 if (retval) { 1923 dev_dbg(hsotg->dev, 1924 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n"); 1925 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n", 1926 hsotg->flags.b.port_connect_status_change); 1927 dev_dbg(hsotg->dev, " port_reset_change: %d\n", 1928 hsotg->flags.b.port_reset_change); 1929 dev_dbg(hsotg->dev, " port_enable_change: %d\n", 1930 hsotg->flags.b.port_enable_change); 1931 dev_dbg(hsotg->dev, " port_suspend_change: %d\n", 1932 hsotg->flags.b.port_suspend_change); 1933 dev_dbg(hsotg->dev, " port_over_current_change: %d\n", 1934 hsotg->flags.b.port_over_current_change); 1935 } 1936 1937 return retval; 1938 } 1939 1940 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) 1941 { 1942 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); 1943 1944 #ifdef DWC2_DEBUG_SOF 1945 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", 1946 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT); 1947 #endif 1948 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; 1949 } 1950 1951 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg) 1952 { 1953 return hsotg->op_state == OTG_STATE_B_HOST; 1954 } 1955 1956 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg, 1957 int iso_desc_count, 1958 gfp_t mem_flags) 1959 { 1960 struct dwc2_hcd_urb *urb; 1961 u32 size = sizeof(*urb) + iso_desc_count * 1962 sizeof(struct dwc2_hcd_iso_packet_desc); 1963 1964 urb = kzalloc(size, mem_flags); 1965 if (urb) 1966 urb->packet_count = iso_desc_count; 1967 return urb; 1968 } 1969 1970 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg, 1971 struct dwc2_hcd_urb *urb, u8 dev_addr, 1972 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps) 1973 { 1974 if (dbg_perio() || 1975 ep_type == USB_ENDPOINT_XFER_BULK || 1976 ep_type == USB_ENDPOINT_XFER_CONTROL) 1977 dev_vdbg(hsotg->dev, 1978 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n", 1979 dev_addr, ep_num, ep_dir, ep_type, mps); 1980 urb->pipe_info.dev_addr = dev_addr; 1981 urb->pipe_info.ep_num = ep_num; 1982 urb->pipe_info.pipe_type = ep_type; 1983 urb->pipe_info.pipe_dir = ep_dir; 1984 urb->pipe_info.mps = mps; 1985 } 1986 1987 /* 1988 * NOTE: This function will be removed once the peripheral controller code 1989 * is integrated and the driver is stable 1990 */ 1991 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) 1992 { 1993 #ifdef DEBUG 1994 struct dwc2_host_chan *chan; 1995 struct dwc2_hcd_urb *urb; 1996 struct dwc2_qtd *qtd; 1997 int num_channels; 1998 u32 np_tx_status; 1999 u32 p_tx_status; 2000 int i; 2001 2002 num_channels = hsotg->core_params->host_channels; 2003 dev_dbg(hsotg->dev, "\n"); 2004 dev_dbg(hsotg->dev, 2005 "************************************************************\n"); 2006 dev_dbg(hsotg->dev, "HCD State:\n"); 2007 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels); 2008 2009 for (i = 0; i < num_channels; i++) { 2010 chan = hsotg->hc_ptr_array[i]; 2011 dev_dbg(hsotg->dev, " Channel %d:\n", i); 2012 dev_dbg(hsotg->dev, 2013 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n", 2014 chan->dev_addr, chan->ep_num, chan->ep_is_in); 2015 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed); 2016 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type); 2017 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet); 2018 dev_dbg(hsotg->dev, " data_pid_start: %d\n", 2019 chan->data_pid_start); 2020 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count); 2021 dev_dbg(hsotg->dev, " xfer_started: %d\n", 2022 chan->xfer_started); 2023 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf); 2024 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n", 2025 (unsigned long)chan->xfer_dma); 2026 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len); 2027 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count); 2028 dev_dbg(hsotg->dev, " halt_on_queue: %d\n", 2029 chan->halt_on_queue); 2030 dev_dbg(hsotg->dev, " halt_pending: %d\n", 2031 chan->halt_pending); 2032 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status); 2033 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split); 2034 dev_dbg(hsotg->dev, " complete_split: %d\n", 2035 chan->complete_split); 2036 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr); 2037 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port); 2038 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos); 2039 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests); 2040 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh); 2041 2042 if (chan->xfer_started) { 2043 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; 2044 2045 hfnum = dwc2_readl(hsotg->regs + HFNUM); 2046 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); 2047 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); 2048 hcint = dwc2_readl(hsotg->regs + HCINT(i)); 2049 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); 2050 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); 2051 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); 2052 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); 2053 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint); 2054 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk); 2055 } 2056 2057 if (!(chan->xfer_started && chan->qh)) 2058 continue; 2059 2060 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) { 2061 if (!qtd->in_process) 2062 break; 2063 urb = qtd->urb; 2064 dev_dbg(hsotg->dev, " URB Info:\n"); 2065 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n", 2066 qtd, urb); 2067 if (urb) { 2068 dev_dbg(hsotg->dev, 2069 " Dev: %d, EP: %d %s\n", 2070 dwc2_hcd_get_dev_addr(&urb->pipe_info), 2071 dwc2_hcd_get_ep_num(&urb->pipe_info), 2072 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 2073 "IN" : "OUT"); 2074 dev_dbg(hsotg->dev, 2075 " Max packet size: %d\n", 2076 dwc2_hcd_get_mps(&urb->pipe_info)); 2077 dev_dbg(hsotg->dev, 2078 " transfer_buffer: %p\n", 2079 urb->buf); 2080 dev_dbg(hsotg->dev, 2081 " transfer_dma: %08lx\n", 2082 (unsigned long)urb->dma); 2083 dev_dbg(hsotg->dev, 2084 " transfer_buffer_length: %d\n", 2085 urb->length); 2086 dev_dbg(hsotg->dev, " actual_length: %d\n", 2087 urb->actual_length); 2088 } 2089 } 2090 } 2091 2092 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n", 2093 hsotg->non_periodic_channels); 2094 dev_dbg(hsotg->dev, " periodic_channels: %d\n", 2095 hsotg->periodic_channels); 2096 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); 2097 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); 2098 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", 2099 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2100 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", 2101 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2102 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); 2103 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", 2104 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); 2105 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", 2106 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); 2107 dwc2_hcd_dump_frrem(hsotg); 2108 dwc2_dump_global_registers(hsotg); 2109 dwc2_dump_host_registers(hsotg); 2110 dev_dbg(hsotg->dev, 2111 "************************************************************\n"); 2112 dev_dbg(hsotg->dev, "\n"); 2113 #endif 2114 } 2115 2116 /* 2117 * NOTE: This function will be removed once the peripheral controller code 2118 * is integrated and the driver is stable 2119 */ 2120 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg) 2121 { 2122 #ifdef DWC2_DUMP_FRREM 2123 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n"); 2124 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2125 hsotg->frrem_samples, hsotg->frrem_accum, 2126 hsotg->frrem_samples > 0 ? 2127 hsotg->frrem_accum / hsotg->frrem_samples : 0); 2128 dev_dbg(hsotg->dev, "\n"); 2129 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n"); 2130 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2131 hsotg->hfnum_7_samples, 2132 hsotg->hfnum_7_frrem_accum, 2133 hsotg->hfnum_7_samples > 0 ? 2134 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0); 2135 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n"); 2136 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2137 hsotg->hfnum_0_samples, 2138 hsotg->hfnum_0_frrem_accum, 2139 hsotg->hfnum_0_samples > 0 ? 2140 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0); 2141 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n"); 2142 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2143 hsotg->hfnum_other_samples, 2144 hsotg->hfnum_other_frrem_accum, 2145 hsotg->hfnum_other_samples > 0 ? 2146 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples : 2147 0); 2148 dev_dbg(hsotg->dev, "\n"); 2149 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n"); 2150 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2151 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a, 2152 hsotg->hfnum_7_samples_a > 0 ? 2153 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0); 2154 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n"); 2155 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2156 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a, 2157 hsotg->hfnum_0_samples_a > 0 ? 2158 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0); 2159 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n"); 2160 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2161 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a, 2162 hsotg->hfnum_other_samples_a > 0 ? 2163 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a 2164 : 0); 2165 dev_dbg(hsotg->dev, "\n"); 2166 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n"); 2167 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2168 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b, 2169 hsotg->hfnum_7_samples_b > 0 ? 2170 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0); 2171 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n"); 2172 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2173 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b, 2174 (hsotg->hfnum_0_samples_b > 0) ? 2175 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0); 2176 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n"); 2177 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n", 2178 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b, 2179 (hsotg->hfnum_other_samples_b > 0) ? 2180 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b 2181 : 0); 2182 #endif 2183 } 2184 2185 struct wrapper_priv_data { 2186 struct dwc2_hsotg *hsotg; 2187 }; 2188 2189 /* Gets the dwc2_hsotg from a usb_hcd */ 2190 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd) 2191 { 2192 struct wrapper_priv_data *p; 2193 2194 p = (struct wrapper_priv_data *) &hcd->hcd_priv; 2195 return p->hsotg; 2196 } 2197 2198 static int _dwc2_hcd_start(struct usb_hcd *hcd); 2199 2200 void dwc2_host_start(struct dwc2_hsotg *hsotg) 2201 { 2202 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2203 2204 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg); 2205 _dwc2_hcd_start(hcd); 2206 } 2207 2208 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg) 2209 { 2210 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg); 2211 2212 hcd->self.is_b_host = 0; 2213 } 2214 2215 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr, 2216 int *hub_port) 2217 { 2218 struct urb *urb = context; 2219 2220 if (urb->dev->tt) 2221 *hub_addr = urb->dev->tt->hub->devnum; 2222 else 2223 *hub_addr = 0; 2224 *hub_port = urb->dev->ttport; 2225 } 2226 2227 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context) 2228 { 2229 struct urb *urb = context; 2230 2231 return urb->dev->speed; 2232 } 2233 2234 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2235 struct urb *urb) 2236 { 2237 struct usb_bus *bus = hcd_to_bus(hcd); 2238 2239 if (urb->interval) 2240 bus->bandwidth_allocated += bw / urb->interval; 2241 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2242 bus->bandwidth_isoc_reqs++; 2243 else 2244 bus->bandwidth_int_reqs++; 2245 } 2246 2247 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw, 2248 struct urb *urb) 2249 { 2250 struct usb_bus *bus = hcd_to_bus(hcd); 2251 2252 if (urb->interval) 2253 bus->bandwidth_allocated -= bw / urb->interval; 2254 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) 2255 bus->bandwidth_isoc_reqs--; 2256 else 2257 bus->bandwidth_int_reqs--; 2258 } 2259 2260 /* 2261 * Sets the final status of an URB and returns it to the upper layer. Any 2262 * required cleanup of the URB is performed. 2263 * 2264 * Must be called with interrupt disabled and spinlock held 2265 */ 2266 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 2267 int status) 2268 { 2269 struct urb *urb; 2270 int i; 2271 2272 if (!qtd) { 2273 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__); 2274 return; 2275 } 2276 2277 if (!qtd->urb) { 2278 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__); 2279 return; 2280 } 2281 2282 urb = qtd->urb->priv; 2283 if (!urb) { 2284 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__); 2285 return; 2286 } 2287 2288 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb); 2289 2290 if (dbg_urb(urb)) 2291 dev_vdbg(hsotg->dev, 2292 "%s: urb %p device %d ep %d-%s status %d actual %d\n", 2293 __func__, urb, usb_pipedevice(urb->pipe), 2294 usb_pipeendpoint(urb->pipe), 2295 usb_pipein(urb->pipe) ? "IN" : "OUT", status, 2296 urb->actual_length); 2297 2298 2299 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2300 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb); 2301 for (i = 0; i < urb->number_of_packets; ++i) { 2302 urb->iso_frame_desc[i].actual_length = 2303 dwc2_hcd_urb_get_iso_desc_actual_length( 2304 qtd->urb, i); 2305 urb->iso_frame_desc[i].status = 2306 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i); 2307 } 2308 } 2309 2310 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) { 2311 for (i = 0; i < urb->number_of_packets; i++) 2312 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n", 2313 i, urb->iso_frame_desc[i].status); 2314 } 2315 2316 urb->status = status; 2317 if (!status) { 2318 if ((urb->transfer_flags & URB_SHORT_NOT_OK) && 2319 urb->actual_length < urb->transfer_buffer_length) 2320 urb->status = -EREMOTEIO; 2321 } 2322 2323 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2324 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2325 struct usb_host_endpoint *ep = urb->ep; 2326 2327 if (ep) 2328 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg), 2329 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2330 urb); 2331 } 2332 2333 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb); 2334 urb->hcpriv = NULL; 2335 kfree(qtd->urb); 2336 qtd->urb = NULL; 2337 2338 spin_unlock(&hsotg->lock); 2339 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status); 2340 spin_lock(&hsotg->lock); 2341 } 2342 2343 /* 2344 * Work queue function for starting the HCD when A-Cable is connected 2345 */ 2346 static void dwc2_hcd_start_func(struct work_struct *work) 2347 { 2348 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2349 start_work.work); 2350 2351 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg); 2352 dwc2_host_start(hsotg); 2353 } 2354 2355 /* 2356 * Reset work queue function 2357 */ 2358 static void dwc2_hcd_reset_func(struct work_struct *work) 2359 { 2360 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg, 2361 reset_work.work); 2362 unsigned long flags; 2363 u32 hprt0; 2364 2365 dev_dbg(hsotg->dev, "USB RESET function called\n"); 2366 2367 spin_lock_irqsave(&hsotg->lock, flags); 2368 2369 hprt0 = dwc2_read_hprt0(hsotg); 2370 hprt0 &= ~HPRT0_RST; 2371 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2372 hsotg->flags.b.port_reset_change = 1; 2373 2374 spin_unlock_irqrestore(&hsotg->lock, flags); 2375 } 2376 2377 /* 2378 * ========================================================================= 2379 * Linux HC Driver Functions 2380 * ========================================================================= 2381 */ 2382 2383 /* 2384 * Initializes the DWC_otg controller and its root hub and prepares it for host 2385 * mode operation. Activates the root port. Returns 0 on success and a negative 2386 * error code on failure. 2387 */ 2388 static int _dwc2_hcd_start(struct usb_hcd *hcd) 2389 { 2390 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2391 struct usb_bus *bus = hcd_to_bus(hcd); 2392 unsigned long flags; 2393 2394 dev_dbg(hsotg->dev, "DWC OTG HCD START\n"); 2395 2396 spin_lock_irqsave(&hsotg->lock, flags); 2397 hsotg->lx_state = DWC2_L0; 2398 hcd->state = HC_STATE_RUNNING; 2399 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2400 2401 if (dwc2_is_device_mode(hsotg)) { 2402 spin_unlock_irqrestore(&hsotg->lock, flags); 2403 return 0; /* why 0 ?? */ 2404 } 2405 2406 dwc2_hcd_reinit(hsotg); 2407 2408 /* Initialize and connect root hub if one is not already attached */ 2409 if (bus->root_hub) { 2410 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n"); 2411 /* Inform the HUB driver to resume */ 2412 usb_hcd_resume_root_hub(hcd); 2413 } 2414 2415 spin_unlock_irqrestore(&hsotg->lock, flags); 2416 return 0; 2417 } 2418 2419 /* 2420 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are 2421 * stopped. 2422 */ 2423 static void _dwc2_hcd_stop(struct usb_hcd *hcd) 2424 { 2425 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2426 unsigned long flags; 2427 2428 /* Turn off all host-specific interrupts */ 2429 dwc2_disable_host_interrupts(hsotg); 2430 2431 /* Wait for interrupt processing to finish */ 2432 synchronize_irq(hcd->irq); 2433 2434 spin_lock_irqsave(&hsotg->lock, flags); 2435 /* Ensure hcd is disconnected */ 2436 dwc2_hcd_disconnect(hsotg, true); 2437 dwc2_hcd_stop(hsotg); 2438 hsotg->lx_state = DWC2_L3; 2439 hcd->state = HC_STATE_HALT; 2440 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2441 spin_unlock_irqrestore(&hsotg->lock, flags); 2442 2443 usleep_range(1000, 3000); 2444 } 2445 2446 static int _dwc2_hcd_suspend(struct usb_hcd *hcd) 2447 { 2448 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2449 unsigned long flags; 2450 int ret = 0; 2451 u32 hprt0; 2452 2453 spin_lock_irqsave(&hsotg->lock, flags); 2454 2455 if (hsotg->lx_state != DWC2_L0) 2456 goto unlock; 2457 2458 if (!HCD_HW_ACCESSIBLE(hcd)) 2459 goto unlock; 2460 2461 if (!hsotg->core_params->hibernation) 2462 goto skip_power_saving; 2463 2464 /* 2465 * Drive USB suspend and disable port Power 2466 * if usb bus is not suspended. 2467 */ 2468 if (!hsotg->bus_suspended) { 2469 hprt0 = dwc2_read_hprt0(hsotg); 2470 hprt0 |= HPRT0_SUSP; 2471 hprt0 &= ~HPRT0_PWR; 2472 dwc2_writel(hprt0, hsotg->regs + HPRT0); 2473 } 2474 2475 /* Enter hibernation */ 2476 ret = dwc2_enter_hibernation(hsotg); 2477 if (ret) { 2478 if (ret != -ENOTSUPP) 2479 dev_err(hsotg->dev, 2480 "enter hibernation failed\n"); 2481 goto skip_power_saving; 2482 } 2483 2484 /* Ask phy to be suspended */ 2485 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2486 spin_unlock_irqrestore(&hsotg->lock, flags); 2487 usb_phy_set_suspend(hsotg->uphy, true); 2488 spin_lock_irqsave(&hsotg->lock, flags); 2489 } 2490 2491 /* After entering hibernation, hardware is no more accessible */ 2492 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2493 2494 skip_power_saving: 2495 hsotg->lx_state = DWC2_L2; 2496 unlock: 2497 spin_unlock_irqrestore(&hsotg->lock, flags); 2498 2499 return ret; 2500 } 2501 2502 static int _dwc2_hcd_resume(struct usb_hcd *hcd) 2503 { 2504 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2505 unsigned long flags; 2506 int ret = 0; 2507 2508 spin_lock_irqsave(&hsotg->lock, flags); 2509 2510 if (hsotg->lx_state != DWC2_L2) 2511 goto unlock; 2512 2513 if (!hsotg->core_params->hibernation) { 2514 hsotg->lx_state = DWC2_L0; 2515 goto unlock; 2516 } 2517 2518 /* 2519 * Set HW accessible bit before powering on the controller 2520 * since an interrupt may rise. 2521 */ 2522 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 2523 2524 /* 2525 * Enable power if not already done. 2526 * This must not be spinlocked since duration 2527 * of this call is unknown. 2528 */ 2529 if (!IS_ERR_OR_NULL(hsotg->uphy)) { 2530 spin_unlock_irqrestore(&hsotg->lock, flags); 2531 usb_phy_set_suspend(hsotg->uphy, false); 2532 spin_lock_irqsave(&hsotg->lock, flags); 2533 } 2534 2535 /* Exit hibernation */ 2536 ret = dwc2_exit_hibernation(hsotg, true); 2537 if (ret && (ret != -ENOTSUPP)) 2538 dev_err(hsotg->dev, "exit hibernation failed\n"); 2539 2540 hsotg->lx_state = DWC2_L0; 2541 2542 spin_unlock_irqrestore(&hsotg->lock, flags); 2543 2544 if (hsotg->bus_suspended) { 2545 spin_lock_irqsave(&hsotg->lock, flags); 2546 hsotg->flags.b.port_suspend_change = 1; 2547 spin_unlock_irqrestore(&hsotg->lock, flags); 2548 dwc2_port_resume(hsotg); 2549 } else { 2550 /* Wait for controller to correctly update D+/D- level */ 2551 usleep_range(3000, 5000); 2552 2553 /* 2554 * Clear Port Enable and Port Status changes. 2555 * Enable Port Power. 2556 */ 2557 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | 2558 HPRT0_ENACHG, hsotg->regs + HPRT0); 2559 /* Wait for controller to detect Port Connect */ 2560 usleep_range(5000, 7000); 2561 } 2562 2563 return ret; 2564 unlock: 2565 spin_unlock_irqrestore(&hsotg->lock, flags); 2566 2567 return ret; 2568 } 2569 2570 /* Returns the current frame number */ 2571 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd) 2572 { 2573 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2574 2575 return dwc2_hcd_get_frame_number(hsotg); 2576 } 2577 2578 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb, 2579 char *fn_name) 2580 { 2581 #ifdef VERBOSE_DEBUG 2582 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2583 char *pipetype; 2584 char *speed; 2585 2586 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb); 2587 dev_vdbg(hsotg->dev, " Device address: %d\n", 2588 usb_pipedevice(urb->pipe)); 2589 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n", 2590 usb_pipeendpoint(urb->pipe), 2591 usb_pipein(urb->pipe) ? "IN" : "OUT"); 2592 2593 switch (usb_pipetype(urb->pipe)) { 2594 case PIPE_CONTROL: 2595 pipetype = "CONTROL"; 2596 break; 2597 case PIPE_BULK: 2598 pipetype = "BULK"; 2599 break; 2600 case PIPE_INTERRUPT: 2601 pipetype = "INTERRUPT"; 2602 break; 2603 case PIPE_ISOCHRONOUS: 2604 pipetype = "ISOCHRONOUS"; 2605 break; 2606 default: 2607 pipetype = "UNKNOWN"; 2608 break; 2609 } 2610 2611 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype, 2612 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ? 2613 "IN" : "OUT"); 2614 2615 switch (urb->dev->speed) { 2616 case USB_SPEED_HIGH: 2617 speed = "HIGH"; 2618 break; 2619 case USB_SPEED_FULL: 2620 speed = "FULL"; 2621 break; 2622 case USB_SPEED_LOW: 2623 speed = "LOW"; 2624 break; 2625 default: 2626 speed = "UNKNOWN"; 2627 break; 2628 } 2629 2630 dev_vdbg(hsotg->dev, " Speed: %s\n", speed); 2631 dev_vdbg(hsotg->dev, " Max packet size: %d\n", 2632 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); 2633 dev_vdbg(hsotg->dev, " Data buffer length: %d\n", 2634 urb->transfer_buffer_length); 2635 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n", 2636 urb->transfer_buffer, (unsigned long)urb->transfer_dma); 2637 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n", 2638 urb->setup_packet, (unsigned long)urb->setup_dma); 2639 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval); 2640 2641 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { 2642 int i; 2643 2644 for (i = 0; i < urb->number_of_packets; i++) { 2645 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i); 2646 dev_vdbg(hsotg->dev, " offset: %d, length %d\n", 2647 urb->iso_frame_desc[i].offset, 2648 urb->iso_frame_desc[i].length); 2649 } 2650 } 2651 #endif 2652 } 2653 2654 /* 2655 * Starts processing a USB transfer request specified by a USB Request Block 2656 * (URB). mem_flags indicates the type of memory allocation to use while 2657 * processing this URB. 2658 */ 2659 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 2660 gfp_t mem_flags) 2661 { 2662 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2663 struct usb_host_endpoint *ep = urb->ep; 2664 struct dwc2_hcd_urb *dwc2_urb; 2665 int i; 2666 int retval; 2667 int alloc_bandwidth = 0; 2668 u8 ep_type = 0; 2669 u32 tflags = 0; 2670 void *buf; 2671 unsigned long flags; 2672 struct dwc2_qh *qh; 2673 bool qh_allocated = false; 2674 struct dwc2_qtd *qtd; 2675 2676 if (dbg_urb(urb)) { 2677 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n"); 2678 dwc2_dump_urb_info(hcd, urb, "urb_enqueue"); 2679 } 2680 2681 if (ep == NULL) 2682 return -EINVAL; 2683 2684 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS || 2685 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) { 2686 spin_lock_irqsave(&hsotg->lock, flags); 2687 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep)) 2688 alloc_bandwidth = 1; 2689 spin_unlock_irqrestore(&hsotg->lock, flags); 2690 } 2691 2692 switch (usb_pipetype(urb->pipe)) { 2693 case PIPE_CONTROL: 2694 ep_type = USB_ENDPOINT_XFER_CONTROL; 2695 break; 2696 case PIPE_ISOCHRONOUS: 2697 ep_type = USB_ENDPOINT_XFER_ISOC; 2698 break; 2699 case PIPE_BULK: 2700 ep_type = USB_ENDPOINT_XFER_BULK; 2701 break; 2702 case PIPE_INTERRUPT: 2703 ep_type = USB_ENDPOINT_XFER_INT; 2704 break; 2705 default: 2706 dev_warn(hsotg->dev, "Wrong ep type\n"); 2707 } 2708 2709 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets, 2710 mem_flags); 2711 if (!dwc2_urb) 2712 return -ENOMEM; 2713 2714 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe), 2715 usb_pipeendpoint(urb->pipe), ep_type, 2716 usb_pipein(urb->pipe), 2717 usb_maxpacket(urb->dev, urb->pipe, 2718 !(usb_pipein(urb->pipe)))); 2719 2720 buf = urb->transfer_buffer; 2721 2722 if (hcd->self.uses_dma) { 2723 if (!buf && (urb->transfer_dma & 3)) { 2724 dev_err(hsotg->dev, 2725 "%s: unaligned transfer with no transfer_buffer", 2726 __func__); 2727 retval = -EINVAL; 2728 goto fail0; 2729 } 2730 } 2731 2732 if (!(urb->transfer_flags & URB_NO_INTERRUPT)) 2733 tflags |= URB_GIVEBACK_ASAP; 2734 if (urb->transfer_flags & URB_ZERO_PACKET) 2735 tflags |= URB_SEND_ZERO_PACKET; 2736 2737 dwc2_urb->priv = urb; 2738 dwc2_urb->buf = buf; 2739 dwc2_urb->dma = urb->transfer_dma; 2740 dwc2_urb->length = urb->transfer_buffer_length; 2741 dwc2_urb->setup_packet = urb->setup_packet; 2742 dwc2_urb->setup_dma = urb->setup_dma; 2743 dwc2_urb->flags = tflags; 2744 dwc2_urb->interval = urb->interval; 2745 dwc2_urb->status = -EINPROGRESS; 2746 2747 for (i = 0; i < urb->number_of_packets; ++i) 2748 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i, 2749 urb->iso_frame_desc[i].offset, 2750 urb->iso_frame_desc[i].length); 2751 2752 urb->hcpriv = dwc2_urb; 2753 qh = (struct dwc2_qh *) ep->hcpriv; 2754 /* Create QH for the endpoint if it doesn't exist */ 2755 if (!qh) { 2756 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags); 2757 if (!qh) { 2758 retval = -ENOMEM; 2759 goto fail0; 2760 } 2761 ep->hcpriv = qh; 2762 qh_allocated = true; 2763 } 2764 2765 qtd = kzalloc(sizeof(*qtd), mem_flags); 2766 if (!qtd) { 2767 retval = -ENOMEM; 2768 goto fail1; 2769 } 2770 2771 spin_lock_irqsave(&hsotg->lock, flags); 2772 retval = usb_hcd_link_urb_to_ep(hcd, urb); 2773 if (retval) 2774 goto fail2; 2775 2776 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd); 2777 if (retval) 2778 goto fail3; 2779 2780 if (alloc_bandwidth) { 2781 dwc2_allocate_bus_bandwidth(hcd, 2782 dwc2_hcd_get_ep_bandwidth(hsotg, ep), 2783 urb); 2784 } 2785 2786 spin_unlock_irqrestore(&hsotg->lock, flags); 2787 2788 return 0; 2789 2790 fail3: 2791 dwc2_urb->priv = NULL; 2792 usb_hcd_unlink_urb_from_ep(hcd, urb); 2793 if (qh_allocated && qh->channel && qh->channel->qh == qh) 2794 qh->channel->qh = NULL; 2795 fail2: 2796 spin_unlock_irqrestore(&hsotg->lock, flags); 2797 urb->hcpriv = NULL; 2798 kfree(qtd); 2799 fail1: 2800 if (qh_allocated) { 2801 struct dwc2_qtd *qtd2, *qtd2_tmp; 2802 2803 ep->hcpriv = NULL; 2804 dwc2_hcd_qh_unlink(hsotg, qh); 2805 /* Free each QTD in the QH's QTD list */ 2806 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list, 2807 qtd_list_entry) 2808 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh); 2809 dwc2_hcd_qh_free(hsotg, qh); 2810 } 2811 fail0: 2812 kfree(dwc2_urb); 2813 2814 return retval; 2815 } 2816 2817 /* 2818 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success. 2819 */ 2820 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, 2821 int status) 2822 { 2823 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2824 int rc; 2825 unsigned long flags; 2826 2827 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n"); 2828 dwc2_dump_urb_info(hcd, urb, "urb_dequeue"); 2829 2830 spin_lock_irqsave(&hsotg->lock, flags); 2831 2832 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 2833 if (rc) 2834 goto out; 2835 2836 if (!urb->hcpriv) { 2837 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); 2838 goto out; 2839 } 2840 2841 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); 2842 2843 usb_hcd_unlink_urb_from_ep(hcd, urb); 2844 2845 kfree(urb->hcpriv); 2846 urb->hcpriv = NULL; 2847 2848 /* Higher layer software sets URB status */ 2849 spin_unlock(&hsotg->lock); 2850 usb_hcd_giveback_urb(hcd, urb, status); 2851 spin_lock(&hsotg->lock); 2852 2853 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n"); 2854 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status); 2855 out: 2856 spin_unlock_irqrestore(&hsotg->lock, flags); 2857 2858 return rc; 2859 } 2860 2861 /* 2862 * Frees resources in the DWC_otg controller related to a given endpoint. Also 2863 * clears state in the HCD related to the endpoint. Any URBs for the endpoint 2864 * must already be dequeued. 2865 */ 2866 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd, 2867 struct usb_host_endpoint *ep) 2868 { 2869 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2870 2871 dev_dbg(hsotg->dev, 2872 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n", 2873 ep->desc.bEndpointAddress, ep->hcpriv); 2874 dwc2_hcd_endpoint_disable(hsotg, ep, 250); 2875 } 2876 2877 /* 2878 * Resets endpoint specific parameter values, in current version used to reset 2879 * the data toggle (as a WA). This function can be called from usb_clear_halt 2880 * routine. 2881 */ 2882 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd, 2883 struct usb_host_endpoint *ep) 2884 { 2885 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2886 unsigned long flags; 2887 2888 dev_dbg(hsotg->dev, 2889 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n", 2890 ep->desc.bEndpointAddress); 2891 2892 spin_lock_irqsave(&hsotg->lock, flags); 2893 dwc2_hcd_endpoint_reset(hsotg, ep); 2894 spin_unlock_irqrestore(&hsotg->lock, flags); 2895 } 2896 2897 /* 2898 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if 2899 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid 2900 * interrupt. 2901 * 2902 * This function is called by the USB core when an interrupt occurs 2903 */ 2904 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd) 2905 { 2906 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2907 2908 return dwc2_handle_hcd_intr(hsotg); 2909 } 2910 2911 /* 2912 * Creates Status Change bitmap for the root hub and root port. The bitmap is 2913 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 2914 * is the status change indicator for the single root port. Returns 1 if either 2915 * change indicator is 1, otherwise returns 0. 2916 */ 2917 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf) 2918 { 2919 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2920 2921 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1; 2922 return buf[0] != 0; 2923 } 2924 2925 /* Handles hub class-specific requests */ 2926 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue, 2927 u16 windex, char *buf, u16 wlength) 2928 { 2929 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq, 2930 wvalue, windex, buf, wlength); 2931 return retval; 2932 } 2933 2934 /* Handles hub TT buffer clear completions */ 2935 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd, 2936 struct usb_host_endpoint *ep) 2937 { 2938 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd); 2939 struct dwc2_qh *qh; 2940 unsigned long flags; 2941 2942 qh = ep->hcpriv; 2943 if (!qh) 2944 return; 2945 2946 spin_lock_irqsave(&hsotg->lock, flags); 2947 qh->tt_buffer_dirty = 0; 2948 2949 if (hsotg->flags.b.port_connect_status) 2950 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL); 2951 2952 spin_unlock_irqrestore(&hsotg->lock, flags); 2953 } 2954 2955 static struct hc_driver dwc2_hc_driver = { 2956 .description = "dwc2_hsotg", 2957 .product_desc = "DWC OTG Controller", 2958 .hcd_priv_size = sizeof(struct wrapper_priv_data), 2959 2960 .irq = _dwc2_hcd_irq, 2961 .flags = HCD_MEMORY | HCD_USB2, 2962 2963 .start = _dwc2_hcd_start, 2964 .stop = _dwc2_hcd_stop, 2965 .urb_enqueue = _dwc2_hcd_urb_enqueue, 2966 .urb_dequeue = _dwc2_hcd_urb_dequeue, 2967 .endpoint_disable = _dwc2_hcd_endpoint_disable, 2968 .endpoint_reset = _dwc2_hcd_endpoint_reset, 2969 .get_frame_number = _dwc2_hcd_get_frame_number, 2970 2971 .hub_status_data = _dwc2_hcd_hub_status_data, 2972 .hub_control = _dwc2_hcd_hub_control, 2973 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete, 2974 2975 .bus_suspend = _dwc2_hcd_suspend, 2976 .bus_resume = _dwc2_hcd_resume, 2977 2978 .map_urb_for_dma = dwc2_map_urb_for_dma, 2979 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma, 2980 }; 2981 2982 /* 2983 * Frees secondary storage associated with the dwc2_hsotg structure contained 2984 * in the struct usb_hcd field 2985 */ 2986 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 2987 { 2988 u32 ahbcfg; 2989 u32 dctl; 2990 int i; 2991 2992 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n"); 2993 2994 /* Free memory for QH/QTD lists */ 2995 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive); 2996 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active); 2997 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive); 2998 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready); 2999 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned); 3000 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued); 3001 3002 /* Free memory for the host channels */ 3003 for (i = 0; i < MAX_EPS_CHANNELS; i++) { 3004 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i]; 3005 3006 if (chan != NULL) { 3007 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n", 3008 i, chan); 3009 hsotg->hc_ptr_array[i] = NULL; 3010 kfree(chan); 3011 } 3012 } 3013 3014 if (hsotg->core_params->dma_enable > 0) { 3015 if (hsotg->status_buf) { 3016 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE, 3017 hsotg->status_buf, 3018 hsotg->status_buf_dma); 3019 hsotg->status_buf = NULL; 3020 } 3021 } else { 3022 kfree(hsotg->status_buf); 3023 hsotg->status_buf = NULL; 3024 } 3025 3026 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); 3027 3028 /* Disable all interrupts */ 3029 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 3030 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); 3031 dwc2_writel(0, hsotg->regs + GINTMSK); 3032 3033 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { 3034 dctl = dwc2_readl(hsotg->regs + DCTL); 3035 dctl |= DCTL_SFTDISCON; 3036 dwc2_writel(dctl, hsotg->regs + DCTL); 3037 } 3038 3039 if (hsotg->wq_otg) { 3040 if (!cancel_work_sync(&hsotg->wf_otg)) 3041 flush_workqueue(hsotg->wq_otg); 3042 destroy_workqueue(hsotg->wq_otg); 3043 } 3044 3045 del_timer(&hsotg->wkp_timer); 3046 } 3047 3048 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg) 3049 { 3050 /* Turn off all host-specific interrupts */ 3051 dwc2_disable_host_interrupts(hsotg); 3052 3053 dwc2_hcd_free(hsotg); 3054 } 3055 3056 /* 3057 * Initializes the HCD. This function allocates memory for and initializes the 3058 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the 3059 * USB bus with the core and calls the hc_driver->start() function. It returns 3060 * a negative error on failure. 3061 */ 3062 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) 3063 { 3064 struct usb_hcd *hcd; 3065 struct dwc2_host_chan *channel; 3066 u32 hcfg; 3067 int i, num_channels; 3068 int retval; 3069 3070 if (usb_disabled()) 3071 return -ENODEV; 3072 3073 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n"); 3074 3075 retval = -ENOMEM; 3076 3077 hcfg = dwc2_readl(hsotg->regs + HCFG); 3078 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); 3079 3080 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3081 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) * 3082 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3083 if (!hsotg->frame_num_array) 3084 goto error1; 3085 hsotg->last_frame_num_array = kzalloc( 3086 sizeof(*hsotg->last_frame_num_array) * 3087 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL); 3088 if (!hsotg->last_frame_num_array) 3089 goto error1; 3090 hsotg->last_frame_num = HFNUM_MAX_FRNUM; 3091 #endif 3092 3093 /* Check if the bus driver or platform code has setup a dma_mask */ 3094 if (hsotg->core_params->dma_enable > 0 && 3095 hsotg->dev->dma_mask == NULL) { 3096 dev_warn(hsotg->dev, 3097 "dma_mask not set, disabling DMA\n"); 3098 hsotg->core_params->dma_enable = 0; 3099 hsotg->core_params->dma_desc_enable = 0; 3100 } 3101 3102 /* Set device flags indicating whether the HCD supports DMA */ 3103 if (hsotg->core_params->dma_enable > 0) { 3104 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3105 dev_warn(hsotg->dev, "can't set DMA mask\n"); 3106 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0) 3107 dev_warn(hsotg->dev, "can't set coherent DMA mask\n"); 3108 } 3109 3110 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev)); 3111 if (!hcd) 3112 goto error1; 3113 3114 if (hsotg->core_params->dma_enable <= 0) 3115 hcd->self.uses_dma = 0; 3116 3117 hcd->has_tt = 1; 3118 3119 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg; 3120 hsotg->priv = hcd; 3121 3122 /* 3123 * Disable the global interrupt until all the interrupt handlers are 3124 * installed 3125 */ 3126 dwc2_disable_global_interrupts(hsotg); 3127 3128 /* Initialize the DWC_otg core, and select the Phy type */ 3129 retval = dwc2_core_init(hsotg, true); 3130 if (retval) 3131 goto error2; 3132 3133 /* Create new workqueue and init work */ 3134 retval = -ENOMEM; 3135 hsotg->wq_otg = create_singlethread_workqueue("dwc2"); 3136 if (!hsotg->wq_otg) { 3137 dev_err(hsotg->dev, "Failed to create workqueue\n"); 3138 goto error2; 3139 } 3140 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change); 3141 3142 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected, 3143 (unsigned long)hsotg); 3144 3145 /* Initialize the non-periodic schedule */ 3146 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive); 3147 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active); 3148 3149 /* Initialize the periodic schedule */ 3150 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive); 3151 INIT_LIST_HEAD(&hsotg->periodic_sched_ready); 3152 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned); 3153 INIT_LIST_HEAD(&hsotg->periodic_sched_queued); 3154 3155 /* 3156 * Create a host channel descriptor for each host channel implemented 3157 * in the controller. Initialize the channel descriptor array. 3158 */ 3159 INIT_LIST_HEAD(&hsotg->free_hc_list); 3160 num_channels = hsotg->core_params->host_channels; 3161 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array)); 3162 3163 for (i = 0; i < num_channels; i++) { 3164 channel = kzalloc(sizeof(*channel), GFP_KERNEL); 3165 if (channel == NULL) 3166 goto error3; 3167 channel->hc_num = i; 3168 hsotg->hc_ptr_array[i] = channel; 3169 } 3170 3171 if (hsotg->core_params->uframe_sched > 0) 3172 dwc2_hcd_init_usecs(hsotg); 3173 3174 /* Initialize hsotg start work */ 3175 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func); 3176 3177 /* Initialize port reset work */ 3178 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func); 3179 3180 /* 3181 * Allocate space for storing data on status transactions. Normally no 3182 * data is sent, but this space acts as a bit bucket. This must be 3183 * done after usb_add_hcd since that function allocates the DMA buffer 3184 * pool. 3185 */ 3186 if (hsotg->core_params->dma_enable > 0) 3187 hsotg->status_buf = dma_alloc_coherent(hsotg->dev, 3188 DWC2_HCD_STATUS_BUF_SIZE, 3189 &hsotg->status_buf_dma, GFP_KERNEL); 3190 else 3191 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE, 3192 GFP_KERNEL); 3193 3194 if (!hsotg->status_buf) 3195 goto error3; 3196 3197 /* 3198 * Create kmem caches to handle descriptor buffers in descriptor 3199 * DMA mode. 3200 * Alignment must be set to 512 bytes. 3201 */ 3202 if (hsotg->core_params->dma_desc_enable || 3203 hsotg->core_params->dma_desc_fs_enable) { 3204 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc", 3205 sizeof(struct dwc2_hcd_dma_desc) * 3206 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA, 3207 NULL); 3208 if (!hsotg->desc_gen_cache) { 3209 dev_err(hsotg->dev, 3210 "unable to create dwc2 generic desc cache\n"); 3211 3212 /* 3213 * Disable descriptor dma mode since it will not be 3214 * usable. 3215 */ 3216 hsotg->core_params->dma_desc_enable = 0; 3217 hsotg->core_params->dma_desc_fs_enable = 0; 3218 } 3219 3220 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc", 3221 sizeof(struct dwc2_hcd_dma_desc) * 3222 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL); 3223 if (!hsotg->desc_hsisoc_cache) { 3224 dev_err(hsotg->dev, 3225 "unable to create dwc2 hs isoc desc cache\n"); 3226 3227 kmem_cache_destroy(hsotg->desc_gen_cache); 3228 3229 /* 3230 * Disable descriptor dma mode since it will not be 3231 * usable. 3232 */ 3233 hsotg->core_params->dma_desc_enable = 0; 3234 hsotg->core_params->dma_desc_fs_enable = 0; 3235 } 3236 } 3237 3238 hsotg->otg_port = 1; 3239 hsotg->frame_list = NULL; 3240 hsotg->frame_list_dma = 0; 3241 hsotg->periodic_qh_count = 0; 3242 3243 /* Initiate lx_state to L3 disconnected state */ 3244 hsotg->lx_state = DWC2_L3; 3245 3246 hcd->self.otg_port = hsotg->otg_port; 3247 3248 /* Don't support SG list at this point */ 3249 hcd->self.sg_tablesize = 0; 3250 3251 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3252 otg_set_host(hsotg->uphy->otg, &hcd->self); 3253 3254 /* 3255 * Finish generic HCD initialization and start the HCD. This function 3256 * allocates the DMA buffer pool, registers the USB bus, requests the 3257 * IRQ line, and calls hcd_start method. 3258 */ 3259 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 3260 if (retval < 0) 3261 goto error4; 3262 3263 device_wakeup_enable(hcd->self.controller); 3264 3265 dwc2_hcd_dump_state(hsotg); 3266 3267 dwc2_enable_global_interrupts(hsotg); 3268 3269 return 0; 3270 3271 error4: 3272 kmem_cache_destroy(hsotg->desc_gen_cache); 3273 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 3274 error3: 3275 dwc2_hcd_release(hsotg); 3276 error2: 3277 usb_put_hcd(hcd); 3278 error1: 3279 kfree(hsotg->core_params); 3280 3281 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3282 kfree(hsotg->last_frame_num_array); 3283 kfree(hsotg->frame_num_array); 3284 #endif 3285 3286 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval); 3287 return retval; 3288 } 3289 3290 /* 3291 * Removes the HCD. 3292 * Frees memory and resources associated with the HCD and deregisters the bus. 3293 */ 3294 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) 3295 { 3296 struct usb_hcd *hcd; 3297 3298 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n"); 3299 3300 hcd = dwc2_hsotg_to_hcd(hsotg); 3301 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd); 3302 3303 if (!hcd) { 3304 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n", 3305 __func__); 3306 return; 3307 } 3308 3309 if (!IS_ERR_OR_NULL(hsotg->uphy)) 3310 otg_set_host(hsotg->uphy->otg, NULL); 3311 3312 usb_remove_hcd(hcd); 3313 hsotg->priv = NULL; 3314 3315 kmem_cache_destroy(hsotg->desc_gen_cache); 3316 kmem_cache_destroy(hsotg->desc_hsisoc_cache); 3317 3318 dwc2_hcd_release(hsotg); 3319 usb_put_hcd(hcd); 3320 3321 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS 3322 kfree(hsotg->last_frame_num_array); 3323 kfree(hsotg->frame_num_array); 3324 #endif 3325 } 3326